WO2021159583A1 - 栅极驱动电路及包含其的显示装置 - Google Patents

栅极驱动电路及包含其的显示装置 Download PDF

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Publication number
WO2021159583A1
WO2021159583A1 PCT/CN2020/080110 CN2020080110W WO2021159583A1 WO 2021159583 A1 WO2021159583 A1 WO 2021159583A1 CN 2020080110 W CN2020080110 W CN 2020080110W WO 2021159583 A1 WO2021159583 A1 WO 2021159583A1
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Prior art keywords
node
transistor
potential
signal
module
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PCT/CN2020/080110
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English (en)
French (fr)
Inventor
张留旗
韩佰祥
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/757,408 priority Critical patent/US11610550B2/en
Publication of WO2021159583A1 publication Critical patent/WO2021159583A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present invention relates to the field of display technology, and in particular to a gate driving circuit for a display panel.
  • Indium Gallium Zinc Oxide is widely used in large-size active-matrix organic light-emitting diodes due to its high mobility.
  • light-emitting diode, AMOLED light-emitting diode
  • active organic light emitting diode displays must use a compensation circuit to ensure the brightness uniformity of the display.
  • the compensation circuit requires a positive pulse waveform and a negative pulse waveform.
  • the existing gate drive circuits that generate negative pulse waveforms still lack stability.
  • the object of the present invention is to provide a gate driving circuit and a display device to improve the stability of the negative pulse circuit.
  • the present invention provides a gate driving circuit including a plurality of cascaded gate driving units, wherein the gate driving unit includes: an input module, including a first transistor, The gate is connected to the clock signal, the source of the first transistor is connected to the previous stage transmission signal, the drain of the first transistor is connected to the first node, and the input module is used to connect The pre-stage transmission signal is output to the first node; a first output module, the first output module is connected to the clock signal and the second node, and is used to output under the control of the potential of the second node This level transmits the signal; the second output module, the second output module is connected to the clock signal and the second node, and is used to output the scan signal under the control of the potential of the second node; the feedback module, the The feedback module is connected to the clock signal, the second node and the first DC high voltage, and is used to output a feedback signal of the current level under the control of the potential of the second node; an output control module, the output control module Connect
  • the present invention also provides a gate drive circuit, including a plurality of cascaded gate drive units, wherein the gate drive unit includes: an input module, the input module is connected to the clock signal, the previous stage The stage transmission signal and the first node are used to output the previous stage transmission signal to the first node under the control of the clock signal; a first output module, where the first output module is connected to the clock The signal and the second node are used to output the current level transmission signal under the control of the potential of the second node; the second output module, the second output module is connected to the clock signal and the second node, Under the control of the potential of the second node, a scan signal is output; a feedback module, the feedback module is connected to the clock signal, the second node and the first DC high voltage, and is used to connect to the second node Under the potential control of, output the feedback signal of the current stage; and an output control module connected to the feedback signal of the next stage, the first DC high voltage, the second DC high voltage, the first node,
  • the gate driving unit further includes: an inverter module connected to the first node, the second node, the DC low voltage, and the first DC high voltage, Used to control the potential of the second node under the control of the potential of the first node; and a maintenance module that connects the DC low voltage, the first node and the second node, and Under the control of the potential of the second node, the potential of the first node is maintained at the DC low voltage potential.
  • the input module includes a first transistor, the gate of the first transistor is connected to the clock signal, the source of the first transistor is connected to the previous stage transmission signal, and the first transistor is The drain of the transistor is connected to the first node.
  • the inverter module includes: a second transistor, a gate of the second transistor is connected to the first node, and a source of the second transistor is connected to the DC low voltage; and a third transistor , The gate of the third transistor is connected to the first node, the source of the third transistor is connected to the DC low voltage, and the drain of the third transistor is connected to the second node; a fourth transistor, The gate and source of the fourth transistor are connected to the first DC high voltage, and the drain of the fourth transistor is connected to the drain of the second transistor; and a fifth transistor, The gate is connected to the drain of the second transistor, the source of the fifth transistor is connected to the first DC high voltage, and the drain of the fifth transistor is connected to the second node.
  • the sustain module includes a sixth transistor, the gate of the sixth transistor is connected to the second node, the source of the sixth transistor is connected to the DC low voltage, and the sixth transistor The drain is connected to the first node.
  • the first output module includes a seventh transistor, the gate of the seventh transistor is connected to the second node, the source of the seventh transistor is connected to the clock signal, and the seventh transistor is connected to the clock signal.
  • the drain of the transistor is connected to the signal of the current stage.
  • the second output module includes an eighth transistor, a gate of the eighth transistor is connected to the second node, a source of the eighth transistor is connected to the clock signal, and the eighth transistor is connected to the clock signal. The drain of the transistor is connected to the scan signal.
  • the output control module includes: a ninth transistor, a gate of the ninth transistor is connected to the first node, and a source of the ninth transistor is connected to the second DC high voltage, so The drain of the ninth transistor is connected to the current stage signal; and the tenth transistor, the gate of the tenth transistor is connected to the first node, and the source of the tenth transistor is connected to the first node. A high voltage is applied, and the drain of the tenth transistor is connected to the scan signal.
  • the feedback module includes: an eleventh transistor, a gate of the eleventh transistor is connected to the second node, a source of the eleventh transistor is connected to the clock signal, and the The drain of the eleventh transistor is connected to the feedback signal of this stage; and the twelfth transistor, the gate of the twelfth transistor is connected to the first node, and the source of the twelfth transistor is connected to the first node. A high voltage is applied, and the drain of the twelfth transistor is connected to the feedback signal of this stage.
  • the gate driving unit further includes a first capacitor, and the gate of the ninth transistor and the gate of the tenth transistor are connected to the next-stage feedback signal through the first capacitor.
  • the gate driving unit further includes a thirteenth transistor, the gate and source of the thirteenth transistor are connected to a reset signal, and the drain of the thirteenth transistor is connected to the first node .
  • the present invention also provides a display device, including a gate driving circuit, the gate driving circuit includes a plurality of cascaded gate driving units, wherein the gate driving unit includes: an input module, The input module is connected to the clock signal, the previous stage transmission signal and the first node, and is used to output the previous stage transmission signal to the first node under the control of the clock signal; the first output module, The first output module is connected to the clock signal and the second node, and is used to output the current level transmission signal under the control of the potential of the second node; the second output module, the second output module is connected to the The clock signal and the second node are used to output a scan signal under the control of the potential of the second node; a feedback module that connects the clock signal, the second node and the first DC high The voltage is used to output the feedback signal of the current stage under the control of the potential of the second node; and an output control module connected to the feedback signal of the next stage, the first DC high voltage, and the second DC The high voltage, the
  • the invention provides a gate driving circuit and a display device to improve the stability of the negative pulse circuit.
  • Figure 1 is a functional block diagram of a gate drive circuit of a display device according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the circuit structure of the gate drive unit shown in Figure 1;
  • FIG. 3 is a working timing diagram of the gate driving unit shown in FIG. 2.
  • FIG. 1 shows a functional block diagram of a gate driving circuit of a display device according to an embodiment of the present invention.
  • the display device at least includes a gate driving circuit 1.
  • the gate driving circuit 1 includes a plurality of cascaded gate driving units 20.
  • the gate driving unit 20 of each stage is used for outputting a scanning signal G(n) with a negative pulse waveform and a stage transmission signal Cout(n) with a negative pulse waveform.
  • the gate driving circuit 1 works, the first-stage gate driving unit 20 is driven by the start signal STV. Subsequently, the remaining gate driving units 20 are sequentially driven by the level transmission signal Cout(n) of the previous gate driving unit 20.
  • FIG. 2 shows a schematic diagram of the circuit structure of the gate driving unit shown in FIG. 1.
  • the gate driving unit 20 includes an input module 101, an inverter module 102, a maintenance module 103, a first output module 104, a second output module 105, an output control module 106, and a feedback module 107.
  • the gate driving unit 20 is an n-th stage gate driving unit, where n is a positive integer.
  • the input module 101 is connected to the clock signal CK, the previous stage transmission signal Cout(n-1) and the first node QB.
  • the input module 101 is used to output the previous stage transmission signal Cout(n-1) to the first node QB under the control of the clock signal CK.
  • the input module 101 includes a first transistor T1, the gate of the first transistor T1 is connected to the clock signal CK, the source of the first transistor T1 is connected to the previous stage transmission signal Cout(n-1), and the drain of the first transistor T1 is connected to the second One node QB.
  • the inverter module 102 is connected to the first node QB, the second node Q, the DC low voltage VGL and the first DC high voltage VGH1.
  • the inverter module 102 is used to control the potential of the second node Q under the control of the potential of the first node QB.
  • the inverter module 102 includes a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the gate of the second transistor T2 is connected to the first node QB, and the source of the second transistor T2 is connected to the DC low voltage VGL.
  • the gate of the third transistor T3 is connected to the first node QB, the source of the third transistor T3 is connected to the DC low voltage VGL, and the drain of the third transistor T3 is connected to the second node Q.
  • the gate and source of the fourth transistor T4 are connected to the first DC high voltage VGH1, and the drain of the fourth transistor T4 is connected to the drain of the second transistor T2.
  • the gate of the fifth transistor T5 is connected to the drain of the second transistor T2, the source of the fifth transistor T5 is connected to the first DC high voltage VGH1, and the drain of the fifth transistor T5 is connected to the second node Q.
  • the maintaining module 103 is connected to the DC low voltage VGL, the first node QB and the second node Q.
  • the sustaining module 103 is used for maintaining the potential of the first node QB at the potential of the DC low voltage VGL under the control of the potential of the second node Q.
  • the sustain module 103 includes a sixth transistor T6, the gate of the sixth transistor T6 is connected to the second node Q, the source of the sixth transistor T6 is connected to the DC low voltage VGL, and the drain of the sixth transistor T6 is connected to the first node QB.
  • the first output module 104 is connected to the clock signal CK and the second node Q.
  • the first output module 104 is configured to output the transmission signal Cout(n) of the current stage under the control of the potential of the second node Q.
  • the first output module 104 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the second node Q, the source of the seventh transistor T7 is connected to the clock signal CK, and the drain of the seventh transistor T7 is connected to the current stage transmission signal Cout (n).
  • the second output module 105 is connected to the clock signal CK and the second node Q.
  • the second output module 105 is configured to output the scan signal G(n) under the control of the potential of the second node Q.
  • the second output module 105 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the second node Q, the source of the eighth transistor T8 is connected to the clock signal CK, and the drain of the eighth transistor T8 is connected to the scan signal G(n) .
  • the output control module 106 is connected to the next-stage feedback signal Cp(n+1), the first DC high voltage VGH1, the second DC high voltage VGH2, the first node QB, the first output module 104, and the second Two output module 105.
  • the output control module 106 is used for pulling up the scan signal G(n) to the potential of the first DC high voltage VGH1 under the potential control of the first node QB and the next-stage feedback signal Cp(n+1), and The transmission signal Cout(n) of this stage is pulled up to the potential of the second DC high voltage VGH2.
  • the output control module 106 includes a ninth transistor T9 and a tenth transistor T10.
  • the gate of the ninth transistor T9 is connected to the first node QB, the source of the ninth transistor T9 is connected to the second DC high voltage VGH2, and the drain of the ninth transistor T9 is connected to the current stage transmission signal Cout(n).
  • the gate of the tenth transistor T10 is connected to the first node QB, the source of the tenth transistor T10 is connected to the first DC high voltage VGH1, and the drain of the tenth transistor T10 is connected to the scan signal G(n).
  • the feedback module 107 is connected to the clock signal CK, the second node Q and the first DC high voltage VGH1.
  • the feedback module 107 is used to output the feedback signal Cp(n) of the current stage under the control of the potential of the second node Q.
  • the feedback module 107 includes an eleventh transistor T11 and a twelfth transistor T12. The gate of the eleventh transistor T11 is connected to the second node Q, the source of the eleventh transistor T11 is connected to the clock signal CK, and the drain of the eleventh transistor T11 is connected to the feedback signal Cp(n) of the current stage.
  • the gate of the twelfth transistor T12 is connected to the first node QB, the source of the twelfth transistor T12 is connected to the first DC high voltage VGH1, and the drain of the twelfth transistor T12 is connected to the feedback signal Cp(n) of the current stage.
  • the gate driving unit 20 further includes a first capacitor C1 and a thirteenth transistor T13.
  • the gate of the ninth transistor T9 and the gate of the tenth transistor T10 are connected to the next-stage feedback signal Cp(n+1) through the first capacitor C1.
  • the gate and source of the thirteenth transistor T13 are connected to the reset signal Reset, and the drain of the thirteenth transistor T13 is connected to the first node QB.
  • FIG. 3 shows a working timing diagram of the gate driving unit shown in FIG. 2.
  • the start signal STV inputs a low potential to the first node QB(1) through the first transistor T1; the second transistor T2, the third transistor T3, the ninth transistor T9, and the second transistor T1.
  • the tenth transistor T10 and the twelfth transistor T12 are turned off; the second node Q(1) is pulled to a high potential via the inverter module 102 and the first DC high voltage VGH1; the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 and the eleventh transistor T11 are turned on; the clock signal CK maintains the scanning signal G(1) and the transfer signal Cout(1) of the current stage at a high level.
  • the clock signal CK changes from a high level to a low level; the first transistor T1 is turned off; the first node QB(1) is maintained at a low level through the sixth transistor T6 and the DC low voltage VGL Potential state; the second node Q(1) is maintained at a high potential state; the clock signal CK passes through the seventh transistor T7, the eighth transistor T8, and the eleventh transistor T11 to transmit the signal Cout(1) and the scan signal G to the current stage, respectively (1) and the feedback signal Cp(1) of this level output negative pulse waveform.
  • the clock signal CK changes from a low level to a high level; the first transistor T1 is turned on; the first node QB(2) is pulled up by the previous-stage transmission signal Cout(1) High potential; the second transistor T2, the third transistor T3, the ninth transistor T9, the tenth transistor T10, and the twelfth transistor T12 are turned on; the second node Q(2) is pulled down to a low potential by the DC low voltage VGL; this level
  • the transmission signal Cout(2), the scanning signal G(2) and the feedback signal Cp(2) of this stage are pulled to a high potential by the first DC high voltage VGH1 and the second DC high voltage VGH2.
  • the first node QB(1) is coupled to a higher potential through the feedback signal Cp(2) of this stage and the first capacitor C1.
  • the stability of the current level transmission signal Cout(n) is improved. Therefore, it is ensured that the gate driving unit maintains the first node QB in a high potential state within a larger threshold voltage margin, so that the stability of the gate driving circuit is improved.
  • the present invention ensures that the gate driving unit maintains the first node QB in a high potential state within a larger threshold voltage margin, so that the stability of the gate driving circuit is improved.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种栅极驱动单元（20）包括输入模块（101）、第一和第二输出模块（104，105）、反馈模块（107）及输出控制模块（106）。输入模块（101）将前级级传信号输出至第一节点（QB）。第一输出模块（104）输出本级级传信号。第二输出模块（105）输出扫描信号。反馈模块（107）输出本级反馈信号。输出控制模块（106）将扫描信号上拉至第一直流高电压的电位且将本级级传信号上拉至第二直流高电压的电位。

Description

栅极驱动电路及包含其的显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种用于显示面板的栅极驱动电路。
 背景技术
氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)由于具有高迁移率的优点，而被广泛使用于大尺寸主动式有机发光二极体(active-matrix organic light-emitting diode，AMOLED)显示器。然而，由于氧化铟镓锌缺少稳定性，主动式有机发光二极体显示器必须使用补偿电路以保证显示器的亮度均匀性。
通常，补偿电路需要正脉冲波形及负脉冲波形。然而，现有产生负脉冲波形的栅极驱动电路仍缺乏稳定性。
 技术问题
现有产生负脉冲波形的栅极驱动电路仍缺乏稳定性。
 技术解决方案
本发明的目的在于提供一种栅极驱动电路和显示装置，以提高负脉冲电路的稳定性。
为实现上述目的，本发明提供一种栅极驱动电路，包括多个级联的栅极驱动单元，其中，所述栅极驱动单元包括:输入模块，包括第一晶体管，所述第一晶体管的栅极连接时钟信号，所述第一晶体管的源极连接前级级传信号，所述第一晶体管的漏极连接第一节点，所述输入模块用于在所述时钟信号的控制下，将所述前级级传信号输出至所述第一节点；第一输出模块，所述第一输出模块连接所述时钟信号及第二节点，用于在所述第二节点的电位控制下，输出本级级传信号；第二输出模块，所述第二输出模块连接所述时钟信号及所述第二节点，用于在所述第二节点的电位控制下，输出扫描信号；反馈模块，所述反馈模块连接所述时钟信号、所述第二节点及第一直流高电压，用于在所述第二节点的电位控制下，输出本级反馈信号；输出控制模块，所述输出控制模块连接下一级反馈信号、所述第一直流高电压、第二直流高电压、所述第一节点、所述第一输出模块及所述第二输出模块，用于在所述第一节点和所述下一级反馈信号的电位控制下，将所述扫描信号上拉至所述第一直流高电压的电位，且将所述本级级传信号上拉至所述第二直流高电压的电位；反相模块，所述反相模块连接所述第一节点、所述第二节点、直流低电压及所述第一直流高电压，用于在所述第一节点的电位控制下，控制所述第二节点的电位；以及维持模块，所述维持模块连接所述直流低电压、所述第一节点及所述第二节点，用于在所述第二节点的电位控制下，维持所述第一节点的电位在所述直流低电压的电位。
为实现上述目的，本发明还提供一种栅极驱动电路，包括多个级联的栅极驱动单元，其中，所述栅极驱动单元包括:输入模块，所述输入模块连接时钟信号、前级级传信号及第一节点，用于在所述时钟信号的控制下，将所述前级级传信号输出至所述第一节点；第一输出模块，所述第一输出模块连接所述时钟信号及第二节点，用于在所述第二节点的电位控制下，输出本级级传信号；第二输出模块，所述第二输出模块连接所述时钟信号及所述第二节点，用于在所述第二节点的电位控制下，输出扫描信号；反馈模块，所述反馈模块连接所述时钟信号、所述第二节点及第一直流高电压，用于在所述第二节点的电位控制下，输出本级反馈信号；以及输出控制模块，所述输出控制模块连接下一级反馈信号、所述第一直流高电压、第二直流高电压、所述第一节点、所述第一输出模块及所述第二输出模块，用于在所述第一节点和所述下一级反馈信号的电位控制下，将所述扫描信号上拉至所述第一直流高电压的电位，且将所述本级级传信号上拉至所述第二直流高电压的电位。
在一些实施例中，所述栅极驱动单元还包括:反相模块，所述反相模块连接所述第一节点、所述第二节点、直流低电压及所述第一直流高电压，用于在所述第一节点的电位控制下，控制所述第二节点的电位；以及维持模块，所述维持模块连接所述直流低电压、所述第一节点及所述第二节点，用于在所述第二节点的电位控制下，维持所述第一节点的电位在所述直流低电压的电位。
在一些实施例中，所述输入模块包括第一晶体管，所述第一晶体管的栅极连接所述时钟信号，所述第一晶体管的源极连接所述前级级传信号，所述第一晶体管的漏极连接所述第一节点。
在一些实施例中，所述反相模块包括：第二晶体管，所述第二晶体管的栅极连接所述第一节点，所述第二晶体管的源极连接所述直流低电压；第三晶体管，所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述直流低电压，所述第三晶体管的漏极连接所述第二节点；第四晶体管，所述第四晶体管的栅极和源极连接所述第一直流高电压，所述第四晶体管的漏极连接所述第二晶体管的漏极；以及第五晶体管，所述第五晶体管的栅极连接所述第二晶体管的漏极，所述第五晶体管的源极连接所述第一直流高电压，所述第五晶体管的漏极连接所述第二节点。
在一些实施例中，所述维持模块包括第六晶体管，所述第六晶体管的栅极连接所述第二节点，所述第六晶体管的源极连接所述直流低电压，所述第六晶体管的漏极连接所述第一节点。
在一些实施例中，所述第一输出模块包括第七晶体管，所述第七晶体管的栅极连接所述第二节点，所述第七晶体管的源极连接所述时钟信号，所述第七晶体管的漏极连接所述本级级传信号。
在一些实施例中，所述第二输出模块包括第八晶体管，所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的源极连接所述时钟信号，所述第八晶体管的漏极连接所述扫描信号。
在一些实施例中，所述输出控制模块包括：第九晶体管，所述第九晶体管的栅极连接所述第一节点，所述第九晶体管的源极连接所述第二直流高电压，所述第九晶体管的漏极连接所述本级级传信号；以及第十晶体管，所述第十晶体管的栅极连接所述第一节点，所述第十晶体管的源极连接所述第一直流高电压，所述第十晶体管的漏极连接所述扫描信号。
在一些实施例中，所述反馈模块包括：第十一晶体管，所述第十一晶体管的栅极连接所述第二节点，所述第十一晶体管的源极连接所述时钟信号，所述第十一晶体管的漏极连接本级反馈信号；以及第十二晶体管，所述第十二晶体管的栅极连接所述第一节点，所述第十二晶体管的源极连接所述第一直流高电压，所述第十二晶体管的漏极连接所述本级反馈信号。
在一些实施例中，所述栅极驱动单元还包括第一电容，所述第九晶体管的栅极及所述第十晶体管的栅极通过所述第一电容连接所述下一级反馈信号。
在一些实施例中，所述栅极驱动单元还包括第十三晶体管，所述第十三晶体管的栅极和源极连接复位信号，所述第十三晶体管的漏极连接所述第一节点。
为实现上述目的，本发明还提供一种显示装置，包括栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动单元，其中，所述栅极驱动单元包括:输入模块，所述输入模块连接时钟信号、前级级传信号及第一节点，用于在所述时钟信号的控制下，将所述前级级传信号输出至所述第一节点；第一输出模块，所述第一输出模块连接所述时钟信号及第二节点，用于在所述第二节点的电位控制下，输出本级级传信号；第二输出模块，所述第二输出模块连接所述时钟信号及所述第二节点，用于在所述第二节点的电位控制下，输出扫描信号；反馈模块，所述反馈模块连接所述时钟信号、所述第二节点及第一直流高电压，用于在所述第二节点的电位控制下，输出本级反馈信号；以及输出控制模块，所述输出控制模块连接下一级反馈信号、所述第一直流高电压、第二直流高电压、所述第一节点、所述第一输出模块及所述第二输出模块，用于在所述第一节点和所述下一级反馈信号的电位控制下，将所述扫描信号上拉至所述第一直流高电压的电位，且将所述本级级传信号上拉至所述第二直流高电压的电位。
 有益效果
本发明提供一种栅极驱动电路和显示装置，以提高负脉冲电路的稳定性。
 附图说明
为让本发明的特征以及技术内容能更明显易懂，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考用，并非用来对本发明加以限制。
图1为根据本发明实施例的显示装置的栅极驱动电路的功能框图;
图2为图1所示的栅极驱动单元的电路结构示意图;
图3为图2所示的栅极驱动单元的工作时序图。
 本发明的实施方式
为了使本发明的目的、技术手段及其效果更加清楚明确，以下将结合附图对本发明作进一步地阐述。应当理解，此处所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例，并不用于限定本发明。
请参考图1，其示出根据本发明实施例的显示装置的栅极驱动电路的功能框图。在本实施例中，所述显示装置至少包括栅极驱动电路1。栅极驱动电路1包括多个级联的栅极驱动单元20。每一级栅极驱动单元20均用于输出负脉冲波形的扫描信号G(n)及负脉冲波形的级传信号Cout(n)。当栅极驱动电路1工作时，第一级栅极驱动单元20被起始信号STV所驱动。随后，其馀栅极驱动单元20依次被前一级栅极驱动单元20的级传信号Cout(n)所驱动。
请参考图2，其示出图1所示的栅极驱动单元的电路结构示意图。栅极驱动单元20包括输入模块101、反相模块102、维持模块103、第一输出模块104、第二输出模块105、输出控制模块106及反馈模块107。在本实施例中，栅极驱动单元20为第n级栅极驱动单元，其中n为正整数。
如图2所示，输入模块101连接时钟信号CK、前级级传信号Cout(n-1)及第一节点QB。输入模块101用于在时钟信号CK的控制下，将前级级传信号Cout(n-1)输出至第一节点QB。输入模块101包括第一晶体管T1，第一晶体管T1的栅极连接时钟信号CK，第一晶体管T1的源极连接前级级传信号Cout(n-1)，第一晶体管T1的漏极连接第一节点QB。
如图2所示，反相模块102连接第一节点QB、第二节点Q、直流低电压VGL及第一直流高电压VGH1。反相模块102用于在第一节点QB的电位控制下，控制第二节点Q的电位。反相模块102包括第二晶体管T2、第三晶体管T3、第四晶体管T4及第五晶体管T5。第二晶体管T2的栅极连接第一节点QB，第二晶体管T2的源极连接直流低电压VGL。第三晶体管T3的栅极连接第一节点QB，第三晶体管T3的源极连接直流低电压VGL，第三晶体管T3的漏极连接第二节点Q。第四晶体管T4的栅极和源极连接第一直流高电压VGH1，第四晶体管T4的漏极连接第二晶体管T2的漏极。第五晶体管T5的栅极连接第二晶体管T2的漏极，第五晶体管T5的源极连接第一直流高电压VGH1，第五晶体管T5的漏极连接第二节点Q。
如图2所示，维持模块103连接直流低电压VGL、第一节点QB及第二节点Q。维持模块103用于在第二节点Q的电位控制下，维持第一节点QB的电位在直流低电压VGL的电位。维持模块103包括第六晶体管T6，第六晶体管T6的栅极连接第二节点Q，第六晶体管T6的源极连接直流低电压VGL，第六晶体管T6的漏极连接第一节点QB。
如图2所示，第一输出模块104连接时钟信号CK及第二节点Q。第一输出模块104用于在第二节点Q的电位控制下，输出本级级传信号Cout(n)。第一输出模块104包括第七晶体管T7，第七晶体管T7的栅极连接第二节点Q，第七晶体管T7的源极连接时钟信号CK，第七晶体管T7的漏极连接本级级传信号Cout(n)。
如图2所示，第二输出模块105连接时钟信号CK及第二节点Q。第二输出模块105用于在第二节点Q的电位控制下，输出扫描信号G(n)。第二输出模块105包括第八晶体管T8，第八晶体管T8的栅极连接第二节点Q，第八晶体管T8的源极连接时钟信号CK，第八晶体管T8的漏极连接扫描信号G(n)。
如图2所示，输出控制模块106连接下一级反馈信号Cp(n+1)、第一直流高电压VGH1、第二直流高电压VGH2、第一节点QB、第一输出模块104及第二输出模块105。输出控制模块106用于在第一节点QB和下一级反馈信号Cp(n+1)的电位控制下，将扫描信号G(n)上拉至第一直流高电压VGH1的电位，且将本级级传信号Cout(n)上拉至第二直流高电压VGH2的电位。输出控制模块106包括第九晶体管T9和第十晶体管T10。第九晶体管T9的栅极连接第一节点QB，第九晶体管T9的源极连接第二直流高电压VGH2，第九晶体管T9的漏极连接本级级传信号Cout(n)。第十晶体管T10的栅极连接第一节点QB，第十晶体管T10的源极连接第一直流高电压VGH1，第十晶体管T10的漏极连接扫描信号G(n)。
如图2所示，反馈模块107连接时钟信号CK、第二节点Q及第一直流高电压VGH1。反馈模块107用于在第二节点Q的电位控制下，输出本级反馈信号Cp(n)。反馈模块107包括第十一晶体管T11和第十二晶体管T12。第十一晶体管T11的栅极连接第二节点Q，第十一晶体管T11的源极连接时钟信号CK，第十一晶体管T11的漏极连接本级反馈信号Cp(n)。第十二晶体管T12的栅极连接第一节点QB，第十二晶体管T12的源极连接第一直流高电压VGH1，第十二晶体管T12的漏极连接本级反馈信号Cp(n)。
如图2所示，栅极驱动单元20还包括第一电容C1和第十三晶体管T13。第九晶体管T9的栅极及第十晶体管T10的栅极通过第一电容C1连接下一级反馈信号Cp(n+1)。第十三晶体管T13的栅极和源极连接复位信号Reset，第十三晶体管T13的漏极连接第一节点QB。
请参考图3，其示出图2所示的栅极驱动单元的工作时序图。当本级栅极驱动单元20进入阶段t1时，通过复位信号Reset对所有级栅极驱动单元20的第一节点QB输出高电位。
当本级栅极驱动单元20进入阶段t2时，起始信号STV通过第一晶体管T1对第一节点QB(1)输入低电位；第二晶体管T2、第三晶体管T3、第九晶体管T9、第十晶体管T10及第十二晶体管T12关闭；第二节点Q(1)经由反相模块102和第一直流高电压VGH1被拉到高电位；第六晶体管T6、第七晶体管T7、第八晶体管T8及第十一晶体管T11打开；时钟信号CK维持扫描信号G(1)和本级级传信号Cout(1)在高电位状态。
当本级栅极驱动单元20进入阶段t3时，时钟信号CK由高电位变为低电位；第一晶体管T1关闭；第一节点QB(1)通过第六晶体管T6和直流低电压VGL维持在低电位状态；第二节点Q(1)维持在高电位状态；时钟信号CK通过第七晶体管T7、第八晶体管T8和第十一晶体管T11分别向本级级传信号Cout(1)、扫描信号G(1)和本级反馈信号Cp(1)输出负脉冲波形。
当下一级栅极驱动单元20进入阶段t4时，时钟信号CK由低电位变为高电位；第一晶体管T1打开；第一节点QB(2)被前级级传信号Cout(1)上拉到高电位；第二晶体管T2、第三晶体管T3、第九晶体管T9、第十晶体管T10和第十二晶体管T12打开；第二节点Q(2)被直流低电压VGL下拉为低电位；本级级传信号Cout(2)、扫描信号G(2)和本级反馈信号Cp(2)被第一直流高电压VGH1和第二直流高电压VGH2拉为高电位。在此期间，第一节点QB(1)通过本级反馈信号Cp(2)和第一电容C1被耦合到更高电位。
综上所述，由于本级级传信号Cout(n)和本级反馈信号Cp(n)分离，提高了本级级传信号Cout(n)的稳定性。因此，确保栅极驱动单元在更大的阈值电压幅度(threshold voltage margin)内维持第一节点QB在高电位状态，使得栅极驱动电路的稳定性提高。
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。
 工业实用性
本发明确保栅极驱动单元在更大的阈值电压幅度(threshold voltage margin)内维持第一节点QB在高电位状态，使得栅极驱动电路的稳定性提高。

Claims (14)

  1. 一种栅极驱动电路，包括多个级联的栅极驱动单元，其中，所述栅极驱动单元包括:
    输入模块，包括第一晶体管，所述第一晶体管的栅极连接时钟信号，所述第一晶体管的源极连接前级级传信号，所述第一晶体管的漏极连接第一节点，所述输入模块用于在所述时钟信号的控制下，将所述前级级传信号输出至所述第一节点；
    第一输出模块，所述第一输出模块连接所述时钟信号及第二节点，用于在所述第二节点的电位控制下，输出本级级传信号；
    第二输出模块，所述第二输出模块连接所述时钟信号及所述第二节点，用于在所述第二节点的电位控制下，输出扫描信号；
    反馈模块，所述反馈模块连接所述时钟信号、所述第二节点及第一直流高电压，用于在所述第二节点的电位控制下，输出本级反馈信号；
    输出控制模块，所述输出控制模块连接下一级反馈信号、所述第一直流高电压、第二直流高电压、所述第一节点、所述第一输出模块及所述第二输出模块，用于在所述第一节点和所述下一级反馈信号的电位控制下，将所述扫描信号上拉至所述第一直流高电压的电位，且将所述本级级传信号上拉至所述第二直流高电压的电位；
    反相模块，所述反相模块连接所述第一节点、所述第二节点、直流低电压及所述第一直流高电压，用于在所述第一节点的电位控制下，控制所述第二节点的电位；以及
    维持模块，所述维持模块连接所述直流低电压、所述第一节点及所述第二节点，用于在所述第二节点的电位控制下，维持所述第一节点的电位在所述直流低电压的电位。
  2. 一种栅极驱动电路，包括多个级联的栅极驱动单元，其中，所述栅极驱动单元包括:
    输入模块，所述输入模块连接时钟信号、前级级传信号及第一节点，用于在所述时钟信号的控制下，将所述前级级传信号输出至所述第一节点；
    第一输出模块，所述第一输出模块连接所述时钟信号及第二节点，用于在所述第二节点的电位控制下，输出本级级传信号；
    第二输出模块，所述第二输出模块连接所述时钟信号及所述第二节点，用于在所述第二节点的电位控制下，输出扫描信号；
    反馈模块，所述反馈模块连接所述时钟信号、所述第二节点及第一直流高电压，用于在所述第二节点的电位控制下，输出本级反馈信号；以及
    输出控制模块，所述输出控制模块连接下一级反馈信号、所述第一直流高电压、第二直流高电压、所述第一节点、所述第一输出模块及所述第二输出模块，用于在所述第一节点和所述下一级反馈信号的电位控制下，将所述扫描信号上拉至所述第一直流高电压的电位，且将所述本级级传信号上拉至所述第二直流高电压的电位。
  3. 如权利要求2所述的栅极驱动电路，其中，所述栅极驱动单元还包括:
    反相模块，所述反相模块连接所述第一节点、所述第二节点、直流低电压及所述第一直流高电压，用于在所述第一节点的电位控制下，控制所述第二节点的电位；以及
    维持模块，所述维持模块连接所述直流低电压、所述第一节点及所述第二节点，用于在所述第二节点的电位控制下，维持所述第一节点的电位在所述直流低电压的电位。
  4. 如权利要求2所述的栅极驱动电路，其中，所述输入模块包括第一晶体管，所述第一晶体管的栅极连接所述时钟信号，所述第一晶体管的源极连接所述前级级传信号，所述第一晶体管的漏极连接所述第一节点。
  5. 如权利要求3所述的栅极驱动电路，其中，所述反相模块包括：
    第二晶体管，所述第二晶体管的栅极连接所述第一节点，所述第二晶体管的源极连接所述直流低电压；
    第三晶体管，所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述直流低电压，所述第三晶体管的漏极连接所述第二节点；
    第四晶体管，所述第四晶体管的栅极和源极连接所述第一直流高电压，所述第四晶体管的漏极连接所述第二晶体管的漏极；以及
    第五晶体管，所述第五晶体管的栅极连接所述第二晶体管的漏极，所述第五晶体管的源极连接所述第一直流高电压，所述第五晶体管的漏极连接所述第二节点。
  6. 如权利要求3所述的栅极驱动电路，其中，所述维持模块包括第六晶体管，所述第六晶体管的栅极连接所述第二节点，所述第六晶体管的源极连接所述直流低电压，所述第六晶体管的漏极连接所述第一节点。
  7. 如权利要求2所述的栅极驱动电路，其中，所述第一输出模块包括第七晶体管，所述第七晶体管的栅极连接所述第二节点，所述第七晶体管的源极连接所述时钟信号，所述第七晶体管的漏极连接所述本级级传信号。
  8. 如权利要求2所述的栅极驱动电路，其中，所述第二输出模块包括第八晶体管，所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的源极连接所述时钟信号，所述第八晶体管的漏极连接所述扫描信号。
  9. 如权利要求2所述的栅极驱动电路，其中，所述输出控制模块包括：
    第九晶体管，所述第九晶体管的栅极连接所述第一节点，所述第九晶体管的源极连接所述第二直流高电压，所述第九晶体管的漏极连接所述本级级传信号；以及
    第十晶体管，所述第十晶体管的栅极连接所述第一节点，所述第十晶体管的源极连接所述第一直流高电压，所述第十晶体管的漏极连接所述扫描信号。
  10. 如权利要求2所述的栅极驱动电路，其中，所述反馈模块包括：
    第十一晶体管，所述第十一晶体管的栅极连接所述第二节点，所述第十一晶体管的源极连接所述时钟信号，所述第十一晶体管的漏极连接本级反馈信号；以及
    第十二晶体管，所述第十二晶体管的栅极连接所述第一节点，所述第十二晶体管的源极连接所述第一直流高电压，所述第十二晶体管的漏极连接所述本级反馈信号。
  11. 如权利要求9所述的栅极驱动电路，其中，所述栅极驱动单元还包括第一电容，所述第九晶体管的栅极及所述第十晶体管的栅极通过所述第一电容连接所述下一级反馈信号。
  12. 如权利要求2所述的栅极驱动电路，其中，所述栅极驱动单元还包括第十三晶体管，所述第十三晶体管的栅极和源极连接复位信号，所述第十三晶体管的漏极连接所述第一节点。
  13. 一种显示装置，包括栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动单元，其中，所述栅极驱动单元包括:
    输入模块，所述输入模块连接时钟信号、前级级传信号及第一节点，用于在所述时钟信号的控制下，将所述前级级传信号输出至所述第一节点；
    第一输出模块，所述第一输出模块连接所述时钟信号及第二节点，用于在所述第二节点的电位控制下，输出本级级传信号；
    第二输出模块，所述第二输出模块连接所述时钟信号及所述第二节点，用于在所述第二节点的电位控制下，输出扫描信号；
    反馈模块，所述反馈模块连接所述时钟信号、所述第二节点及第一直流高电压，用于在所述第二节点的电位控制下，输出本级反馈信号；以及
    输出控制模块，所述输出控制模块连接下一级反馈信号、所述第一直流高电压、第二直流高电压、所述第一节点、所述第一输出模块及所述第二输出模块，用于在所述第一节点和所述下一级反馈信号的电位控制下，将所述扫描信号上拉至所述第一直流高电压的电位，且将所述本级级传信号上拉至所述第二直流高电压的电位。
  14. 如权利要求13所述的显示装置，其中，所述栅极驱动单元还包括:
    反相模块，所述反相模块连接所述第一节点、所述第二节点、直流低电压及所述第一直流高电压，用于在所述第一节点的电位控制下，控制所述第二节点的电位；以及
    维持模块，所述维持模块连接所述直流低电压、所述第一节点及所述第二节点，用于在所述第二节点的电位控制下，维持所述第一节点的电位在所述直流低电压的电位。
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