WO2021155626A1 - 阵列基板、显示面板及阵列基板的制作方法 - Google Patents

阵列基板、显示面板及阵列基板的制作方法 Download PDF

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Publication number
WO2021155626A1
WO2021155626A1 PCT/CN2020/079624 CN2020079624W WO2021155626A1 WO 2021155626 A1 WO2021155626 A1 WO 2021155626A1 CN 2020079624 W CN2020079624 W CN 2020079624W WO 2021155626 A1 WO2021155626 A1 WO 2021155626A1
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Prior art keywords
array substrate
sub
display area
lower bottom
groove
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PCT/CN2020/079624
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English (en)
French (fr)
Inventor
王东雷
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武汉华星光电技术有限公司
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Priority to US16/756,151 priority Critical patent/US11315888B2/en
Publication of WO2021155626A1 publication Critical patent/WO2021155626A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present invention relates to the field of display technology, and in particular to a manufacturing method of an array substrate, a display panel and an array substrate.
  • the display panel design requirements based on low-temperature polysilicon is a schematic diagram of the structure of an existing display panel.
  • the general condition in the industry is 2um. -3um, there are likely to be residues of subsequent film layers at the position of the trench 92, such as indium tin oxide.
  • the remaining indium tin oxide 93 shortens the separation distance from the metal of the array substrate 94, and the remaining indium tin oxide 93 is prone to electrostatic discharge with the metal of the array substrate 94 to cause explosion damage.
  • the thickness of the photoresist layer at the trenches of the flat organic layer is thicker than the normal position, and the thickness of the normal position is generally 1.5um.
  • the groove position reaches 2.8 um, which results in the inability to wash off all the photoresist during development, and the indium tin oxide at the groove position is protected by the photoresist and cannot be completely removed when the photoresist layer is patterned and etched.
  • the inclination angle (Taper angle) of the trench is about 45°-60°. If the inclination angle is reduced, the accumulation of photoresist on both sides of the bottom of the trench can be reduced, and the formation of a flat organic layer on both sides of the bottom of the trench is fundamentally reduced. The purpose of metal residue.
  • the purpose of the present invention is to provide a manufacturing method of an array substrate, a display panel and an array substrate, which solves the problem that in the exposure process, the photoresist is accumulated thick at the bottom of the retaining wall and is difficult to be effectively exposed and developed to remove the photoresist, thereby avoiding residual photoresist In this way, metal residues are formed on both sides of the bottom of the trenches in the flat organic layer, resulting in explosion damage caused by electrostatic discharge, which improves the yield of the display panel.
  • the present invention provides an array substrate including a flat layer provided with a display area and a non-display area, the flat layer is located in the non-display area with a groove surrounding the display area, so
  • the groove includes a lower bottom surface and side inclined surfaces located on both sides of the lower bottom surface; wherein the included angle (Taper angle) between the lower bottom surface and the side inclined surface is 30°-45°.
  • the included angle between the lower bottom surface and the side inclined surface is 30°-35°.
  • the present invention also provides a manufacturing method of the array substrate, including the steps:
  • a trench is formed on the flat layer located in the non-display area, and the trench is arranged around the display area.
  • the trench includes a lower bottom surface and side slopes located on both sides of the lower bottom surface. The included angle between the lower bottom surface and the side slope is 30°-45°;
  • a plurality of sub-side slopes are formed at intervals, and the plurality of sub-side slopes are connected to each other to form the side slope.
  • the length of the connection between the sub-side inclined surface and the lower bottom surface is 1.3um-1.5um.
  • the separation distance between any two adjacent sub-side slopes is 1.0um-1.4um.
  • any two adjacent sub-side slopes are arranged at equal intervals.
  • the contour of the sub-side inclined surface is one or more of a triangle, a rectangle, and a trapezoid.
  • the height of the contour of the sub-side slope is 10um-15um.
  • the contour of the sub-side slope is an isosceles trapezoid
  • the isosceles trapezoid includes an upper base, a lower base and two waists, the upper base or the lower base and the lower base Phase connection.
  • the length of the upper bottom side is 1.0um-1.2um, and the length of the bottom bottom side is 1.3um-1.4um.
  • the present invention also provides a display device including the above-mentioned array substrate.
  • the beneficial effect of the present invention is to provide a manufacturing method of an array substrate, a display panel, and an array substrate.
  • a plurality of sub-side slopes are formed at equal intervals to form the side slopes of a flat organic layer groove.
  • the side slope produced under the condition that only semi-analysis can be achieved is a smooth plane, which reduces the total amount of photoresist formed on both sides of the bottom of the groove, thereby reducing the included angle, and solving the problem of exposure
  • the photoresist is thicker at the bottom of the retaining wall, which is difficult to be effectively removed by exposure and development, resulting in photoresist residues, thereby avoiding the formation of metal residues on both sides of the bottom of the flat organic layer grooves, resulting in electrostatic discharge and explosion damage.
  • the yield rate of the display panel is difficult to be effectively removed by exposure and development, resulting in photoresist residues, thereby avoiding the formation of metal residues on both sides of the bottom of the flat organic layer grooves, resulting in electrostatic discharge
  • FIG. 1 is a schematic diagram of the structure of a conventional display panel
  • FIG. 2 is a schematic diagram of the structure of an array substrate in an embodiment of the present invention.
  • Figure 3 is a top view of the groove in Figure 2;
  • Figure 4 is a structural schematic diagram of the contour of the sub-side slope
  • FIG. 5 is a flowchart of a manufacturing method of an array substrate in an embodiment of the present invention.
  • Array substrate 101, display area, 102, non-display area,
  • an array substrate 100 which includes a flat layer 1 provided with a display area 101 and a non-display area 102, and the flat layer 1 is located in the non-display area 102.
  • Groove 2 As shown in Figures 3 and 4, the groove 2 includes a lower bottom surface 21 and side inclined surfaces 22 located on both sides of the lower bottom surface 21; wherein, the included angle between the lower bottom surface 21 and the side inclined surface 22 ⁇ is 30°-45°.
  • the side slope 22 is a smooth flat surface.
  • a plurality of sub-side slopes 221 are made at intervals, that is, a plurality of the sub-side slopes 221 are connected to each other to form the side slope. 22.
  • the contour of the sub-side inclined surface 221 is preferably trapezoidal. It can be understood that a plurality of trapezoidal sub-side inclined surfaces 221 are connected to form the side inclined surface 22. Due to the small gap, the plurality of sub-side inclined surfaces
  • the side inclined surface 22 formed by the fusion of 221 is a smooth plane, which can be observed by microscopes and other instruments.
  • the included angle between the lower bottom surface and the side slope is 30°-35°.
  • an embodiment of the present invention also provides a manufacturing method of the array substrate 100, which includes the steps:
  • a trench 2 is formed on the flat layer 1 located in the non-display area 102, the trench 2 is arranged around the display area 101, and the trench 2 includes a bottom surface 21 and a bottom
  • the side inclined surfaces 22 on both sides of the bottom surface 21, the side inclined surface 22 is a smooth flat surface, and the included angle between the lower bottom surface 21 and the side inclined surface 22 is 30°-45°;
  • a plurality of sub-side slopes 221 are made at intervals, that is, a plurality of the sub-side slopes 221 are connected to each other to form the side slope 22, and the contour of the sub-side slopes 221 is preferably a trapezoid. It is understandable that a plurality of trapezoidal sub-side slopes 221 are connected to each other to form the side slope 22. Due to the small gap, the multiple sub-side slopes 221 are integrated to form a smooth side slope 22. Plane, the smooth plane can be observed through microscopes and other instruments.
  • the limit analytical capability of the comprehensive exposure machine is 3.0um.
  • a plurality of the sub-side slopes 221 are made by blur exposure to form the smooth flat side slopes 22 to achieve the purpose of reducing the included angle ⁇ .
  • This embodiment not only ensures the smooth shape of the groove 2 but also effectively reduces the included angle ⁇ from 45° to about 30°.
  • this design can achieve a purposeful blur exposure at about 43%-46% of the limit resolution of the exposure machine, and can effectively reduce the included angle ⁇ to ensure that no photoresist remains on both sides of the bottom of the groove 2 and effectively improve
  • metal residues are formed on both sides of the bottom of the trench 2 in the flat organic layer due to the photoresist residues, resulting in explosion damage caused by electrostatic discharge, which improves the yield of the display panel.
  • the lower bottom surface 21 has a rectangular ring shape and includes a long side 211 along the extending direction of the lower bottom surface 21.
  • the display area 101 has a rectangular shape, and the lower bottom surface 21 surrounds the
  • the display area 101 is arranged in a rectangular ring shape, that is, it continuously exists around the entire array substrate 100 in the non-display area 102, and the area surrounding each side of the display area 101 on the lower bottom surface 21 can be divided Is a rectangular plane, including the bottom bottom surface 211 and the wide side 212 perpendicular to the bottom bottom surface 211; the side slope 22 is connected to the bottom bottom surface 211, and one side of the sub-side slope 221 is connected to the bottom bottom surface 211.
  • the bottom surface 211 is connected.
  • the length S connecting the sub-side inclined surface 221 and the lower bottom surface 211 is 1.3um-1.5um, preferably S is 1.3um-1.4um.
  • the distance L between any two adjacent sub-side inclined surfaces 221 is 1.0um-1.4um, preferably L is 1.3um-1.4um.
  • any two adjacent sub-side slopes 211 are arranged at equal intervals. Because the limit resolution value of the comprehensive exposure machine is 3.0um, the limit resolution value of this embodiment is 1.0-1.5um, and the preferred limit resolution value is 1.3um-1.4um, so this design is 43% of the limit resolution capacity of the exposure machine. %-46% can achieve the purposeful blur exposure.
  • a plurality of the sub-side slopes 221 are made by blur exposure to form the smooth and flat side slopes 22, that is, to ensure the groove 2
  • the smooth shape effectively reduces the angle ⁇ from 45° to about 30°.
  • By effectively reducing the included angle ⁇ it is ensured that there is no photoresist residue on both sides of the bottom of the trench 2, which effectively improves the formation of metal residues on both sides of the bottom of the flat organic layer trench 2 due to photoresist residues, resulting in electrostatic discharge.
  • the explosion phenomenon is generated, and the yield rate of the display panel is improved.
  • the contour of the sub-side inclined surface 221 is one or more of a triangle, a rectangle, and a trapezoid.
  • the height of the contour of the sub-side slope 221 is 10um-15um; that is, the width of the side slope 22 is 10um-15um.
  • the contour of the sub-side slope 221 is an isosceles trapezoid.
  • the isosceles trapezoid includes an upper base, a lower base, and two waists.
  • the bottom surface 21 is connected.
  • the length of the upper bottom side is 1.0um-1.2um, and the length of the bottom bottom side is 1.3um-1.4um.
  • the blur exposure is about 40%-50% of the design limit resolution of the exposure machine. More specifically, the limit resolution of the Nikon FX-66s exposure machine used in this embodiment is 43%-46%, and its optimal blur exposure design limit resolution value is (3um * 43%)-(3um * 46%) , That is, 1.3um-1.4um; in this embodiment, the limit resolution of the Nikon FX-68 exposure machine is 40%-50%, and its limit resolution value is 1.5um, and its fuzzy exposure design limit resolution value theory Is (1.5um * 40%)-(1.5um * 50%), that is, 0.6um-0.75um.
  • the length of the connection between the sub-side inclined surface 221 and the lower bottom surface 211 is 1.3um-1.5um, preferably 1.3um-1.4um.
  • the distance L between any two adjacent sub-side inclined surfaces 221 is 1.0um-1.4um. That is, the smooth shape of the groove 2 is ensured, and the included angle ⁇ is effectively reduced from 45° to about 30°. Therefore, this design can achieve a purposeful blur exposure at about 43%-46% of the limit resolution of the exposure machine.
  • the included angle ⁇ can be effectively reduced to ensure that no photoresist remains on both sides of the bottom of the groove 2 and effectively improve As a result, metal residues are formed on both sides of the bottom of the trench 2 in the flat organic layer due to the photoresist residue, resulting in explosion damage caused by electrostatic discharge, which improves the yield of the display panel.
  • the contour of the sub-side inclined surface 221 is one or more of a triangle, a rectangle, and a trapezoid.
  • the height of the contour of the sub-side slope 221 is 10um-15um; that is, the width of the side slope 22 is 10um-15um.
  • the contour of the sub-side slope 221 is an isosceles trapezoid.
  • the isosceles trapezoid includes an upper base, a lower base, and two waists.
  • the bottom surface 21 is connected.
  • the length of the upper bottom side is 1.0um-1.2um, and the length of the bottom bottom side is 1.3um-1.4um.
  • the present invention also provides a display device, which includes the above-mentioned array substrate 100.
  • the beneficial effect of the present invention is to provide a manufacturing method of an array substrate, a display panel, and an array substrate.
  • a plurality of sub-side slopes are formed at equal intervals to form the side slopes of a flat organic layer groove.
  • the side slope made under the condition that only semi-analysis can be achieved is a smooth flat surface, which reduces the total amount of photoresist formed on both sides of the bottom of the groove, thereby reducing the angle ⁇ , which solves the problem of
  • the photoresist is thicker at the bottom of the barrier wall, which is difficult to be effectively removed by exposure and development, resulting in photoresist residues, thereby avoiding the formation of metal residues on both sides of the bottom of the flat organic layer grooves, resulting in electrostatic discharge and explosion damage.
  • the yield rate of the display panel is 3.0um, the side slope made under the condition that only semi-analysis can be achieved is a smooth flat surface, which reduces the total amount of photoresist formed on both sides of the bottom of the groove,

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Abstract

本发明提供一种阵列基板、显示面板及阵列基板的制作方法。显示面板包括阵列基板，阵列基板包括平坦层，平坦层在位于非显示区内设有环绕显示区的沟槽，沟槽包括下底面和两个侧斜面；下底面与侧斜面之间的夹角（Taper角）为30°-45°。在制作所述沟槽时，通过间隔制作多个子侧斜面，多个子侧斜面相互连接形成侧斜面。

Description

阵列基板、显示面板及阵列基板的制作方法 技术领域
本发明涉及显示技术领域，特别是涉及一种阵列基板、显示面板及阵列基板的制作方法。
 背景技术
基于低温多晶硅的显示面板设计需求，如图1所示，为现有的一种显示面板的结构示意图，在显示面板外围均有平坦有机层91，因其膜层较厚，业内一般条件为2um-3um，在其沟槽92位置易有后续膜层的残留，例如氧化铟锡等。残留的氧化铟锡93缩短了与阵列基板94的金属的间隔距离，残留的氧化铟锡93容易与阵列基板94的金属发生静电释放产生炸伤。
经分析，在制作氧化铟锡层时的图案化过程中，发现在光阻涂布时，在平坦有机层沟槽处的光阻层厚度较正常位置厚，一般正常位置厚度为1.5um，在沟槽位置达到2.8um，导致其在显影时无法将全部光阻洗掉，进而在图案化蚀刻光阻层时在沟槽位置处的氧化铟锡有光阻保护而无法完全去除。
通过上述现象不难分析出氧化铟锡残留的真实原因，即有平坦有机层较厚，导致在其沟槽处光阻涂布时有明显的堆积，导致在沟槽处的光阻层匹配曝光及显影条件无法有效感应而完全去除。
目前，沟槽的倾斜角（Taper角）约为45°-60°，若倾斜角降低可以减少光阻在沟槽的底部两侧堆积，达到根本性降低平坦有机层沟槽的底部两侧形成金属残留的目的。
 技术问题
本发明的目的在于，提供一种阵列基板、显示面板及阵列基板的制作方法，解决了在曝光工艺中，光阻在挡墙底部堆积较厚难以有效被曝光显影去除导致光阻残留，从而避免了在平坦有机层沟槽的底部两侧形成金属残留以致出现静电释放产生炸伤现象，提高了显示面板的良率。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，包括平坦层，设有显示区和非显示区，所述平坦层在位于所述非显示区内设有环绕所述显示区的沟槽，所述沟槽包括下底面和位于所述下底面两侧的侧斜面；其中，所述下底面与所述侧斜面之间的夹角（Taper角）为30°-45°。
进一步地，所述下底面与所述侧斜面之间的夹角为30°-35°。
本发明还提供一种阵列基板的制作方法，包括步骤：
制作一平坦层，所述平坦层设有显示区和非显示区；以及
在位于所述非显示区内的所述平坦层上制作沟槽，所述沟槽环绕所述显示区设置，所述沟槽包括下底面和位于所述下底面两侧的侧斜面，所述下底面与所述侧斜面之间的夹角为30°-45°；
其中，在制作所述沟槽时，通过间隔制作多个子侧斜面，多个所述子侧斜面相互连接形成所述侧斜面。
进一步地，所述子侧斜面与所述下底面相连接的长度为1.3um-1.5um。
进一步地，任意相邻两个所述子侧斜面的间隔距离为1.0um-1.4um。
进一步地，任意相邻两个所述子侧斜面等距离间隔设置。
进一步地，所述子侧斜面的外形轮廓呈三角形、矩形、梯形中的一种或多种。
进一步地，所述子侧斜面的外形轮廓的高度为10um-15um。
进一步地，所述子侧斜面的外形轮廓为等腰梯形，所述等腰梯形包括上底边、下底边以及两个腰，所述上底边或所述下底边与所述下底面相连接。
进一步地，所述上底边的长度为1.0um-1.2um，所述下底边的长度为1.3um-1.4um。
本发明还提供一种显示装置，包括上述阵列基板。
 有益效果
本发明的有益效果在于，提供一种阵列基板、显示面板及阵列基板的制作方法，通过等距离间隔制作多个子侧斜面以形成平坦有机层沟槽的侧斜面，在综合曝光机的极限解析能力值为3.0um的情况下，实现仅能达成半解析的状况下制作的侧斜面为光滑平面，减少了在沟槽的底部两侧形成光阻的总量，进而降低夹角，解决了在曝光工艺中，光阻在挡墙底部堆积较厚难以有效被曝光显影去除导致光阻残留，从而避免了在平坦有机层沟槽的底部两侧形成金属残留以致出现静电释放产生炸伤现象，提高了显示面板的良率。
 附图说明
图1为现有的一种显示面板的结构示意图；
图2为本发明实施例中一种阵列基板的结构示意图；
图3为图2中所述沟槽的俯视图；
图4为所述子侧斜面的外形轮廓的结构示意图；
图5为本发明实施例中一种阵列基板的制作方法的流程图；
图6为L=S=2.0um时的所述沟槽的制作后状态的俯视照片；
图7为L=S=1.0um时的所述沟槽的截面图。
附图中部分标识如下：
1、平坦层，2、沟槽，21、下底面，22、侧斜面，
100、阵列基板，101、显示区，102、非显示区，
211、长边，212、宽边，221、子侧斜面。
 本发明的实施方式
以下参考说明书附图介绍本发明的优选实施例，用以举例证明本发明可以实施，这些实施例可以向本领域中的技术人员完整介绍本发明的技术内容，使得本发明的技术内容更加清楚和便于理解。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例。
如图2所示，本发明实施例中提供一种阵列基板100，包括平坦层1，设有显示区101和非显示区102，所述平坦层1在位于所述非显示区102内设有沟槽2。如图3、图4所示，所述沟槽2包括下底面21和位于所述下底面21两侧的侧斜面22；其中，所述下底面21与所述侧斜面22之间的夹角α为30°-45°。
其中，所述侧斜面22为一光滑平面，在制作所述沟槽2的侧斜面22时，通过间隔制作多个子侧斜面221，即多个所述子侧斜面221相互连接形成所述侧斜面22，所述子侧斜面221外形轮廓优选呈梯形，可以理解的是多个梯形的所述子侧斜面221相互连接构成了所述侧斜面22，由于间隙很小，多个所述子侧斜面221融为一体形成的所述侧斜面22为一光滑平面，可通过显微镜等仪器在观察到该光滑平面。
本实施例中，所述下底面与所述侧斜面之间的夹角为30°-35°。
如图5所示，本发明实施例中还提供一种阵列基板100的制作方法，包括步骤：
S1、制作一平坦层1，所述平坦层1设有显示区101和非显示区102；以及
S2、在位于所述非显示区102内的所述平坦层1上制作沟槽2，所述沟槽2环绕所述显示区101设置，所述沟槽2包括下底面21和位于所述下底面21两侧的侧斜面22，所述侧斜面22为一光滑平面，所述下底面21与所述侧斜面22之间的夹角为30°-45°；
其中，在制作所述沟槽2时，通过间隔制作多个子侧斜面221，即多个所述子侧斜面221相互连接形成所述侧斜面22，所述子侧斜面221外形轮廓优选呈梯形，可以理解的是多个梯形的所述子侧斜面221相互连接构成了所述侧斜面22，由于间隙很小，多个所述子侧斜面221融为一体形成的所述侧斜面22为一光滑平面，可通过显微镜等仪器在观察到该光滑平面。
综合曝光机的极限解析能力值为3.0um，本实施例通过模糊曝光的方式制作多个所述子侧斜面221从而形成光滑平面的所述侧斜面22，达到夹角α降低的目的。本实施例即保证了所述沟槽2的平滑形态，又有效将夹角α由45°降低至30°左右。因此该设计在曝光机极限解析能力的43%-46%左右可达到目的性的模糊曝光，可将夹角α有效降低，确保在所述沟槽2的底部两侧无光阻残留，有效改善了因光阻残留导致在平坦有机层沟槽2的底部两侧形成金属残留以致出现静电释放产生炸伤现象，提高了显示面板的良率。
本实施例中，所述下底面21呈矩形环状，包括沿所述下底面21延伸方向的长边211，可以理解的是，所述显示区101呈矩形，所述下底面21环绕所述显示区101设置则呈矩形环状，即其在所述非显示区102内环绕整个阵列基板100的四周连续存在，在所述下底面21环绕所述显示区101的每一边的区域均可划分为一矩形平面，包括所述下底面211和垂直所述下底面211的宽边212；所述侧斜面22与所述下底面211相连接，所述子侧斜面221的其中一边与所述下底面211相连接。
如图3所示，本实施例中，所述子侧斜面221与所述下底面211相连接的长度S为1.3um-1.5um，优选S为1.3um-1.4um。任意相邻两个所述子侧斜面221的间隔距离L为1.0um-1.4um，优选L为1.3um-1.4um。优选任意相邻两个所述子侧斜面211等距离间隔设置。因为综合曝光机的极限解析能力值为3.0um，本实施例的极限解析能力值为1.0-1.5um，优选极限解析能力值为1.3um-1.4um，因此该设计在曝光机极限解析能力的43%-46%左右可达到目的性的模糊曝光，本实施例通过模糊曝光的方式在制作多个所述子侧斜面221从而形成光滑平面的所述侧斜面22，即保证了所述沟槽2的平滑形态，又有效将夹角α由45°降低至30°左右。通过将夹角α有效降低，确保在所述沟槽2的底部两侧无光阻残留，有效改善了因光阻残留导致在平坦有机层沟槽2的底部两侧形成金属残留以致出现静电释放产生炸伤现象，提高了显示面板的良率。
如图4所示，所述子侧斜面221的外形轮廓呈三角形、矩形、梯形中的一种或多种。
本实施例中，所述子侧斜面221的外形轮廓的高度为10um-15um；即所述侧斜面22的宽度为10um-15um。
本实施例中，所述子侧斜面221的外形轮廓为等腰梯形，所述等腰梯形包括上底边、下底边以及两个腰，所述上底边或所述下底边与所述下底面21相连接。
本实施例中，所述上底边的长度为1.0um-1.2um，所述下底边的长度为1.3um-1.4um。
在本实施例模糊曝光的验证中，所述模糊曝光为曝光机设计极限解析度的40%-50%左右。更具体的，本实施例中使用Nikon FX-66s曝光机的极限解析度为43%-46%，其最佳模糊曝光设计极限解析能力值为（3um * 43%）-（3um * 46% ），即1.3um-1.4um；再如本实施例中使用Nikon FX-68曝光机的极限解析度为40%-50%，其极限解析能力值为1.5um，其模糊曝光设计极限解析能力值理论为（1.5um * 40%）-（1.5um * 50%），即0.6um-0.75um。
在产品上设计共计11组实验，其中任意相邻两个所述子侧斜面221的间隔距离L为1.0um，所述子侧斜面221与所述下底面211相连接的长度S为1.0um-2.0um，得到结果为：L≤1.5um且S≤1.5um时方可保证所述沟槽2的基本形态。
如图6所示，为L=S=2.0um时的所述沟槽2制作后状态的俯视照片，存在明显锯齿；其夹角α降低至20°左右。
如图7所示，为L=S=1.0um时的所述沟槽2的截面图，其夹角α基本无变化，夹角α维持在40°-60°，所述沟槽2为平滑形态且在所述侧斜面22与所述下底面211相连接位置边缘齐平。
综上可知，所述子侧斜面221与所述下底面211相连接的长度为1.3um-1.5um，优选为1.3um-1.4um。任意相邻两个所述子侧斜面221的间隔距离L为1.0um-1.4um。即保证了所述沟槽2的平滑形态，又有效将夹角α由45°降低至30°左右。因此该设计在曝光机极限解析能力的43%-46%左右可达到目的性的模糊曝光，可将夹角α有效降低，确保在所述沟槽2的底部两侧无光阻残留，有效改善了因光阻残留导致在平坦有机层沟槽2的底部两侧形成金属残留以致出现静电释放产生炸伤现象，提高了显示面板的良率。
本实施例中，所述子侧斜面221的外形轮廓呈三角形、矩形、梯形中的一种或多种。
本实施例中，所述子侧斜面221的外形轮廓的高度为10um-15um；即所述侧斜面22的宽度为10um-15um。
本实施例中，所述子侧斜面221的外形轮廓为等腰梯形，所述等腰梯形包括上底边、下底边以及两个腰，所述上底边或所述下底边与所述下底面21相连接。
本实施例中，所述上底边的长度为1.0um-1.2um，所述下底边的长度为1.3um-1.4um。
本发明还提供一种显示装置，包括上述阵列基板100。
本发明的有益效果在于，提供一种阵列基板、显示面板及阵列基板的制作方法，通过等距离间隔制作多个子侧斜面以形成平坦有机层沟槽的侧斜面，在综合曝光机的极限解析能力值为3.0um的情况下，实现仅能达成半解析的状况下制作的侧斜面为光滑平面，减少了在沟槽的底部两侧形成光阻的总量，进而降低夹角α，解决了在曝光工艺中，光阻在挡墙底部堆积较厚难以有效被曝光显影去除导致光阻残留，从而避免了在平坦有机层沟槽的底部两侧形成金属残留以致出现静电释放产生炸伤现象，提高了显示面板的良率。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，其包括：
    平坦层，设有显示区和非显示区，所述平坦层在位于所述非显示区内设有环绕所述显示区的沟槽，所述沟槽包括下底面和位于所述下底面两侧的侧斜面；
    其中，所述下底面与所述侧斜面之间的夹角为30°-45°。
  2. 根据权利要求1所述的阵列基板，其中，所述下底面与所述侧斜面之间的夹角为30°-35°。
  3. 一种阵列基板的制作方法，其中，包括步骤：
    制作一平坦层，所述平坦层设有显示区和非显示区；以及
    在位于所述非显示区内的所述平坦层上制作沟槽，所述沟槽环绕所述显示区设置，所述沟槽包括下底面和位于所述下底面两侧的侧斜面，所述下底面与所述侧斜面之间的夹角为30°-45°；
    其中，在制作所述沟槽时，通过间隔制作多个子侧斜面，多个所述子侧斜面相互连接形成所述侧斜面。
  4. 根据权利要求3所述的阵列基板的制作方法，其中，所述子侧斜面与所述下底面相连接的长度为1.3um-1.5um。
  5. 根据权利要求3所述的阵列基板的制作方法，其中，任意相邻两个所述子侧斜面的间隔距离为1.0um-1.4um。
  6. 根据权利要求3所述的阵列基板的制作方法，其中，所述子侧斜面的外形轮廓呈三角形、矩形、梯形中的一种或多种。
  7. 根据权利要求6所述的阵列基板的制作方法，其中，所述子侧斜面的外形轮廓的高度为10um-15um。
  8. 根据权利要求6所述的阵列基板的制作方法，其中，所述子侧斜面的外形轮廓为等腰梯形，所述等腰梯形包括上底边、下底边以及两个腰，所述上底边或所述下底边与所述下底面相连接。
  9. 根据权利要求8所述的阵列基板的制作方法，其中，所述上底边的长度为1.0um-1.2um，所述下底边的长度为1.3um-1.4um。
  10. 一种显示装置，其包括权利要求1所述的阵列基板。
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