WO2021142874A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2021142874A1
WO2021142874A1 PCT/CN2020/075679 CN2020075679W WO2021142874A1 WO 2021142874 A1 WO2021142874 A1 WO 2021142874A1 CN 2020075679 W CN2020075679 W CN 2020075679W WO 2021142874 A1 WO2021142874 A1 WO 2021142874A1
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metal layer
layer
patterned
metal
etching
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PCT/CN2020/075679
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English (en)
French (fr)
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陈梦
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Tcl华星光电技术有限公司
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Priority to US16/757,389 priority Critical patent/US11552106B2/en
Publication of WO2021142874A1 publication Critical patent/WO2021142874A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof.
  • copper material as a metal wire has a tendency to replace traditional aluminum materials due to its low impedance and strong resistance to electromigration.
  • adhesion between copper metal and glass is poor, metal peeling easily occurs, and copper metal is easily diffused.
  • Thin film transistors (Thin Film Transistor, TFT) device performance has deteriorated.
  • a metal layer is usually added to improve the adhesion of the copper metal layer and prevent copper diffusion.
  • the added metal layer is usually selected from molybdenum/titanium/molybdenum titanium alloy.
  • molybdenum metal As the bimetal layer, because the copper/molybdenum structure is prone to bimetal corrosion during the metal patterning process, the copper metal will be corroded during the subsequent photoresist stripping process, resulting in copper hollowing. The occurrence of copper hollowing will form a metal tip. In the subsequent manufacturing process, different layers of metals are prone to electrostatic breakdown, which greatly affects the product yield.
  • the use of molybdenum-titanium alloy as an added metal layer can significantly improve the corrosion of copper metal.
  • a fluorine-containing wet etching solution must be used for etching in the patterning process of the metal. The rate is low, and the problem of molybdenum and titanium metal residues is prone to occur.
  • the purpose of the present application is to provide an array substrate and a manufacturing method thereof to improve the adhesion of copper on the array substrate and prevent the diffusion of copper, while avoiding copper corrosion and metal residue problems caused by adding a metal layer.
  • the present application provides an array substrate, the array substrate includes a substrate and a patterned metal member, the patterned metal member includes a patterned first metal layer and a patterned metal layer which are sequentially stacked on the substrate.
  • the adhesion force between the patterned first metal layer and the substrate is greater than the adhesion force between the patterned copper layer and the substrate, and the patterned metal members are sequentially stacked on the substrate after etching with an etchant.
  • the first metal layer, the second metal layer and the copper layer are obtained from the upper metal layer, the etching rate of the etching solution for etching the second metal layer is lower than the etching rate of the etching solution for etching the first metal layer, and the first
  • the preparation material of the metal layer includes molybdenum, and the preparation material of the second metal layer includes at least one of titanium and vanadium.
  • the first metal layer is a molybdenum layer
  • the second metal layer is a molybdenum-titanium alloy layer.
  • the sum of the thickness of the first metal layer and the second metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.
  • the patterned metal member includes source and drain electrodes and data lines, and/or, the patterned metal member includes a gate electrode and a scan line.
  • a manufacturing method of an array substrate includes the following steps:
  • a photoresist layer is formed on the surface of the copper layer. After the photoresist layer is exposed to a photomask and developed by a developer, the remaining part of the photoresist layer covering the copper layer is a reserved area, and the developer removes the light. The area of the resist layer is the etching area;
  • the etching rate of the etching solution for etching the first metal layer is greater than the etching rate of the etching solution for etching the second metal layer, and the adhesion between the first metal layer and the substrate is greater than that of the copper layer Adhesion to the substrate.
  • the preparation material of the first metal layer includes molybdenum
  • the preparation material of the second metal layer includes at least one of titanium and vanadium.
  • the first metal layer is a molybdenum layer
  • the second metal layer is a molybdenum-titanium alloy layer.
  • the sum of the thickness of the first metal layer and the second metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers, and the content of fluorine ions in the etching solution is greater than 0wt% And less than 0.1wt%.
  • the sum of the thickness of the first metal layer and the second metal layer is greater than or equal to 10 nanometers and less than or equal to 50 nanometers, and the content of fluoride ions in the etching solution is greater than 0 wt% And less than 0.01wt%.
  • the value range of the thickness of the first metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers
  • the value range of the thickness of the second metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.
  • the patterned metal member includes source and drain electrodes and data lines, and/or, the patterned metal member includes gates and scan lines.
  • An array substrate the array substrate includes a substrate and a patterned metal member, the patterned metal member includes a patterned first metal layer, a patterned second metal layer, and a patterned copper layer that are sequentially stacked on the substrate Floor,
  • the adhesion force between the patterned first metal layer and the substrate is greater than the adhesion force between the patterned copper layer and the substrate, and the patterned metal members are sequentially stacked on the substrate after etching with an etchant.
  • the first metal layer, the second metal layer, and the copper layer on the upper surface are obtained, and the etching rate of the etching solution for etching the second metal layer is lower than the etching rate of the etching solution for etching the first metal layer.
  • the first metal layer is a molybdenum layer
  • the second metal layer is a molybdenum-titanium alloy layer.
  • the sum of the thickness of the first metal layer and the second metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.
  • the patterned metal member includes source and drain electrodes and data lines, and/or, the patterned metal member includes a gate electrode and a scan line.
  • the present application provides an array substrate and a manufacturing method thereof.
  • the patterned metal member of the array substrate includes a patterned first metal layer, a patterned second metal layer, and a patterned copper layer that are sequentially stacked on the substrate.
  • the etching solution etches the second metal layer.
  • the rate of the second metal layer is lower than the rate of the etching solution to etch the first metal layer.
  • the structure of patterning the second metal layer and patterning the first metal layer can avoid the problem of metal residue in the second metal layer and avoid patterning.
  • the second metal layer is corroded to cause the copper hollowing problem, and the adhesion of the patterned first metal layer to the substrate is greater than the adhesion of the patterned copper layer to the substrate, which improves the adhesion of the patterned metal component on the substrate and can Block the diffusion of copper.
  • FIG. 1 is a schematic diagram of the structure of an array substrate according to an embodiment of the application.
  • FIG. 2 is a schematic diagram of the structure of source and drain electrodes in the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a process of manufacturing an array substrate according to an embodiment of the present application.
  • 4A-4E are schematic diagrams of the process of manufacturing the array substrate according to the process shown in FIG. 3.
  • FIG. 1 is a schematic diagram of the structure of an array substrate according to an embodiment of the application
  • FIG. 2 is a schematic diagram of the structure of source and drain electrodes in the array substrate shown in FIG.
  • the array substrate 100 is a thin film transistor array substrate, and the array substrate 100 can be used in a liquid crystal display panel, and can also be used in an organic light emitting diode display panel.
  • the array substrate 100 includes a substrate 10, a plurality of thin film transistors 11, data lines (not shown), scan lines (not shown), etc., arranged on the substrate 10 and arranged in an array.
  • the thin film transistor may be a bottom gate type thin film transistor or a top gate type thin film transistor.
  • the thin film transistor is a top-gate thin film transistor.
  • the thin film transistor includes an active layer 111, a gate 112, source and drain electrodes 113, a gate insulating layer 114, and an interlayer insulating layer 115.
  • the gate insulating layer 114 is formed between the gate 112 and the active layer 111, and the interlayer insulating
  • the layer 115 is formed between the source and drain electrodes 113 and the gate 112.
  • the source and drain electrodes 113 include a source electrode 1131 and a drain electrode 1132. Both the source electrode 1131 and the drain electrode 1132 pass through the interlayer insulating layer 115 and the gate insulating layer 114.
  • the via hole is in contact with the active layer 111.
  • the patterned metal member includes source and drain electrodes 113, data lines, and other metal wires in the same layer.
  • the patterned metal member is obtained by sequentially stacking the first metal layer, the second metal layer, and the copper layer on the substrate 10 by etching with an etching solution.
  • the adhesion force between the patterned first metal layer and the substrate 10 is greater than the adhesion force between the patterned copper layer and the substrate 10, which improves the adhesion of the patterned metal member on the substrate 10 while preventing the copper in the copper layer from diffusing to In the active layer 111, to prevent copper diffusion from affecting the electrical performance of the thin film transistor, the etching rate of the etching solution for the second metal layer is lower than the etching rate for the etching solution to etch the first metal layer, so that the second metal layer needs to be completely etched before the second metal layer can be etched.
  • a metal layer prevents the second metal layer from remaining, and the patterned second metal layer will not corrode, and also avoids the patterned second metal layer from corroding and causing the patterned copper layer to be hollowed out.
  • the patterned metal member will be described below in conjunction with source and drain electrodes.
  • the patterned metal member includes a patterned first metal layer 11311, a patterned second metal layer 1312, and a patterned copper layer 11313 which are sequentially stacked and disposed on the substrate 10.
  • the patterned first metal layer 11311 is used to improve the adhesion of the patterned metal member on the substrate and block the diffusion of copper, and also to avoid the problem of residual etching of the second metal layer.
  • the preparation material of the first metal layer includes molybdenum. It may be molybdenum; it may also be a binary alloy including molybdenum, such as molybdenum-niobium alloy, molybdenum-tantalum alloy, and molybdenum-tungsten alloy; it may also be a ternary alloy including molybdenum, such as molybdenum-niobium-tungsten alloy.
  • the range of the thickness of the patterned first metal layer 11311 is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.
  • the thickness of the patterned first metal layer 11311 is too thin, which on the one hand will lead to poor diffusion barrier to copper On the other hand, the patterned metal member is easily peeled off; too thick the patterned first metal layer 11311 will increase the difficulty of etching and reduce the mass production of the array substrate 100.
  • the thickness of the patterned first metal layer 11311 is 5 nanometers, 10 nanometers, and 50 nanometers.
  • the patterned second metal layer 11312 is used to improve the problem of copper corrosion in the process of forming the patterned copper layer. Since the etching liquid etches the second metal layer at a slower rate than the first metal layer, the patterning of the second metal layer is even worse. Corrosion is prone to occur, and the prerequisite for forming the copper hollow is that the patterned second metal layer is corroded, so the patterned second metal layer 11312 can avoid the copper hollow problem in the patterned copper layer. In addition, because during etching, the first metal layer needs to be etched completely after the second metal layer is etched, the second metal layer to be removed will not be left, and the rate of etching the first metal layer is fast, and the first metal layer to be removed There will be no residue.
  • the range of the thickness of the patterned second metal layer 11312 is greater than 5 nanometers and less than 100 nanometers.
  • the thickness of the patterned second metal layer 11312 is 10 nanometers, 30 nanometers, or 50 nanometers.
  • the preparation material of the second metal layer includes at least one of titanium and vanadium.
  • the adhesion of the patterned metal member on the substrate can be improved, and metal residues and copper can be avoided.
  • the first metal layer is a molybdenum layer
  • the second metal layer is a molybdenum-titanium alloy layer, so as to improve the adhesion of the patterned metal member on the substrate while avoiding the diffusion of copper into the active layer and avoiding patterning
  • Metal residues and copper hollowing problems occur in the process of metalizing components, which reduces the risk of electrostatic breakdown.
  • the sum of the thickness of the first metal layer and the second metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers, for example, the sum of the thicknesses of the first metal layer and the second metal layer is 8 nanometers, 10 nanometers, 20 nanometers. Nanometer or 50 nanometers, the sum of the thickness of the first metal layer and the second metal layer is less than or equal to the thickness of the traditional single-layer molybdenum layer or molybdenum-titanium alloy layer, so that the thickness of the molybdenum-titanium alloy is reduced, and the fluoride ions in the etching solution can be reduced.
  • the content of fluoride ion is reduced, and the content of fluoride ion in the etching solution is greater than 0wt% and less than 0.1wt% to avoid corrosion of the substrate (generally glass) caused by the fluorine-containing etching solution, and to avoid the problem that the substrate cannot be reworked.
  • the ratio of the number of molybdenum atoms to the number of titanium atoms in the molybdenum-titanium alloy layer is 1:1, and this ratio can also be adjusted as required.
  • the sum of the thickness of the first metal layer and the second metal layer is greater than or equal to 10 nanometers and less than or equal to 50 nanometers, and the content of fluoride ions in the etching solution is greater than 0wt% and less than 0.01wt%, so as to further realize the first
  • the patterning of the metal layer, the second metal layer, and the copper layer can further prevent the fluorine-containing etching solution from corroding the substrate 10, especially when the thin film transistor is a bottom-gate thin film transistor and the gate is directly formed on the glass.
  • the patterned metal member includes source and drain electrodes and data lines. In other embodiments, the patterned metal member may also include gates and scan lines.
  • FIG. 3 is a schematic diagram of a process of manufacturing an array substrate according to an embodiment of the present application.
  • the manufacturing method of the array substrate includes the following steps:
  • the substrate 10 is provided with an active layer 111, a gate insulating layer 114 covering the active layer 111 and the substrate 10, and a gate insulating layer 114 formed on the gate insulating layer 114 and correspondingly disposed directly above the active layer 111.
  • the electrode 112, the interlayer insulating layer 115 covering the gate 112 and the gate insulating layer 114, the interlayer insulating layer 115 and the gate insulating layer 114 have communicating via holes to expose a part of the active layer 111.
  • the first metal layer is formed by sputtering deposition on the surface of the interlayer insulating layer 115 and its via holes.
  • the adhesion of the first metal layer to the substrate 10 is greater than the adhesion of the copper layer to the substrate 10 to improve the adhesion of the patterned metal member to be formed on the substrate 10.
  • the preparation material of the first metal layer includes molybdenum.
  • the value range of the thickness of the first metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.
  • a sputtering deposition process is used to form the entire second metal layer on the surface of the first metal layer away from the substrate.
  • the preparation material of the second metal layer includes at least one of titanium and vanadium.
  • the value range of the thickness of the second metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers.
  • a sputtering deposition process is used to form an entire copper layer on the surface of the second metal layer away from the first metal layer.
  • the copper layer makes the patterned metal member to be produced have good conductivity.
  • a photoresist layer 116 is formed on the surface of the copper layer. After the photoresist layer 116 is exposed to the photomask and developed by the developer, the area where the remaining part of the photoresist layer 116 covers the copper layer is a reserved area, and the area where the developer removes the photoresist layer is Etched area, as shown in Figure 4D.
  • S105 Etching the copper layer, the second metal layer, and the first metal layer in the etching area with an etching solution, and removing the remaining photoresist layer to obtain a patterned metal component of the array substrate.
  • the etching solution is etching acid.
  • the etching solution includes hydrogen peroxide, copper ion chelating agent, fluoride ion and water.
  • the etching acid is sprayed onto the copper layer to gradually etch the copper layer, the second metal layer and the first metal layer to form a patterned metal member.
  • the patterned metal member includes source and drain electrodes (1131, 1132) and data lines (not shown) ), as shown in Figure 4E.
  • the etching rate of the etching solution to etch the first metal layer is greater than the etching rate of the etching solution to etch the second metal layer, so that the first metal layer can be completely etched away without residue, and the second metal layer needs to be completely etched before the second metal layer can be etched.
  • the first metal layer is a molybdenum layer
  • the second metal layer is a molybdenum-titanium alloy layer. Since the etching ability of the etching solution for molybdenum metal is stronger than that of molybdenum-titanium metal, the possibility of molybdenum-titanium residues is reduced; because the molybdenum-titanium metal layer is in direct contact with the copper metal layer, and the copper/molybdenum-titanium bimetallic corrosion potential difference is small, No copper corrosion will occur.
  • the sum of the thickness of the first metal layer and the second metal layer is greater than or equal to 5 nanometers and less than or equal to 100 nanometers, so that the thickness of the first metal layer and the second metal layer is the same as that of a conventional single layer of molybdenum and titanium.
  • the thickness of the alloy layer is the same.
  • the thickness of the molybdenum-titanium alloy layer is smaller than that of the traditional molybdenum-titanium alloy, which can reduce the content of fluoride ions in the etching solution.
  • the content of fluoride ions in the etching solution is greater than 0wt% and less than 0.1wt%.
  • the content of fluoride ions in the etching solution is greater than 0wt% and less than 0.01wt%, for example, the content of fluoride ions in the etching solution is 0.005wt%, so as to avoid the problem of substrate corrosion caused by excessive fluoride ion content.
  • the patterned metal member includes source and drain electrodes (1131, 1132) and data lines (not shown).
  • the patterned metal member may also include a gate electrode and a scan line.
  • the preparation method of the gate electrode and the scan line is the same as the preparation method of the source and drain electrodes and the data line, which will not be described in detail here.
  • the manufacturing method of the array substrate of this embodiment is to sequentially form the first metal layer, the second metal layer, and the copper layer that are stacked.
  • the rate of etching the second metal layer by the etchant is lower than the rate at which the first metal layer is etched by the etchant to pattern the first metal layer.
  • the structure of the second metal layer and the patterned first metal layer can avoid the problem of metal residues in the second metal layer, and at the same time avoid the corrosion of the patterned second metal layer and lead to copper hollowing, and reduce the risk of electrostatic breakdown
  • the adhesion between the first metal layer and the substrate is greater than the adhesion between the copper layer and the substrate, which improves the adhesion of the patterned metal member on the substrate and can block the diffusion of copper.

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Abstract

一种阵列基板（100）及其制造方法，阵列基板（100）的图案化金属构件包括依次层叠设置于基板（10）上的图案化第一金属层（11311）、图案化第二金属层（11312）以及图案化铜层（11313），蚀刻液蚀刻第二金属层（11312）的速率小于蚀刻液蚀刻第一金属层（11311）的速率，且图案化第一金属层（11311）与基板（10）的附着力大于图案化铜层（11313）与基板（10）的附着力，从而避免第二金属层（11312）残留，也避免第二金属层（11312）腐蚀导致的图案化铜层（11313）出现掏空现象。

Description

阵列基板及其制造方法 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法。
 背景技术
在高世代液晶面板中，铜材料作为金属线因其阻抗低、抗电迁移能力强等优点使得代替传统的铝材料称为趋势。但铜金属与玻璃附着性差，易发生金属剥离，且铜金属易发生扩散，薄膜晶体管（Thin Film Transistor，TFT）器件性能产生恶化。通常会增加一层金属层来改善铜金属层的附着性及阻挡铜扩散，传统显示面板的制造工艺中，通常使用增加的金属层选择有钼/钛/钼钛合金等。在使用钼金属作为双金属层的工艺中，因铜/钼结构在金属图案化过程中易发生双金属腐蚀，在后续光阻剥离过程中会发生铜金属的腐蚀，形成铜掏空的现象，铜掏空的发生会形成金属尖端，在后续制造工艺中不同层别的金属易发生静电击穿现象，对产品良率造成极大影响。使用钼钛合金作为增加的金属层能明显改善铜金属腐蚀的现象，但由于钼钛合金中钛金属的存在，在金属的图案化制程中必须使用含氟元素的湿蚀刻液进行蚀刻，且蚀刻速率较低，易发生钼钛金属残留的问题。
因此，有必要提出一种技术方案提升铜层的附着性以及阻挡铜扩散的同时，避免增加一层金属层导致的铜腐蚀以及金属残留问题。
 技术问题
本申请的目的在于提供一种阵列基板及其制造方法，以提高阵列基板上的铜的附着性并阻挡铜扩散的同时，避免增加一层金属层导致的铜腐蚀以及金属残留问题。
 技术解决方案
为实现上述目的，本申请提供一种阵列基板，所述阵列基板包括基板以及图案化金属构件，所述图案化金属构件包括依次层叠设置于所述基板上的图案化第一金属层、图案化第二金属层以及图案化铜层，
其中，所述图案化第一金属层与所述基板的附着力大于所述图案化铜层与所述基板的附着力，所述图案化金属构件是经过蚀刻液蚀刻依次层叠设置于所述基板上的第一金属层、第二金属层以及铜层得到，所述蚀刻液蚀刻所述第二金属层的蚀刻速率小于所述蚀刻液蚀刻所述第一金属层的蚀刻速率，所述第一金属层的制备材料包括钼，所述第二金属层的制备材料包括钛以及钒中的至少一种。
在上述阵列基板中，所述第一金属层为钼层，所述第二金属层为钼钛合金层。
在上述阵列基板中，所述第一金属层和所述第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米。
在上述阵列基板中，所述图案化金属构件包括源漏电极以及数据线，和/或，所述图案化金属构件包括栅极以及扫描线。
一种阵列基板的制造方法，所述制造方法包括如下步骤：
于基板上形成整面的第一金属层；
于所述第一金属层远离所述基板的表面上形成整面的第二金属层；
于所述第二金属层远离所述第一金属层的表面上形成整面的铜层；
于所述铜层表面形成光阻层，所述光阻层经光罩曝光以及显影液显影后，剩余部分所述光阻层覆盖所述铜层的区域为保留区，显影液去除所述光阻层的区域为蚀刻区；
采用蚀刻液蚀刻所述蚀刻区的铜层、第二金属层以及第一金属层，去除剩余所述光阻层，得所述阵列基板的图案化金属构件；
其中，所述蚀刻液蚀刻所述第一金属层的蚀刻速率大于所述蚀刻液蚀刻所述第二金属层的蚀刻速率，所述第一金属层与所述基板的附着力大于所述铜层与所述基板的附着力。
在上述阵列基板的制造方法中，所述第一金属层的制备材料包括钼，所述第二金属层的制备材料包括钛以及钒中的至少一种。
在上述阵列基板的制造方法中，所述第一金属层为钼层，所述第二金属层为钼钛合金层。
在上述阵列基板的制造方法中，所述第一金属层和所述第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米，所述蚀刻液中氟离子的含量大于0wt%且小于0.1wt%。
在上述阵列基板的制造方法中，所述第一金属层和所述第二金属层的厚度之和大于或等于10纳米且小于或等于50纳米，所述蚀刻液中氟离子的含量大于0wt%且小于0.01wt%。
在上述阵列基板的制造方法中，所述第一金属层的厚度的取值范围为大于或等于5纳米且小于或等于100纳米，所述第二金属层的厚度的取值范围为大于或等于5纳米且小于或等于100纳米。
在上述阵列基板的制造方法中，所述图案化金属构件包括源漏电极以及数据线，和/或，所述图案化金属构件包括栅极以及扫描线。
一种阵列基板，所述阵列基板包括基板以及图案化金属构件，所述图案化金属构件包括依次层叠设置于所述基板上的图案化第一金属层、图案化第二金属层以及图案化铜层，
其中，所述图案化第一金属层与所述基板的附着力大于所述图案化铜层与所述基板的附着力，所述图案化金属构件是经过蚀刻液蚀刻依次层叠设置于所述基板上的第一金属层、第二金属层以及铜层得到，所述蚀刻液蚀刻所述第二金属层的蚀刻速率小于所述蚀刻液蚀刻所述第一金属层的蚀刻速率。
在上述阵列基板中，所述第一金属层为钼层，所述第二金属层为钼钛合金层。
在上述阵列基板中，所述第一金属层和所述第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米。
在上述阵列基板中，所述图案化金属构件包括源漏电极以及数据线，和/或，所述图案化金属构件包括栅极以及扫描线。
 有益效果
本申请提供一种阵列基板及其制造方法，阵列基板的图案化金属构件包括依次层叠设置于基板上的图案化第一金属层、图案化第二金属层以及图案化铜层，蚀刻液蚀刻第二金属层的速率小于蚀刻液蚀刻第一金属层的速率，图案化第二金属层和图案化第一金属层的结构，可以避免第二金属层出现金属残留的问题的同时，可以避免图案化第二金属层被腐蚀而导致铜掏空问题，且图案化第一金属层与基板的附着力大于图案化铜层与基板的附着力，提高图案化金属构件在基板上的附着力，且能阻挡铜扩散。
 附图说明
图1为本申请实施例阵列基板的结构示意图；
图2为图1所示阵列基板中源漏电极的结构示意图；
图3为制造本申请实施例阵列基板的流程示意图；
图4A-4E为按图3所示流程制造阵列基板的过程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1以及图2，图1为本申请实施例阵列基板的结构示意图，图2为图1所示阵列基板中源漏电极的结构示意图。阵列基板100为薄膜晶体管阵列基板，阵列基板100可以用于液晶显示面板，也可以应用于有机发光二极管显示面板。阵列基板100包括基板10以及设置于基板10上多个阵列排布的薄膜晶体管11、数据线（未示出）以及扫描线（未示出）等。
薄膜晶体管可以为底栅型薄膜晶体管或顶栅型薄膜晶体管。在本实施例中，薄膜晶体管为顶栅型薄膜晶体管。薄膜晶体管包括有源层111、栅极112、源漏电极113、栅极绝缘层114以及层间绝缘层115，栅极绝缘层114形成于栅极112以及有源层111之间，层间绝缘层115形成于源漏电极113和栅极112之间，源漏电极113包括源电极1131以及漏电极1132，源电极1131和漏电极1132均通过层间绝缘层115和栅极绝缘层114上的过孔与有源层111接触。
在本实施例中，图案化金属构件包括同层设置的源漏电极113、数据线以及其他金属导线等。图案化金属构件是通过蚀刻液蚀刻依次层叠设置于基板10上的第一金属层、第二金属层以及铜层得到。其中，图案化第一金属层与基板10的附着力大于图案化铜层与基板10的附着力，提高图案化金属构件在基板10上的附着力的同时，能避免铜层中的铜扩散至有源层111中，避免铜扩散影响薄膜晶体管的电性能，蚀刻液蚀刻第二金属层的速率小于蚀刻液蚀刻第一金属层的蚀刻速率，以使得需要完全蚀刻掉第二金属层才能蚀刻第一金属层，避免第二金属层残留，且图案化第二金属层不会出现腐蚀，也避免图案化第二金属层腐蚀导致图案化铜层出现掏空问题。
以下结合源漏电极对图案化金属构件进行描述。图案化金属构件包括依次层叠设置于基板10上的图案化第一金属层11311、图案化第二金属层1312以及图案化铜层11313。
图案化第一金属层11311用于提高图案化金属构件在基板上的附着力以及阻挡铜扩散的同时，还用于避免第二金属层蚀刻出现残留的问题。第一金属层的制备材料包括钼。可以为钼；也可以为包括钼的二元合金，例如，钼铌合金、钼钽合金以及钼钨合金等；也可以为包括钼的三元合金，例如，钼铌钨合金等。
图案化第一金属层11311的厚度的取值范围为大于或等于5纳米且小于或等于100纳米，图案化第一金属层11311的厚度太薄，一方面会导致对铜的扩散性阻挡较差，另一方面会导致图案化金属构件易剥离；图案化第一金属层11311太厚会增加蚀刻难度，降低阵列基板100的可量产性。图案化第一金属层11311的厚度为5纳米、10纳米以及50纳米。
图案化第二金属层11312用于改善形成图案化铜层过程中的铜腐蚀问题，由于蚀刻液蚀刻第二金属层的速率较蚀刻第一金属层的速率慢，图案化第二金属层更不容易出现腐蚀，而形成铜掏空的前提条件是要图案化第二金属层被腐蚀，故图案化第二金属层11312可以避免图案化铜层出现铜掏空问题。另外，由于蚀刻时，需要第二金属层蚀刻完全后才能蚀刻第一金属层，待去除的第二金属层不会出现残留，而蚀刻第一金属层的速率快，待去除的第一金属层也不会出现残留。图案化第二金属层11312的厚度的取值范围为大于5纳米且小于100纳米。例如图案化第二金属层11312的厚度为10纳米、30纳米或50纳米。第二金属层的制备材料包括钛以及钒中的至少一种。
因此，第一金属层、第二金属层以及铜层的叠层结构以蚀刻得到图案化金属构件时，可以提高图案化金属构件在基板上的附着力的同时，避免出现金属残留，避免出现铜掏空的问题，且提高阻挡铜的扩散性的能力，避免铜扩散至有源层而影响薄膜晶体管的电性能。
具体地，第一金属层为钼层，第二金属层为钼钛合金层，以提高图案化金属构件在基板上的附着力的同时，避免铜扩散至有源层中，且能避免形成图案化金属构件的过程中出现金属残留以及铜掏空的问题，降低静电击穿的风险。
进一步地，第一金属层和第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米，例如第一金属层和第二金属层的厚度之和为8纳米、10纳米、20纳米或者50纳米，第一金属层和第二金属层的厚度之和小于或等于传统单层钼层或钼钛合金层的厚度，使得钼钛合金的厚度减小，可以使得蚀刻液中氟离子的含量减少，蚀刻液中氟离子的含量大于0wt%且小于0.1wt%，以避免含氟蚀刻液对基板（一般为玻璃）造成腐蚀，避免基板出现无法重工的问题。其中，钼钛合金层中，钼原子与钛原子的数目之比为1：1，此比例也可以根据需要调整。
进一步地，第一金属层和第二金属层的厚度之和大于或等于10纳米且小于或等于50纳米，蚀刻液中氟离子的含量大于0wt%且小于0.01wt%，以进一步地实现第一金属层、第二金属层以及铜层的图案化的同时，进一步地避免含氟蚀刻液对基板10造成腐蚀，特别是薄膜晶体管为底栅型薄膜晶体管且栅极直接形成于玻璃上时。
在本实施例中，图案化金属构件包括源漏电极以及数据线。在其他实施例中，图案化金属构件也可以包括栅极以及扫描线。
请参阅图3，其为制造本申请实施例阵列基板的流程示意图。阵列基板的制造方法包括如下步骤：
S101：于基板上形成整面的第一金属层。
如图4A所示，基板10设置有有源层111、覆盖有源层111和基板10的栅极绝缘层114、形成于栅极绝缘层114上且对应设置于有源层111正上方的栅极112、覆盖栅极112以及栅极绝缘层114的层间绝缘层115，层间绝缘层115和栅极绝缘层114有连通的过孔以使部分有源层111显露。采用溅射沉积于层间绝缘层115的表面及其过孔中形成第一金属层。第一金属层与基板10的附着力大于铜层与基板10的附着力，以提高待形成的图案化金属构件在基板10上的附着力。第一金属层的制备材料包括钼。第一金属层的厚度的取值范围为大于或等于5纳米且小于或等于100纳米。
S102: 于第一金属层远离基板的表面上形成整面的第二金属层。
如图4B所示，采用溅射沉积工艺于第一金属层远离基板的表面上形成整面的第二金属层。第二金属层的制备材料包括钛以及钒中的至少一种。第二金属层的厚度的取值范围为大于或等于5纳米且小于或等于100纳米。
S103：于第二金属层远离第一金属层的表面上形成整面的铜层。
如图4C所示，采用溅射沉积工艺于第二金属层远离第一金属层的表面上形成整面的铜层。铜层使得待制得的图案化金属构件具有良好的导电性。
S104: 于铜层表面形成光阻层116，光阻层116经光罩曝光以及显影液显影后，剩余部分光阻层116覆盖铜层的区域为保留区，显影液去除光阻层的区域为蚀刻区，如图4D所示。
S105:采用蚀刻液蚀刻蚀刻区的铜层、第二金属层以及第一金属层，去除剩余光阻层，得阵列基板的图案化金属构件。
此阶段为湿法蚀刻，蚀刻液为蚀刻酸。蚀刻液包括过氧化氢、铜离子螯合剂、氟离子以及水。蚀刻酸喷射至铜层上，以逐渐蚀刻铜层、第二金属层以及第一金属层，形成图案化金属构件，图案化金属构件包括源漏电极（1131，1132）以及数据线（未示出），如图4E所示。蚀刻液蚀刻第一金属层的蚀刻速率大于蚀刻液蚀刻第二金属层的蚀刻速率，使得第一金属层可以完全蚀刻掉，不会出现残留，且需要完全蚀刻掉第二金属层，才能蚀刻第一金属层，使得第二金属层也不会出现蚀刻残留，由于第二金属层在蚀刻过程中更不容易出现腐蚀，而形成铜掏空的前提条件时图案化第二金属层被腐蚀，故图案化第二金属层可以避免图案化铜层出现铜掏空问题。
在本实施例中，第一金属层为钼层，第二金属层为钼钛合金层。由于蚀刻液对钼金属的蚀刻能力强于钼钛金属，发生钼钛残留的可能性降低；由于与铜金属层直接接触的是钼钛金属层，而铜/钼钛双金属腐蚀电位差异小，不会发生铜腐蚀的现象。
在本实施例中，第一金属层和第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米，使得第一金属层和第二金属层的厚度与传统的单层钼钛合金层的厚度相同，钼钛合金层的厚度小于传统钼钛合金的厚度，可以减少蚀刻液中的氟离子的含量，蚀刻液中氟离子的含量大于0wt%且小于0.1wt%，进一步地，蚀刻液中氟离子的含量大于0wt%且小于0.01wt%，例如蚀刻液中的氟离子的含量为0.005wt%，以避免氟离子含量过高造成基板腐蚀的问题。
在本实施例中，图案化金属构件包括源漏电极（1131，1132）以及数据线（未示出）。在其他实施例中，图案化金属构件也可以包括栅极以及扫描线，栅极以及扫描线的制备方法与源漏电极以及数据线的制备方法相同，此处不作详述。
本实施例阵列基板的制造方法通过依次形成层叠设置的第一金属层、第二金属层以及铜层，蚀刻液蚀刻第二金属层的速率小于蚀刻液蚀刻第一金属层的速率，图案化第二金属层和图案化第一金属层的结构，可以避免第二金属层出现金属残留的问题的同时，可以避免图案化第二金属层被腐蚀而导致铜掏空问题，降低静电击穿的风险，且第一金属层与基板的附着力大于铜层与基板的附着力，提高图案化金属构件在基板上的附着力，且能阻挡铜扩散。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (15)

  1. 一种阵列基板，其中，所述阵列基板包括基板以及图案化金属构件，所述图案化金属构件包括依次层叠设置于所述基板上的图案化第一金属层、图案化第二金属层以及图案化铜层，
    其中，所述图案化第一金属层与所述基板的附着力大于所述图案化铜层与所述基板的附着力，所述图案化金属构件是经过蚀刻液蚀刻依次层叠设置于所述基板上的第一金属层、第二金属层以及铜层得到，所述蚀刻液蚀刻所述第二金属层的蚀刻速率小于所述蚀刻液蚀刻所述第一金属层的蚀刻速率，所述第一金属层的制备材料包括钼，所述第二金属层的制备材料包括钛以及钒中的至少一种。
  2. 根据权利要求1所述的阵列基板，其中，所述第一金属层为钼层，所述第二金属层为钼钛合金层。
  3. 根据权利要求2所述的阵列基板，其中，所述第一金属层和所述第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米。
  4. 根据权利要求1所述的阵列基板，其中，所述图案化金属构件包括源漏电极以及数据线，和/或，所述图案化金属构件包括栅极以及扫描线。
  5. 一种阵列基板的制造方法，其中，所述制造方法包括如下步骤：
    于基板上形成整面的第一金属层；
    于所述第一金属层远离所述基板的表面上形成整面的第二金属层；
    于所述第二金属层远离所述第一金属层的表面上形成整面的铜层；
    于所述铜层表面形成光阻层，所述光阻层经光罩曝光以及显影液显影后，剩余部分所述光阻层覆盖所述铜层的区域为保留区，显影液去除所述光阻层的区域为蚀刻区；
    采用蚀刻液蚀刻所述蚀刻区的铜层、第二金属层以及第一金属层，去除剩余所述光阻层，得所述阵列基板的图案化金属构件；
    其中，所述蚀刻液蚀刻所述第一金属层的蚀刻速率大于所述蚀刻液蚀刻所述第二金属层的蚀刻速率，所述第一金属层与所述基板的附着力大于所述铜层与所述基板的附着力。
  6. 根据权利要求5所述的阵列基板的制造方法，其中，所述第一金属层的制备材料包括钼，所述第二金属层的制备材料包括钛以及钒中的至少一种。
  7. 根据权利要求5所述的阵列基板的制造方法，其中，所述第一金属层为钼层，所述第二金属层为钼钛合金层。
  8. 根据权利要求7所述的阵列基板的制造方法，其中，所述第一金属层和所述第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米，所述蚀刻液中氟离子的含量大于0wt%且小于0.1wt%。
  9. 根据权利要求8所述的阵列基板的制造方法，其中，所述第一金属层和所述第二金属层的厚度之和大于或等于10纳米且小于或等于50纳米，所述蚀刻液中氟离子的含量大于0wt%且小于0.01wt%。
  10. 根据权利要求5所述的阵列基板的制造方法，其中，所述第一金属层的厚度的取值范围为大于或等于5纳米且小于或等于100纳米，所述第二金属层的厚度的取值范围为大于或等于5纳米且小于或等于100纳米。
  11. 根据权利要求5所述的阵列基板的制造方法，其中，所述图案化金属构件包括源漏电极以及数据线，和/或，所述图案化金属构件包括栅极以及扫描线。
  12. 一种阵列基板，其中，所述阵列基板包括基板以及图案化金属构件，所述图案化金属构件包括依次层叠设置于所述基板上的图案化第一金属层、图案化第二金属层以及图案化铜层，
    其中，所述图案化第一金属层与所述基板的附着力大于所述图案化铜层与所述基板的附着力，所述图案化金属构件是经过蚀刻液蚀刻依次层叠设置于所述基板上的第一金属层、第二金属层以及铜层得到，所述蚀刻液蚀刻所述第二金属层的蚀刻速率小于所述蚀刻液蚀刻所述第一金属层的蚀刻速率。
  13. 根据权利要求12所述的阵列基板，其中，所述第一金属层为钼层，所述第二金属层为钼钛合金层。
  14. 根据权利要求13所述的阵列基板，其中，所述第一金属层和所述第二金属层的厚度之和大于或等于5纳米且小于或等于100纳米。
  15. 根据权利要求12所述的阵列基板，其中，所述图案化金属构件包括源漏电极以及数据线，和/或，所述图案化金属构件包括栅极以及扫描线。
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