WO2021107116A1 - Carte de câblage imprimé et procédé de fabrication d'une carte de câblage imprimé - Google Patents

Carte de câblage imprimé et procédé de fabrication d'une carte de câblage imprimé Download PDF

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Publication number
WO2021107116A1
WO2021107116A1 PCT/JP2020/044278 JP2020044278W WO2021107116A1 WO 2021107116 A1 WO2021107116 A1 WO 2021107116A1 JP 2020044278 W JP2020044278 W JP 2020044278W WO 2021107116 A1 WO2021107116 A1 WO 2021107116A1
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Prior art keywords
layer
cavity
build
conductor layer
core substrate
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PCT/JP2020/044278
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English (en)
Japanese (ja)
Inventor
淳男 川越
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京セラ株式会社
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Priority to JP2021561562A priority Critical patent/JPWO2021107116A1/ja
Publication of WO2021107116A1 publication Critical patent/WO2021107116A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present disclosure relates to a printed wiring board having a cavity and a method for manufacturing the printed wiring board.
  • the printed wiring board of the present disclosure has a multilayer board.
  • the multilayer board is located on a core substrate having a first surface and a second surface, a first build-up layer located on the first surface of the core substrate, and a second surface of the core substrate. It has a second build-up layer to be used.
  • the multilayer substrate has a cavity, a first conductor layer, and a second conductor layer. The cavity penetrates the first build-up layer and the core substrate, the bottom surface is the surface of the second build-up layer, and the first conductor layer is located on the bottom surface of the cavity.
  • the second conductor layer is located in the second build-up layer and is located so as to overlap at least a part of the peripheral edge of the bottom surface of the cavity in plan perspective.
  • the method for manufacturing a printed wiring board of the present disclosure includes a first step of preparing a core substrate having a first surface and a second surface and having a seed layer provided on the second surface, and the core substrate. A second step of pattern plating the seed layer provided in the above to form a first conductor layer, and a cavity is formed on the surface of the seed layer including the first conductor layer of the core substrate. A third step of removing a part of the seed layer so that the seed layer remains in the central portion of the core substrate, which is a region of the core substrate, and a first insulating resin layer on the first surface of the core substrate.
  • FIG. 2 is a cross-sectional view taken along the line II-II of FIG. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the printed wiring board of embodiment. It is sectional drawing explaining the manufacturing method of the
  • FIG. 1 is a diagram showing a configuration of a printed wiring board according to one of the disclosed embodiments.
  • the printed wiring board shown in FIG. 1 is an example.
  • the printed wiring board shown as the embodiment has the multilayer board 54 shown below.
  • the multilayer board 54 has a core board 51, a first build-up layer 61, and a second build-up layer 62.
  • the core substrate 51 has a first surface 51a and a second surface 51b.
  • a first build-up layer 61 and a second build-up layer 62 are laminated on the core substrate 51.
  • the first build-up layer 61 has an insulating resin layer 61a and an insulating resin layer 61b.
  • the second build-up layer 62 has an insulating resin layer 62a and an insulating resin layer 62b.
  • the first build-up layer 61 is arranged so as to face the first surface 51a of the core substrate 51.
  • the second build-up layer 62 is arranged so as to face the second surface 51b of the core substrate 51.
  • the multilayer substrate 54 has a cavity 20, a first conductor layer 17, and a second conductor layer 12a.
  • the cavity 20 is open to the multilayer board 54 from the first build-up layer 61 side to the core board 51.
  • the cavity 20 is provided so that the surface 62aa of the second build-up layer 62 is the bottom surface 79.
  • the first conductor layer 17 is arranged so as to be exposed on the bottom surface 79 of the cavity 20.
  • the second conductor layer 12a is provided on the surface 62ab of the insulating resin layer 62a opposite to the core substrate 51.
  • the second conductor layer 12a is located in the second build-up layer 62. Further, when the multilayer substrate 54 is viewed through a plane, it is located so as to overlap at least a part of the peripheral edge portion 79t of the bottom surface 79 of the cavity 20. In other words, the second conductor layer 12a is provided at a position corresponding to the peripheral edge portion 79t of the bottom surface 79 of the cavity 20 when the multilayer substrate 54 is viewed through the plane. According to such a configuration, even if the printed wiring board is provided with the cavity 20 having a large volume, the printed wiring board can be made difficult to bend.
  • the cavity 20 having a large volume and a small thickness on the bottom surface side is formed on the multilayer substrate 54, it is easy to bend on the bottom surface 79 side.
  • Mechanical strength can be increased by inserting a metal member into the peripheral portion 79t of the bottom surface 79 of the bendable cavity 20. This is due to the high elastic modulus of the metal member.
  • the position of the second conductor layer 12a is arranged at the position of the lower layer separated from the first conductor layer 17 exposed on the bottom surface 79 of the cavity 20 and the seed layer 12 by the thickness of the insulating resin layer 62a. Has been done.
  • the first conductor layer 17 is located at the center of the bottom surface 79 of the cavity 20, and the second conductor layer 12a is located at the peripheral edge 79t of the bottom surface 79 of the cavity 20. Further, the first conductor layer 17 and the second conductor layer 12a are arranged so as to separate the insulating resin layer by about one layer in the thickness (lamination) direction of the multilayer substrate 54.
  • the multilayer substrate 54 can be made difficult to bend. If the second conductor layer 12a is arranged so as to be exposed on the bottom surface 79 of the cavity 20, the multilayer substrate 54 becomes easy to bend, and the first conductor layer originally arranged in the cavity 20 becomes easy to bend. There is a concern that it will be difficult to secure electrical insulation with 17.
  • the printed wiring board of this embodiment has a multilayer board 54.
  • the multilayer board 54 has a core board 51, a first build-up layer 61, and a second build-up layer 62.
  • the core substrate 51 is, for example, a substrate having seed layers 12 on both sides of the base material 11.
  • the base material 11 is a so-called sheet-shaped molded body made of an insulating resin.
  • a conductor layer 16 forming an electric circuit is formed on one surface (upper surface) of the core substrate 51.
  • a conductor layer 17 forming an electric circuit is formed on the other surface (lower surface) of the core substrate 51.
  • the core substrate 51 has a via 15 that connects the conductor layer 16 and the conductor layer 17.
  • the multilayer substrate 54 has a conductor layer 16, a conductor layer 17, and a via 15.
  • the via 15 penetrates in the thickness direction of the insulating resin layer 11.
  • the via 15 is arranged between the conductor layer 16 and the conductor layer 17.
  • the conductor layer 16 is arranged so as to partially overlap the seed layer 12 formed on one surface (upper surface) of the base material 11.
  • the conductor layer 17 is arranged so as to partially overlap the seed layer 12 formed on the other surface (lower surface) of the base material 11.
  • the first build-up layer 61 is arranged on the upper surface of the core substrate 51 and has the insulating resin layer 61a and the conductor layer shown below.
  • one surface (lower surface) is the insulating resin layer 61a in contact with the core substrate 51
  • one surface (lower surface) is the other surface (lower surface) of the insulating resin layer 61a. It has an insulating resin layer 61b in contact with the upper surface).
  • a conductive layer forming an electric circuit is formed on the upper surface of the insulating resin layer 61a.
  • the insulating resin layer 61a has a via 15 that connects the conductor layer formed on the upper surface thereof and the conductor layer 16 formed on the upper surface of the core substrate 51.
  • the via 15 is formed so as to penetrate the insulating resin layer 61a in the thickness direction.
  • a conductor layer 63 is formed on the other surface (upper surface) of the insulating resin layer 61b.
  • the insulating resin layer 61b has a via 15 that connects the conductor layer 63 formed on the upper surface thereof and the conductor layer formed on the upper surface of the insulating resin layer 61a.
  • the via 15 is formed so as to penetrate the insulating resin layer 61b in the thickness direction.
  • the via 15 is provided on each of the two first build-up layers 61 arranged on the upper surface side of the core substrate 15.
  • the second build-up layer 62 is arranged on the other surface (lower surface) of the core substrate 51, and has the insulating resin layer 62a and the conductor layer shown below.
  • the second build-up layer 62 has an insulating resin layer 62a whose one surface (upper surface) is in contact with the core substrate 51 and one surface (upper surface) of the other surface (upper surface) of the insulating resin layer 62a. It has an insulating resin layer 62b in contact with the lower surface).
  • the insulating resin layer 62a may be referred to as a first insulating resin layer 62a.
  • the insulating resin layer 62b may be referred to as a second insulating resin layer 62b.
  • a first conductor layer 17 forming an electric circuit is formed on the upper surface of the insulating resin layer 62a.
  • a conductive layer forming an electric circuit is formed on the other surface (lower surface) of the insulating resin layer 62a.
  • the insulating resin layer 62a has a via 15 that connects the first conductor layer 17 formed on the upper surface and the conductive layer formed on the lower surface.
  • the via 15 is formed so as to penetrate the insulating resin layer 62a in the thickness direction. Further, the via 15 is formed so as to overlap the first conductor layer 17 in the insulating resin layer 62a in the direction parallel to the surface.
  • a conductor layer 64 is formed on the other surface (lower surface) of the insulating resin layer 62b.
  • the insulating resin layer 62b has a via 15 that connects the conductor layer 64 formed on the lower surface and the conductive layer formed on the lower surface of the insulating resin layer 62a. That is, the insulating resin layer 62b located at the bottom of the multilayer substrate 54 has a via 15.
  • the via 15 is formed so as to penetrate the insulating resin layer 62b in the thickness direction.
  • the via 15 provided on the insulating resin layer 62a and the via 15 provided on the insulating resin layer 62b are in an overlapping state.
  • the via 15 formed in the second build-up layer 62 is formed within the range of the cavity forming region 65 and directly below the cavity 20.
  • the insulating resin layer 62a and the insulating resin layer 62b are in an overlapping state.
  • the multilayer board 54 has a cavity 20.
  • the cavity 20 penetrates the first build-up layer 61 and the core substrate 51 from the conductor layer 63 side of the multilayer substrate 54. That is, the cavity 20 forms a space with the upper surface of the second build-up layer 62 as the bottom surface.
  • the cavity 20 is opened so as to occupy a part of a region (cavity forming region 65) on the forming surface of the conductor layer 63 of the multilayer substrate 54.
  • the cavity 20 has a concave cross section.
  • the cavity 20 has an insulating resin surface (bottom surface 79) in a part of the second build-up layer 62 and a first conductor layer 17 formed on the upper surface of the second build-up layer 62. It is formed so as to be exposed as a bottom surface (in a flat state) of the same height. That is, the first conductor layer 17 in the cavity 20 is arranged so as to be exposed on the surface of the insulating resin layer 62a which is the bottom surface of the cavity 20.
  • the first conductor layer 17 in the cavity 20 is in a state in which a part thereof is embedded in the insulating resin layer 62a. Then, on the bottom surface of the cavity 20, it is preferable that the surface 79 (bottom surface 79) on the insulating resin layer 62a and the first conductor layer 17 are arranged substantially flush with each other. The reason why it is described as "almost” is that since the first conductor layer 17 is exposed by the etching process, some (2 ⁇ m to 3 ⁇ m) irregularities (steps) may occur. A part of the first conductor layer 17 formed on the bottom surface of the cavity 20 functions as a connection pad for electronic components.
  • the multilayer substrate 54 has a seed layer 12a (hereinafter referred to as a second conductor layer 12a) in addition to the conductor layer 16, the first conductor layer 17, and the via 15 described above around the cavity 20. There is.
  • a seed layer 12a hereinafter referred to as a second conductor layer 12a
  • the second build-up layer 62 has a second conductor layer 12a at a position corresponding to the cavity forming region 65 at a substantially central portion in the thickness direction.
  • the second conductor layer 12a is formed at a position corresponding to at least the side wall surface with respect to the depth direction of the cavity 20. That is, the second conductor layer 12a is located at a portion where the side wall surface (reference numeral 20a in FIG. 1) of the cavity 20 is extended toward the first insulating resin layer 62a and the second insulating resin layer 62b.
  • the position when the second conductor layer 12a is viewed in the thickness direction with respect to the multilayer board 54 is such that the side wall surface 20a of the cavity 20 is located in the second build-up layer 62 arranged on the lower layer side of the core board 51. 1 It is a position where the insulating resin layer 62a is hung down in the direction of the insulating resin layer 62a.
  • the position of the second conductor layer 12a on the multilayer substrate 54 in the plane direction is such that the center is directly below the wall surface 20a of the cavity 20.
  • the position of the wall surface 20a of the cavity 20 and the position of hanging from the position of the wall surface 20a of the cavity 20 in the direction of the first insulating resin layer 62a can also be referred to as a contour portion of the cavity 20.
  • the second conductor layer 12a is preferably arranged directly below the contour portion of the cavity 20.
  • the second conductor layer 12a can be formed, for example, between the insulating resin layer 62a and the insulating resin layer 62b (on the joint surface).
  • the second conductor layer 12a may be in a state where it is not connected to other conductor layers and the conductive layer. That is, the second conductor layer 12a may be electrically isolated from the other conductor layer and the conductive layer.
  • the conductor layer 63 and the conductor layer 64 are connected to each other via a through hole 10 penetrating the first build-up layer 61, the core substrate 51, and the second build-up layer 62 in a region other than the cavity forming region 65. ing. If necessary, conductor layers 73 and 74 (see FIG. 14) and solder resists 71 and 72 (see FIG. 13) may be formed above and below the through hole 10 in a subsequent step. The solder resists 71 and 72 are formed on the surface of the uppermost layer and / or the lowermost layer of the multilayer substrate 54. The conductor layers 73 and 74 have an insulating coating around them by the solder resists 71 and 72 and function as a connection pad.
  • the conductor layer 16 and the conductor layer 17 are electrically the same, the conductor layer integrally formed with the via 15 is called the conductor layer 16, and the conductor layer laminated on the seed layer 12 described later is the first. It is called the conductor layer 17 of 1.
  • the first build-up layer 61 is laminated on the upper surface (first surface) of the core substrate 51 as the substrate having the insulating resin layer 11, and the lower surface of the core substrate 51 (the first surface).
  • the cavity forming region 65 of the multilayer board 54 in which the second build-up layer 62 is laminated on the second surface) penetrates the core substrate 51 by counterbore processing from above the first build-up layer 61.
  • the cavity 20 is formed with the surface 79 of the insulating resin layer 62a of the build-up layer 62 as the bottom surface, and has a surface having the same height as the surface 79 of the insulating resin layer 62a of the second build-up layer 62.
  • a conductor layer 17 embedded in the insulating resin layer 62a of the second build-up layer 62 is provided so as to form a part of the bottom surface of the cavity 20.
  • a seed layer 12 is formed in advance on the lower surface of the core substrate 51 in a range including the cavity forming region 65, and the insulating resin layer 11 of the core substrate 51 is formed by counterbore processing at the time of cavity formation. It has been removed and only the conductor layer 17 remains.
  • the printed wiring board of the embodiment has a second conductor layer 12a in the second build-up layer 62 arranged on the lower layer side of the cavity 20.
  • the cavity 20 penetrates from the first build-up layer 61 to the core board 51, and the range exceeding 1/2 of the thickness of the multi-layer board 54, particularly 3/5. It is formed to exceed the range.
  • the cavity 20 is formed up to a deep position in the thickness direction of the multilayer substrate 54. Since the cavity 20 is formed deep in the thickness direction of the multilayer substrate 54, the multilayer substrate 54 tends to bend around the cavity 20. That is, it is easier to bend as compared with a printed wiring board in which the cavity 20 is formed to a position of 1/2 or less in the thickness direction of the multilayer board 54.
  • the printed wiring board of the embodiment even the portion of the core substrate 51 located at the central portion in the thickness direction of the multilayer substrate 54 is removed. That is, the member of the core substrate 51 that normally has a glass cloth does not exist at the formation position of the cavity 20. Since the core substrate 51 is partially removed in this way, the mechanical strength of this printed wiring board may be weakened.
  • this printed wiring board When this printed wiring board is used as a connector part for electrical connection, for example, a socket or the like is inserted into the cavity 20. Normally, when the connector is inserted into the cavity 20, the printed wiring board is easily deformed.
  • the printed wiring board of the embodiment since the second conductor layer 12a is provided under the wall surface 20a of the cavity 20, the printed wiring board is difficult to bend even at the position where the cavity 20 exists. In this printed wiring board, even if the cavity 20 penetrating the core substrate 51 is formed, it is possible to increase the mechanical strength of the second build-up layer 62 located on the bottom surface side of the cavity 20.
  • the second conductor layer 12a may be formed so as to extend from the contour portion of the cavity 20.
  • the second conductor layer 12a is preferably arranged so as to straddle the position on the cavity 20 side and the position on the outside of the cavity 20 with the hanging position of the wall surface 20a of the cavity 20 at the center.
  • the shape of the second conductor layer 12a may be strip-shaped.
  • the strip shape is a shape forming a long shape with a predetermined width.
  • the predetermined width is a region extending in both directions from the center when the position of the wall surface 20a of the cavity 20 is set as the center.
  • the expanded region is a range in which an insulating portion is provided between the adjacent conductor (the conductor layer including the via 15 in FIG. 1).
  • As a specific predetermined width 5 ⁇ m or more and 500 ⁇ m or less can be used as a guide.
  • the second conductor layer 12a may be arranged so as to circulate just below the position where the bottom surface 79 of the cavity 20 provided in the multilayer substrate 54 and the wall surface 20a intersect.
  • FIG. 2 is a view showing a plan view of the interface between the insulating resin layer 62a and the insulating resin layer 62b so that the second conductor layer 12a forms a band and orbits the peripheral edge portion 79t of the cavity 20. The state of placement in is shown. That is, if the second conductor layer 12a is arranged in the second build-up layer 62 in a ring-shaped state, the multilayer substrate 54 can be made more difficult to bend.
  • the cavity 20 shields a part of a region of a predetermined layer of the multilayer substrate 54 (the range of the seed layer 12 formed on the core substrate 51 and the boundary portion between the cavity portion and the non-cavity portion where the seed layer 12 is not formed).
  • the cavity formation region 65 (see FIG. 7) including the conductor prohibition area) is drilled and / or laser machined to a predetermined depth (a position near the seed layer 12 from which the thickness center or more inside the core substrate 51 is removed). It is a concave cross-section portion obtained by counterboring, removing the remainder remaining by this processing by laser processing to expose the seed layer 12, and then removing the seed layer 12 by flash etching.
  • the plate thickness center or more means a depth that is 1 ⁇ 2 or more of the plate thickness of the core substrate 51 and does not reach the seed layer 12.
  • the cavity forming region 65 is counterbored in an area that can accommodate electronic components to expose the seed layer 12 formed on the lower surface of the core substrate 51, and then the exposed seed layer 12 is flash-etched. It has a cavity bottom (bottom surface) that has been removed to expose the insulating resin layer 62a and the conductor layer 17 underneath it substantially flat. Further, in the cavity forming region 65 described above, immediately below the boundary portion between the cavity portion and the non-cavity portion where the seed layer 12 is not formed, a layer further below the bottom surface of the cavity 20 (insulating resin layer 62a and insulating resin layer). A second conductor layer 12a is formed (between 62b).
  • the second conductor layer 12a extends from directly below the bottom surface of the cavity 20 to the periphery. Further, in the present embodiment, the second conductor layer 12a extends in a band shape around and inside the cavity contour portion on the bottom surface of the cavity 20.
  • the second conductor layer 12a is made of, for example, copper or the like having a thickness of 12 ⁇ m or more, and is made of a dummy pattern, a ground layer, a power supply layer, or the like.
  • the electronic component housed in the cavity 20 is, for example, a bare chip (an unpackaged IC without terminals), and has an electrode for connecting to the multilayer board 54 at the bottom.
  • the electrode at the bottom of the electronic component may be connected to the surface of the conductor layer 17 flatly exposed at the bottom of the cavity as a component mounting land, and the metal plating layer 80 formed by plating on the conductor layer 17 (see FIG. 14). ) May be connected.
  • the metal plating layer 80 is formed by laminating plating layers such as nickel plating and gold plating.
  • the conductor layers 63 and 64 are formed on the surface of the multilayer board 54 (the core board 51 and the first and second build-up layers 61 and 62 above and below the core board 51), and are one of the circuit wirings in the subsequent etching. It is formed as a portion (conductor layer 63a).
  • the conductor layers 63 and 64 have a solid copper pattern, and are formed by, for example, copper foil (thickness of about 9 ⁇ m) and copper plating (thickness of about 15 ⁇ m).
  • the via 15 is connected to the stretch destination (direction along the surface) of the conductor layers 63 and 64.
  • the via 15 interconnects conductors (conductor layers 16, 17, 63, 64, etc.) provided in an arbitrary layer of the multilayer substrate 54.
  • the core substrate 51 is formed by processing an insulating resin layer 11 (see FIG. 3-7) having seed layers 12 formed on the upper and lower surfaces to form vias 15.
  • Examples of the insulating resin forming the insulating resin layer 11 include epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenol resin, polytetrafluoroethylene (PTFE) resin, silicon resin, and polybutadiene resin. , Polyester resin, melamine resin, urea resin, polyphenylene sulfide (PPS) resin, polyphenylene oxide (PPO) resin and the like. Two or more of these resins may be mixed.
  • the via 15 is a via hole pilot hole 14 (see FIG. 4) filled with metal plating by a plating process.
  • the via 15 connects the conductors (conductor layers 63, 64, 16, 17, etc.) provided in each layer (including the inner layer and the outer layer) of the multilayer substrate 54 (see FIG. 8) between layers.
  • the upper surface conductor layer 63 is connected to the conductor layer 17 through the via
  • the lower surface conductor layer 64 is connected to the conductor layer 17 through the via 15.
  • the seed layer 12 is, for example, copper having a thickness of 1 ⁇ m to 10 ⁇ m (1 ⁇ m or more and 10 ⁇ m or less), and is arranged in a state where a part of the seed layer 12 remains under the conductor layer 17.
  • the seed layer 12 is not particularly limited as long as it is electrically connected and can shield the laser, but for example, thin copper foil or electroless copper plating is used. Thin copper foil with a dense metal composition is more suitable.
  • the upper surface and the lower surface of the insulating resin layer 11 are formed by a method such as a modified semi-additive process (M-SAP) or a semi-additive process (SAP), and the connection is provided in a part of the seed layer 12.
  • M-SAP modified semi-additive process
  • SAP semi-additive process
  • the printed wiring board of the present disclosure can be basically obtained by going through the first step to the sixth step described above.
  • a method of manufacturing the printed wiring board of the embodiment will be described with reference to FIGS. 3 to 15.
  • the core substrate base material 11A has a seed layer 12 (for example, a thin copper foil or the like) on the upper surface (first surface 11a) and the lower surface (second surface 11b) of the insulating resin base material 11. (Conducting metal leaf) is laminated.
  • the thickness of the seed layer 12 is preferably, for example, about 1 ⁇ m to 10 ⁇ m.
  • the base material 11A for the core substrate one having a seed layer 12 on at least the lower surface of the upper surface and the lower surface of the base material 11 may be used.
  • a thin resin film may remain at the bottom of the via hole pilot hole 14.
  • desmear processing is performed.
  • the resin is swollen with a strong alkali, and then the resin is decomposed and removed using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.).
  • an oxidizing agent for example, chromic acid, an aqueous solution of permanganate, etc.
  • the resin film may be removed by, for example, a wet blast treatment with an abrasive or a plasma treatment.
  • the inner wall surface of the via hole pilot hole 14 may be roughened for the plating process.
  • the roughening treatment include a wet process using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.), a dry process such as a plasma treatment and an ashing treatment, and the like.
  • pattern plating process In this step, as shown in FIG. 5, pattern plating is performed on the upper surface and the lower surface of the insulating resin base material 11 and a part of the seed layer 12 and the via hole pilot hole 14, and the conductor layer 16 and the third are formed.
  • This is a step of forming the conductor layer 17 and the via 15 of 1.
  • a dry film 13 (plating resist) is laminated on the seed layer 12 and then exposed and developed to provide a circuit portion such as a conductor layer 16 and a via 15 on the upper surface and a conductive circuit on the lower surface.
  • the dry film 13 at the portion where the first conductor layer 17 is desired to be formed is removed.
  • the via hole pilot hole 14 for forming the circuit portion of the insulating resin base material 11 from which a part of the dry film 13 has been removed and the seed layer 12 around the via hole pilot hole 14 are subjected to pattern plating treatment to perform the insulating resin base material 11.
  • the conductor layer 16 on the upper surface of the base material 11, the via 15 inside the base material 11, and the conductive layer on the lower surface of the base material 11 (including the seed layer 12 and the first conductor layer 17) are formed.
  • nickel plating acts as a barrier to the removal of the seed layer 12.
  • Nickel plating and copper plating are performed continuously.
  • the thickness of the nickel plating is preferably 2 ⁇ m or more.
  • This nickel plating process may be called "barrier plating".
  • the plating film formed in this step also serves as a plating film for surface treatment of component mounting, continuous plating of nickel, gold, nickel, and copper plating may be performed.
  • the thickness of nickel plating is preferably 2 ⁇ m or more for the first time and 3 ⁇ m or more for the second time, and 0.3 ⁇ m or more for wire bonding, although it depends on the mounting method of the parts for gold plating.
  • the correction of the circuit width is not different from the normal M-SAP or semi-additive method just because of this technology, and it is sufficient to correct the design value + 6 ⁇ m thickly and expose it.
  • a dry film 18 (photosensitive etching resist) is laminated to the seed layer 12 and the first conductor layer 17 on the lower surface (second surface 11b) of the base material 11. After that, exposure and development are performed to leave the dry film 18 in the cavity forming region 65 (excluding the shield conductor prohibited area at the boundary between the cavity portion and the non-cavity portion), and remove the dry film 18 in other portions. The portion of the exposed seed layer 12 that is not covered with the dry film 18 and is unnecessary as a conductive circuit is removed by flash etching. After this, the dry film 18 is removed from the surfaces of the seed layer 12 and the first conductor layer 17.
  • the dry film 18 is attached to the cavity forming region 65 in the area where the seed layer 12 on the surface (in this case, the second surface 11b) side of the base material 11 is formed. Subsequently, the seed layer 12 outside the dry film 18 is removed by flash etching. Then, the dry film 18 on the seed layer 12 is peeled off. In this case, the seed layer 12 formed on the upper surface (first surface 11a) side of the base material 11 is also removed.
  • the core substrate 51 as shown in FIG. 7 is completed.
  • a conductor layer 16 is formed on the upper surface (first surface 11a) of the base material 11 of the core substrate 51 as a part of a circuit electrically connected to the via 15.
  • the seed layer 12 remains in the cavity forming region 65 (excluding the shield conductor prohibited area at the boundary between the cavity portion and the non-cavity portion) on the lower surface (second surface 11b) of the core substrate 51. ..
  • the portion of the seed layer 12 in the cavity forming region 65 serves as a laser receiving (shielding member) during laser machining, which will be described later.
  • a first conductor layer 17 as a conductive circuit is formed on the lower surface of the base material 11.
  • the circuit was formed using M-SAP as an example, but the circuit (in this case, the first conductor layer 17) can also be formed by SAP using electroless copper plating as the seed layer.
  • the insulating resin layer 61a is attached to the core substrate base material 11A to be the core substrate 51, and then a via hole is formed by using a laser. After that, the surface of the insulating resin layer 61a including the via holes is plated to form the vias 15 and the conductor layer 17.
  • the first build-up layer 61 is multi-layered as shown in FIG. 7, the same process is repeated.
  • first build-up layer 61 and the second build-up layer 62 for example, not only the subtractive method of removing unnecessary conductors as a circuit by etching, but also the case of the core substrate 51, M- SAP, SAP, etc. can be applied. Techniques such as multi-stage pressing or resin lamination are used for laminating the first and second build-up layers 61 and 62.
  • the insulating resin layer 61a, the insulating resin layer 61b, and the conductor layer 17 are formed on the first build-up layer 61 of the upper layer.
  • a conductor layer 63 connected to the via 15 is formed on the upper surface of the first build-up layer 61 of the uppermost layer (surface layer).
  • the second build-up layer 62 has an insulating resin layer 62a, an insulating resin layer 62b, and a conductor layer 17.
  • a via 15 is formed in the cavity forming region 65 on the insulating resin layer 62a directly below the core substrate base material 11A serving as the core substrate 51.
  • the via 15 is connected to the first conductor layer 17 of the core substrate 51 at the upper part, and is connected to the via 15 of the insulating resin layer 62b of the lower layer at the lower part.
  • a first conductor layer 17 is formed on the left and right lower surfaces of the insulating resin layer 62a and the insulating resin layer 62b.
  • a layer (insulating resin layer 62a) further below the bottom surface of the cavity 20 is formed.
  • the insulating resin layer 62b) the above-mentioned second conductor layer 12a is formed.
  • the second conductor layer 12a serves as a receiving (shielding member) for the laser during laser processing described later, and prevents the laser from penetrating into the lower layer.
  • the method for forming the second conductor layer 12a may be any method, such as a subtractive method, M-SAP, or a semi-additive method.
  • the drill is directed from the side of the first build-up layer 61 of the laminated substrate 54A toward the seed layer 12 left on the core substrate 51 for processing.
  • the cavity forming region 65 provided in advance on the laminated substrate 54A is processed so as to be drilled.
  • the drill penetrates the first build-up layer 61 so as to pierce the cavity forming region 65 in the stacking direction (thickness direction), and a part of the base material 11 is placed on the seed layer 12 inside the core substrate 51.
  • the step of forming the cavity 20 by partially removing the insulating resin layer 61a and the insulating resin layer 61b (counterbore processing 1), and the second conductor layer 12a of the seed layer 12 and the lower layer are subjected to laser light. It has two steps of forming a shielding member, removing the insulating resin 68 left in the cavity 20 by laser processing, and exposing the seed layer 12 to the bottom of the cavity 20 (counterbore processing 2).
  • Counterbore processing 1 (drill processing)
  • counterbore processing (drill processing and laser processing are used in combination) is performed from above the laminated substrate 54A to the base material 11 in the core substrate base material 11A through the first build-up layer 61 of the cavity forming region 65.
  • By cutting most of the insulating resin is removed to form the cavity 20 while leaving a part of the base material 11 on the seed layer 12 on the lower surface of the base material 11A for the core substrate.
  • a drill 66 having a sensor at the tip of the bit is arranged at one end of the cavity forming region 65 (for example, the left end when facing the drawing), and a seed on the surface of the core substrate base material 11A is provided.
  • the drill 66 is scraped to a position in front of the layer 12 (a position in front of the bottom of the cavity 20), and the drill 66 is moved from that position in the lateral direction A to remove the insulating resin layer 11 by the drill 66.
  • the seed layer 12 may be cut to the very edge of the surface.
  • the reason why the counterbore processing is performed in two stages including not only the laser processing described later but also the drill processing is that the seed layer 12 or the like is used as the receiving conductor (shielding member) of the laser processing of the laser processing described later, and the base material 11 This is because the remaining insulating resin 68 is removed.
  • a laser beam is irradiated from above the opening of the cavity 20 in the direction of arrow B to remove the insulating resin 68 left at the bottom of the cavity 20 by the drilling process of FIG.
  • a processing laser such as a carbon dioxide gas laser (CO 2 laser) or a YAG laser can be applied.
  • the seed layer 12 and the second conductor layer 12a of the lower layer are used as a shielding member for laser light, and the remaining portion of the upper layer portion left at the bottom of the cavity 20 is removed by laser processing.
  • the flat surface seed layer 12 is exposed to the bottom of the cavity 20.
  • the laser is used in the shielding conductor prohibition area at the boundary between the cavity portion and the non-cavity portion. Can be prevented from penetrating the lower layer and damaging the base material (in this case, the insulating resin layer 62a).
  • a thin resin film (fine resin debris) may remain in that portion.
  • the carbonized portion is cleaned by the laser.
  • water washing treatment such as high-pressure water washing or plasma treatment, desmear treatment such as permanganate treatment is performed. These processes may be performed twice or three times.
  • the desmear treatment is a treatment in which the resin is swollen with a strong alkali and then decomposed and removed using an oxidizing agent (for example, chromic acid, an aqueous solution of permanganate, etc.). Further, the resin film may be removed by a wet blast treatment with an abrasive or a plasma treatment. When performing the plasma treatment, masking may be performed with a dry film in order to protect the surface substrate.
  • an oxidizing agent for example, chromic acid, an aqueous solution of permanganate, etc.
  • the steps may be changed to form the cavity 20 and then the outermost layer circuit may be formed.
  • the steps in order to protect the cavity 20, it is necessary to protect it with a dry film or the like.
  • Electroplated resist ED, etc. can also be used.
  • the second conductor layer 12a used as a laser beam receiving conductor can improve the rigidity of the multilayer substrate 54, which is lowered due to the absence of the superstructure due to the cavity 20.
  • the second conductor layer 12a is provided only on the contour portion of the cavity as a member for shielding the laser light, but if it is arranged on the entire bottom surface of the cavity, the rigidity can be further enhanced. Further, it is possible to stabilize the plate thickness of the cavity portion, which is easily varied only by wiring.
  • the second conductor layer 12a When the second conductor layer 12a is arranged only on the contour portion of the cavity, the second conductor layer 12a has a width of 200 ⁇ m outward with reference to the end portion of the seed layer 12 in consideration of the laser irradiation diameter and the displacement between layers.
  • the laser can be sufficiently shielded by arranging.
  • the seed layer 12 is contained in the base material 11, if a plurality of circuits are to be extended from the first conductor layer 17 to the outside of the cavity, the plurality of circuits will be short-circuited by the seed layer 12. However, by forming the seed layer 12 slightly narrower than the cavity 20, the seed layer 12 does not enter the base material 11, and a plurality of circuits can be extended outside the cavity.
  • the copper foil (barrier layer) of the seed layer 12 at the bottom of the cavity 20 can be used in various ways such as profile-free foil, low-profile foil, and standard foil.
  • FIG. 16 is a diagram showing an outline of the cavity 20
  • FIG. 17 is an enlarged view of the periphery of the contour portion of the cavity 20 shown by the broken line A in FIG.
  • the second conductor layer 12a is arranged on the lower surface of the insulating resin layer 62a, it functions as a shielding member for the laser beam L as described above.
  • the insulating resin layer 62a may be processed so that the vicinity of the surface thereof is locally affected by the laser beam.
  • the upper side of the second conductor layer 12a is slightly scooped out when the contour portion is processed by the laser beam. This is because its volume is smaller than when the second conductor layer 12a is not provided.
  • the shape of the hollowed out portion is such that the wall surface 20a side (62aL in the figure) of the cavity 20 has a step, but the inner side (reference numeral 62aR) of the cavity 20 on the opposite side is the surface of the insulating resin layer 62a.
  • the shape is perpendicular to (bottom surface 79).
  • the solder resist R When the solder resist R is formed on the bottom surface 79 side of the cavity 20, it is possible to suppress the crawling up of the wall surface 20a, and at the same time, the solder resist can be formed on the bottom surface of the cavity 20 with a uniform thickness. This is because the wall surface 20a side (62aL) of the cavity 20 has a stepped shape, so that the solder resist easily crawls up, but the inner side (62aR) is a vertical surface, so that the solder resist does not easily crawl up. is there.
  • the solder resist can have the same thickness as the other portion of the bottom surface 79. That is, in FIG. 17, the thickness t C1 of the solder resist at the corner of the hollowed portion and the thickness t 79 of the solder resist on the bottom surface 79 can be the same.
  • “same” generally means a relationship that satisfies the following equation. t C1- t 79 ⁇ 1 ⁇ m
  • the outermost layer circuit is formed and then the cavity 20 is formed.
  • the cavity 20 is subjected to desmear treatment such as permanganate treatment after laser treatment, the surface substrate is used.
  • the cavity 20 may be formed before forming the circuit of the outermost layer in order to protect the circuit and prevent deterioration of the circuit peel strength.
  • the circuit of the outermost layer is formed by pattern plating such as M-SAP, the number of steps can be reduced by combining with the seed layer removing step described later.
  • the seed layer 12 exposed at the bottom of the cavity 20 is removed by flash etching and embedded in the surface 79 of the insulating resin layer 62a of the second build-up layer 62 and the insulating resin.
  • the seed layer 12 (copper foil), which is a barrier layer, is removed by flash etching the bottom of the cavity forming region 65.
  • the multilayer board 54 is obtained.
  • a part of the bottom surface 79 of the cavity 20 is formed.
  • the first conductor layer 17 flatly exposed on the bottom surface of the cavity 20 functions as a component mounting land, and the circuit wiring in the multilayer board 54 can be connected to the electronic components accommodated in the cavity 20. ..
  • the pattern-plated portion other than the seed layer may be slightly etched, but the etching amount is about 2 ⁇ m, and the flash etching solution is uniformly etched in the vertical direction. Due to its nature, it does not adversely affect the conductor thickness.
  • nickel plating is used as barrier plating, nickel is further etched.
  • a nickel remover NH-1860 series manufactured by MEC COMPANY Ltd. or the like is suitable.
  • the ferric chloride solution and cupric chloride solution which are typical etching solutions of the subtractive method, do not dissolve gold, so in principle. However, since it has a strong penetrating power to the interface, it penetrates into the interface between the gold plating and the insulating material, and side etching that melts the nickel plating and the copper plating below the gold plating occurs, which is not suitable.
  • Outer layer circuit formation process In this step, as shown in FIG. 13, the conductor layer 64 of the second build-up layer 62 below the multilayer substrate 54 formed as shown in FIG. 12 is etched to remove a part of the region. , A conductor layer 64a is formed as a circuit. Further, by etching the conductor layer 63 of the first build-up layer 61 on the upper part of the substrate, a part of the region is removed to form the conductor layer 63a as a circuit wiring or a wiring pattern. For the formation of the outer layer circuit, a subtractive method using an electrodeposited resist having excellent followability to the wall surface of the dent or the through hole as the etching resist may be applied.
  • the electrodeposition resist is an etching resist that applies the properties of electrodeposition coating.
  • solder resist process In this step, the first and second build-up layers 61 and 62 shown in FIG. 13 are coated with an insulating film including a part of the conductor layers 63a and 64a, and as shown in FIG. 14, the solder resist 71, Form 72.
  • solder resist a dry film type and a liquid type can be used.
  • connection pad which is a component mounting land in which a metal plating layer 80 is formed by plating on a conductor layer 17 exposed at the bottom of a cavity 20 and a step is provided from the bottom surface.
  • a circuit pattern may be formed by similarly plating the conductor layer 63a of the first build-up layer 61 on the upper part of the multilayer board 54. At this time, if the through holes 10 are filled with resin or metal, the upper and lower portions of the through holes 10 without the solder resist 71 are also plated, so that the conductor layers 73 and 74 are also formed here. ..
  • the process of mounting electronic components may be added as follows.
  • the electronic component is housed in the cavity 20, and the electrode provided at the bottom of the electronic component and the metal plating layer 80 (connection pad) are brought into contact with each other to connect the circuits to each other. It should be noted that, when the electronic component is not mounted here and is mounted elsewhere, the steps below the electronic component mounting step are unnecessary.
  • the base material 11A for the core substrate for forming the printed wiring board of this embodiment has a first surface (upper surface) 11a and a second surface facing the first surface (upper surface) 11a. It has a base material 11 made of an insulating resin having (lower surface) 11b. A seed layer 12 is formed on the second surface (lower surface) 11b of the base material 11 made of an insulating resin. A first conductor layer 17 is formed by pattern plating in a part of the seed layer 12.
  • the core substrate 51 has a base material 11 made of an insulating resin, a seed layer 12, and a first conductor layer 17.
  • a second build-up layer 62 built up with an insulating resin is formed on at least the lower surface of the core substrate 51 to form a multi-layer substrate (laminated substrate 54A).
  • a part of the core substrate 51 (cavity forming region 65) is counterbored from the side of the first build-up layer 61 with respect to the laminated substrate 54, and the seed of the second surface (lower surface) 51b of the core substrate 51 is formed.
  • the cavity 20 is formed by processing the layer 12 so that it is exposed at the bottom.
  • the surface (bottom surface 79) of the insulating resin layer 62a of the second build-up layer 62 located below the core substrate 51 remains.
  • the first conductor layer 17 is embedded in the bottom surface 79 so that the top surfaces are substantially flush with each other. With such a configuration, the circuit connection between the electronic component housed in the cavity 20 and the substrate side can be made at the bottom of the electronic component.
  • the first conductor layer 17 substantially flush with the bottom surface 79 of the cavity 20 as a connection pad (component mounting land) and connecting it to the electrode at the bottom of the electronic component in this way, the wiring pattern at the bottom of the cavity 20
  • the peel strength of the component mounting land can be improved.
  • the example of the manufacturing procedure of the printed wiring board in each of the above embodiments is an example, and the processing processes can be changed in various ways by replacing each processing process, adding a new processing process, and deleting a part of the processing processes. It is also possible.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

La présente invention concerne une carte de câblage imprimé qui est pourvue d'un substrat multicouche comprenant : un substrat principal ayant une première surface et une seconde surface ; une première couche d'accumulation positionnée sur la première surface du substrat principal ; et une seconde couche d'accumulation positionnée sur la seconde surface du substrat principal. Le substrat multicouche comprend une cavité, une première couche conductrice et une seconde couche conductrice. La cavité pénètre à travers la première couche d'accumulation et le substrat principal, et a une surface inférieure qui est une surface de la seconde couche d'accumulation. La première couche conductrice est positionnée au niveau de la surface inférieure de la cavité. La seconde couche conductrice est positionnée dans la seconde couche d'accumulation, et est positionnée pour chevaucher au moins une partie d'une partie périphérique de la surface inférieure de la cavité dans une perspective plane.
PCT/JP2020/044278 2019-11-29 2020-11-27 Carte de câblage imprimé et procédé de fabrication d'une carte de câblage imprimé WO2021107116A1 (fr)

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Citations (7)

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Publication number Priority date Publication date Assignee Title
JP2005158887A (ja) * 2003-11-21 2005-06-16 Dept Corp 回路基板及びその製造方法
WO2010050627A1 (fr) * 2008-10-31 2010-05-06 太陽誘電株式会社 Carte de circuit imprimé et son procédé de production
JP2012060056A (ja) * 2010-09-13 2012-03-22 Nec Corp 電子装置及び電子モジュール
WO2014125852A1 (fr) * 2013-02-14 2014-08-21 株式会社村田製作所 Substrat de circuit et son procédé de production
JP2018200952A (ja) * 2017-05-26 2018-12-20 富士通株式会社 電子部品、電子部品の製造方法及び電子装置
JP2019046860A (ja) * 2017-08-30 2019-03-22 京セラ株式会社 印刷配線板およびその製造方法
JP2019121766A (ja) * 2018-01-11 2019-07-22 イビデン株式会社 プリント配線板およびその製造方法

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Publication number Priority date Publication date Assignee Title
JP6778709B2 (ja) * 2018-03-29 2020-11-04 京セラ株式会社 印刷配線板の製造方法
TWM570577U (zh) * 2018-08-02 2018-11-21 興普科技股份有限公司 Cavity printed circuit board rubber structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005158887A (ja) * 2003-11-21 2005-06-16 Dept Corp 回路基板及びその製造方法
WO2010050627A1 (fr) * 2008-10-31 2010-05-06 太陽誘電株式会社 Carte de circuit imprimé et son procédé de production
JP2012060056A (ja) * 2010-09-13 2012-03-22 Nec Corp 電子装置及び電子モジュール
WO2014125852A1 (fr) * 2013-02-14 2014-08-21 株式会社村田製作所 Substrat de circuit et son procédé de production
JP2018200952A (ja) * 2017-05-26 2018-12-20 富士通株式会社 電子部品、電子部品の製造方法及び電子装置
JP2019046860A (ja) * 2017-08-30 2019-03-22 京セラ株式会社 印刷配線板およびその製造方法
JP2019121766A (ja) * 2018-01-11 2019-07-22 イビデン株式会社 プリント配線板およびその製造方法

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