WO2021103110A1 - 芯片封装结构以及封装方法 - Google Patents

芯片封装结构以及封装方法 Download PDF

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Publication number
WO2021103110A1
WO2021103110A1 PCT/CN2019/123634 CN2019123634W WO2021103110A1 WO 2021103110 A1 WO2021103110 A1 WO 2021103110A1 CN 2019123634 W CN2019123634 W CN 2019123634W WO 2021103110 A1 WO2021103110 A1 WO 2021103110A1
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WIPO (PCT)
Prior art keywords
hole
shaped
wafer
insulating layer
chip
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PCT/CN2019/123634
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English (en)
French (fr)
Inventor
陈然
杨剑宏
袁文杰
沈戌林
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苏州晶方半导体科技股份有限公司
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Publication of WO2021103110A1 publication Critical patent/WO2021103110A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

Definitions

  • This application relates to the field of semiconductor manufacturing technology, for example, to a chip packaging structure and packaging method.
  • the technology is generally used for circuit interconnection, that is, a hole and wiring process are formed on one side of the wafer, and the electrical signal of the chip unit is transmitted to the metal solder ball through the wiring layer.
  • the present application provides a chip packaging structure and a packaging method, which solves the technical problem that the electrical signals of the chip unit of the chip packaging structure cannot be well transmitted to the metal solder balls through the wiring layer in the related art.
  • This application provides a chip packaging structure, including:
  • the wafer includes at least one Y-shaped through hole, the Y-shaped through hole includes a connected T-shaped hole and a straight hole, and the straight hole exposes part or all of the metal pad.
  • the slope of the side wall of the T-shaped hole is greater than or equal to 58 degrees.
  • the slope of the side wall of the T-shaped hole is less than or equal to 61 degrees.
  • the depth of the straight hole is greater than or equal to 35 microns.
  • the depth of the straight hole is less than or equal to 55 microns.
  • the surface of the wafer connecting two adjacent Y-shaped through holes is parallel to the first surface, and the minimum distance between any two adjacent Y-shaped through holes is greater than or equal to 16 micrometers.
  • the distance between the central axes of any two adjacent straight holes is greater than or equal to 117 microns.
  • It also includes a first insulating layer covering the sidewalls of the Y-shaped through hole and the second surface.
  • It also includes a wiring layer, which is located on the surface of the first insulating layer away from the wafer, and is electrically connected to the metal pad.
  • It also includes at least one metal solder ball, which is located on the surface of the wiring layer away from the first insulating layer that covers the second surface of the wafer, and is electrically connected to the wiring layer.
  • the thickness of the first insulating layer is greater than or equal to 3 microns.
  • the first insulating layer includes an organic insulating material.
  • the second insulating layer includes a solder resist layer.
  • an embodiment of the present application provides a chip packaging method, including:
  • a wafer is provided, the wafer has a first surface and a second surface opposite to the first surface, the wafer contains a plurality of chip units, the second surface is provided with a plurality of metal pads, the metal pads The pad is electrically connected to the chip unit;
  • At least one Y-shaped through hole is formed in the wafer.
  • the Y-shaped through hole includes a connected T-shaped hole and a straight hole, and the straight hole exposes part or all of the metal pad.
  • At least one Y-shaped through hole is formed on the wafer, the Y-shaped through hole includes a T-shaped hole and a straight hole that are connected, and the straight hole exposes part or all of the metal pad and includes:
  • a dry etching process is used to form a straight hole communicating with the T-shaped hole, and the straight hole exposes part or all of the metal liner.
  • the method further includes:
  • a first insulating layer is formed on the sidewall of the Y-shaped through hole and the second surface.
  • the method further includes:
  • a wiring layer is formed on the surface of the first insulating layer far away from the wafer, and is electrically connected to the metal pad.
  • a wiring layer is formed on the surface of the first insulating layer on the side away from the wafer, and after being electrically connected to the metal pad, the method further includes:
  • At least one metal solder ball is formed on the surface of the wiring layer away from the first insulating layer that covers the second surface of the wafer, and is electrically connected to the wiring layer.
  • the method further includes:
  • a metal solder ball is formed in one of the opening structures.
  • the wafer includes at least one Y-shaped through hole, the Y-shaped through hole includes a T-shaped hole and a straight hole that are connected, and the straight hole exposes part or all of the metal pads, and the metal is electrically connected to the chip unit.
  • the pad is equivalent to the lead-out electrode of each chip unit.
  • the metal pad is connected to the circuit structure in the chip unit, and is connected with the wiring layer formed later to derive the electrical signal of the chip unit.
  • the Y-shaped through hole is compared with the V-shaped in the related art.
  • the slope of the T-shaped hole sidewall is more gentle, and it is easier to form a first insulating layer of a preset thickness on the Y-shaped through hole, so that the electrical signal of the chip unit of the chip package structure can be transmitted to the wiring layer through the wiring layer.
  • Metal solder balls are used to complete the preparation of the package structure while maintaining the original opening and the slope of the sidewall of the T-shaped hole.
  • FIG. 1 is a schematic structural diagram of a chip package provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of another chip package provided by an embodiment of the application.
  • FIG. 3 is a schematic flowchart of a chip packaging method provided by an embodiment of the application.
  • 4 to 5 are cross-sectional views corresponding to each step of a chip packaging method provided by an embodiment of the application;
  • FIG. 6 is a schematic flowchart of another chip packaging method provided by an embodiment of the application.
  • FIG. 7 is a schematic flowchart of another chip packaging method provided by an embodiment of the application.
  • 8-10 are cross-sectional views corresponding to each step of another chip packaging method provided by an embodiment of the application.
  • FIG. 11 is a schematic flowchart of another chip packaging method provided by an embodiment of the application.
  • FIG. 1 is a schematic structural diagram of a chip package provided by an embodiment of the application.
  • the chip packaging structure includes: a wafer 10, the wafer 10 has a first surface 100 and a second surface 101 opposite to the first surface 100, the wafer 10 contains a plurality of chip units 11, the first surface 100 A number of metal pads 12 are provided, and the metal pads 12 are electrically connected to the chip unit 11; the wafer 10 includes at least one Y-shaped through hole 13, and the Y-shaped through hole 13 includes a T-shaped hole 130 and a straight hole 131 that communicate with each other. The hole 131 exposes part or all of the metal pad 12.
  • the wafer 10 may be silicon, germanium or other semiconductor substrate materials.
  • the chip unit is, for example, a circuit structure composed of multilayer electronic components with specific functions formed on the first surface of the wafer through multiple photolithography, ion implantation, etching, and evaporation processes.
  • the metal pad 12 electrically connected to the chip unit 11 is equivalent to the lead electrode of each chip unit, and the metal pad 12 is connected to the circuit structure in the chip unit.
  • the Y-shaped through hole 13 may be formed by, for example, a continuous etching process.
  • the through-silicon via technology is generally used for circuit interconnection, that is, a hole and wiring process are formed on one side of the wafer, and the electrical signal of the chip unit is transmitted to the metal solder ball through the wiring layer.
  • TSVs are usually V-shaped vias. Because the sidewalls of the V-shaped holes have a relatively steep slope, a predetermined thickness of the first insulating layer is subsequently formed on the V-shaped holes, especially at the corners of the V-shaped holes. This problem is more likely to occur when the first insulating layer is an organic material. If the first insulating layer cannot reach the preset thickness, the wiring layer formed on the first insulating layer cannot be well insulated from the wafer. The problem is that the electrical signal of the chip unit of the chip package structure is not good. The transmission through the wiring layer to the metal solder balls.
  • the wafer 10 includes at least one Y-shaped through hole 13, the Y-shaped through hole 13 includes a connected T-shaped hole 130 and a straight hole 131, and the straight hole 131 exposes part or all of the metal pad 12
  • the metal pad 12 electrically connected to the chip unit 11 is equivalent to the lead-out electrode of each chip unit 11.
  • the metal pad 12 is connected to the circuit structure in the chip unit 11, and is connected to the wiring layer formed subsequently to derive the electrical signal of the chip unit
  • the Y-shaped through hole 13 has a gentler slope of the side wall of the T-shaped hole, and it is easier to form a first insulating layer of a preset thickness on the Y-shaped through hole 13 subsequently, so that The electrical signal of the chip unit of the chip package structure can be transmitted to the metal solder ball through the wiring layer.
  • the depth of the straight hole 131 can be changed to complete the preparation of the package structure while maintaining the original opening and the slope of the sidewall of the T-shaped hole 130.
  • the slope ⁇ 1 of the side wall of the T-shaped hole 130 is greater than or equal to 58 degrees.
  • the slope of the sidewall of the T-shaped hole 130 is less than 58 degrees, the opening of the T-shaped hole 130 is larger, the etching material is larger, the etching time is longer, and the etching cost is higher.
  • the slope of the side wall of the T-shaped hole ⁇ 1 is less than or equal to 61 degrees.
  • the slope of the side wall of the T-shaped hole is greater.
  • the slope ⁇ 1 of the sidewall of the T-shaped hole is greater than 61 degrees, it is more difficult to form a first insulating layer with a predetermined thickness on the sidewall of the T-shaped hole 130 subsequently.
  • the preparation of the package structure can be completed while maintaining the original opening and the slope of the sidewall of the T-shaped hole 130 by changing the depth of the straight hole 131.
  • the depth L1 of the straight hole 131 is greater than or equal to 35 microns.
  • the relatively thin wafer 10 can be selected while maintaining the original opening and sidewall slope of the T-shaped hole 130, but when the depth L1 of the straight hole 131 is less than 35 microns, the wafer 10 If the thickness is too thin, the mechanical strength of the package structure may be affected.
  • the depth L1 of the straight hole 131 is less than or equal to 55 microns. While maintaining the original opening and sidewall slope of the T-shaped hole 130, the greater the depth of the straight hole 131, the relatively thicker wafer 10 can be selected, but when the depth L1 of the straight hole 131 is greater than 55 microns, the wafer 10 is too thick. Thick, increase the cost of preparation.
  • the surface 102 of the wafer 10 connecting two adjacent Y-shaped through holes 13 is parallel to the first surface 100, and any two adjacent Y-shaped through holes 13
  • the minimum distance between L2 is greater than or equal to 16 microns.
  • the distance L3 between the central axes of any two adjacent straight holes 131 is greater than or equal to 117 microns.
  • the distance L3 between the center axes of any two adjacent straight holes 131 is too small, and the distance between two adjacent metal pads 12 is too close, which is easy to form electrical signal crosstalk, and the center axes of any two adjacent straight holes 131 The distance L3 between them is too large, which increases the production cost.
  • the structure of the chip package further includes a first insulating layer 20 covering the sidewall of the Y-shaped through hole 13 and the second surface 101.
  • the first insulating layer 20 may be an inorganic material SiO2, and may be formed by a thermal growth or deposition process.
  • the thermal growth process is to supply high-purity oxygen from the outside to make it react with the wafer (such as a silicon wafer) to form an oxide layer on the surface of the silicon wafer, and the oxide layer is the first insulating layer 20.
  • Deposition means that oxygen and silicon sources are supplied from the outside to make them react in the cavity, thereby forming an oxide film on the surface of the silicon wafer, that is, the first insulating layer 20.
  • the first insulating layer 20 may also be an organic material, and may be formed by spraying or in a manner.
  • the first insulating layer 20 may be formed by a spray coating or spin coating process.
  • the first insulating layer 20 may be a photosensitive resin photoresist. Since the first insulating layer 20 is a photosensitive material, it may be exposed through a mask with an exposure pattern. The exposure can be carried out by ultraviolet light. The ultraviolet light penetrates the exposure pattern of the mask, irradiates the first insulating layer 20, and reacts with it.
  • the developer After exposure and development, the developer will react with the first insulating layer 20 irradiated by ultraviolet light to dissolve and remove it, exposing the bottom surface and sidewalls of the straight hole 131, and leaving the first insulating layer 20 not irradiated by ultraviolet light. .
  • removing the first insulating layer 20 on the bottom surface and sidewalls of the straight hole 131 by photolithography does not damage the metal substrate 12 on the one hand, and on the other hand, it is compared with dry etching or wet etching to remove the straight hole.
  • the first insulating layer 20 on the bottom surface and sidewalls of 131 can save subsequent etching processes, reduce the number of processes, and improve production efficiency.
  • the structure of the chip package further includes a wiring layer 30 located on the surface of the first insulating layer 20 away from the wafer 10 and electrically connected to the metal pad 12.
  • the wiring layer 30 may include one or more layers of metal.
  • the preparation process of the wiring layer 30 may be, for example, a magnetron sputtering process.
  • the wiring layer 30 leads the electrical signal of the metal pad 12 to the second surface 101 of the wafer 10. It should be noted that the multi-layer metal-forming wiring layer 30 can better form an electrical connection with the metal pad 12 than the one-layer metal-forming wiring layer 30.
  • metallic titanium is sputtered on the surface of the first insulating layer 20 far away from the wafer 10, and then a layer of metallic copper is sputtered on the surface of the metallic titanium by magnetron sputtering, thereby completing the fabrication of the wiring layer 30.
  • the structure of the chip package further includes at least one metal solder ball 40 located in the wiring layer 30 away from the first insulating layer 20 and covering the second surface 101 of the wafer 10
  • the side surface is electrically connected to the wiring layer 30.
  • the metal solder ball 40 is electrically connected to the wiring layer 30 and can lead the electrical signal of the chip unit to the second surface 101 of the wafer 10.
  • the structure of the chip package further includes a second insulating layer 50, the second insulating layer includes at least one opening structure 51, and the second insulating layer 50 covers the wiring layer 30, Each opening structure 51 exposes a metal solder ball 40.
  • the second insulating layer 50 functions to protect the wiring layer 30.
  • the thickness of the first insulating layer 20 is greater than or equal to 3 microns.
  • the wafer 10 includes at least one Y-shaped through hole 13, and the Y-shaped through hole 13 includes a T-shaped hole 130 and a straight hole 131 that communicate with each other.
  • the straight hole 131 exposes part or all of the metal pad 12 and is connected to the chip.
  • the metal pad 12 electrically connected to the unit 11 is equivalent to the lead-out electrode of each chip unit.
  • the metal pad 12 is connected to the circuit structure in the chip unit, and is connected to the wiring layer formed subsequently to derive the electrical signal of the chip unit.
  • the slope of the side wall of the T-shaped hole is more gentle, and it is easier to form the first insulating layer 20 with a preset thickness on the Y-shaped through hole 13, so that the chip package structure is The electrical signal of the chip unit can be transmitted to the metal solder ball through the wiring layer.
  • the preset thickness of the first insulating layer 20 is greater than or equal to 3 microns.
  • the wiring layer 30 formed on the first insulating layer 20 cannot be as good as the wafer 10 Maintaining insulation causes a problem that the electrical signals of the chip unit 11 of the chip package structure cannot be transmitted to the metal solder balls 40 through the wiring layer 30 well.
  • the first insulating layer 20 includes an organic insulating material.
  • the organic insulating material can be formed by spraying or spin coating.
  • the organic insulating material may be a photosensitive resin photoresist, and the photosensitive resin photoresist is a photoresist with good photosensitive properties.
  • the photosensitive resin photoresist has good insulating properties, and the remaining part after photolithography does not need to be peeled off. It is used as an insulating material to isolate the wafer from the subsequent metal wiring layer and will not affect the performance of the device.
  • the second insulating layer 50 includes a solder resist layer.
  • the solder resist layer functions to protect the wiring layer 30.
  • FIG. 3 shows a preparation flow chart of the chip packaging method provided by the embodiment of the present application. Referring to FIG. 3, the method includes the following steps:
  • Step 110 Provide a wafer.
  • the wafer has a first surface and a second surface opposite to the first surface.
  • the wafer contains a plurality of chip units.
  • the second surface is provided with a plurality of metal pads.
  • the metal pads are electrically connected to the chip units. connection.
  • a wafer 10 is provided.
  • the wafer 10 has a first surface 100 and a second surface 101 opposite to the first surface 100.
  • the wafer 10 contains a plurality of chip units 11, and the second surface 101 is provided with a plurality of metal linings.
  • the pad 12 and the metal pad 12 are electrically connected to the chip unit 11.
  • the chip unit 11 forms a circuit structure composed of multilayer electronic components with specific functions on the first surface 100 of the wafer 10 through multiple photolithography, ion implantation, etching, and evaporation processes, for example.
  • the metal pad 12 is equivalent to the lead electrode of each chip unit 11, and the metal pad 12 is connected to the circuit structure in the chip unit 11.
  • the wafer 10 may be silicon, germanium or other semiconductor substrate materials.
  • Step 120 At least one Y-shaped through hole is formed in the wafer.
  • the Y-shaped through hole includes a connected T-shaped hole and a straight hole, and the straight hole exposes part or all of the metal pads.
  • the Y-shaped through hole 13 includes a T-shaped hole 130 and a straight hole 131 that are connected to each other, and the straight hole 131 exposes part or all of the metal pad 12.
  • the Y-shaped through hole 13 may be formed by, for example, a continuous etching process.
  • the through-silicon via technology is generally used for circuit interconnection, that is, a hole and wiring process are formed on one side of the wafer, and the electrical signal of the chip unit is transmitted to the metal solder ball through the wiring layer.
  • TSVs are usually V-shaped vias. Because the sidewalls of the V-shaped holes have a relatively steep slope, a predetermined thickness of the first insulating layer is subsequently formed on the V-shaped holes, especially at the corners of the V-shaped holes. This problem is more likely to occur when the first insulating layer is an organic material. If the first insulating layer cannot reach the preset thickness, the wiring layer formed on the first insulating layer cannot be well insulated from the wafer. The problem is that the electrical signal of the chip unit of the chip package structure is not good. The transmission through the wiring layer to the metal solder balls.
  • the wafer 10 includes at least one Y-shaped through hole 13, the Y-shaped through hole 13 includes a connected T-shaped hole 130 and a straight hole 131, and the straight hole 131 exposes part or all of the metal pad 12
  • the metal pad 12 electrically connected to the chip unit 11 is equivalent to the lead-out electrode of each chip unit.
  • the metal pad 12 is connected to the circuit structure in the chip unit and is connected to the wiring layer formed subsequently to derive the electrical signal of the chip unit.
  • the sidewall of the T-shaped through hole 13 has a gentler slope, and it is easier to form a first insulating layer with a preset thickness on the Y-shaped through hole 13 to make the chip package
  • the electrical signal of the chip unit of the structure can be transmitted to the metal solder ball through the wiring layer.
  • the depth of the straight hole 131 can be changed to complete the preparation of the package structure while maintaining the original opening and the slope of the sidewall of the T-shaped hole 130.
  • step 120 forms at least one Y-shaped through hole in the wafer.
  • the Y-shaped through hole includes a connected T-shaped hole and a straight hole, and the straight hole exposes part or all of it.
  • the metal backing includes:
  • Step 1201 A T-shaped hole is formed in the wafer by using a dry etching process.
  • a T-shaped hole 130 is formed in the wafer by a dry etching process.
  • the T-shaped hole 130 may be formed in the wafer through photolithography and deep reactive ion etching processes.
  • Step 1202 using a dry etching process to form a straight hole communicating with the T-shaped hole, and the straight hole exposes part or all of the metal pads.
  • a dry etching process is used to form a straight hole 131 communicating with the T-shaped hole 130, and the straight hole 131 exposes part or all of the metal pad 12.
  • the straight hole 131 communicating with the T-shaped hole 130 can be formed by photolithography and deep reactive ion etching processes.
  • the dry etching process can utilize an electron cyclotron accelerated oscillation reactor, a reactive ion etching reactor, a magnetic enhanced reactive ion etching reactor or an inductively coupled plasma reactor for etching.
  • the etching gas for dry etching is an etching gas containing halogen elements such as fluorine, chlorine, bromine, and iodine, or oxygen or sulfur.
  • step 120 after forming at least one Y-shaped through hole on the wafer further includes:
  • Step 130 forming a first insulating layer on the sidewall and the second surface of the Y-shaped through hole.
  • a first insulating layer 20 is formed on the sidewalls of the Y-shaped through hole 13 and the second surface 101.
  • the first insulating layer 20 may be an inorganic material SiO2, and may be formed by a thermal growth or deposition process.
  • the thermal growth process is to supply high-purity oxygen from the outside to make it react with the wafer (such as a silicon wafer) to form an oxide layer on the surface of the silicon wafer, and the oxide layer is the first insulating layer 20.
  • Deposition means that oxygen and silicon sources are supplied from the outside to make them react in the cavity, thereby forming an oxide film on the surface of the silicon wafer, that is, the first insulating layer 20.
  • the first insulating layer 20 can also be an organic glue, which can be formed by spraying or spin coating.
  • the first insulating layer 20 may be formed by a spray coating or spin coating process.
  • the first insulating layer 20 may be a photosensitive resin photoresist, and the photosensitive resin photoresist is a photoresist with good photosensitive properties.
  • the photosensitive resin photoresist has good insulating properties, and the remaining part after photolithography does not need to be peeled off. It is used as an insulating material to isolate the wafer from the subsequent metal wiring layer and will not affect the performance of the device. Photosensitive material, so it can be exposed through a mask with an exposure pattern. The exposure can be carried out by ultraviolet light.
  • the ultraviolet light penetrates the exposure pattern of the mask, irradiates the first insulating layer 20, and reacts with it. After exposure and development, the developer will react with the first insulating layer 20 irradiated by ultraviolet light to dissolve and remove it, exposing the bottom surface and sidewalls of the straight hole 131, and leaving the first insulating layer 20 not irradiated by ultraviolet light. .
  • removing the first insulating layer 20 on the bottom surface and sidewalls of the straight hole 131 by photolithography does not damage the metal substrate 12 on the one hand, and on the other hand, it is compared with dry etching or wet etching to remove the straight hole.
  • the first insulating layer 20 on the bottom surface and sidewalls of 131 can save subsequent etching processes, reduce the number of processes, and improve production efficiency.
  • step 130 further includes after forming the first insulating layer on the sidewall and the second surface of the Y-shaped through hole:
  • Step 140 A wiring layer is formed on the surface of the first insulating layer far away from the wafer, which is electrically connected to the metal pad.
  • a wiring layer 30 is formed on the surface of the first insulating layer 20 far away from the wafer 10 and is electrically connected to the metal pad 12.
  • the wiring layer 30 may include one or more layers of metal.
  • the preparation process of the wiring layer 30 may be, for example, a magnetron sputtering process.
  • the wiring layer 30 leads the electrical signal of the metal pad 12 to the second surface 101 of the wafer 10. It should be noted that the multi-layer metal-forming wiring layer 30 can better form an electrical connection with the metal pad 12 than the one-layer metal-forming wiring layer 30.
  • metallic titanium is sputtered on the surface of the first insulating layer 20 far away from the wafer 10, and then a layer of metallic copper is sputtered on the surface of the metallic titanium by magnetron sputtering, thereby completing the fabrication of the wiring layer 30.
  • step 140 forming a wiring layer on the surface of the first insulating layer far from the wafer side, and after being electrically connected to the metal pad further includes:
  • Step 150 At least one metal solder ball is formed on the surface of the wiring layer away from the first insulating layer that covers the second surface of the wafer, and is electrically connected to the wiring layer.
  • At least one metal solder ball 40 is formed on the surface of the wiring layer 30 away from the first insulating layer 20 that covers the second surface 101 of the wafer 10 and is electrically connected to the wiring layer 30.
  • the metal solder ball 40 is electrically connected to the wiring layer 30 and can lead the electrical signal of the chip unit to the second surface 101 of the wafer 10.
  • step 150 forms at least one metal solder ball on the surface of the wiring layer away from the first insulating layer that covers the second surface of the wafer, and is electrically connected to the wiring layer It also included:
  • Step 1401 forming a second insulating layer on the surface of the wiring layer away from the first insulating layer, the second insulating layer including an opening structure.
  • a second insulating layer 50 is formed on the surface of the wiring layer 30 away from the first insulating layer 20, and the second insulating layer 50 includes an opening structure (not shown).
  • Step 1402 forming a metal solder ball in an opening structure.
  • a metal solder ball 40 is formed in an opening structure.
  • the metal solder ball 40 is electrically connected to the wiring layer 30 and can lead the electrical signal of the chip unit to the second surface 101 of the wafer 10.

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Abstract

本申请公开了一种芯片封装结构以及封装方法，该封装结构包括：晶圆，晶圆具有第一表面以及与第一表面相对的第二表面，晶圆内含多个芯片单元，第一表面设置有若干金属衬垫，金属衬垫与芯片单元电连接；晶圆包括至少一个Y型通孔，Y型通孔包括相连通的T型孔和直孔，直孔暴露部分或全部金属衬垫。

Description

芯片封装结构以及封装方法
本公开要求在2019年11月28日提交中国专利局、申请号为201911195017.6的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请涉及半导体制造技术领域，例如涉及一种芯片封装结构以及封装方法。
背景技术
相关的晶圆级封装技术对芯片进行封装时，一般利用技术进行线路互联，即在晶圆的一面形成孔和布线工艺，将芯片单元的电信号通过布线层传输到金属焊球。
但是采用此技术完成的芯片封装结构，芯片封装结构的芯片单元的电信号不能很好的通过布线层传输到金属焊球。
发明内容
本申请提供了一种芯片封装结构以及封装方法，解决了相关技术中芯片封装结构的芯片单元的电信号不能很好的通过布线层传输到金属焊球的技术问题。
本申请提供了一种芯片封装结构，包括：
晶圆，所述晶圆具有第一表面以及与第一表面相对的第二表面，所述晶圆内含多个芯片单元，所述第一表面设置有若干金属衬垫，所述金属衬垫与所述芯片单元电连接；
所述晶圆包括至少一个Y型通孔，所述Y型通孔包括相连通的T型孔和直孔，所述直孔暴露部分或全部所述金属衬垫。
所述T型孔的侧壁的坡度大于或等于58度。
所述T型孔的侧壁的坡度小于或等于61度。
所述直孔的深度大于或等于35微米。
所述直孔的深度小于或等于55微米。
所述晶圆连通两个相邻所述Y型通孔的表面平行于所述第一表面，任意相邻两个所述Y型通孔之间的最小间距大于或等于16微米。
所述任意相邻两个直孔中心轴线之间的距离大于或等于117微米。
还包括第一绝缘层，覆盖所述Y型通孔的侧壁以及所述第二表面。
还包括布线层，位于所述第一绝缘层远离所述晶圆一侧的表面，与所述金属衬垫电连接。
还包括至少一个金属焊球，位于所述布线层远离所述第一绝缘层中覆盖所述晶圆第二表面一侧的表面，且与所述布线层电连接。
还包括第二绝缘层，所述第二绝缘层包括至少一个开口结构，所述第二绝缘层覆盖所述布线层，每一所述开口结构暴露一个所述金属焊球。
所述第一绝缘层的厚度大于或等于3微米。
所述第一绝缘层包括有机绝缘材料。
所述第二绝缘层包括阻焊层。
第二方面，本申请实施例提供了一种芯片封装方法，包括：
提供晶圆，所述晶圆具有第一表面以及与第一表面相对的第二表面，所述晶圆内含多个芯片单元，所述第二表面设置有若干金属衬垫，所述金属衬垫与所述芯片单元电连接；
在所述晶圆形成至少一个Y型通孔，所述Y型通孔包括相连通的T型孔和直孔，所述直孔暴露部分或全部所述金属衬垫。
在所述晶圆形成至少一个Y型通孔，所述Y型通孔包括相连通的T型孔和直孔，所述直孔暴露部分或全部所述金属衬垫包括：
采用干法刻蚀工艺在晶圆形成T型孔；
采用干法刻蚀工艺形成与所述T型孔相连通的直孔，所述直孔暴露部分或全部所述金属衬垫。
在所述晶圆形成至少一个Y型通孔之后还包括：
在所述Y型通孔的侧壁以及所述第二表面之上形成第一绝缘层。
在所述Y型通孔的侧壁以及所述第二表面之上形成第一绝缘层之后还包括：
所述第一绝缘层远离所述晶圆一侧的表面形成布线层，与所述金属衬垫电连接。
所述第一绝缘层远离所述晶圆一侧的表面形成布线层，与所述金属衬垫电连接之后还包括：
在所述布线层远离所述第一绝缘层中覆盖所述晶圆第二表面一侧的表面形成至少一个金属焊球，且与所述布线层电连接。
在所述布线层远离所述第一绝缘层中覆盖所述晶圆第二表面一侧的表面形成至少一个金属焊球，且与所述布线层电连接之前还包括：
在所述布线层远离所述第一绝缘层一侧的表面形成第二绝缘层，所述第二绝缘层包括开口结构；
在一个所述开口结构内形成一个金属焊球。
本申请提供的技术方案中，晶圆包括至少一个Y型通孔，Y型通孔包括相连通的T型孔和直孔，直孔暴露部分或全部金属衬垫，与芯片单元电连接的金属衬垫相当于每个芯片单元的引出电极，金属衬垫与芯片单元中的电路结构连接，与后续形成的布线层将芯片单元的电信号导出，Y型通孔相比相关技术中的V型通孔，T型孔侧壁的坡度更为平缓，后续在Y型通孔上更容易形成预设的厚度的第一绝缘层，使得芯片封装结构的芯片单元的电信号可以通过布线层传输到金属焊球。且在晶圆厚度可变的情况下，改变直孔的深度便可以在保持T型孔原有开口和侧壁坡度的情况下完成封装结构的制备。
附图说明
图1为本申请实施例提供的一种芯片封装的结构示意图；
图2为本申请实施例提供的另一种芯片封装的结构示意图；
图3为本申请实施例提供的一种芯片封装方法的流程示意图；
图4-图5为本申请实施例提供的一种芯片封装方法的各步骤对应的剖面图；
图6为本申请实施例提供的另一种芯片封装方法的流程示意图；
图7为本申请实施例提供的又一种芯片封装方法的流程示意图；
图8-图10为本申请实施例提供的另一种芯片封装方法的各步骤对应的剖面图；
图11为本申请实施例提供的又一种芯片封装方法的流程示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。图1为本申请实施例提供的一种芯片封装的结构示意图。参见图1，该芯片封装结构包括：晶圆 10，晶圆10具有第一表面100以及与第一表面100相对的第二表面101，晶圆10内含多个芯片单元11，第一表面100设置有若干金属衬垫12，金属衬垫12与芯片单元11电连接；晶圆10包括至少一个Y型通孔13，Y型通孔13包括相连通的T型孔130和直孔131，直孔131暴露部分或全部金属衬垫12。
在本实施例中，晶圆10可以是硅、锗或其他半导体衬底材料。芯片单元例如是通过多次光刻、离子注入、刻蚀以及蒸镀等工艺在晶圆第一表面形成具有特定功能的多层电子元件组成的电路结构。与芯片单元11电连接的金属衬垫12相当于每个芯片单元的引出电极，金属衬垫12与芯片单元中的电路结构连接。Y型通孔13例如可以通过连续刻蚀工艺形成。
相关的晶圆级封装技术对芯片进行封装时，一般利用硅通孔技术进行线路互联，即在晶圆的一面形成孔和布线工艺，将芯片单元的电信号通过布线层传输到金属焊球。但是硅通孔通常是V型通孔，由于V型孔侧壁的坡度较大，比较陡峭，后续在V型孔上形成预设的厚度的第一绝缘层，尤其是在V型孔的拐角处，以及当第一绝缘层是有机材料时，更容易出现这种问题。如果第一绝缘层不能达到预设厚度，那么在第一绝缘层之上形成的布线层便不能和晶圆很好的保持绝缘，导致的问题是芯片封装结构的芯片单元的电信号不能很好的通过布线层传输到金属焊球。
本实施例提供的技术方案中，晶圆10包括至少一个Y型通孔13，Y型通孔13包括相连通的T型孔130和直孔131，直孔131暴露部分或全部金属衬垫12，与芯片单元11电连接的金属衬垫12相当于每个芯片单元11的引出电极，金属衬垫12与芯片单元11中的电路结构连接，与后续形成的布线层将芯片单元的电信号导出，Y型通孔13相比相关技术中的V型通孔，T型孔侧壁的坡度更为平缓，后续在Y型通孔13上更容易形成预设的厚度的第一绝缘层，使得芯片封装结构的芯片单元的电信号可以通过布线层传输到金属焊球。且在晶圆厚度可变的情况下，改变直孔131的深度便可以在保持T型孔130原有开口和侧壁坡度的情况下完成封装结构的制备。
可选地，在上述技术方案的基础上，见图1，T型孔130的侧壁的坡度∠1大于或等于58度。在本实施例中，T型孔130的侧壁的坡度越小，后续在T型孔130的侧壁越容易形成预设的厚度的第一绝缘层。当T型孔130的侧壁的坡 度小于58度时，导致T型孔130的开口较大，刻蚀材料较多，刻蚀时间较多，且刻蚀成本较大。
可选地，在上述技术方案的基础上，参见图1，T型孔的侧壁的坡度∠1小于或等于61度。在本实施例中，T型孔的侧壁的坡度越大。T型孔的侧壁的坡度∠1大于61度时，后续在T型孔130的侧壁越不容易形成预设的厚度的第一绝缘层。
在晶圆厚度可变的情况下，可以通过改变直孔131的深度便可以在保持T型孔130原有开口和侧壁坡度的情况下完成封装结构的制备。
可选地，在上述技术方案的基础上，参见图1，直孔131的深度L1大于或等于35微米。直孔131的深度越小，在保持T型孔130原有开口和侧壁坡度的情况下，可以选取相对较薄的晶圆10，但是当直孔131的深度L1小于35微米，晶圆10的厚度太薄，可能影响封装结构的机械强度。
可选地，在上述技术方案的基础上，参见图1，直孔131的深度L1小于或等于55微米。在保持T型孔130原有开口和侧壁坡度的情况下，直孔131的深度越大，可以选取相对较厚的晶圆10，但是当直孔131的深度L1大于55微米，晶圆10太厚，增加制备成本。
可选地，在上述技术方案的基础上，参见图1，晶圆10连通两个相邻Y型通孔13的表面102平行于第一表面100，任意相邻两个Y型通孔13之间的最小间距L2大于或等于16微米。改变直孔131的深度便可以在保持T型孔130原有开口和侧壁坡度的情况下完成封装结构的制备。保持T型孔130原有开口和侧壁坡度，任意相邻两个Y型通孔13之间的最小间距L2也可以保持在一个预设范围内。任意相邻两个Y型通孔13之间的最小间距L2越小，后续在晶圆10连通两个相邻Y型通孔13的表面102形成预设的厚度的第一绝缘层，越不容易做到。当任意相邻两个Y型通孔13之间的最小间距L2大于或等于16微米，便可以后续在晶圆10连通两个相邻Y型通孔13的表面102较容易形成预设的厚度的第一绝缘层。
可选地，在上述技术方案的基础上，参见图1，任意相邻两个直孔131中心轴线之间的距离L3大于或等于117微米。任意相邻两个直孔131中心轴线之间的距离L3太小，相邻两个金属衬垫12之间的距离太近，容易形成电信号的串 扰，任意相邻两个直孔131中心轴线之间的距离L3太大，增加了制备成本。
可选地，在上述技术方案的基础上，参见图2，该芯片封装的结构还包括第一绝缘层20，覆盖Y型通孔13的侧壁以及第二表面101。第一绝缘层20可以是无机材料SiO2，可以通过热生长或者淀积工艺形成。热生长工艺即通过外部供给高纯氧气使之与晶圆(例如硅片)反应，在硅片表面形成一层氧化层，该氧化层即为第一绝缘层20。淀积即通过外部供给氧气和硅源，使它们在腔体内反应，从而在硅片表面形成一层氧化层薄膜，即第一绝缘层20。第一绝缘层20也可以是有机材料，可以通过喷涂或者的方式形成。例如可以通过喷涂或者旋涂工艺形成第一绝缘层20。示例性的，第一绝缘层20可以为感光树脂光刻胶，由于第一绝缘层20为感光材料，因此可以通过具有曝光图形的掩膜版进行曝光。可以通过紫外光进行曝光，紫外光透过掩膜版的曝光图形，照射到第一绝缘层20上，并与之反应。曝光后进行显影，显影剂会将被紫外光照射的第一绝缘层20发生反应进而将其溶解去除，露出直孔131底面和侧壁，并留下未被紫外光照射的第一绝缘层20。此外，通过光刻的方式去除直孔131底面和侧壁的第一绝缘层20，一方面不会破坏金属衬底12，另一方面相比于干法刻蚀或者湿法刻蚀去除直孔131底面和侧壁的第一绝缘层20，可以节省后续的刻蚀工艺，减少了工艺制程，提高了生产效率。
可选地，在上述技术方案的基础上，参见图2，该芯片封装的结构还包括布线层30，位于第一绝缘层20远离晶圆10一侧的表面，与金属衬垫12电连接。布线层30可以包括一层或多层金属。布线层30的制备工艺例如可以是磁控溅射工艺。布线层30将金属衬垫12的电信号引出至晶圆10的第二表面101。需要说明的是，多层金属形成布线层30较一层金属形成布线层30可以更好的与金属衬垫12之间形成电连接。示例性的，在第一绝缘层20远离晶圆10一侧的表面溅射金属钛，再通过磁控溅射在金属钛表面溅射一层金属铜，从而完成布线层30的制作。
可选地，在上述技术方案的基础上，参见图2，该芯片封装的结构还包括至少一个金属焊球40，位于布线层30远离第一绝缘层20中覆盖晶圆10第二表面101一侧的表面，且与布线层30电连接。金属焊球40与布线层30电连接，可以将芯片单元的电信号引出至晶圆10的第二表面101。
可选地，在上述技术方案的基础上，参见图2，该芯片封装的结构还包括第 二绝缘层50，第二绝缘层包括至少一个开口结构51，第二绝缘层50覆盖布线层30，每一开口结构51暴露一个金属焊球40。第二绝缘层50起到保护布线层30的作用。
可选地，在上述技术方案的基础上，第一绝缘层20的厚度大于或等于3微米。在本实施例中，晶圆10包括至少一个Y型通孔13，Y型通孔13包括相连通的T型孔130和直孔131，直孔131暴露部分或全部金属衬垫12，与芯片单元11电连接的金属衬垫12相当于每个芯片单元的引出电极，金属衬垫12与芯片单元中的电路结构连接，与后续形成的布线层将芯片单元的电信号导出，Y型通孔13相比相关技术中的V型通孔，T型孔侧壁的坡度更为平缓，后续在Y型通孔13上更容易形成预设的厚度的第一绝缘层20，使得芯片封装结构的芯片单元的电信号可以通过布线层传输到金属焊球。第一绝缘层20的预设厚度大于或等于3微米，如果第一绝缘层20的厚度小于3微米，那么在第一绝缘层20之上形成的布线层30便不能和晶圆10很好的保持绝缘，导致的问题是芯片封装结构的芯片单元11的电信号不能很好的通过布线层30传输到金属焊球40。
可选地，在上述技术方案的基础上，第一绝缘层20包括有机绝缘材料。有机绝缘材料可以通过喷涂或者旋涂的方式形成。示例性的，有机绝缘材料可以是感光树脂光刻胶，感光树脂光刻胶是一种光敏特性良好的光刻胶。感光树脂光刻胶具有良好的绝缘性，并且光刻后剩余的部分不用剥离，作为隔离晶圆与后续金属布线层的绝缘材料，不会影响对器件性能。
可选地，在上述技术方案的基础上，第二绝缘层50包括阻焊层。阻焊层起到保护布线层30的作用。
基于同一构思，本申请实施例还提供了一种芯片封装方法，图3示出了本申请实施例提供的一种芯片封装方法的制备流程图，参见图3，该方法包括如下步骤：
步骤110、提供晶圆，晶圆具有第一表面以及与第一表面相对的第二表面，晶圆内含多个芯片单元，第二表面设置有若干金属衬垫，金属衬垫与芯片单元电连接。
参见图4，提供晶圆10，晶圆10具有第一表面100以及与第一表面100相对的第二表面101，晶圆10内含多个芯片单元11，第二表面101设置有若干金 属衬垫12，金属衬垫12与芯片单元11电连接。芯片单元11例如是通过多次光刻、离子注入、刻蚀以及蒸镀等工艺在晶圆10第一表面100形成具有特定功能的多层电子元件组成的电路结构。金属衬垫12相当于每个芯片单元11的引出电极，金属衬垫12与芯片单元11中的电路结构连接。晶圆10可以是硅、锗或其他半导体衬底材料。
步骤120、在晶圆形成至少一个Y型通孔，Y型通孔包括相连通的T型孔和直孔，直孔暴露部分或全部金属衬垫。
参见图5，在晶圆10形成至少一个Y型通孔13，Y型通孔13包括相连通的T型孔130和直孔131，直孔131暴露部分或全部金属衬垫12。Y型通孔13例如可以通过连续刻蚀工艺形成。
相关的晶圆级封装技术对芯片进行封装时，一般利用硅通孔技术进行线路互联，即在晶圆的一面形成孔和布线工艺，将芯片单元的电信号通过布线层传输到金属焊球。但是硅通孔通常是V型通孔，由于V型孔侧壁的坡度较大，比较陡峭，后续在V型孔上形成预设的厚度的第一绝缘层，尤其是在V型孔的拐角处，以及当第一绝缘层是有机材料时，更容易出现这种问题。如果第一绝缘层不能达到预设厚度，那么在第一绝缘层之上形成的布线层便不能和晶圆很好的保持绝缘，导致的问题是芯片封装结构的芯片单元的电信号不能很好的通过布线层传输到金属焊球。
本实施例提供的技术方案中，晶圆10包括至少一个Y型通孔13，Y型通孔13包括相连通的T型孔130和直孔131，直孔131暴露部分或全部金属衬垫12，与芯片单元11电连接的金属衬垫12相当于每个芯片单元的引出电极，金属衬垫12与芯片单元中的电路结构连接，与后续形成的布线层将芯片单元的电信号导出，Y型通孔13相比相关技术中的V型通孔，T型孔侧壁的坡度更为平缓，后续在Y型通孔13上更容易形成预设的厚度的第一绝缘层，使得芯片封装结构的芯片单元的电信号可以通过布线层传输到金属焊球。且在晶圆厚度可变的情况下，改变直孔131的深度便可以在保持T型孔130原有开口和侧壁坡度的情况下完成封装结构的制备。
可选地，在上述技术方案的基础上，参见图6，步骤120在晶圆形成至少一个Y型通孔，Y型通孔包括相连通的T型孔和直孔，直孔暴露部分或全部金属 衬垫包括：
步骤1201、采用干法刻蚀工艺在晶圆形成T型孔。
以图5为例进行说明，采用干法刻蚀工艺在晶圆形成T型孔130。例如可以通过光刻和深反应离子刻蚀工艺在晶圆形成T型孔130。
步骤1202、采用干法刻蚀工艺形成与T型孔相连通的直孔，直孔暴露部分或全部金属衬垫。
以图5为例进行说明，采用干法刻蚀工艺形成与T型孔130相连通的直孔131，直孔131暴露部分或全部金属衬垫12。例如可以通过光刻和深反应离子刻蚀工艺形成与T型孔130相连通的直孔131。
在上述技术方案中，所述干法刻蚀工艺可以利用电子回旋加速振荡反应器、反应离子刻蚀反应器、磁增强反应离子刻蚀反应器或电感耦合等离子体反应器进行刻蚀，且所述干法刻蚀的刻蚀气体为含有氟、氯、溴、碘等卤族元素或氧元素或硫元素的刻蚀气体。
可选地，在上述技术方案的基础上，参见图7，步骤120在晶圆形成至少一个Y型通孔之后还包括：
步骤130、在Y型通孔的侧壁以及第二表面之上形成第一绝缘层。
参见图8，在Y型通孔13的侧壁以及第二表面101之上形成第一绝缘层20。第一绝缘层20可以是无机材料SiO2，可以通过热生长或者淀积工艺形成。热生长工艺即通过外部供给高纯氧气使之与晶圆(例如硅片)反应，在硅片表面形成一层氧化层，该氧化层即为第一绝缘层20。淀积即通过外部供给氧气和硅源，使它们在腔体内反应，从而在硅片表面形成一层氧化层薄膜，即第一绝缘层20。第一绝缘层20也可以有机胶，可以通过喷涂或者旋涂的方式形成。例如可以通过喷涂或者旋涂工艺形成第一绝缘层20。示例性的，第一绝缘层20可以是感光树脂光刻胶，感光树脂光刻胶是一种光敏特性良好的光刻胶。感光树脂光刻胶具有良好的绝缘性，并且光刻后剩余的部分不用剥离，作为隔离晶圆与后续金属布线层的绝缘材料，不会影响对器件性能。感光材料，因此可以通过具有曝光图形的掩膜版进行曝光。可以通过紫外光进行曝光，紫外光透过掩膜版的曝光图形，照射到第一绝缘层20上，并与之反应。曝光后进行显影，显影剂会将 被紫外光照射的第一绝缘层20发生反应进而将其溶解去除，露出直孔131底面和侧壁，并留下未被紫外光照射的第一绝缘层20。此外，通过光刻的方式去除直孔131底面和侧壁的第一绝缘层20，一方面不会破坏金属衬底12，另一方面相比于干法刻蚀或者湿法刻蚀去除直孔131底面和侧壁的第一绝缘层20，可以节省后续的刻蚀工艺，减少了工艺制程，提高了生产效率。
可选地，在上述技术方案的基础上，参见图7，步骤130在Y型通孔的侧壁以及第二表面之上形成第一绝缘层之后还包括：
步骤140、第一绝缘层远离晶圆一侧的表面形成布线层，与金属衬垫电连接。
参见图9，第一绝缘层20远离晶圆10一侧的表面形成布线层30，与金属衬垫12电连接。布线层30可以包括一层或多层金属。布线层30的制备工艺例如可以是磁控溅射工艺。布线层30将金属衬垫12的电信号引出至晶圆10的第二表面101。需要说明的是，多层金属形成布线层30较一层金属形成布线层30可以更好的与金属衬垫12之间形成电连接。示例性的，在第一绝缘层20远离晶圆10一侧的表面溅射金属钛，再通过磁控溅射在金属钛表面溅射一层金属铜，从而完成布线层30的制作。
可选地，在上述技术方案的基础上，参见图7，步骤140第一绝缘层远离晶圆一侧的表面形成布线层，与金属衬垫电连接之后还包括：
步骤150、在布线层远离第一绝缘层中覆盖晶圆第二表面一侧的表面形成至少一个金属焊球，且与布线层电连接。
参见图10，在布线层30远离第一绝缘层20中覆盖晶圆10第二表面101一侧的表面形成至少一个金属焊球40，且与布线层30电连接。金属焊球40与布线层30电连接，可以将芯片单元的电信号引出至晶圆10的第二表面101。
可选地，在上述技术方案的基础上，参见图11，步骤150在布线层远离第一绝缘层中覆盖晶圆第二表面一侧的表面形成至少一个金属焊球，且与布线层电连接之前还包括：
步骤1401、在布线层远离第一绝缘层一侧的表面形成第二绝缘层，第二绝缘层包括开口结构。
以图2为例进行说明，在布线层30远离第一绝缘层20一侧的表面形成第 二绝缘层50，第二绝缘层50包括开口结构(未示出)。
步骤1402、在一个开口结构内形成一个金属焊球。
以图2为例进行说明，在一个开口结构内形成一个金属焊球40。金属焊球40与布线层30电连接，可以将芯片单元的电信号引出至晶圆10的第二表面101。

Claims (20)

  1. 一种芯片封装结构，包括：
    晶圆，所述晶圆具有第一表面以及与第一表面相对的第二表面，所述晶圆内含多个芯片单元，所述第一表面设置有若干金属衬垫，所述金属衬垫与所述芯片单元电连接；
    所述晶圆包括至少一个Y型通孔，所述Y型通孔包括相连通的T型孔和直孔，所述直孔暴露部分或全部所述金属衬垫。
  2. 根据权利要求1所述的芯片封装结构，其中，所述T型孔的侧壁的坡度大于或等于58度。
  3. 根据权利要求2所述的芯片封装结构，其中，所述T型孔的侧壁的坡度小于或等于61度。
  4. 根据权利要求1所述的芯片封装结构，其中，所述直孔的深度大于或等于35微米。
  5. 根据权利要求4所述的芯片封装结构，其中，所述直孔的深度小于或等于55微米。
  6. 根据权利要求1所述的芯片封装结构，其中，所述晶圆连通两个相邻所述Y型通孔的表面平行于所述第一表面，任意相邻两个所述Y型通孔之间的最小间距大于或等于16微米。
  7. 根据权利要求6所述的芯片封装结构，其中，所述任意相邻两个直孔中心轴线之间的距离大于或等于117微米。
  8. 根据权利要求1所述的芯片封装结构，还包括第一绝缘层，覆盖所述Y型通孔的侧壁以及所述第二表面。
  9. 根据权利要求8所述的芯片封装结构，还包括布线层，位于所述第一绝缘层远离所述晶圆一侧的表面，与所述金属衬垫电连接。
  10. 根据权利要求9所述的芯片封装结构，还包括至少一个金属焊球，位于所述布线层远离所述第一绝缘层中覆盖所述晶圆第二表面一侧的表面，且与所述布线层电连接。
  11. 根据权利要求10所述的芯片封装结构，还包括第二绝缘层，所述第二绝缘层包括至少一个开口结构，所述第二绝缘层覆盖所述布线层，每一所述开口结构暴露一个所述金属焊球。
  12. 根据权利要求8所述的芯片封装结构，其中，所述第一绝缘层的厚度大于或等于3微米。
  13. 根据权利要求8所述的芯片封装结构，其中，所述第一绝缘层包括有机绝缘材料。
  14. 根据权利要求11所述的芯片封装结构，其中，所述第二绝缘层包括阻焊层。
  15. 一种芯片封装方法，包括：
    提供晶圆，所述晶圆具有第一表面以及与第一表面相对的第二表面，所述晶圆内含多个芯片单元，所述第二表面设置有若干金属衬垫，所述金属衬垫与所述芯片单元电连接；
    在所述晶圆形成至少一个Y型通孔，所述Y型通孔包括相连通的T型孔和直孔，所述直孔暴露部分或全部所述金属衬垫。
  16. 根据权利要求15所述的芯片封装方法，其中，在所述晶圆形成至少一个Y型通孔，所述Y型通孔包括相连通的T型孔和直孔，所述直孔暴露部分或全部所述金属衬垫包括：
    采用干法刻蚀工艺在晶圆形成T型孔；
    采用干法刻蚀工艺形成与所述T型孔相连通的直孔，所述直孔暴露部分或全部所述金属衬垫。
  17. 根据权利要求15所述的芯片封装方法，其中，在所述晶圆形成至少一个Y型通孔之后还包括：
    在所述Y型通孔的侧壁以及所述第二表面之上形成第一绝缘层。
  18. 根据权利要求17所述的芯片封装方法，其中，在所述Y型通孔的侧壁以及所述第二表面之上形成第一绝缘层之后还包括：
    所述第一绝缘层远离所述晶圆一侧的表面形成布线层，与所述金属衬垫电连接。
  19. 根据权利要求17所述的芯片封装方法，其中，所述第一绝缘层远离所述晶圆一侧的表面形成布线层，与所述金属衬垫电连接之后还包括：
    在所述布线层远离所述第一绝缘层中覆盖所述晶圆第二表面一侧的表面形成至少一个金属焊球，且与所述布线层电连接。
  20. 根据权利要求19所述的芯片封装方法，其中，在所述布线层远离所述 第一绝缘层中覆盖所述晶圆第二表面一侧的表面形成至少一个金属焊球，且与所述布线层电连接之前还包括：
    在所述布线层远离所述第一绝缘层一侧的表面形成第二绝缘层，所述第二绝缘层包括开口结构；
    在一个所述开口结构内形成一个金属焊球。
PCT/CN2019/123634 2019-11-28 2019-12-06 芯片封装结构以及封装方法 WO2021103110A1 (zh)

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