WO2021098324A1 - 半导体器件及半导体器件的制备方法 - Google Patents

半导体器件及半导体器件的制备方法 Download PDF

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Publication number
WO2021098324A1
WO2021098324A1 PCT/CN2020/111399 CN2020111399W WO2021098324A1 WO 2021098324 A1 WO2021098324 A1 WO 2021098324A1 CN 2020111399 W CN2020111399 W CN 2020111399W WO 2021098324 A1 WO2021098324 A1 WO 2021098324A1
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mask
strip
layer
semiconductor device
mask layer
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PCT/CN2020/111399
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to EP20891144.6A priority Critical patent/EP3933887B1/en
Publication of WO2021098324A1 publication Critical patent/WO2021098324A1/zh
Priority to US17/342,508 priority patent/US11990340B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present invention relates to the field of semiconductors, in particular to a semiconductor device and a method for preparing the semiconductor device.
  • Integrated circuit or microcircuit (microcircuit), microchip (microchip), chip (chip), in electronics is a small circuit (mainly including semiconductor devices, but also passive components, etc.) It is usually manufactured on the surface of a semiconductor wafer.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the invention provides a semiconductor device and a preparation method of the semiconductor device.
  • the present invention provides a method for manufacturing a semiconductor device, including: providing a layer to be etched; forming a patterned first mask layer on the layer to be etched; and forming a patterned first mask layer on the layer to be etched Two mask layers, the second mask layer and the first mask layer jointly define an opening, the opening exposing the layer to be etched; and the first mask layer and the second mask layer
  • the mask layer is a mask, and the layer to be etched is etched to form a pattern to be etched.
  • the present invention also provides a semiconductor device, including: a layer to be etched; a patterned first mask layer formed on the layer to be etched; and a patterned second mask layer formed on the layer to be etched On the etching layer, the second mask layer and the first mask layer jointly define an opening, and the opening exposes the layer to be etched.
  • Fig. 1 is a flow chart of a method for manufacturing a semiconductor device of the present invention
  • FIGS. 2 to 5 are schematic diagrams of the structures presented in each step of the manufacturing method of the semiconductor device of the present invention.
  • Figure 6a is a top view of a first mask layer in a semiconductor device in an embodiment of the present invention.
  • FIG. 6b is a top view of the second mask layer in the semiconductor device in an embodiment of the present invention.
  • FIG. 6c is a top view of the first mask layer and the second mask layer in the semiconductor device in an embodiment of the present invention.
  • Figure 7a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 7b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 7c is a top view of the first mask layer and the second mask layer in a semiconductor device in another embodiment of the present invention.
  • Fig. 8a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 8b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 8c is a top view of the first mask layer and the second mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 9a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 9b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 9c is a top view of the first mask layer and the second mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 10a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention.
  • 10b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention.
  • 10c is a top view of the first mask layer and the second mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 11a is a top view of a first mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 11b is a top view of a second mask layer in a semiconductor device in another embodiment of the present invention.
  • FIG. 11c is a top view of the first mask layer and the second mask layer in a semiconductor device in another embodiment of the present invention.
  • DRAM continues to develop toward smaller dimensions, which requires continuous reduction of the minimum line width and spacing of integrated circuit design.
  • the feature size of the exposure line is close to the theoretical resolution limit of the exposure system, the image on the surface of the silicon wafer will be severely distorted, resulting in a serious degradation of the quality of the photolithography image.
  • One embodiment, as shown in FIG. 1, provides a method for manufacturing a semiconductor device, including: providing a layer 10 to be etched; forming a patterned first mask layer 20 on the layer 10 to be etched; A patterned second mask layer 30 is formed on the layer 10.
  • the second mask layer 30 and the first mask layer 20 jointly define an opening 40 that exposes the layer to be etched 10; the first mask layer 20 and The second mask layer 30 is a mask, and the layer 10 to be etched is etched to form a pattern to be etched.
  • the method for manufacturing the semiconductor device described above makes the feature size of the first mask layer 20 and the second mask layer 30 larger when the device feature size is the same, and it is a further reduction in the feature size of the device. Possibly, it can also improve the yield of the device and save costs.
  • S10 Provide a layer 10 to be etched, as shown in FIG. 2.
  • the method for forming the first mask layer 20 includes chemical vapor deposition or atomic layer deposition.
  • the material of the first mask layer 20 includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and amorphous.
  • a patterned second mask layer 30 is formed on the layer to be etched 10.
  • the second mask layer 30 and the first mask layer 20 jointly define an opening 40, and the opening 40 exposes the layer to be etched 10, as shown in the figure 4 shown.
  • the method for forming the second mask layer 30 includes chemical vapor deposition or atomic layer deposition.
  • the material of the second mask layer 30 includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and amorphous.
  • the material of the first mask layer 20 and the material of the second mask layer 30 are different and a larger etching selection ratio is required.
  • the second mask layer 30 is formed on the dielectric layer.
  • the first mask layer 20 and the second mask layer 30 are not located on the same plane.
  • the material of the dielectric layer is different from the material of the first mask layer 20 and the material of the second mask layer 30 and requires a large etching selection ratio. Among them, the material of the first mask layer 20 is compared with the material of the second mask layer 30. The material can be the same.
  • the method of forming the dielectric layer includes chemical vapor deposition or atomic layer deposition.
  • the material of the dielectric layer includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, and oxide.
  • titanium, zirconium oxide, titanium nitride, tantalum nitride, and titanium is one or more of titanium, zirconium oxide, titanium nitride, tantalum nitride, and titanium.
  • the opening 40 includes a bit line contact hole.
  • the first mask layer 20 includes a plurality of first strip masks 201 that are parallel to each other
  • the second mask layer 30 includes a plurality of second strip masks 301 that are parallel to each other.
  • the film 201 and a plurality of second strip masks 301 are alternately arranged in parallel.
  • a plurality of first strip-shaped masks 201 are arranged equidistantly, and a plurality of second strip-shaped masks 301 are arranged equidistantly.
  • At least one side of the first strip mask 201 has recesses 50 arranged equidistantly
  • at least one side of the second strip mask 301 has recesses 50 arranged equidistantly.
  • the recess 50 of the strip mask 201 and the second strip mask 301 define an opening 40
  • the recess 50 of the second strip mask 301 and the first strip mask 201 define an opening 40, for example, the first strip
  • One side of the mask 201 and one side of the second strip mask 301 have recesses 50 arranged equidistantly
  • the recesses 50 of the first strip mask 201 and the recesses 50 of the second strip mask 301 An opening 40 is defined, as shown in Fig. 8a, Fig. 8b, and Fig. 8c.
  • the two sides of the first strip mask 201 and the two sides of the second strip mask 301 both have recesses 50 that are arranged equidistantly, and the recesses 50 of the first strip mask 201
  • the recess 50 with the second strip mask 301 defines an opening 40, as shown in FIGS. 6a, 6b, and 6c.
  • the two sides of the first strip mask 201 or the second strip mask 301 have equidistantly arranged recesses 50, and the recesses 50 of the first strip mask 201 and the second strip mask 301
  • the film 301 defines the opening 40 or the recess 50 of the second strip mask 301 and the first strip mask 201 define the opening 40, as shown in FIGS. 7a, 7b, and 7c.
  • the shape of the recess 50 includes a triangle, an arc, or a rectangle.
  • the shape of the recess 50 is a triangle, as shown in Fig. 6a, Fig. 6b, and Fig. 6c.
  • the shape of the recess 50 is an arc, as shown in Fig. 10a, Fig. 10b, and Fig. 10c.
  • the shape of the recess 50 is rectangular, as shown in Figs. 9a, 9b, and 9c.
  • the first mask layer 20 includes a plurality of first windows 202
  • the second mask layer 30 includes a plurality of second windows 302
  • the first mask layer 20 and the second mask layer 30 are arranged in a staggered arrangement to define
  • the exit opening 40 is as shown in Fig. 11a, Fig. 11b, and Fig. 11c.
  • the first windows 202 are arranged in an array
  • the second windows 302 are arranged in an array.
  • the shapes of the first windows 202 and the second windows 302 include but are not limited to rectangles.
  • An embodiment, as shown in FIG. 4, provides a semiconductor device, including: a layer to be etched 10; a patterned first mask layer 20 formed on the layer to be etched 10; and a patterned second mask
  • the layer 30 is formed on the layer 10 to be etched.
  • the second mask layer 30 and the first mask layer 20 jointly define an opening 40, and the opening 40 exposes the layer 10 to be etched.
  • the above-mentioned semiconductor device makes it possible to increase the feature size of the first mask layer 20 and the second mask layer 30 when the feature size of the device is the same, and to further reduce the feature size of the device. It can improve the yield of the device and save cost.
  • the material of the first mask layer 20 includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, and nitride.
  • One or more of tantalum and titanium is one or more of tantalum and titanium.
  • the material of the second mask layer 30 includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, and nitride.
  • tantalum and titanium One or more of tantalum and titanium.
  • the material of the first mask layer 20 and the material of the second mask layer 30 are different and a larger etching selection ratio is required.
  • a dielectric layer is further included between the first mask layer 20 and the second mask layer 30.
  • the material of the dielectric layer is different from the material of the first mask layer 20 and the material of the second mask layer 30 and requires a large etching selection ratio.
  • the material of the dielectric layer includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium. One or more of them.
  • the opening 40 includes a bit line contact hole.
  • the first mask layer 20 includes a plurality of first strip masks 201 that are parallel to each other
  • the second mask layer 30 includes a plurality of second strip masks 301 that are parallel to each other.
  • the film 201 and a plurality of second strip masks 301 are alternately arranged in parallel.
  • a plurality of first strip-shaped masks 201 are arranged equidistantly, and a plurality of second strip-shaped masks 301 are arranged equidistantly.
  • At least one side of the first strip mask 201 has recesses 50 arranged at equal intervals
  • at least one side of the second strip mask 301 has recesses 50 arranged at equal intervals.
  • the recess 50 of the strip mask 201 and the second strip mask 301 define an opening 40
  • the recess 50 of the second strip mask 301 and the first strip mask 201 define an opening 40, for example, the first strip
  • One side of the mask 201 and one side of the second strip mask 301 have recesses 50 arranged equidistantly, the recesses 50 of the first strip mask 201 and the recesses 50 of the second strip mask 301
  • An opening 40 is defined, as shown in Fig. 8a, Fig. 8b, and Fig. 8c.
  • the two sides of the first strip mask 201 and the two sides of the second strip mask 301 both have recesses 50 arranged at equal intervals, and the recesses 50 of the first strip mask 201
  • the recess 50 with the second strip mask 301 defines an opening 40, as shown in FIGS. 6a, 6b, and 6c.
  • the two sides of the first strip mask 201 or the second strip mask 301 have equidistantly arranged recesses 50, and the recesses 50 of the first strip mask 201 and the second strip mask 301
  • the film 301 defines the opening 40 or the recess 50 of the second strip mask 301 and the first strip mask 201 define the opening 40, as shown in FIGS. 7a, 7b, and 7c.
  • the shape of the recess 50 includes a triangle, an arc, or a rectangle.
  • the shape of the recess 50 is a triangle, as shown in Fig. 6a, Fig. 6b, and Fig. 6c.
  • the shape of the recess 50 is an arc, as shown in Fig. 10a, Fig. 10b, and Fig. 10c.
  • the shape of the recess 50 is rectangular, as shown in Figs. 9a, 9b, and 9c.
  • the first mask layer 20 includes a plurality of first windows 202
  • the second mask layer 30 includes a plurality of second windows 302
  • the first mask layer 20 and the second mask layer 30 are arranged in a staggered arrangement to define
  • the exit opening 40 is as shown in Fig. 11a, Fig. 11b, and Fig. 11c.
  • the first windows 202 are arranged in an array
  • the second windows 302 are arranged in an array.
  • the shapes of the first windows 202 and the second windows 302 include but are not limited to rectangles.
  • the order and position of the formation of the first mask layer 20 and the second mask layer 30 above can be exchanged.
  • the layout direction of the opening 40 relative to the layer to be etched 10 can be adjusted arbitrarily according to requirements.
  • the layout direction of the mask layer 30 relative to the layer to be etched 10 can be arbitrarily adjusted according to requirements, and the above should be regarded as the scope of this specification.

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Abstract

本发明涉及一种半导体器件及半导体器件的制备方法，半导体器件的制备方法包括：提供待刻蚀层；于待刻蚀层上形成图形化的第一掩膜层；于待刻蚀层上形成图形化的第二掩膜层，第二掩膜层和第一掩膜层共同定义出开口，开口暴露待刻蚀层；以第一掩膜层和第二掩膜层为掩膜，刻蚀待刻蚀层，以形成待刻蚀图形。上述半导体器件的制备方法使得在器件特征尺寸相同的情况下，第一掩膜层和第二掩膜层的特征尺寸变大，而且为器件特征尺寸的进一步缩小成为可能，还能提高器件的良率，节约成本。

Description

半导体器件及半导体器件的制备方法
相关申请交叉引用
本申请要求2019年11月19日递交的、标题为“半导体器件及半导体器件的制备方法”、申请号为2019111347757的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本发明涉及半导体领域，特别是涉及一种半导体器件及半导体器件的制备方法。
背景技术
集成电路(integrated circuit,IC)，或称微电路(microcircuit)、微芯片(microchip)、芯片(chip)，在电子学中是一种把电路(主要包括半导体器件，也包括被动组件等)小型化的方式，并通常制造在半导体晶圆表面上。比如，DRAM(Dynamic Random Access Memory)，即动态随机存取存储器芯片，是最为常见的内存芯片。这些年来，DRAM持续向更小的外型尺寸发展，使得每个芯片可以封装更多的电路。这样增加了每单位面积容量，可以降低成本和增加功能。
发明内容
本发明提供一种半导体器件及半导体器件的制备方法。
本发明提供一种半导体器件的制备方法，包括：提供待刻蚀层；于所述待刻蚀层上形成图形化的第一掩膜层；于所述待刻蚀层上形成图形化的第二掩膜层，所述第二掩膜层和所述第一掩膜层共同定义出开口，所述开口暴露所述待刻蚀层；以及以所述第一掩膜层和所述第二掩膜层为掩膜，刻蚀所述待刻蚀层，以形成待刻蚀图形。
本发明还提供一种半导体器件，包括：待刻蚀层；图形化的第一掩膜层，形成于所述待刻蚀层上；以及图形化的第二掩膜层，形成于所述待刻蚀层上，所述第二掩膜层和所述第一掩膜层共同定义出开口，所述开口暴露所述待刻 蚀层。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明的半导体器件的制备方法的流程图；
图2～图5为本发明的半导体器件的制备方法各步骤所呈现的结构示意图；
图6a为本发明一个实施例中的半导体器件中第一掩膜层的俯视图；
图6b为本发明一个实施例中的半导体器件中第二掩膜层的俯视图；
图6c为本发明一个实施例中的半导体器件中第一掩膜层和第二掩膜层的俯视图；
图7a为本发明另一个实施例中的半导体器件中第一掩膜层的俯视图；
图7b为本发明另一个实施例中的半导体器件中第二掩膜层的俯视图；
图7c为本发明另一个实施例中的半导体器件中第一掩膜层和第二掩膜层的俯视图；
图8a为本发明另一个实施例中的半导体器件中第一掩膜层的俯视图；
图8b为本发明另一个实施例中的半导体器件中第二掩膜层的俯视图；
图8c为本发明另一个实施例中的半导体器件中第一掩膜层和第二掩膜层的俯视图；
图9a为本发明另一个实施例中的半导体器件中第一掩膜层的俯视图；
图9b为本发明另一个实施例中的半导体器件中第二掩膜层的俯视图；
图9c为本发明另一个实施例中的半导体器件中第一掩膜层和第二掩膜层的俯视图；
图10a为本发明另一个实施例中的半导体器件中第一掩膜层的俯视图；
图10b为本发明另一个实施例中的半导体器件中第二掩膜层的俯视图；
图10c为本发明另一个实施例中的半导体器件中第一掩膜层和第二掩膜层的俯视图；
图11a为本发明另一个实施例中的半导体器件中第一掩膜层的俯视图；
图11b为本发明另一个实施例中的半导体器件中第二掩膜层的俯视图；
图11c为本发明另一个实施例中的半导体器件中第一掩膜层和第二掩膜层的俯视图。
10 待刻蚀层
20 第一掩膜层
201 第一条状掩膜
202 第一窗口
30 第二掩膜层
301 第二条状掩膜
302 第二窗口
40 开口
50 凹部
具体实施方式
如背景技术部分所述，DRAM持续向更小的外型尺寸发展，这需要集成电路设计的最小线宽和间距的不断缩小。但是，当曝光线条的特征尺寸接近于曝光系统的理论分辨极限时，硅片表面的成像就会发生严重的畸变，从而导致光刻图形质量的严重下降。
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技 术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
一个实施例，如图1所示，提供一种半导体器件的制备方法，包括：提供待刻蚀层10；于待刻蚀层10上形成图形化的第一掩膜层20；于待刻蚀层10上形成图形化的第二掩膜层30，第二掩膜层30和第一掩膜层20共同定义出开口40，开口40暴露待刻蚀层10；以第一掩膜层20和第二掩膜层30为掩膜，刻蚀待刻蚀层10，以形成待刻蚀图形。
在本实施例中，上述半导体器件的制备方法使得在器件特征尺寸相同的情况下，第一掩膜层20和第二掩膜层30的特征尺寸变大，而且为器件特征尺寸的进一步缩小成为可能，还能提高器件的良率，节约成本。
S10：提供待刻蚀层10，如图2所示。
S20：于待刻蚀层10上形成图形化的第一掩膜层20，如图3所示。
在一个实施例中，形成第一掩膜层20的方法包括化学气相沉积或原子层沉积工艺，第一掩膜层20的材质包括氧化硅、氮化硅、碳化硅、氮氧化硅、无定形碳、多晶硅、氧化铪、氧化钛、氧化锆、氮化钛、氮化钽、钛中的一种或几种。
S30：于待刻蚀层10上形成图形化的第二掩膜层30，第二掩膜层30和第一掩膜层20共同定义出开口40，开口40暴露待刻蚀层10，如图4所示。
在一个实施例中，形成第二掩膜层30的方法包括化学气相沉积或原子层沉积工艺，第二掩膜层30的材质包括氧化硅、氮化硅、碳化硅、氮氧化硅、无定形碳、多晶硅、氧化铪、氧化钛、氧化锆、氮化钛、氮化钽、钛中的一种或几种。
S40：以第一掩膜层20和第二掩膜层30为掩膜，刻蚀待刻蚀层10，以 形成待刻蚀图形，如图5所示。
在本实施例中，第一掩膜层20的材质与第二掩膜层30的材质不同且要有大的刻蚀选择比。
在另外一个实施例中，在S20与S30之间还包括，于第一掩膜层20上形成介质层。于第一掩膜层20上形成介质层之后，于介质层上形成第二掩膜层30，此时，第一掩膜层20与第二掩膜层30不位于同一平面上。介质层的材质与第一掩膜层20的材质和第二掩膜层30的材质不同且要有大的刻蚀选择比，其中，第一掩膜层20的材质与第二掩膜层30的材质可以相同。
在一个实施例中，形成介质层的方法包括化学气相沉积或原子层沉积工艺，介质层的材质包括氧化硅、氮化硅、碳化硅、氮氧化硅、无定形碳、多晶硅、氧化铪、氧化钛、氧化锆、氮化钛、氮化钽、钛中的一种或几种。
在一个实施例中，开口40包括位线接触孔。
在一个实施例中，第一掩膜层20包括若干相互平行的第一条状掩膜201，第二掩膜层30包括若干相互平行的第二条状掩膜301，若干第一条状掩膜201与若干第二条状掩膜301交替平行排布。
在本实施例中，若干第一条状掩膜201等距排列，若干第二条状掩膜301等距排列。
在一个实施例中，第一条状掩膜201的至少1个侧边具有等距排列的凹部50，第二条状掩膜301的至少1个侧边具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301定义出开口40，第二条状掩膜301的凹部50与第一条状掩膜201定义出开口40，例如，第一条状掩膜201的1个侧边和第二条状掩膜301的1个侧边具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301的凹部50定义出开口40，如图8a、图8b、图8c所示。
在一个实施例中，第一条状掩膜201的2个侧边和第二条状掩膜301的2个侧边都具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301的凹部50定义出开口40，如图6a、图6b、图6c所示。
在一个实施例中，第一条状掩膜201或第二条状掩膜301的2个侧边具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301定义出开口40或第二条状掩膜301的凹部50与第一条状掩膜201定义出开口 40，如图7a、图7b、图7c所示。
在一个实施例中，凹部50的形状包括三角形、弧形或矩形。
在其中一个实施例中，凹部50的形状为三角形，如图6a、图6b、图6c所示。
在其中一个实施例中，凹部50的形状为弧形，如图10a、图10b、图10c所示。
在其中一个实施例中，凹部50的形状为矩形，如图9a、图9b、图9c所示。
在一个实施例中，第一掩膜层20包括若干第一窗口202，第二掩膜层30包括若干第二窗口302，第一掩膜层20与第二掩膜层30错位排布以定义出开口40，如图11a、图11b、图11c所示。
在本实施例中，第一窗口202呈阵列排布，第二窗口302呈阵列排布，第一窗口202和第二窗口302的形状包括矩形但不限于矩形。
一个实施例，如图4所示，提供一种半导体器件，包括：待刻蚀层10；图形化的第一掩膜层20，形成于待刻蚀层10上；图形化的第二掩膜层30，形成于待刻蚀层10上，第二掩膜层30和第一掩膜层20共同定义出开口40，开口40暴露待刻蚀层10。
在本实施例中，上述半导体器件使得在器件特征尺寸相同的情况下，第一掩膜层20和第二掩膜层30的特征尺寸变大，而且为器件特征尺寸的进一步缩小成为可能，还能提高器件的良率，节约成本。
在一个实施例中，第一掩膜层20的材质包括氧化硅、氮化硅、碳化硅、氮氧化硅、无定形碳、多晶硅、氧化铪、氧化钛、氧化锆、氮化钛、氮化钽、钛中的一种或几种。
在一个实施例中，第二掩膜层30的材质包括氧化硅、氮化硅、碳化硅、氮氧化硅、无定形碳、多晶硅、氧化铪、氧化钛、氧化锆、氮化钛、氮化钽、钛中的一种或几种。
在本实施例中，第一掩膜层20的材质与第二掩膜层30的材质不同且要有大的刻蚀选择比。
在另外一个实施例中，在第一掩膜层20与第二掩膜层30之间还包括介质层。介质层的材质与第一掩膜层20的材质和第二掩膜层30的材质不同且 要有大的刻蚀选择比。
在一个实施例中，介质层的材质包括氧化硅、氮化硅、碳化硅、氮氧化硅、无定形碳、多晶硅、氧化铪、氧化钛、氧化锆、氮化钛、氮化钽、钛中的一种或几种。
在一个实施例中，开口40包括位线接触孔。
在一个实施例中，第一掩膜层20包括若干相互平行的第一条状掩膜201，第二掩膜层30包括若干相互平行的第二条状掩膜301，若干第一条状掩膜201与若干第二条状掩膜301交替平行排布。
在本实施例中，若干第一条状掩膜201等距排列，若干第二条状掩膜301等距排列。
在一个实施例中，第一条状掩膜201的至少1个侧边具有等距排列的凹部50，第二条状掩膜301的至少1个侧边具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301定义出开口40，第二条状掩膜301的凹部50与第一条状掩膜201定义出开口40，例如，第一条状掩膜201的1个侧边和第二条状掩膜301的1个侧边具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301的凹部50定义出开口40，如图8a、图8b、图8c所示。
在一个实施例中，第一条状掩膜201的2个侧边和第二条状掩膜301的2个侧边都具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301的凹部50定义出开口40，如图6a、图6b、图6c所示。
在一个实施例中，第一条状掩膜201或第二条状掩膜301的2个侧边具有等距排列的凹部50，第一条状掩膜201的凹部50与第二条状掩膜301定义出开口40或第二条状掩膜301的凹部50与第一条状掩膜201定义出开口40，如图7a、图7b、图7c所示。
在一个实施例中，凹部50的形状包括三角形、弧形或矩形。
在其中一个实施例中，凹部50的形状为三角形，如图6a、图6b、图6c所示。
在其中一个实施例中，凹部50的形状为弧形，如图10a、图10b、图10c所示。
在其中一个实施例中，凹部50的形状为矩形，如图9a、图9b、图9c所 示。
在一个实施例中，第一掩膜层20包括若干第一窗口202，第二掩膜层30包括若干第二窗口302，第一掩膜层20与第二掩膜层30错位排布以定义出开口40，如图11a、图11b、图11c所示。
在本实施例中，第一窗口202呈阵列排布，第二窗口302呈阵列排布，第一窗口202和第二窗口302的形状包括矩形但不限于矩形。
以上第一掩膜层20和第二掩膜层30的形成顺序以及位置可以互换，开口40相对于待刻蚀层10的布局方向可以根据需求任意调节，第一掩膜层20和第二掩膜层30相对于待刻蚀层10的布局方向可以根据需求任意调节，上述都应当认为是本说明书记载的范围。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种半导体器件的制备方法，包括：
    提供待刻蚀层；
    于所述待刻蚀层上形成图形化的第一掩膜层；
    于所述待刻蚀层上形成图形化的第二掩膜层，所述第二掩膜层和所述第一掩膜层共同定义出开口，所述开口暴露所述待刻蚀层；以及
    以所述第一掩膜层和所述第二掩膜层为掩膜，刻蚀所述待刻蚀层，以形成待刻蚀图形。
  2. 根据权利要求1所述的半导体器件的制备方法，其中所述第一掩膜层包括若干相互平行的第一条状掩膜，所述第二掩膜层包括若干相互平行的第二条状掩膜，所述若干第一条状掩膜与所述若干第二条状掩膜交替平行排布。
  3. 根据权利要求2所述的半导体器件的制备方法，其中所述第一条状掩膜的至少1个侧边具有等距排列的凹部，所述第二条状掩膜的至少1个侧边具有等距排列的凹部，所述第一条状掩膜的所述凹部与所述第二条状掩膜构成所述开口，所述第二条状掩膜的所述凹部与所述第一条状掩膜构成所述开口。
  4. 根据权利要求3所述的半导体器件的制备方法，其中所述第一条状掩膜的2个侧边和所述第二条状掩膜的2个侧边都具有等距排列的凹部，所述第一条状掩膜的所述凹部与所述第二条状掩膜的所述凹部构成所述开口。
  5. 根据权利要求2所述的半导体器件的制备方法，其中所述第一条状掩膜或所述第二条状掩膜的2个侧边具有等距排列的凹部，所述第一条状掩膜的所述凹部与所述第二条状掩膜构成所述开口或所述第二条状掩膜的所述凹部与所述第一条状掩膜构成所述开口。
  6. 根据权利要求3～5中任意一项所述的半导体器件的制备方法，其中所述凹部的形状包括三角形、弧形或矩形。
  7. 根据权利要求1所述的半导体器件的制备方法，其中所述第一掩膜层包括若干第一窗口，所述第二掩膜层包括若干第二窗口，所述第一掩膜层与所述第二掩膜层错位排布以构成所述开口。
  8. 根据权利要求1所述的半导体器件的制备方法，在形成所述第一掩膜层之后，还包括在所述第一掩膜层上形成介质层。
  9. 一种半导体器件，包括：
    待刻蚀层；
    图形化的第一掩膜层，形成于所述待刻蚀层上；以及
    图形化的第二掩膜层，形成于所述待刻蚀层上，所述第二掩膜层和所述第一掩膜层共同定义出开口，所述开口暴露所述待刻蚀层。
  10. 根据权利要求9所述的半导体器件，其中所述第一掩膜层包括若干相互平行的第一条状掩膜，所述第二掩膜层包括若干相互平行的第二条状掩膜，所述若干第一条状掩膜与所述若干第二条状掩膜交替平行排布。
  11. 根据权利要求10所述的半导体器件，其中所述第一条状掩膜的至少1个侧边具有等距排列的凹部，所述第二条状掩膜的至少1个侧边具有等距排列的凹部，所述第一条状掩膜的所述凹部与所述第二条状掩膜构成所述开口，所述第二条状掩膜的所述凹部与所述第一条状掩膜构成所述开口。
  12. 根据权利要求11所述的半导体器件，其中所述第一条状掩膜的2个侧边和所述第二条状掩膜的2个侧边都具有等距排列的凹部，所述第一条状掩膜的所述凹部与所述第二条状掩膜的所述凹部构成所述开口。
  13. 根据权利要求10所述的半导体器件，其中所述第一条状掩膜或所述第二条状掩膜的2个侧边具有等距排列的凹部，所述第一条状掩膜的所述凹部与所述第二条状掩膜构成所述开口或所述第二条状掩膜的所述凹部与所述第一条状掩膜构成所述开口。
  14. 根据权利要求11～13中任意一项所述的半导体器件，其中所述凹部的形状包括三角形、弧形或矩形。
  15. 根据权利要求9所述的半导体器件，其中所述第一掩膜层包括若干第一窗口，所述第二掩膜层包括若干第二窗口，所述第一掩膜层与所述第二掩膜层错位排布以构成所述开口。
  16. 根据权利要求9所述的半导体器件，在所述第一掩膜层和所述第二掩膜层之间还包括介质层。
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