WO2021258560A1 - 存储器的形成方法及存储器 - Google Patents

存储器的形成方法及存储器 Download PDF

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Publication number
WO2021258560A1
WO2021258560A1 PCT/CN2020/115396 CN2020115396W WO2021258560A1 WO 2021258560 A1 WO2021258560 A1 WO 2021258560A1 CN 2020115396 W CN2020115396 W CN 2020115396W WO 2021258560 A1 WO2021258560 A1 WO 2021258560A1
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WO
WIPO (PCT)
Prior art keywords
bit line
layer
line contact
contact layer
top surface
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Application number
PCT/CN2020/115396
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English (en)
French (fr)
Inventor
张林涛
权锺完
张令国
刘旭
周贤贵
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to JP2022552654A priority Critical patent/JP7487324B2/ja
Priority to KR1020227038285A priority patent/KR20220163433A/ko
Priority to EP20942150.2A priority patent/EP4099386A4/en
Priority to US17/371,267 priority patent/US20210398984A1/en
Publication of WO2021258560A1 publication Critical patent/WO2021258560A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a method for forming a memory and a memory.
  • DRAM Dynamic Random Access Memory
  • the purpose of some embodiments of this application is to provide a method for forming a memory and a memory.
  • the embodiment of the present application provides a method for forming a memory, including: providing a substrate, the substrate including at least a word line structure and an active area, and a bottom dielectric layer and a bit line contact layer on the top surface of the substrate.
  • the bottom dielectric layer has The bit line contact opening, the bit line contact opening exposes the active area in the substrate, the bit line contact layer covers the bottom dielectric layer and fills the bit line contact opening; part of the bit line contact layer is etched to form bit line contact layers of different heights;
  • a conductive layer is formed on the top surface of the bit line contact layer, the top surface of the conductive layer is located at different heights in the direction perpendicular to the extending direction of the word line structure, and the top surface of the conductive layer is located at different heights in the extending direction of the word line structure;
  • a top dielectric layer is formed on the top surface of the conductive layer; parts of the top dielectric layer, the conductive layer and the bit line contact layer are sequentially etched to form a discret
  • etching part of the bit line contact layer to form bit line contact layers of different heights includes: forming a first photolithography mask layer on the top surface of the bit line contact layer; Set the patterns arranged at intervals in the direction; there is an angle ⁇ between the preset direction and the extending direction of the word line structure, and the range of ⁇ is 0 ⁇ 90°; based on the pattern arranged at intervals, part of the bit line contact layer is etched to form different heights The bit line contact layer; remove the spaced pattern.
  • the spaced patterns include: spaced and extended strips or discrete ellipses or rectangles spaced apart.
  • etching part of the bit line contact layer to form bit line contact layers of different heights includes: forming a second photolithography mask layer on the top surface of the bit line contact layer; the second photolithography mask layer is located on the extension of the word line structure In the direction, and in the direction perpendicular to the extension of the word line structure, there are gaps between adjacent second photolithography mask layers; wherein the substrate at the bottom of the bit line contact layer exposed by the gap includes at least two columns of word line structures A part of the bit line contact layer is etched based on the gap to form a bit line contact layer of different heights; the second photolithography mask layer is removed.
  • forming a conductive layer on the top surface of the bit line contact layer includes: forming a conductive film on the top surface of the bit line contact layer; etching the conductive film to form a conductive layer with uniform thickness on the top surface of the bit line contact layer at different heights.
  • forming a top dielectric layer on the top surface of the conductive layer includes: forming a top dielectric film on the top surface of the conductive layer; flattening the top surface of the top dielectric film to form a top dielectric layer, and the top surface of the top dielectric layer has the same height.
  • filling the bit line contact opening and covering the bit line contact layer of the bottom dielectric layer includes: forming a first bit line contact layer filling the bit line contact opening, the first bit line contact layer covering the bottom dielectric layer; A barrier layer is formed on the top surface of the first bit line contact layer on the top; a second bit line contact layer is formed on the top surface of the barrier layer and the top surface of the first bit line contact layer, and the second bit line contact layer covers the first bit line contact layer and Barrier layer.
  • the height of the conductive layer in the bit line structure etched on the top of the bottom dielectric layer is consistent with that of the barrier layer, and the height difference of the conductive layer in different bit line structures is reduced, so that the conductive layer is The wire is wavy to improve the stability of the memory structure.
  • the embodiment of the present application also provides a memory, including: a substrate, the substrate includes at least a word line structure and an active area; a bottom dielectric layer, the bottom dielectric layer is located on the top of the substrate, and the bottom dielectric layer has a bit line contact opening, The line contact opening exposes the active region in the substrate; the discrete bit line structure, the top surface of the bit line structure is at the same height, the bit line structure includes: on the top of the bottom dielectric layer and the bit line contact layer in the bit line contact opening, located The conductive layer on the top of the bit line contact layer, and the top dielectric layer on the top of the conductive layer; wherein, in the direction in which the bit line structure extends, the conductive layers in the same bit line structure are located at different heights, and in the direction in which the word line structure extends Above, the conductive layers in adjacent bit line structures are located at different heights.
  • connection line of the conductive layer is wave-shaped. Reduce the height difference of the conductive layer in different bit line structures to improve the stability of the memory structure.
  • the conductive layers in different bit line structures are located at the same height, and there is an angle ⁇ between the preset direction and the extending direction of the word line structure, and the range of ⁇ is 0 ⁇ 90°.
  • the embodiments of the present application form bit line contact layers of different heights, so that the conductive layers formed on the top surface of the bit line contact layers are located at different heights; in the direction perpendicular to the extension of the word line structure , The top surface of the conductive layer is located at the same height, and the top surface of the conductive layer is located at a different height in the direction in which the word line structure extends.
  • the layers are located at different heights, and the conductive layers in different bit line structures are located at different heights; on the basis of not changing the arrangement of the bit line structures, the conductive layers in adjacent discrete bit line structures are located at different heights, and the conductive layers are located at different heights.
  • the distance between the conductive layers is changed from a horizontal distance to an oblique distance, thereby increasing the spacing of the conductive layers in the bit line structure; thereby reducing the parasitic capacitance between the bit line structures, and
  • the saturation current of the memory is increased, and at the same time, the method for forming the memory provided by this embodiment has a simple process, low cost, and easy implementation.
  • FIG. 1 is a schematic diagram of the structure corresponding to each step of the method for forming a memory provided by the first embodiment of the present application according to FIG. 1 to FIG. 12 in the first embodiment of the present application;
  • FIG. 13 is a schematic cross-sectional view of a memory formed by the first embodiment of the application.
  • FIG. 14 is a schematic structural diagram corresponding to another graphical manner in the method for forming a memory provided by the second embodiment of this application;
  • 15 is a schematic cross-sectional view of a memory formed by the second embodiment of this application.
  • the spacing between adjacent bit line structures has also become smaller and smaller. The smaller the distance between adjacent bit line structures will cause the parasitic capacitance between adjacent bit line structures to increase continuously, which affects the saturation current of the DRAM array area, and further affects the operating efficiency of the DRAM.
  • the first embodiment of the present application relates to a method for forming a memory, including: providing a substrate including at least a word line structure and an active area, and a bottom dielectric layer and a bit line contact layer on the top surface of the substrate, in the bottom dielectric layer It has a bit line contact opening, which exposes the active area in the substrate, the bit line contact layer covers the bottom dielectric layer and fills the bit line contact opening; part of the bit line contact layer is etched to form bit line contact layers of different heights Forming a conductive layer on the top surface of the bit line contact layer, in the direction perpendicular to the extension of the word line structure, the top surface of the conductive layer is located at different heights, in the direction in which the word line structure extends, the top surface of the conductive layer is located at different heights; A top dielectric layer is formed on the top surface of the conductive layer; part of the top dielectric layer, the conductive layer and the bit line contact layer are sequentially etched to form a discrete bit line structure.
  • FIGS. 1 to 12 are schematic diagrams of the structure corresponding to each step of the memory forming method provided by the first embodiment of the application. The following describes the memory forming method of this embodiment in detail.
  • a substrate 100 is provided.
  • the substrate 100 includes at least a word line structure 102 and an active region 101, and a bottom dielectric layer 110 and a bit line contact layer 120 on the top surface of the substrate 100.
  • the dielectric layer has bits.
  • the line contact opening 111, the bit line contact opening 111 exposes the active region 101 in the substrate 100, and the bit line contact layer 120 covers the bottom dielectric layer 110 and fills the bit line contact opening 111.
  • a substrate 100 is provided, and the substrate 100 includes at least a word line structure 102 and an active region 101.
  • FIG. 1 shows the direction 10 in which the word line structure extends, that is, the dotted line 10 in the figure.
  • a plurality of edge regions 101 are arranged in parallel and spaced apart, and the active regions 101 in the i-th column and the active regions 101 in the i+3th column are in the direction 10 perpendicular to the extension of the word line structure, and the different active regions 101 are located at the same horizontal position ;
  • the active area 101 of the i-th column and the active area 101 of the adjacent columns (i+1-th column and i-1th column) are located at different horizontal positions in the direction 10 perpendicular to the extension of the word line structure.
  • the middle part of the active region 101 separated by the alternately arranged word line structures 102 is a bit line contact point, which is used to connect the bit line structure to be formed later.
  • the substrate 100 also includes other memory structures other than the word line structure 102 and the active region 101, such as shallow trench isolation structures. Since other memory structures are not related to the core technology of this application, here It is not repeated here; those skilled in the art can understand that the substrate 100 also includes other memory structures besides the word line structure 102 and the active area 101 for normal operation of the memory.
  • the material of the substrate 100 may include sapphire, silicon, silicon carbide, gallium arsenide, aluminum nitride or zinc oxide, etc.; in this embodiment, the substrate 100 is formed of silicon material. It is clear to those skilled in the art that this embodiment uses silicon material as The substrate 100 is to facilitate the understanding of subsequent forming methods by those skilled in the art, and does not constitute a limitation. In the actual application process, a suitable substrate material can be selected according to requirements.
  • a bottom dielectric layer 110 and a bit line contact layer 120 are formed on the top surface of the substrate 100.
  • the bottom dielectric layer 110 has a bit line contact opening 111, and the bit line contact opening 111 exposes the active area in the substrate 100. 101.
  • the bit line contact layer 120 covers the bottom dielectric layer 110 and fills the bit line contact opening 111.
  • a bottom dielectric layer 110 is formed on the top surface of the substrate 100.
  • the bottom dielectric layer 110 has a bit line contact opening 111, and the bit line contact opening 111 is used to expose the active region 101 in the substrate 100.
  • the bit line contact opening 111 is used to expose the bit line contact point, that is, to expose the middle of the active region 101 separated by the word line structure 102.
  • the bottom dielectric layer 110 is used to isolate the bit line structure 200 at the position of the non-bit line contact point from contacting the active region 101.
  • the material of the bottom dielectric layer is silicon nitride.
  • the material of the bottom dielectric layer may also be an insulating material such as silicon oxide or silicon oxynitride.
  • FIG. 3 is a schematic top view of the substrate 100.
  • FIG. 3 shows the position where the bit line structure 200 needs to be formed later based on the formation of the bottom dielectric layer 110 in FIG.
  • the direction 20 is the dotted line 20 in the figure; the bit line structure 200 connects a row of bit line contact points of the active region 101.
  • a bit line contact layer 120 is formed on the top surface of the substrate 100.
  • the bit line contact layer 120 covers the bottom dielectric layer 120 and fills the bit line contact opening 111.
  • FIG. 4 shows the bit line structure 200 that needs to be formed later Position, in any cross section along the direction 10 in which the word line structure extends, the bit lines connected to the active region 101 and the bit lines located on the bottom dielectric layer 110 are alternately arranged.
  • the bit line contact layer 120 includes a first bit line contact layer 122 and a second bit line contact layer 123.
  • the first bit line contact layer 122 filling the bit line contact opening 111 is formed, the first bit line contact layer 122 covers the bottom dielectric layer 110, and the top surface of the first bit line contact layer 122 on the top of the bottom dielectric layer 110 forms a barrier.
  • Layer 124, a second bit line contact layer 123 is formed on the top surface of the barrier layer 124 and the top surface of the first bit line contact layer 122, and the second bit line contact layer 123 covers the first bit line contact layer 122 and the barrier layer 124.
  • the barrier layer 124 in the bit line contact layer 120 By forming the barrier layer 124 in the bit line contact layer 120, the conductive layer in the bit line structure on the top of the bottom dielectric layer formed by subsequent etching and the barrier layer have the same height, thereby reducing the height difference of the conductive layer in different bit line structures , So that the connection of the conductive layer is wavy, so as to improve the stability of the formed memory structure.
  • the material of the barrier layer 124 is the same as the material of the bottom dielectric layer 110. In other embodiments, it is only necessary to ensure that the material of the barrier layer is different from the material of the bit line contact layer to ensure that the bit line contact layer is etched. When the barrier layer is etched.
  • both the first bit line contact layer 122 and the second bit line contact layer 123 are made of polysilicon material, which is used for the subsequent formation of the bit line structure 200 to connect to the active area in the substrate 100 through the bit line contact opening 111 101.
  • bit line contact layer 120 can also be formed with a single-layer structure. This embodiment does not limit the specific number of layers of the bit line contact layer 120. Those skilled in the art will know that the above embodiment The objective of the multi-layer embodiment provided is that the subsequently formed conductive layers have a small drop at different heights, and the connection of the conductive layer forms a wavy line to improve the stability of the memory.
  • bit line contact layer 120 is etched to form the bit line contact layer 121 of different heights.
  • the reasons for forming the bit line contact layer 121 of different heights include: after the bit line contact layer 121 is used to subsequently form a conductive layer, the conductive layer is located at a different height.
  • a first photolithography mask layer 130 is formed on the top surface of the bit line contact layer 120, and a photoresist 140 is formed on the top surface of the first photolithography mask layer 130.
  • the first photolithography mask layer 130 is patterned to form patterns 131 arranged at intervals in a predetermined direction.
  • the pattern 131 arranged at intervals includes: elongated strips arranged at intervals and extending or arranged at intervals in the form of discrete ellipses or rectangles.
  • the first photolithography mask layer 130 is patterned.
  • the spaced patterns 131 formed by the patterned first photolithography mask layer 130 are in a preset direction, and there is an angle ⁇ between the preset direction and the extending direction 10 of the word line structure, and the range of ⁇ is 0 ⁇ ⁇ 90° (refers to the angle ⁇ of the straight line refers to the angle between the straight line 40 and the straight line 10, if it is the angle of the ray, then the range of ⁇ is 0 ⁇ 360° and ⁇ 90°, ⁇ 180° and ⁇ ⁇ 270°). In this embodiment, ⁇ is 25° as an example.
  • ⁇ can be 10°, 20°, 30°, 40°, 50°, 60°, 70°, or 80° Wait.
  • the circle 401 in the figure represents the bit line contact points covered by the spaced patterns 131. Those skilled in the art can see that in the cross-sectional direction of the dotted line 30 and the broken line 31, the bit line contact points covered by the spaced patterns 131 and The bit line contact points that are not covered by the pattern 131 arranged at intervals are alternately arranged.
  • the spaced patterns 131 are arranged at intervals and extend as an example for illustration. In other embodiments, the spaced patterns 131 may also be discrete ellipses or rectangles arranged at intervals. .
  • bit line contact layer 120 is etched based on the spaced patterns 131 to form bit line contact layers 121 of different heights.
  • the pattern 131 and the barrier layer 124 arranged at intervals are removed.
  • the direction of the dashed line 30 and the direction of the dashed line 31 in the figure are the two cross-sectional positions shown in FIG. 3 for those skilled in the art to understand the principle of the present application.
  • FIG. 9 shows a schematic cross-sectional view in the direction of the dashed line 30 and the direction of the dashed line 31.
  • the bit line contact layer 121 is located at different heights;
  • the bit line contact layer 121 is located at different heights, and the bit line contact layer 121 at the position of the bit line contact opening 111 is located at the first height convex portion and located at The recesses of the second height are alternately arranged.
  • a mask can be further formed to further etch the bit line contact layers of different heights, so that the height of the top surface of the remaining bit line contact layers can be alternately arranged according to a preset height order.
  • a conductive layer 140 is formed on the top surface of the bit line contact layer 121 of different heights.
  • a conductive film 141 is formed on the top surface of the bit line contact layer 121 of different heights.
  • the conductive film 141 is etched (refer to FIG. 10), and a conductive layer 140 of uniform thickness is formed on the top surface of the bit line contact layer 121 at different heights.
  • a conductive layer 140 of uniform thickness is formed on the top surface of the bit line contact layer 121 at different heights.
  • the thickness of the conductive layer on the top surface of the bit line contact layer at different heights can be different, but it is necessary to ensure that the top surface of the conductive layer is at a different height, so that the conductive layer between different bit line structures is connected.
  • Oblique lines are used to increase the spacing of the conductive layers between the bit line structures without changing the arrangement of the bit line structures.
  • the top surface is located at different heights, and the connection is wave-shaped; in the direction 10 where the word line structure extends, the top surface is located at different heights, and the connection is wave-shaped .
  • the conductive layer 140 is formed of one conductive material or multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, tungsten, and tungsten composites.
  • a top dielectric layer 150 is formed on the top surface of the conductive layer 140.
  • the dielectric film is topped on the top surface of the conductive layer, and the surface of the top dielectric film is planarized to form the top dielectric layer 150, and the top surface of the top dielectric layer 150 has the same height.
  • a chemical mechanical polishing method is used to planarize the top surface of the top dielectric film.
  • the chemical mechanical polishing process has a higher removal rate than the etching process, which is beneficial to shorten the process cycle.
  • the material of the top dielectric layer 150 includes materials such as silicon nitride, silicon oxynitride, or silicon oxide.
  • the material of the top dielectric layer 150 is an insulating material containing nitrogen, that is, the top dielectric layer 150 adopts Silicon nitride material.
  • part of the top dielectric layer 150, the conductive layer 140 and the bit line contact layer 121 of different heights are sequentially etched to form a separate bit line structure 200.
  • connection lines of the conductive layer 140 in the discrete bit line structure 200 are wavy.
  • adjacent discrete bit line structures 200 are The height of the conductive layer 140 is different, and the connecting line of the conductive layer 140 is wave-shaped.
  • the method for forming a memory forms bit line contact layers of different heights so that the conductive layers formed on the top surface of the bit line contact layer are located at different heights;
  • the top surface of the conductive layer In the direction in which the word line structure extends, the top surface of the conductive layer is located at the same height, and in the direction in which the word line structure extends, the top surface of the conductive layer is located at different heights, that is, a discrete bit line structure formed subsequently
  • the conductive layers are located at different heights, and the conductive layers in different bit line structures are located at different heights; on the basis of not changing the arrangement of the bit line structure, the conductive layers in adjacent discrete bit line structures are located at Compared with the conductive layer at the same height, the distance between the conductive layers of different heights and different heights is changed from the horizontal distance to the oblique distance, which increases the distance between the conductive layers in the bit line structure and reduces the bit line structure.
  • the second embodiment of the present application relates to a method for forming a memory.
  • the difference from the first embodiment is that this embodiment has another method of forming a photolithography mask.
  • the method of formation will be described in detail.
  • a second photolithography mask layer is formed on the top surface of the bit line contact layer.
  • This embodiment provides two methods for forming the second photolithography mask layer, which are specifically as follows:
  • the first method for forming the second photolithography mask layer 500 the formed second photolithography mask layer 500 is located in the extending direction 10 of the word line structure, and is adjacent to each other in the direction 10 perpendicular to the extending direction of the word line structure. There are gaps between the second photolithography mask layers 500, and the gaps expose the gaps between at least two columns of word line structures 102 in the substrate at the bottom of the bit line contact layer.
  • the second method of forming the second photolithography mask layer 501 forming a second photolithography mask layer 501, the second photolithography mask layer 501 covers two bit line contact points in the gap between the two columns of word line structure 102 502, and in the direction 10 where the word line structure extends, the second photolithography mask layer 501 is sequentially arranged.
  • the second method for forming the second photolithography mask layer 501 is adopted, and part of the bit line contact layer is etched based on the gap to form bit line contact layers of different heights, and then the second photolithography mask layer is removed.
  • the rest of the process steps are the same as those in the first embodiment. Refer to FIG. 15 for the bit line structure 200 formed according to the mask forming method provided in this embodiment.
  • the conductive layer in the bit line structure 200 formed in the bit line contact point covered by the second photolithography mask layer is located at a higher height, while the bit line contact point not covered by the second photolithography mask layer is formed
  • the conductive layer in the bit line structure 200 is located at a lower height (not shown in the figure), at this time it is located in the direction 10 where the word line structure extends, and the conductive layer in the bit line structure 200 on the bit line contact point is located at the same height
  • the barrier layer is formed in the formation of the bit line contact layer, the height of the bit line structure on the bottom dielectric layer 110 and the bit line structure on the bit line contact point are different.
  • the height of the conductive layer in different bit line structures 200 is different; in the extending direction 20 of the bit line structure, due to the distribution of the second photolithography mask layer, the same bit line structure The height of the conductive layer in 200 is different.
  • the method for forming a memory forms bit line contact layers of different heights so that the conductive layers formed on the top surface of the bit line contact layers are located at different heights;
  • the top surface of the conductive layer In the direction in which the word line structure extends, the top surface of the conductive layer is located at the same height, and in the direction in which the word line structure extends, the top surface of the conductive layer is located at different heights, that is, a discrete bit line structure formed subsequently
  • the conductive layers are located at different heights, and the conductive layers in different bit line structures are located at different heights; on the basis of not changing the arrangement of the bit line structure, the conductive layers in adjacent discrete bit line structures are located at Compared with the conductive layer at the same height, the distance between the conductive layers of different heights and different heights is changed from the horizontal distance to the oblique distance, which increases the distance between the conductive layers in the bit line structure and reduces the bit line structure.
  • the first embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the first embodiment.
  • the related technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Correspondingly, the related technical details mentioned in this embodiment can also be applied to the first embodiment.
  • the third embodiment of the present application relates to a memory.
  • the memory includes: a substrate 100 including at least a word line structure 102 and an active region 101; a bottom dielectric layer 110, the bottom dielectric layer 110 is located on the top of the substrate 100, and the bottom dielectric layer 110 has a bit line contact opening 111,
  • the line contact opening 111 exposes the active area 101 in the substrate; the discrete bit line structure 200, the top surface of the bit line structure 200 is at the same height, the bit line structure 200 includes: the top 110 of the bottom dielectric layer and the bit line contact opening 111
  • the layers 140 are located at different heights, and in the direction 10 in which the word line structure extends, the conductive layers 140 in adjacent bit line structures are located at different heights.
  • the substrate 100 also includes other memory structures other than the word line structure 102 and the active region 101, such as shallow trench isolation structures. Since other memory structures are not related to the core technology of this application, here It is not repeated here; those skilled in the art can understand that the substrate 100 also includes other memory structures besides the word line structure 102 and the active area 101 for normal operation of the memory.
  • the thickness of the conductive layer 140 is the same. In other embodiments, the thickness of the conductive layer 140 on the top surface of the bit line contact layer 121 at different heights may be different, but it is necessary to ensure that the top surface of the conductive layer 140 is located at a different height. Height, so that the connecting lines of the conductive layers between different bit line structures are oblique, so that the spacing of the conductive layers between the bit line structures is increased without changing the arrangement of the bit line structures.
  • the connections of the conductive layer 140 are wave-shaped, that is, in the same bit line structure 200, the conductive layers 140 are located at different heights.
  • the conductive layers 140 in different bit line structures 200 are located at the same height, and the preset direction and the extending direction 10 of the word line structure have an angle ⁇ , and the range of ⁇ is 0 ⁇ 90° (referring to The angle ⁇ of the straight line refers to the angle between the straight line 40 and the straight line 10, if it is a ray included angle, the range of ⁇ is 0 ⁇ 360° and ⁇ 90°, ⁇ 180° and ⁇ 270°).
  • the conductive layer on the top surface of the bit line contact layer is located at different heights; in the direction perpendicular to the extending direction of the word line structure, the top surface of the conductive layer Located at the same height, in the direction in which the word line structure extends, the top surface of the conductive layer is located at different heights, that is, in the discrete bit line structure formed subsequently, the conductive layers in the same bit line structure are located at different heights and different positions.
  • the conductive layers in the line structure are located at different heights; on the basis of not changing the arrangement of the bit line structure, the conductive layers in the adjacent discrete bit line structures are located at different heights, and the conductive layers at different heights are compared with those at the same height.
  • Conductive layer the distance between the conductive layers is changed from the horizontal distance to the oblique distance, thereby increasing the spacing of the conductive layers in the bit line structure; thereby reducing the parasitic capacitance between the bit line structures, and increasing the saturation current of the memory
  • the method for forming the memory provided by this embodiment has a simple process, low cost, and easy implementation.
  • the first embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the first embodiment.
  • the related technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Correspondingly, the related technical details mentioned in this embodiment can also be applied to the first embodiment.

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Abstract

提供了一种存储器的形成方法及存储器。提供基底(100)，基底(100)中至少包括字线结构(102)以及有源区(101)，以及位于基底(100)顶部表面的底介质层(110)和位线接触层(121)，底介质层(110)中具有位线接触开口(111)，位线接触开口(111)暴露出基底(100)中的有源区(101)，位线接触层(121)覆盖底介质层(110)且填充位线接触开口(111)；刻蚀部分位线接触层(121)，形成不同高度的位线接触层(121)；形成导电层(140)，于垂直于字线结构(102)延伸的方向上，导电层(140)顶部表面位于不同高度，于字线结构(102)延伸的方向上，导电层(140)顶部表面位于不同高度；形成顶介质层(150)；刻蚀形成分立的位线结构(200)。

Description

存储器的形成方法及存储器
交叉引用
本申请要求于2020年06月22日递交的名称为“存储器的形成方法及存储器”、申请号为202010575406.8的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体技术领域，特别涉及一种存储器的形成方法及存储器。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，DRAM)的特征尺寸和线宽不断减小，相邻位线结构之间间距也变得越来越小。而相邻位线结构之间间距变小，会导致相邻位线结构之间的寄生电容不断增大，影响DRAM阵列区的饱和电流，进而影响DRAM的运行效率。
在DRAM的线宽不断减小的情况下，如何增大位线结构之间的间距，是当前亟待解决的问题。
发明内容
本申请部分实施例的目的在于提供一种存储器的形成方法及存储器，通 过形成位线结构中的导电层位于不同高度，在不改变位线结构排布方式的基础上，增大位线结构中导电层之间的间距。
本申请实施例提供了一种存储器的形成方法，包括：提供基底，基底中至少包括字线结构以及有源区，以及位于基底顶部表面的底介质层和位线接触层，底介质层中具有位线接触开口，位线接触开口暴露出基底中的有源区，位线接触层覆盖底介质层且填充位线接触开口；刻蚀部分位线接触层，形成不同高度的位线接触层；在位线接触层顶部表面形成导电层，于垂直于字线结构延伸的方向上，导电层顶部表面位于不同高度，于字线结构延伸的方向上，所述导电层顶部表面位于不同高度；在导电层顶部表面形成顶介质层；依次刻蚀部分顶介质层、导电层和位线接触层，形成分立的位线结构。
另外，刻蚀部分位线接触层，形成不同高度的位线接触层，包括：在位线接触层顶部表面形成第一光刻掩膜层；图形化第一光刻掩膜层，形成于预设方向上间隔排列的图形；预设方向与字线结构延伸的方向存在夹角α，α的范围为0<α<90°；基于间隔排列的图形刻蚀部分位线接触层，形成不同高度的位线接触层；去除间隔排列的图形。
另外，间隔排列的图形包括：间隔排列且延伸的长条或者呈分立的椭圆或长方形间隔排列。
另外，刻蚀部分位线接触层，形成不同高度的位线接触层，包括：在位线接触层顶部表面形成第二光刻掩膜层；第二光刻掩膜层位于字线结构延伸的方向上，且在垂直于字线结构延伸的方向上，相邻第二光刻掩膜层之间具有间隙；其中，间隙暴露出的位线接触层底部的基底中至少包含两列字线结构间的空隙；基于间隙刻蚀部分位线接触层，形成不同高度的位线接触层；去除第二 光刻掩膜层。
另外，在位线接触层顶部表面形成导电层，包括：在位线接触层顶部表面形成导电膜；刻蚀导电膜，在位于不同高度的位线接触层顶部表面形成厚度一致的导电层。通过形成厚度一致的导电层，确保位于不同高度的位线接触层顶部表面的导电层位于不同高度。
另外，在导电层顶部表面形成顶介质层，包括：在导电层顶部表面形成顶介质膜；对顶介质膜顶部表面进行平坦化处理形成顶介质层，顶介质层的顶部表面高度一致。
另外，填充位线接触开口，且覆盖底介质层的位线接触层，包括：形成填充位线接触开口的第一位线接触层，第一位线接触层覆盖底介质层；在底介质层顶部的第一位线接触层顶部表面形成阻挡层；在阻挡层顶部表面以及第一位线接触层顶部表面形成第二位线接触层，第二位线接触层覆盖第一位线接触层和阻挡层。通过在位线接触层中形成阻挡层，使得刻蚀位于底介质层顶部的位线结构中的导电层与阻挡层的高度一致，降低不同位线结构中导电层的高度落差，使得导电层的连线呈波浪形，以提高存储器结构的稳定性。
本申请实施例还提供了一种存储器，包括：基底，基底中至少包括字线结构以及有源区；底介质层，底介质层位于基底顶部，且底介质层中具有位线接触开口，位线接触开口暴露出基底中的有源区；分立的位线结构，位线结构的顶部表面于同一高度，位线结构包括：位于底介质层顶部以及位线接触开口中位线接触层，位于位线接触层顶部的导电层，以及位于导电层顶部的顶介质层；其中，在位线结构延伸的方向上，同一位线结构中的导电层位于不同高度，且在字线结构延伸的方向上，相邻位线结构中的导电层位于不同高度。
另外，在位线结构延伸的方向上，导电层的连线呈波浪形。降低不同位线结构中导电层的高度落差，以提高存储器结构的稳定性。
另外，在预设方向上，不同位线结构中的导电层位于同一高度，预设方向与字线结构延伸的方向存在夹角α，α的范围为0＜α＜90°。
本申请实施例现对于现有技术而言，通过形成不同高度的位线接触层，使得在位线接触层顶部表面形成的导电层位于不同高度；于垂直于所述字线结构延伸的方向上，所述导电层顶部表面位于同一高度，于所述字线结构延伸的方向上，所述导电层顶部表面位于不同高度，即后续形成的分立的位线结构中，同一位线结构中的导电层位于不同高度，不同位线结构中导电层位于不同高度；在不改变位线结构排布方式的基础上，相邻分立的位线结构中的导电层位于不同高度，位于不同高度的导电层相比于位于同一高度的导电层，导电层之间的距离由水平距离变为倾斜距离，从而增大了位线结构中导电层的间距；进而减少了位线结构之间的寄生电容，且增大了存储器的饱和电流，同时本实施例提供的存储器的形成方法流程简单、成本较低、容易实施。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例中的图1至图12为本申请第一实施例提供的存储器的形成方法各步骤对应的结构示意图；
图13为本申请第一实施例形成的存储器的剖面示意图；
图14为本申请第二实施例提供的存储器的形成方法中另一种图形化方式对应的结构示意图；
图15为本申请第二实施例形成的存储器的剖面示意图。
具体实施方式
目前，随着动态随机存取存储器的特征尺寸和线宽不断减小，相邻位线结构之间间距也变得越来越小。而相邻位线结构之间间距变小，会导致相邻位线结构之间的寄生电容不断增大，影响DRAM阵列区的饱和电流，进而影响DRAM的运行效率。
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种存储器的形成方法，包括：提供基底，基底中至少包括字线结构以及有源区，以及位于基底顶部表面的底介质层和位线接触层，底介质层中具有位线接触开口，位线接触开口暴露出基底中的有源区，位线接触层覆盖底介质层且填充位线接触开口；刻蚀部分位线接触层，形成不同高度的位线接触层；在位线接触层顶部表面形成导电层，于垂直于字线结构延伸的方向上，导电层顶部表面位于不同高度，于字线结构延伸的方向上，所述导电层顶部表面位于不同高度；在导电层顶部表面形成顶介质层；依次刻蚀部分顶介质层、导电层和位线接触层，形成分立的位线结构。
图1至图12为本申请第一实施例提供的存储器的形成方法各步骤对应的结构示意图，下面对本实施例的存储器的形成方法进行具体说明。
结合参考图1至图5，提供基底100，基底100中至少包括字线结构102以及有源区101，以及位于基底100顶部表面的底介质层110和位线接触层120，介质层中具有位线接触开口111，位线接触开口111暴露出基底100中的有源区101，位线接触层120覆盖底介质层110并填充位线接触开口111。
以下将结合附图对图1至图5进行详细说明。
参考图1，提供基底100，基底100中至少包括字线结构102以及有源区101。
图1中示出了字线结构延伸的方向10，即图中虚线10。
多个有缘区101相互平行间隔排布，且第i列有源区101与第i+3列有源区101在垂直于字线结构延伸的方向10上，不同有源区101位于同一水平位置；第i列有源区101与相邻列(第i+1列和第i-1列)的有源区101在垂直于字线结构延伸的方向10上位于不同水平位置。交替排布的字线结构102分隔开的有源区101的中部为位线接触点，用于连接后续形成的位线结构。
需要说明的是，基底100中还包括除字线结构102和有源区101外的其他存储器结构，例如浅沟槽隔离结构等，由于其他存储器结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除字线结构102和有源区101外的其他存储器结构，用于存储器的正常运行。
基底100的材料可以包括蓝宝石、硅、碳化硅、砷化镓、氮化铝或者氧化锌等；在本实施例中基底100采用硅材料形成，本领域技术人员清楚，本实施例采用硅材料作为基底100是为了方便本领域技术人员对后续形成方法的理解，并不构成限定，在实际应用过程中，可以根据需求选择合适的基底的材料。
参考图2至图5，在基底100顶部表面形成底介质层110和位线接触层120，底介质层110中具有位线接触开口111，位线接触开口111暴露出基底100中的有源区101，位线接触层120覆盖底介质层110并填充位线接触开口111。
参考图2，于基底100顶部表面形成底介质层110，底介质层110中具有位线接触开口111，位线接触开口111用于暴露出基底100中的有源区101。具体地，位线接触开口111用于暴露出位线接触点，即暴露出被字线结构102分隔开的有源区101的中部。
底介质层110用于隔绝非位线接触点位置的位线结构200与有源区101相接触。本实施例中，底介质层的材料为氮化硅，在其他实施例中，底介质层的材料也可以为氧化硅或氮氧化硅等绝缘材料。
参考图3，图3为基底100的俯视示意图，图3基于图2形成底介质层110的基础上给出了后续需要形成位线结构200的位置，图3中示出了位线结构延伸的方向20，即图中虚线20；位线结构200连接一列有源区101的位线接触点。
参考图4，于基底100顶部表面形成的位线接触层120，位线接触层120覆盖底介质层120并填充位线接触开口111，图4中给出了后续需要形成的位线结构200的位置，在任意沿字线结构延伸的方向10上的剖面中，与有源区101连接的位线和位于底介质层110上的位线交替排布。
在本实施例中，位线接触层120包括第一位线接触层122和第二位线接触层123。具体地，形成填充位线接触开口111的第一位线接触层122，第一位线接触层122覆盖底介质层110，在底介质层110顶部的第一位线接触层122顶部表面形成阻挡层124，在阻挡层124顶部表面以及第一位线接触层122顶 部表面形成第二位线接触层123，第二位线接触层123覆盖第一位线接触层122和阻挡层124。通过在位线接触层120中形成阻挡层124，使得后续刻蚀形成位于底介质层顶部的位线结构中的导电层与阻挡层的高度一致，从而降低不同位线结构中导电层的高度落差，使得导电层的连线呈波浪形，以提高形成的存储器结构的稳定性。
本实施例中，阻挡层124的材料与底介质层110的材料相同，在其他实施例中，只需保证阻挡层的材料与位线接触层的材料不同，以保证在刻蚀位线接触层时，阻挡层被刻蚀。另外，本实施例中，第一位线接触层122和第二位线接触层123都采用多晶硅材料，用于后续形成的位线结构200通过位线接触开口111连接基底100中的有源区101。
需要说明的是，在其他实施例中，位线接触层120也可以采用单层结构形成，本实施例并不对位线接触层120的具体层数进行限定，本领域技术人员可知，上述实施例提供的多层实施例的方案目的在于后续形成的导电层位于不同高度的落差较小，导电层的连线构成一条波浪线以提升存储器的稳定性。
参考图5至图8，刻蚀部分位线接触层120，形成不同高度的位线接触层121。
形成不同高度的位线接触层121的原因包括：位线接触层121用于后续形成导电层后，导电层位于不同的高度。
具体地，参考图5，在位线接触层120顶部表面形成第一光刻掩膜层130，并在第一光刻掩膜层130顶部表面形成光刻胶140。
参考图6，图形化第一光刻掩膜层130，形成于预设方向上间隔排列的图形131。间隔排列的图形131包括：间隔排列且延伸的长条或者呈分立的椭圆 或长方形间隔排列。
基于所述光刻胶，图形化第一光刻掩膜层130。参考图7，图形化第一光刻掩膜层130形成的间隔排列的图形131于预设方向上，预设方向与字线结构延伸的方向10存在夹角α，α的范围为0<α<90°(指直线的夹角α指代直线40与直线10的夹角，如为射线夹角，那么α的范围为0<α<360°且α≠90°、α≠180°且α≠270°)，本实施例以α为25°为例进行图示，在其他实施例中α可以为10°、20°、30°、40°、50°、60°、70°或80°等。图中圆形401表示间隔排列的图形131覆盖的位线接触点，本领域技术人员可以看出，在虚线30以及虚线31的截面方向上，被间隔排列的图形131覆盖的位线接触点与未被间隔排列的图形131覆盖的位线接触点交替排布。
需要说明的是，本实施例中，间隔排列的图形131以间隔排列且延伸的长条为例进行举例说明，在其他实施例中，间隔排列的图形131还可以为分立的椭圆或长方形间隔排列。
参考图8，基于间隔排列的图形131刻蚀部分位线接触层120，形成不同高度的位线接触层121。
参考图9，去除间隔排列的图形131以及阻挡层124。
图中虚线30方向和虚线31方向为图3给出的两个剖面位置，供本领域技术人员了解本申请的原理。
图9给出了虚线30方向上和虚线31方向上的剖面示意图，在垂直于字线结构延伸的方向10上(两幅图所在的同一竖直位置)，位线接触层121位于不同高度；于字线结构延伸的方向10上(图示剖面方向)，位线接触层121位于不同高度，且于位线接触开口111位置上的位线接触层121中位于第一高 度凸起部分和位于第二高度的凹陷部分交替排布。
在其他实施例中，还可以继续形成掩膜，对不同高度的位线接触层进行进一步刻蚀，使得剩余位线接触层顶部表面的高度可以按照预设的高度排序进行交替排布。
参考图10至图11，在不同高度的位线接触层121顶部表面形成导电层140。
具体地，参考图10，在不同高度的位线接触层121顶部表面形成导电膜141。
参考图11，刻蚀导电膜141(参考图10)，在位于不同高度的位线接触层121顶部表面形成厚度一致的导电层140。通过形成厚度一致的导电层140，确保位于不同高度的位线接触层121顶部表面的导电层140位于不同高度。
在其他实施例中，位于不同高度的位线接触层顶部表面的导电层的厚度可以不同，但需要保证导电层的顶部表面位于不同高度，从而使得不同位线结构之间的导电层的连线呈斜线，从而在不改变位线结构排布方式的基础上，增大位线结构间导电层的间距。
形成到导电层140于垂直于字线结构延伸的方向10上，顶部表面位于不同高度，且连线波浪形；于字线结构延伸的方向10上，顶部表面位于不同高度，且连线波浪形。
本实施例中，导电层140由一种导电材料或者多种导电材料形成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
参考图12，在导电层140顶部表面形成顶介质层150。
具体地，在导电层顶部表面顶介质膜，对顶介质膜表面进行平坦化处理 处理形成顶介质层150，顶介质层150顶部表面高度一致。
具体地，采用化学机械研磨的方式对顶介质膜顶部表面进行平坦化处理，化学机械研磨工艺相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
本实施例中，顶介质层150的材料包括氮化硅、氮氧化硅或氧化硅等材料，在本实施例中，顶介质层150的材料为含氮的绝缘材料，即顶介质层150采用氮化硅材料。
参考图13，依次刻蚀部分顶介质层150、导电层140和不同高度的位线接触层121，形成分立的位线结构200。
于垂直于字线结构延伸的方向10上，分立的位线结构200中的导电层140的连线呈波浪形，于字线结构延伸的方向10上，相邻分立的位线结构200中的导电层140的高度不同，且导电层140的连线呈波浪形。
相对于现有技术而言，本申请第一实施例提供的存储器的形成方法，通过形成不同高度的位线接触层，使得在位线接触层顶部表面形成的导电层位于不同高度；于垂直于所述字线结构延伸的方向上，所述导电层顶部表面位于同一高度，于所述字线结构延伸的方向上，所述导电层顶部表面位于不同高度，即后续形成的分立的位线结构中，同一位线结构中的导电层位于不同高度，不同位线结构中导电层位于不同高度；在不改变位线结构排布方式的基础上，相邻分立的位线结构中的导电层位于不同高度，位于不同高度的导电层相比于位于同一高度的导电层，导电层之间的距离由水平距离变为倾斜距离，从而增大了位线结构中导电层的间距；进而减少了位线结构之间的寄生电容，且增大了存储器的饱和电流，同时本实施例提供的存储器的形成方法流程简单、成本较低、容易实施。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请第二实施例涉及一种存储器的形成方法，与第一实施例不同的是，本实施例另外一种形成光刻掩膜的方式，参考图14以及图15，下面对本实施例的存储器的形成方法进行具体说明。
在位线接触层顶部表面形成第二光刻掩膜层。
本实施例给出了两种第二光刻掩膜层的形成方式，具体如下：
第一种第二光刻掩膜层500的形成方式：形成的第二光刻掩膜层500位于字线结构延伸的方向10上，且在垂直于字线结构延伸的方向10上，相邻第二光刻掩膜层500之间具有间隙，间隙暴露出位线接触层底部的基底中至少暴露两列字线结构102间的空隙。
第二种第二光刻掩膜层501的形成方式：形成第二光刻掩膜层501，第二光刻掩膜层501覆盖两列字线结构102间隙空隙中的两个位线接触点502，且在字线结构延伸的方向10上，第二光刻掩膜层501依次排布。
本实施例采用上述第二种第二光刻掩膜层501的形成方式，并基于间隙刻蚀部分位线接触层，形成不同高度的位线接触层，然后去除第二光刻掩膜层，其余工艺步骤同第一实施例，按照本实施例提供的掩膜形成方法形成的位线结构200参考图15。
被第二光刻掩膜层覆盖的位线接触点中形成的位线结构200中的导电层位于较高的高度，而未被第二光刻掩膜层覆盖的位线接触点钟形成的位线结构 200中的导电层位于较低的高度(图中未图示)，此时位于字线结构延伸的方向10上，位线接触点上的位线结构200中的导电层位于同一高度，但由于在形成位线接触层中形成有阻挡层，位于底介质层110上的位线结构与位于位线接触点上的位线结构的高度不同。此时于字线结构延伸的方向10上，不同位线结构200中的导电层的高度不同；在位线结构延伸的方向20上，由于第二光刻掩膜层的分布，相同位线结构200中的导电层的高度不同。
相对于现有技术而言，本申请第二实施例提供的存储器的形成方法，通过形成不同高度的位线接触层，使得在位线接触层顶部表面形成的导电层位于不同高度；于垂直于所述字线结构延伸的方向上，所述导电层顶部表面位于同一高度，于所述字线结构延伸的方向上，所述导电层顶部表面位于不同高度，即后续形成的分立的位线结构中，同一位线结构中的导电层位于不同高度，不同位线结构中导电层位于不同高度；在不改变位线结构排布方式的基础上，相邻分立的位线结构中的导电层位于不同高度，位于不同高度的导电层相比于位于同一高度的导电层，导电层之间的距离由水平距离变为倾斜距离，从而增大了位线结构中导电层的间距；进而减少了位线结构之间的寄生电容，且增大了存储器的饱和电流，同时本实施例提供的存储器的形成方法流程简单、成本较低、容易实施。
由于第一实施例与本实施例相互对应，因此本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本申请第三实施例涉及一种存储器。
参考图13，以下将结合附图对本实施例提供的存储器进行详细说明，与第一实施例相同或相应的部分，以下将不做详细赘述。
存储器，包括：基底100，基底100中至少包括字线结构102以及有源区101；底介质层110，底介质层110位于基底100顶部，且底介质层110中具有位线接触开口111，位线接触开口111暴露出基底中的有源区101；分立的位线结构200，位线结构200的顶部表面于同一高度，位线结构200包括：位于底介质层顶部110以及位线接触开口111中位线接触层121，位于位线接触层121顶部的导电层140，以及位于导电层140顶部的顶介质层150；其中，在位线结构延伸的方向20上，同一位线结构中的导电层140位于不同高度，且在字线结构延伸的方向10上，相邻位线结构中的导电层140位于不同高度。
需要说明的是，基底100中还包括除字线结构102和有源区101外的其他存储器结构，例如浅沟槽隔离结构等，由于其他存储器结构并不涉及到本申请的核心技术，在此不过多进行赘述；本领域技术人员可以理解基底100中还包括除字线结构102和有源区101外的其他存储器结构，用于存储器的正常运行。
在本实施例中，导电层140的厚度一致，在其他实施例中，位于不同高度的位线接触层121顶部表面的导电层140的厚度可以不同，但需要保证导电层140的顶部表面位于不同高度，从而使得不同位线结构之间的导电层的连线呈斜线，从而在不改变位线结构排布方式的基础上，增大位线结构间导电层的间距。
在本实施例中，在位线结构延伸的方向20上，导电层140的连线呈波浪 形，即同一位线结构200中，导电层140位于不同高度。且于预设方向上，不同位线结构200中导电层140位于同一高度，预设方向与字线结构延伸的方向10存在夹角α，所述α的范围为0＜α＜90°(指直线的夹角α指代直线40与直线10的夹角，如为射线夹角，那么α的范围为0<α<360°且α≠90°、α≠180°且α≠270°)。
与现有技术相比，通过不同高度的位线接触层，使得在位线接触层顶部表面的导电层位于不同高度；于垂直于所述字线结构延伸的方向上，所述导电层顶部表面位于同一高度，于所述字线结构延伸的方向上，所述导电层顶部表面位于不同高度，即后续形成的分立的位线结构中，同一位线结构中的导电层位于不同高度，不同位线结构中导电层位于不同高度；在不改变位线结构排布方式的基础上，相邻分立的位线结构中的导电层位于不同高度，位于不同高度的导电层相比于位于同一高度的导电层，导电层之间的距离由水平距离变为倾斜距离，从而增大了位线结构中导电层的间距；进而减少了位线结构之间的寄生电容，且增大了存储器的饱和电流，同时本实施例提供的存储器的形成方法流程简单、成本较低、容易实施。
由于第一实施例与本实施例相互对应，因此本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本 申请的精神和范围。

Claims (10)

  1. 一种存储器的形成方法，包括：
    提供基底，所述基底中至少包括字线结构以及有源区，以及位于所述基底顶部表面的底介质层和位线接触层，所述底介质层中具有位线接触开口，所述位线接触开口暴露出所述基底中的所述有源区，所述位线接触层覆盖所述底介质层且填充所述位线接触开口；
    刻蚀部分所述位线接触层，形成不同高度的所述位线接触层；
    在所述位线接触层顶部表面形成导电层，于垂直于所述字线结构延伸的方向上，所述导电层顶部表面位于不同高度，于所述字线结构延伸的方向上，所述导电层顶部表面位于不同高度；
    在所述导电层顶部表面形成顶介质层；
    依次刻蚀部分所述顶介质层、所述导电层和所述位线接触层，形成分立的位线结构。
  2. 根据权利要求1所述的存储器的形成方法，其中，所述刻蚀部分所述位线接触层，形成不同高度的所述位线接触层，包括：
    在所述位线接触层顶部表面形成第一光刻掩膜层；
    图形化所述第一光刻掩膜层，形成于预设方向上间隔排列的图形；
    所述预设方向与所述字线结构延伸的方向存在夹角α，所述α的范围为0<α<90°；
    基于所述间隔排列的图形刻蚀部分所述位线接触层，形成不同高度的所述位线接触层；去除所述间隔排列的图形。
  3. 根据权利要求2所述的存储器的形成方法，其中，所述间隔排列的图形包括：间隔排列且延伸的长条或者呈分立的椭圆或长方形间隔排列。
  4. 根据权利要求1所述的存储器的形成方法，其中，所述刻蚀部分所述位线接触层，形成不同高度的所述位线接触层，包括：
    在所述位线接触层顶部表面形成第二光刻掩膜层；
    所述第二光刻掩膜层位于所述字线结构延伸的方向上，且在垂直于所述字线结构延伸的方向上，相邻第二光刻掩膜层之间具有间隙；
    其中，所述间隙暴露出的位线接触层底部的基底中至少包含两列所述字线结构间的空隙；
    基于所述间隙刻蚀部分所述位线接触层，形成不同高度的所述位线接触层；
    去除所述第二光刻掩膜层。
  5. 根据权利要求1所述的存储器的形成方法，其中，所述在所述位线接触层顶部表面形成导电层，包括：
    在所述位线接触层顶部表面形成导电膜；
    刻蚀所述导电膜，在位于不同高度的所述位线接触层顶部表面形成厚度一致的所述导电层。
  6. 根据权利要求1所述的存储器的形成方法，其中，所述在所述导电层顶部表面形成顶介质层，包括：
    在所述导电层顶部表面形成顶介质膜；
    对所述顶介质膜顶部表面进行平坦化处理形成所述顶介质层，所述顶介质层的顶部表面高度一致。
  7. 根据权利要求1-6任一项所述的存储器的形成方法，其中，所述填充所述位线接触开口，且覆盖所述底介质层的位线接触层，包括：
    形成填充所述位线接触开口的第一位线接触层，所述第一位线接触层覆盖所述底介质层；
    在所述底介质层顶部的第一位线接触层顶部表面形成阻挡层；
    在所述阻挡层顶部表面以及所述第一位线接触层顶部表面形成第二位线接触层，所述第二位线接触层覆盖所述第一位线接触层和所述阻挡层。
  8. 一种存储器，其中，包括：
    基底，所述基底中至少包括字线结构以及有源区；
    底介质层，所述底介质层位于所述基底顶部，且所述底介质层中具有位线接触开口，所述位线接触开口暴露出所述基底中的所述有源区；
    分立的位线结构，所述位线结构的顶部表面于同一高度，所述位线结构包括：位于所述底介质层顶部以及所述位线接触开口中位线接触层，位于所述位线接触层顶部的导电层，以及位于所述导电层顶部的顶介质层；
    其中，在位线结构延伸的方向上，同一所述位线结构中的所述导电层位于不同高度，且在字线结构延伸的方向上，相邻所述位线结构中的所述导电层位于不同高度。
  9. 根据权利要求8所述的存储器，其中，在所述位线结构延伸的方向上，所述导电层的连线呈波浪形。
  10. 根据权利要求8所述的存储器，其中，在预设方向上，不同所述位线结构中的所述导电层位于同一高度，所述预设方向与所述字线结构延伸的方向存在夹角α，所述α的范围为0＜α＜90°。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043035A (zh) * 2006-03-23 2007-09-26 三星电子株式会社 半导体存储器器件和相关的制造方法
US20080081413A1 (en) * 2006-10-02 2008-04-03 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods for forming the same
CN101552276A (zh) * 2008-04-04 2009-10-07 海力士半导体有限公司 半导体器件及其制造方法
CN107910330A (zh) * 2017-11-29 2018-04-13 睿力集成电路有限公司 动态随机存取存储器阵列及其版图结构、制作方法
CN208368506U (zh) * 2018-06-20 2019-01-11 长鑫存储技术有限公司 一种半导体储存器结构
CN109524383A (zh) * 2017-09-19 2019-03-26 三星电子株式会社 半导体存储器件及其制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100503519B1 (ko) * 2003-01-22 2005-07-22 삼성전자주식회사 반도체 장치 및 그 제조방법
KR101610831B1 (ko) * 2010-02-09 2016-04-12 삼성전자주식회사 비트 라인 배선이 비트 라인 콘택 상에서 그 폭이 확장되고 그 레벨이 낮아지는 반도체 소자 및 그 제조방법
KR102396583B1 (ko) * 2017-11-09 2022-05-11 삼성전자주식회사 메모리 소자 및 이의 제조방법
CN108520876B (zh) * 2018-06-26 2023-07-11 长鑫存储技术有限公司 集成电路存储器及其制备方法、半导体器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043035A (zh) * 2006-03-23 2007-09-26 三星电子株式会社 半导体存储器器件和相关的制造方法
US20080081413A1 (en) * 2006-10-02 2008-04-03 Samsung Electronics Co., Ltd. Semiconductor memory devices and methods for forming the same
CN101552276A (zh) * 2008-04-04 2009-10-07 海力士半导体有限公司 半导体器件及其制造方法
CN109524383A (zh) * 2017-09-19 2019-03-26 三星电子株式会社 半导体存储器件及其制造方法
CN107910330A (zh) * 2017-11-29 2018-04-13 睿力集成电路有限公司 动态随机存取存储器阵列及其版图结构、制作方法
CN208368506U (zh) * 2018-06-20 2019-01-11 长鑫存储技术有限公司 一种半导体储存器结构

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4099386A4 *

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