WO2021098137A1 - 显示基板、显示面板及显示装置 - Google Patents

显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2021098137A1
WO2021098137A1 PCT/CN2020/085884 CN2020085884W WO2021098137A1 WO 2021098137 A1 WO2021098137 A1 WO 2021098137A1 CN 2020085884 W CN2020085884 W CN 2020085884W WO 2021098137 A1 WO2021098137 A1 WO 2021098137A1
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Prior art keywords
display area
area
sub
display
pixels
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PCT/CN2020/085884
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English (en)
French (fr)
Inventor
常苗
张露
张金方
许骥
许传志
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昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to EP20890852.5A priority Critical patent/EP4064360A4/en
Priority to KR1020227021061A priority patent/KR102627695B1/ko
Publication of WO2021098137A1 publication Critical patent/WO2021098137A1/zh
Priority to US17/543,796 priority patent/US20220093682A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1613—Constructional details or arrangements for portable computers
    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
    • G06F1/1637—Details related to the display arrangement, including those related to the mounting of the display in the housing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present application relates to the field of display technology, and in particular to a display substrate, a display panel and a display device.
  • a display substrate includes a first display area, a second display area, and a display area adjacent to the first display area and the second display area.
  • a third display area, the light transmittance of the first display area is greater than the light transmittance of the second display area, and the light transmittance of the first display area is greater than the light transmittance of the third display area;
  • the first display area, the second display area, and the third display area are respectively provided with a plurality of sub-pixels, the display substrate is provided with a pixel circuit corresponding to the plurality of sub-pixels one-to-one, and the first The pixel circuits corresponding to the sub-pixels in the display area are arranged in the third display area, the pixel circuits corresponding to the sub-pixels in the second display area are arranged in the second display area, and the pixel circuits corresponding to the sub-pixels in the third display area are arranged in the third display area.
  • the third display area In the third display area;
  • the display area is further provided with a plurality of signal lines, and the pixel circuits corresponding to the plurality of sub-pixels arranged along the first direction in the display area are connected to the same signal line; at least one pixel circuit connected to the signal line includes The pixel circuit corresponding to the sub-pixel in the first display area, the pixel circuit corresponding to the sub-pixel in the second display area, and the pixel circuit corresponding to the sub-pixel in the third display area.
  • a display panel including the above-mentioned display substrate and packaging structure
  • the packaging structure includes a polarizer, the polarizer covers the second display area and the third display area, and does not cover the first display area, or the polarizer covers the first display area, the The second display area and the third display area.
  • a display device including:
  • the above-mentioned display panel is covered on the casing;
  • the device area is located below the first display area, and electronic components are arranged in the device area.
  • the light transmittance of the first display area is greater than that of the second display area, and the light transmittance of the first display area is greater than that of the third display area.
  • the light rate, the earpiece and the photosensitive device can be arranged below the first display area, and a full-screen display of the display substrate can be realized on the premise of ensuring the normal operation of the photosensitive device. Since the pixel circuits corresponding to the sub-pixels in the first display area are arranged in the third display area, the light transmittance of the first display area can be increased, the structural complexity of the first display area can be reduced, and the passage of external light through the first display area can be reduced.
  • At least one pixel circuit connected to the signal line includes a pixel circuit corresponding to a sub-pixel in the first display area, a pixel circuit corresponding to a sub-pixel in the second display area, and a pixel circuit corresponding to a sub-pixel in the third display area.
  • Pixel circuits, the pixel circuits corresponding to the sub-pixels in the first display area, the second display area, and the third display area are driven by the same signal line, which can reduce the wiring complexity in the display area of the display substrate, and at the same time enable the first display
  • the display effects of the second display area, the second display area, and the third display area are more consistent, which is beneficial to improve the user experience.
  • FIG. 1 is a top view of a display substrate provided by an embodiment of the present application.
  • FIG. 2 is a partial schematic diagram of the arrangement of sub-pixels in a display area of a display substrate provided by an embodiment of the present application;
  • FIG. 3 is a partial schematic diagram of the arrangement of pixel circuits and data lines in a display substrate provided by an embodiment of the present application;
  • FIG. 4 is a schematic diagram of a projection of the first electrode on the substrate in the first display area of the display substrate provided by the embodiment of the present application;
  • FIG. 5 is another schematic diagram of projection of the first electrode on the substrate in the first display area of the display substrate provided by the embodiment of the present application;
  • FIG. 6 is another schematic diagram of projection of the first electrode on the substrate in the first display area of the display substrate provided by the embodiment of the present application;
  • FIG. 7 is a top view of a housing of a display device provided by an embodiment of the present application.
  • a slotted area is provided on the display screen of the electronic device, and photosensitive devices such as earpieces, cameras, and infrared sensing elements are arranged in the slotted area, and external light enters the photosensitive device through the slotted area.
  • photosensitive devices such as earpieces, cameras, and infrared sensing elements
  • the slotted area cannot be displayed, a full-screen display of the electronic device cannot be realized.
  • a full-screen display of the electronic device can be realized under the premise of ensuring the normal operation of the photosensitive device.
  • the driving mode of the non-transparent display screen of the electronic equipment is active driving, and the driving mode of the transparent display screen is passive driving. Two driving schemes are required on the screen body, which greatly increases the complexity of the overall screen driving.
  • embodiments of the present application provide a display substrate, a display panel, and a display device, which can well solve the above-mentioned problems.
  • FIG. 1 is a top view of a display substrate provided by an embodiment of the present application
  • FIG. 2 is a partial schematic diagram of sub-pixel arrangement in a display area of a display substrate provided by an embodiment of the present application
  • FIG. 3 is a display substrate provided by an embodiment of the present application A partial schematic diagram of the arrangement of pixel circuits and data lines in the middle
  • FIG. 4 is a schematic diagram of a projection of the first electrode on the substrate in the first display area of the display substrate provided by an embodiment of the present application
  • FIG. 5 is a schematic diagram of a projection of the first electrode on the substrate provided by an embodiment of the present application Another schematic diagram of the projection of the first electrode on the substrate in the first display area of the display substrate
  • FIG. 6 is another projection of the first electrode on the substrate in the first display area of the display substrate provided by an embodiment of the present application A schematic diagram of a projection
  • FIG. 7 is a top view of the housing of the display device provided by an embodiment of the present application.
  • the embodiment of the present application provides a display substrate.
  • the display substrate 100 includes a first display area 10, a second display area 20 and a third display area 30, and the third display area 30 is adjacent to the first display area 10 and the second display area 20.
  • the light transmittance of the first display area 10 is greater than the light transmittance of the second display area 20, and the light transmittance of the first display area 10 is greater than the light transmittance of the third display area 30.
  • the first display area 10, the second display area 20, and the third display area 30 are respectively provided with a plurality of sub-pixels 11, 21, 31, and the display substrate 100 is provided with a plurality of The pixel circuits 12, 22, and 32 correspond to the sub-pixels 11, 21, and 31 in a one-to-one manner.
  • the first display area 10 is provided with a plurality of sub-pixels 11, and the plurality of sub-pixels 11 are in one-to-one correspondence with the plurality of pixel circuits 12;
  • the circuits 22 have a one-to-one correspondence;
  • the third display area 30 is provided with a plurality of sub-pixels 31, and the plurality of sub-pixels 31 correspond to the plurality of pixel circuits 32 in a one-to-one manner.
  • the pixel circuit 12 corresponding to the sub-pixel 11 of the first display area 10 is arranged in the third display area 30, and the pixel circuit 22 corresponding to the sub-pixel 21 in the second display area 20 is arranged in the second display area 20.
  • the pixel circuit 32 corresponding to the sub-pixel 31 in the three display area 30 is arranged in the third display area 30.
  • the display area of the display substrate 100 is further provided with a plurality of signal lines 40, and the pixel circuits corresponding to the plurality of sub-pixels arranged along the first direction in the display area are connected to the same signal line 40.
  • At least one pixel circuit connected to the signal line 40 includes a pixel circuit 12 corresponding to the sub-pixel 11 of the first display area 10, a pixel circuit 22 corresponding to the sub-pixel 21 of the second display area 20, and the third The pixel circuit 32 corresponding to the sub-pixel 31 of the display area 30.
  • the photosensitive device can be arranged under the first display area 10, and a full-screen display of the display substrate 100 can be realized under the premise of ensuring the normal operation of the photosensitive device.
  • the pixel circuits 12 corresponding to the sub-pixels 11 in the first display area 10 are arranged in the third display area 30, the light transmittance of the first display area 10 can be increased, and the structural complexity of the first display area 10 can be reduced, thereby reducing The intensity of the diffraction effect generated when external light passes through the first display area 10.
  • At least one pixel circuit connected to the signal line 40 includes a pixel circuit 12 corresponding to the sub-pixel 11 of the first display area 10, a pixel circuit 22 corresponding to the sub-pixel 21 of the second display area 20, and the third
  • the pixel circuits 32 corresponding to the sub-pixels 31 of the display area 30, the pixel circuits corresponding to the sub-pixels of the first display area 10, the second display area 20, and the third display area 30 are driven by the same signal line, which can reduce the display substrate 100
  • the wiring complexity in the display area can also make the display effects of the first display area 10, the second display area 20, and the third display area 30 more consistent, which is conducive to improving the user experience.
  • the sub-pixel 11 in the first display area 10 is electrically connected to the corresponding pixel circuit 12 through the wiring 13.
  • the sub-pixel 11 includes a first electrode, a light-emitting structure on the first electrode, and a second electrode on the light-emitting structure.
  • the first electrode of the sub-pixel is electrically connected to a corresponding pixel circuit through a wire 13.
  • the first electrode may be an anode
  • the second electrode may be a cathode
  • the first electrodes of the plurality of sub-pixels 11 may be surface electrodes connected in one piece.
  • the pixel circuits corresponding to the multiple sub-pixels arranged along the first direction are connected to the same signal line 40, and the multiple sub-pixels arranged along the first direction may refer to the sub-pixels arranged along the first direction at intervals.
  • the central axes of the plurality of sub-pixels arranged along the first direction in the first direction may overlap, or may be separated by a certain distance.
  • the signal line 40 connected to the pixel circuit 12 corresponding to each sub-pixel 11 in the first display area 10 is connected to the pixel circuit 22 corresponding to the sub-pixel 12 in the second display area 20 and the third display area 30.
  • the first display area 10 is rectangular, and the overall shapes of the first display area 10 and the third display area 30 are rectangular.
  • the borders of the first display area 10 and the third display area 30 are both linear borders, which can prevent the borders of the first display area 10 or the third display area 30 from being non-linear borders, such as arc-shaped borders.
  • the pixel unit adjacent to the border lacks pixels of a certain color, which causes the problem of a single color bright bar at the border, which helps to improve the user experience.
  • the first display area 10 includes a first side 101 and a second side 102 opposite to each other.
  • the first side 101 is parallel to the second side 102 and both are perpendicular to the first direction.
  • the display area 20 includes a third side 201 and a fourth side 202 opposite to the third side 201.
  • the third side 201 is parallel to the fourth side 202 and both are perpendicular to the first direction.
  • 201 and the third side 201 are on the same straight line.
  • the third display area 30 includes a first area 301, a second area 302, and a third area 303 that are sequentially connected, and the first area 301 and the third area 303 are located in the first display area.
  • the second area 302 is adjacent to the second side 102.
  • the pixel circuits 12 corresponding to the sub-pixels 11 of the first display area 10 are arranged in the first area 301 and the third area 303.
  • Each of the first area 301, the second area 302 and the third area 303 is provided with a sub-pixel 31 and a pixel circuit 32 for driving the sub-pixel 31.
  • the first area 301 is provided with sub-pixels 31, a pixel circuit 32 for driving the sub-pixels 31 in the first area 301, and a pixel circuit 12 for driving the sub-pixels 11, and the second area 302 is provided with sub-pixels 31.
  • the pixel circuit 32 for driving the sub-pixel 31 in the second area 302 is provided with the sub-pixel 31, the pixel circuit 32 for driving the sub-pixel 31 in the third area 303, and the pixel circuit 32 for driving the sub-pixel 11 Pixel circuit 12.
  • Arranging the pixel circuit 12 corresponding to the sub-pixel 11 in the first display area 10 in the first area 301 and the third area 303 helps to reduce the complexity of the wiring 13 between the sub-pixel 11 and the corresponding pixel circuit 12 .
  • the pixel circuit corresponding to each sub-pixel is connected to the same signal line 40.
  • the signal line 40 realizes the change of the extension direction in the second area 302, which is also conducive to simplifying the wiring in the first area 301 and the third area 303 Complexity, so that the first area 301 and the third area 303 can have more space for arranging the pixel circuit 12 corresponding to the sub-pixel 11.
  • the pixel circuit 12 corresponding to the sub-pixel 11 adjacent to the first area 301 in the first display area 10 is disposed in the first area 301, and the first display area 10 is adjacent to the third area 301.
  • the pixel circuit 12 corresponding to the sub-pixel 11 of the area 303 is arranged in the third area 303.
  • the distance between the sub-pixels in the first display area 10 adjacent to the first area 301 and the first area 301 is smaller than the distance from the third area 303, and the sub-pixels in the first display area 10 adjacent to the third area 303
  • the distance from the third area 303 is smaller than the distance from the first area 301.
  • This arrangement can make the length of the wiring between the sub-pixel 11 and the corresponding pixel circuit 13 shorter, which helps to simplify the complexity of the wiring.
  • the ratio of the size of the first area 301 in the second direction to the size of the first display area 10 in the second direction ranges from 1/5 to 1/2.
  • the second direction is perpendicular to the first direction.
  • the size of the first area 301 in the second direction is d1
  • the size of the first display area 10 in the second direction is d2
  • the ratio range of d1 to d2 is greater than or equal to 1/5 and less than Or equal to 1/2.
  • the ratio of the size of the third area 303 in the second direction to the size of the first display area 10 in the second direction ranges from 1/5 to 1/2.
  • the size of the third area 303 in the second direction is d3, and the size of the first display area 10 in the second direction is d2, then the ratio range of d3 to d2 is greater than or equal to 1/5 and less than or equal to 1/2 .
  • This arrangement can make the space of the third area 303 suitable for placing the pixel circuits corresponding to the sub-pixels adjacent to the third area 303 in the first display area 10, and can avoid the third area 303 being larger.
  • the ratio of the size of the second area 302 in the first direction to the size of the first display area 10 in the second direction ranges from 1/20 to 1/5.
  • the size of the second area 302 in the first direction is d4, and the size of the first display area 10 in the second direction is d2, and the ratio range of d4 to d2 is greater than or equal to 1/20 and less than or equal to 1/5 .
  • Such a configuration can make the space of the second area 302 available for the direction change of the signal line 40, and can avoid the second area 302 being larger.
  • the first direction may be a column direction and the second direction may be a row direction, or the first direction may be a row direction and the second direction may be a column direction.
  • the first direction is the column direction and the second direction is the row direction as an example for illustration, and other cases are not illustrated.
  • the light transmittance of the third display area 30 is greater than the light transmittance of the second display area 20.
  • the display brightness of the display substrate 100 can gradually transition from the second display area 20 to the first display area 10, avoiding a significant difference between the first display area 10 and the second display area 20, and can improve the use of users. Experience.
  • the density of sub-pixels 31 in the third display area 30 is less than the density of sub-pixels 21 in the second display area 20, and the density of sub-pixels 11 in the first display area 10 is less than that of the second display area.
  • the density of the sub-pixels 11 in the first display area 10 and the density of the sub-pixels 31 in the third display area 30 may be equal or different.
  • the signal line 40 includes a data line.
  • the data line provides a data voltage for the pixel circuit.
  • the data lines include a first-type data line 41, a second-type data line 42, and a third-type data line 43.
  • the pixel circuit connected to the first-type data line 41 is a sub-pixel of the first display area 10.
  • the pixel circuit 12 corresponding to 11, the pixel circuit 22 corresponding to the sub-pixel 21 of the second display area 20, and the pixel circuit 32 corresponding to the sub-pixel 31 of the third display area 30 are connected to the second type data line 42
  • the connected pixel circuits are the pixel circuit 22 corresponding to the sub-pixel 21 of the second display area 20 and the pixel circuit 32 corresponding to the sub-pixel 31 of the third display area 30, which are connected to the third type data line 43
  • the pixel circuit is the pixel circuit 22 corresponding to the sub-pixel 21 of the second display area 20.
  • the arrangement of the three types of data lines enables the pixel circuits corresponding to the multiple sub-pixels arranged in the first direction to be connected to the same data line, which helps to simplify the wiring complexity of the data lines and simplify the control of the sub-pixels.
  • the signal line 40 may also be a scan line or the like.
  • the display substrate 100 includes a substrate, and the sub-pixels 11, 21, and 31 are located on the substrate.
  • the first electrode of the sub-pixel 11 located in the first display area 10 includes one or more electrode blocks. Referring to FIGS. 4 to 6, among the two or more electrode blocks 103 of the first electrode 111, two adjacent electrode blocks 103 are electrically connected.
  • the first electrode 111 may further include a connecting portion 104, and two adjacent electrode blocks 103 are electrically connected through the corresponding connecting portion 104.
  • the light emitting structure includes a light emitting structure block located on the electrode block 103.
  • the projection of the electrode block 103 on the substrate includes one first pattern unit or multiple first pattern units.
  • the first graphic unit includes a circle, an oval, a dumbbell, a gourd or a rectangle.
  • the first electrode 111 includes four electrode blocks 103.
  • the projection of the electrode block 103 on the substrate is composed of a first pattern unit, and the first pattern unit is circular.
  • the first electrode 111 includes four electrode blocks 103, the projection of the electrode block 103 on the substrate is composed of a first pattern unit, and the first pattern unit is dumbbell-shaped. Referring to FIG.
  • the first electrode 111 includes four electrode blocks 103, and the projection of the electrode block 103 on the substrate is composed of a first pattern unit, and the first pattern unit is elliptical.
  • the first graphic unit is circular, elliptical, dumbbell-shaped or gourd-shaped, the above-mentioned shapes can change the periodic structure generated by diffraction, that is, change the distribution of the diffraction field, thereby reducing the incidence of external light passing through the first display area 10 The diffraction effect.
  • the distance between the first electrodes of adjacent sub-pixels changes continuously or intermittently, so that the first electrodes of adjacent sub-pixels produce diffractive In different positions, the diffraction effect at different positions cancels each other out, which helps to reduce the diffraction effect, thereby ensuring that the image taken by the camera located below the first display area has high definition.
  • the projection of the light-emitting structure block on the substrate includes a second graphic unit or a plurality of second graphic units, and the second graphic unit includes a circular shape, an oval shape, a dumbbell shape, a gourd shape, or rectangle.
  • the second graphic unit is circular, elliptical, dumbbell-shaped or gourd-shaped, the above-mentioned shape can change the periodic structure produced by diffraction, that is, change the distribution of the diffraction field, thereby reducing the incidence of external light passing through the first display area 10 The diffraction effect.
  • the second image unit is circular, elliptical, dumbbell-shaped, or gourd-shaped
  • the distance between the light-emitting structures of adjacent sub-pixels changes continuously or intermittently, so that the light-emitting structures of adjacent sub-pixels have different positions where diffraction occurs.
  • the diffraction effects at different positions cancel each other out, so that the diffraction effects can be effectively reduced, thereby ensuring that the images taken by the camera located below the first display area have high definition.
  • the first graphic unit corresponding to the projection of the electrode block on the substrate and the second graphic unit corresponding to the projection of the light-emitting structure block on the electrode block on the substrate may be the same or different.
  • the projection of the electrode block on the substrate is different from the projection of the light-emitting structure block on the substrate, which can further reduce the diffraction effect generated when the light passes through the first display area 10.
  • the material of the connecting portion 104 and the electrode block 103 may include indium tin oxide, or indium zinc oxide, or indium tin oxide doped with silver, or indium zinc oxide doped with silver. In this way, the light transmittance of the connecting portion 104 and the electrode block 103 can be higher.
  • the connection part 104 and the electrode block 103 is silver-doped indium tin oxide or silver-doped indium zinc oxide, the connection part and the electrode block can be reduced on the basis of ensuring the high light transmittance of the first display area The resistance.
  • the second electrode can be a thin film with a certain degree of transparency
  • the material of the second electrode can be magnesium, silver, or silver, or aluminum, or molybdenum, or titanium, or titanium nitride, or nickel, Or aluminum oxide zinc or aluminum oxide titanium.
  • magnesium silver is a mixed material including metallic magnesium and metallic silver.
  • An embodiment of the present application also provides a display panel, which includes any of the above-mentioned display substrates and packaging structures.
  • the packaging structure is located on the side of the display substrate 100 away from the substrate.
  • the packaging structure includes a polarizer, the polarizer covers the second display area 20 and the third display area 30, and does not cover the first display area 10, or the polarizer covers the first display area 10.
  • the polarizer can dissipate the reflected light on the surface of the display panel and improve the user experience. When the polarizer is not provided in the first display area 10, the light transmittance of the first display area 10 can be increased.
  • the packaging structure may further include an packaging layer, a glass cover plate, a touch control layer, and the like.
  • the encapsulation layer can be a thin film encapsulation layer or a glass frit encapsulation layer.
  • An embodiment of the present application also provides a display device, which includes a housing and the above-mentioned display panel.
  • the housing 310 has a device area 320, and the display panel covers the housing 310.
  • the device area 320 is located below the first display area 10, and electronic components 330 are arranged in the device area 320.
  • the electronic components may include earpieces, optical devices, distance sensors, etc., where the optical devices include at least one of a front camera, an infrared sensor, an infrared lens, a flood light sensor, an ambient light sensor, and a dot projector.
  • the optical devices include at least one of a front camera, an infrared sensor, an infrared lens, a flood light sensor, an ambient light sensor, and a dot projector.
  • the device area of the housing may be a slotted area, and the first display area of the display panel may be arranged in a fit manner corresponding to the slotted area, so that the optical device can emit or collect light through the first display area 10.
  • the above-mentioned display device may be a digital device such as a mobile phone, a tablet, or a palmtop computer.

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Abstract

一种显示基板(100)、显示面板及显示装置。显示基板(100)包括第一显示区(10)、第二显示区(20)和第三显示区(30)，第三显示区(30)邻接第一显示区(10)与第二显示区(20); 第一显示区(10)的透光率大于第二显示区(20)的透光率，且第一显示区(10)的透光率大于第三显示区(30)的透光率。第一显示区(10)、第二显示区(20)及第三显示区(30)中分别设有多个子像素(11、21、31)，显示基板(100)设有与多个子像素(11、21、31)一一对应的像素电路(12、22、32),其中，第一显示区(10)的子像素(11)对应的像素电路(12)设置在第三显示区(30); 显示区还设有多个信号线(40)，显示区（10、20、30）中沿第一方向排布的多个子像素(11、21、31)对应的像素电路(12、22、32)连接至同一信号线(40)；至少一个信号线(40)连接的像素电路(12、22、32)包括第一显示区(10)的子像素(11)对应的像素电路(12)、第二显示区(20)的子像素(21)对应的像素电路(22)及第三显示区(30)的子像素(31)对应的像素电路(33)。

Description

显示基板、显示面板及显示装置
相关申请的交叉引用
本申请要求于2019年11月21日提交的、申请号为201922027980.5、名称为“显示基板、显示面板及显示设备”的中国申请的优先权，该申请的全文以引用的方式并入本文中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板、显示面板及显示装置。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，使得电子设备的全面屏显示受到业界越来越多的关注。传统的电子设备如手机、平板电脑等，由于需要集成诸如前置摄像头、听筒以及红外感应元件等，故而可通过在显示屏上开槽(Notch)，在开槽区域设置摄像头、听筒以及红外感应元件等，但开槽区域并不能用来显示画面，屏幕呈刘海屏，或者采用在屏幕上开孔的方式，外界光线可通过屏幕上的开孔处进入位于屏幕下方的感光元件。但是这些电子设备均不是真正意义上的全面屏，并不能在整个屏幕的各个区域均进行显示，如在摄像头区域不能显示画面。
发明内容
根据本申请实施例的第一方面，提供了一种显示基板，所述显示基板的显示区包括第一显示区、第二显示区以及邻接所述第一显示区与所述第二显示区的第三显示区，所述第一显示区的透光率大于所述第二显示区的透光率，且所述第一显示区的透光率大于所述第三显示区的透光率；
所述第一显示区、所述第二显示区及所述第三显示区中分别设有多个子像素，所述显示基板设有与多个所述子像素一一对应的像素电路，第一显示区的子像素对应的像素电路设置在所述第三显示区，第二显示区的子像素对应的像素电路设置在所述第二显示区，第三显示区的子像素对应的像素电路设置在所述第三显示区；
所述显示区还设有多个信号线，所述显示区中沿第一方向排布的多个子像素对应的 像素电路连接至同一所述信号线；至少一个所述信号线连接的像素电路包括所述第一显示区的子像素对应的像素电路、所述第二显示区的子像素对应的像素电路及所述第三显示区的子像素对应的像素电路。
根据本申请实施例的第二方面，提供了一种显示面板，所述显示面板包括上述的显示基板及封装结构；
所述封装结构包括偏光片，所述偏光片覆盖所述第二显示区及第三显示区，且未覆盖所述第一显示区，或者所述偏光片覆盖所述第一显示区、所述第二显示区及所述第三显示区。
根据本申请实施例的第三方面，提供了一种显示装置，包括：
壳体，具有器件区；
上述的显示面板，覆盖在所述壳体上；
其中，所述器件区位于所述第一显示区下方，且所述器件区中设置有电子元件。
本申请实施例提供的显示基板、显示面板及显示装置，由于第一显示区的透光率大于第二显示区的透光率，且第一显示区的透光率大于第三显示区的透光率，则可将听筒、感光器件设置在第一显示区下方，在保证感光器件正常工作的前提下实现显示基板的全面屏显示。由于第一显示区中的子像素对应的像素电路设置在第三显示区内，可提高第一显示区的透光率，降低第一显示区的结构复杂度，进而减弱外部光线通过第一显示区时产生的衍射效应的强度。至少一个所述信号线连接的像素电路包括所述第一显示区的子像素对应的像素电路、所述第二显示区的子像素对应的像素电路及所述第三显示区的子像素对应的像素电路，则第一显示区、第二显示区及第三显示区的子像素对应的像素电路由同一信号线驱动，可降低显示基板的显示区内的布线复杂度，同时可使第一显示区、第二显示区及第三显示区的显示效果更一致，有利于提升用户的使用体验。
附图说明
图1是本申请实施例提供的一种显示基板的俯视图；
图2是本申请实施例提供的显示基板的显示区中子像素排布的局部示意图；
图3是本申请实施例提供的显示基板中像素电路及数据线排布的局部示意图；
图4是本申请实施例提供的显示基板的第一显示区中第一电极在衬底上的一种投影 示意图；
图5是本申请实施例提供的显示基板的第一显示区中第一电极在衬底上的另一种投影示意图；
图6是本申请实施例提供的显示基板的第一显示区中第一电极在衬底上的再一种投影示意图；
图7是本申请实施例提供的显示装置的壳体的俯视图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
电子设备的显示屏上设置开槽区，将听筒、摄像头以及红外感应元件等感光器件设置在开槽区，外界光线通过开槽区进入感光器件。但是由于开槽区不能进行显示，不能实现电子设备的全面屏显示。
通过在电子设备部分屏幕处设置透明显示屏的方式，将感光器件设置在透明显示屏下方，可在保证感光器件正常工作的前提下实现电子设备的全面屏显示。电子设备的非透明显示屏的驱动方式为主动驱动，透明显示屏的驱动方式为被动驱动，在屏体上需要两种驱动方案，这大大增加了全面屏驱动的复杂度。
为解决上述问题，本申请实施例提供了一种显示基板、显示面板及显示装置，其能够很好的解决上述问题。
下面结合附图，对本申请实施例中的显示基板、显示面板及显示装置进行详细说明。在不冲突的情况下，下述的实施例及实施方式中的特征可以相互补充或相互组合。
图1是本申请实施例提供的一种显示基板的俯视图；图2是本申请实施例提供的显示基板的显示区中子像素排布的局部示意图；图3是本申请实施例提供的显示基板中像素电路及数据线排布的局部示意图；图4是本申请实施例提供的显示基板的第一显示区中第一电极在衬底上的一种投影示意图；图5是本申请实施例提供的显示基板的第一显示区中第一电极在衬底上的另一种投影示意图；图6是本申请实施例提供的显示基板的第一显示区中第一电极在衬底上的再一种投影示意图；图7是本申请实施例提供的显示 装置的壳体的俯视图。
本申请实施例提供了一种显示基板。参见图1，所述显示基板100包括第一显示区10、第二显示区20和第三显示区30，第三显示区30邻接所述第一显示区10与所述第二显示区20。所述第一显示区10的透光率大于所述第二显示区20的透光率，且所述第一显示区10的透光率大于所述第三显示区30的透光率。
参见图2，所述第一显示区10、所述第二显示区20及所述第三显示区30中分别设有多个子像素11、21、31，所述显示基板100设有与多个所述子像素11、21、31一一对应的像素电路12、22、32。具体来说，第一显示区10设有多个子像素11，多个子像素11与多个像素电路12一一对应；第二显示区20设有多个子像素21，多个子像素21与多个像素电路22一一对应；第三显示区30设有多个子像素31，多个子像素31与多个像素电路32一一对应。其中，第一显示区10的子像素11对应的像素电路12设置在所述第三显示区30，第二显示区20中的子像素21对应的像素电路22设置在第二显示区20，第三显示区30中的子像素31对应的像素电路32设置在第三显示区30。
所述显示基板100的显示区还设有多个信号线40，所述显示区中沿第一方向排布的多个子像素对应的像素电路连接至同一所述信号线40。至少一个所述信号线40连接的像素电路包括所述第一显示区10的子像素11对应的像素电路12、所述第二显示区20的子像素21对应的像素电路22及所述第三显示区30的子像素31对应的像素电路32。
本申请实施例提供的显示基板100，由于第一显示区10的透光率大于第二显示区20的透光率，且第一显示区10的透光率大于第三显示区30的透光率，则可将感光器件设置在第一显示区10下方，在保证感光器件正常工作的前提下实现显示基板100的全面屏显示。由于第一显示区10中的子像素11对应的像素电路12设置在第三显示区30内，可提高第一显示区10的透光率，降低第一显示区10的结构复杂度，进而减弱外部光线通过第一显示区10时产生的衍射效应的强度。至少一个所述信号线40连接的像素电路包括所述第一显示区10的子像素11对应的像素电路12、所述第二显示区20的子像素21对应的像素电路22及所述第三显示区30的子像素31对应的像素电路32，则第一显示区10、第二显示区20及第三显示区30的子像素对应的像素电路由同一信号线驱动，可降低显示基板100的显示区内的布线复杂度，同时可使第一显示区10、第二显示区20及第三显示区30的显示效果更一致，有利于提升用户的使用体验。
本申请实施例中，参见图3，第一显示区10中的子像素11通过走线13与对应的像素电路12电连接。具体地，子像素11包括第一电极、位于第一电极上的发光结构及位 于发光结构上的第二电极，子像素的第一电极通过走线13与对应的像素电路电连接。其中，第一电极可以是阳极，第二电极可以是阴极，多个子像素11的第一电极可以是连成一片的面电极。
本申请实施例中，沿第一方向排布的多个子像素对应的像素电路连接至同一所述信号线40，其中沿第一方向排布的多个子像素可以指大致沿第一方向间隔排布，沿第一方向排布的多个子像素在第一方向上的中轴线可重合，也可以间隔一定的距离。
本申请实施例中，第一显示区10中各个子像素11对应的像素电路12连接的信号线40，均连接有第二显示区20中子像素12对应的像素电路22及第三显示区30中子像素31对应的像素电路32。如此，可在最大程度上降低信号线40的布线复杂度。
可选地，所述第一显示区10为矩形，所述第一显示区10与所述第三显示区30总体形状为矩形。如此设置，第一显示区10及第三显示区30的边界均为直线型边界，可避免第一显示区10的边界或第三显示区30的边界为非直线型边界例如为弧形边界，而导致邻近边界的像素单元缺少某种颜色的像素，而使得边界处出现单一颜色亮条的问题，有助于提升用户的使用体验。
可选地，所述第一显示区10包括相对的第一边101与第二边102，所述第一边101平行于所述第二边102且均垂直于第一方向，所述第二显示区20包括第三边201及与所述第三边201相对的第四边202，所述第三边201平行于所述第四边202且均垂直于第一方向，所述第一边201与所述第三边201在同一直线上。如此设置，信号线40不需要绕过第一显示区10以连接位于第一显示区10两侧的子像素对应的像素电路，可简化信号线40的走线复杂度。
可选地，所述第三显示区30包括顺次相连的第一区域301、第二区域302及第三区域303，所述第一区域301与所述第三区域303位于所述第一显示区10的相对两侧，所述第二区域302与所述第二边102邻接。所述第一显示区10的子像素11对应的像素电路12设置在所述第一区域301与所述第三区域303。所述第一区域301、所述第二区域302及所述第三区域303均设有子像素31及用于驱动该子像素31的像素电路32。具体来说，第一区域301设有子像素31、用于驱动第一区域301中子像素31的像素电路32及用于驱动子像素11的像素电路12，第二区域302设有子像素31、用于驱动第二区域302中子像素31的像素电路32，第三区域303设有子像素31、用于驱动第三区域303中子像素31的像素电路32及用于驱动子像素11的像素电路12。
将第一显示区10中的子像素11对应的像素电路12设置在第一区域301及第三区域303中，有助于降低子像素11与对应像素电路12之间的走线13的复杂度。并且，在第一方向上间隔排布的子像素11、子像素21及子像素31中，各个子像素对应的像素电路连接至同一信号线40，则信号线经过第三显示区30时，需要从第二区域302经过并延伸至第一区域301或第三区域303，信号线40在第二区域302中实现延伸方向的改变，也有利于简化第一区域301及第三区域303中线路的复杂度，从而第一区域301与第三区域303可以有更多的空间设置子像素11对应的像素电路12。
可选地，所述第一显示区10中邻近所述第一区域301的子像素11对应的像素电路12设置在所述第一区域301，所述第一显示区10中邻近所述第三区域303的子像素11对应的像素电路12设置在所述第三区域303。其中，第一显示区10中邻近第一区域301的子像素与第一区域301之间的距离小于与第三区域303之间的距离，第一显示区10中邻近第三区域303的子像素与第三区域303之间的距离小于与第一区域301之间的距离。如此设置，可使得子像素11与对应的像素电路13之间的走线的长度较短，有助于简化线路的复杂度。
可选地，所述第一区域301在第二方向上的尺寸与所述第一显示区10在所述第二方向上的尺寸的比例范围为1/5～1/2。其中，第二方向与第一方向垂直。再次参见图1，第一区域301在第二方向上的尺寸为d1，第一显示区10在第二方向上的尺寸为d2，则d1与d2的比例范围大于或等于1/5，且小于或等于1/2。如此设置，可使得第一区域301的空间适于放置第一显示区10中邻近第一区域301的子像素对应的像素电路，又可避免第一区域301较大。
可选地，所述第三区域303在第二方向上的尺寸与所述第一显示区10在所述第二方向上的尺寸的比例范围为1/5～1/2。第三区域303在第二方向上的尺寸为d3，第一显示区10在第二方向上的尺寸为d2，则d3与d2的比例范围大于或等于1/5，且小于或等于1/2。如此设置，可使得第三区域303的空间适于放置第一显示区10中邻近第三区域303的子像素对应的像素电路，又可避免第三区域303较大。
可选地，所述第二区域302在第一方向上的尺寸与所述第一显示区10在所述第二方向上的尺寸的比例范围为1/20～1/5。第二区域302在第一方向上的尺寸为d4，第一显示区10在第二方向上的尺寸为d2，则d4与d2的比例范围大于或等于1/20，且小于或等于1/5。如此设置，可使得第二区域302的空间可用于信号线40进行方向改变，又可避免第二区域302较大。
可选地，所述第一方向可以是列方向，第二方向可以是行方向，或者第一方向可以是行方向，第二方向为列方向。图中仅以第一方向为列方向、第二方向为行方向为例进行示意，其他情况不再进行示意。
可选地，第三显示区30的透光率大于第二显示区20的透光率。如此设置，可使得显示基板100的显示亮度从第二显示区20至第一显示区10逐渐过渡，避免第一显示区10与第二显示区20之间出现明显的差别，可提升用户的使用体验。
可选地，所述第三显示区30中子像素31的密度小于所述第二显示区20中子像素21的密度，所述第一显示区10中子像素11的密度小于所述第二显示区20中子像素21的密度。其中，第一显示区10中子像素11的密度与第三显示区30中子像素31的密度可相等，也可不等。
如此设置，第三显示区30中子像素31对应的像素电路32的数量较少，从而可使得第三显示区30中有多余的空间用于设置第一显示区10中子像素11对应的像素电路12。
可选地，所述信号线40包括数据线。数据线为像素电路提供数据电压。所述数据线包括第一类数据线41、第二类数据线42和第三类数据线43，与所述第一类数据线41连接的像素电路为所述第一显示区10的子像素11对应的像素电路12、所述第二显示区20的子像素21对应的像素电路22及所述第三显示区30的子像素31对应的像素电路32，与所述第二类数据线42连接的像素电路为所述第二显示区20的子像素21对应的像素电路22及所述第三显示区30的子像素31对应的像素电路32，与所述第三类数据线43连接的像素电路为所述第二显示区20的子像素21对应的像素电路22。三类数据线的设置可使得沿第一方向上排布的多个子像素对应的像素电路连接至同一数据线，有助于简化数据线的布线复杂度，简化对子像素的控制。
可选地，信号线40也可以是扫描线等。
可选地，所述显示基板100包括衬底，所述子像素11、21、31位于所述衬底上。
可选地，位于所述第一显示区10的子像素11的第一电极包括一个或多个的电极块。参见图4至图6，第一电极111的两个或多个电极块103中，相邻两个所述电极块103电连接。第一电极111还可包括连接部104，相邻两个电极块103通过对应的连接部104电连接。所述发光结构包括位于所述电极块103上的发光结构块。
所述电极块103在所述衬底上的投影包括一个第一图形单元或者多个第一图形单元。所述第一图形单元包括圆形、椭圆形、哑铃形、葫芦形或矩形。参见图4，第一电 极111包括四个电极块103，电极块103在衬底上的投影由一个第一图形单元组成，第一图形单元为圆形。参见图5，第一电极111包括四个电极块103，电极块103在衬底上的投影由一个第一图形单元组成，第一图形单元为哑铃形。参见图6，第一电极111包括四个电极块103，电极块103在衬底上的投影由一个第一图形单元组成，第一图形单元为椭圆形。第一图形单元为圆形、椭圆形、哑铃形及葫芦形时，上述形状可改变衍射产生的周期性结构，即改变了衍射场的分布，从而减弱外部入射光通过第一显示区10时产生的衍射效应。并且，第一图像单元为圆形、椭圆形、哑铃形及葫芦形时，相邻子像素的第一电极之间的距离连续变化或者间断变化，从而相邻子像素的第一电极产生衍射的位置不同，不同位置处的衍射效应相互抵消，有助于减弱衍射效应，进而确保第一显示区下方设置的摄像头拍照得到的图像具有较高的清晰度。
可选地，所述发光结构块在所述衬底上的投影包括一个第二图形单元或者多个第二图形单元，所述第二图形单元包括圆形、椭圆形、哑铃形、葫芦形或矩形。第二图形单元为圆形、椭圆形、哑铃形及葫芦形时，上述形状可改变衍射产生的周期性结构，即改变了衍射场的分布，从而减弱外部入射光通过第一显示区10时产生的衍射效应。并且，第二图像单元为圆形、椭圆形、哑铃形及葫芦形时，相邻子像素的发光结构之间的距离连续变化或者间断变化，从而相邻子像素的发光结构产生衍射的位置不同，不同位置处的衍射效应相互抵消，从而可以有效减弱衍射效应，进而确保第一显示区下方设置的摄像头拍照得到的图像具有较高的清晰度。
可选地，电极块在衬底上的投影对应的第一图形单元、以及电极块上的发光结构块在衬底上的投影对应的第二图形单元可相同或不同。第一图形单元与第二图形单元不同时，则电极块在衬底上的投影与发光结构块在衬底上的投影不同，可进一步减弱光线通过第一显示区10时产生的衍射效应。
可选地，连接部104与电极块103的材料可包括氧化铟锡、或者氧化铟锌、或者掺杂银的氧化铟锡、或者掺杂银的氧化铟锌。如此，可使得连接部104与电极块103的透光率较高。连接部104与电极块103的材料为掺杂银的氧化铟锡或者掺杂银的氧化铟锌时，可在保证第一显示区的高透光率的基础上，减小连接部及电极块的电阻。
可选地，第二电极可为厚度较薄且具有一定透明度的膜层，第二电极的材料可为镁银、或者银、或者铝、或者钼、或者钛、或者氮化钛、或者镍、或者氧化铝锌或者氧化铝钛。其中，镁银是一种包括金属镁和金属银的混合材料。
本申请实施例还提供了一种显示面板，所述显示面板包括上述任一显示基板及封装 结构。封装结构位于显示基板100背离衬底的一侧。
所述封装结构包括偏光片，所述偏光片覆盖所述第二显示区20及第三显示区30，且未覆盖所述第一显示区10，或者所述偏光片覆盖所述第一显示区10、所述第二显示区20及所述第三显示区30。偏光片可消散显示面板表面的反射光，改善用户的使用体验。第一显示区10不设置偏光片时，可提高第一显示区10的透光率。
可选地，所述封装结构还可包括封装层、玻璃盖板、触控层等。封装层可以是薄膜封装层或者玻璃粉封装层。
本申请实施例还提供了一种显示装置，显示装置包括壳体及上述的显示面板。参见图7，壳体310具有器件区320，显示面板覆盖在壳体310上。其中，器件区320位于第一显示区10下方，且器件区320中设置有电子元件330。
电子元件可包括听筒、光学器件、距离传感器等，其中光学器件包括前置摄像头、红外传感器、红外镜头、泛光感应元件、环境光传感器以及点阵投影器中的至少一种。
壳体的器件区可以是开槽区，显示面板的第一显示区可对应于开槽区贴合设置，以使得光学器件能够透过该第一显示区10进行发射或者采集光线。
上述显示装置可以为手机、平板、掌上电脑等数码设备。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。

Claims (20)

  1. 一种显示基板，其中，所述显示基板的显示区包括第一显示区、第二显示区以及邻接所述第一显示区与所述第二显示区的第三显示区，
    所述第一显示区的透光率大于所述第二显示区的透光率，且所述第一显示区的透光率大于所述第三显示区的透光率；
    所述第一显示区、所述第二显示区及所述第三显示区中分别设有多个子像素，所述显示基板设有与多个所述子像素一一对应的像素电路，第一显示区的子像素对应的像素电路设置在所述第三显示区，第二显示区的子像素对应的像素电路设置在所述第二显示区，第三显示区的子像素对应的像素电路设置在所述第三显示区；
    所述显示区还设有多个信号线，所述显示区中沿第一方向排布的多个所述子像素对应的像素电路连接至同一所述信号线；至少一个所述信号线连接的像素电路包括所述第一显示区的子像素对应的像素电路、所述第二显示区的子像素对应的像素电路及所述第三显示区的子像素对应的像素电路。
  2. 根据权利要求1所述的显示基板，其中，所述第一显示区为矩形，所述第一显示区与所述第三显示区总体形状为矩形。
  3. 根据权利要求2所述的显示基板，其中，所述第一显示区包括相对的第一边与第二边，所述第一边平行于所述第二边且均垂直于所述第一方向，所述第二显示区包括第三边及与所述第三边相对的第四边，所述第三边平行于所述第四边且均垂直于所述第一方向，所述第一边与所述第三边在同一直线上。
  4. 根据权利要求3所述的显示基板，其中，所述第三显示区包括顺次相连的第一区域、第二区域及第三区域，所述第一区域与所述第三区域位于所述第一显示区的相对两侧，所述第二区域与所述第二边邻接；
    所述第一显示区的子像素对应的像素电路设置在所述第一区域与所述第三区域；所述第一区域、所述第二区域及所述第三区域均设有子像素及用于驱动该子像素的像素电路。
  5. 根据权利要求4所述的显示基板，其中，所述第一显示区中邻近所述第一区域的子像素对应的像素电路设置在所述第一区域，所述第一显示区中邻近所述第三区域的子像素对应的像素电路设置在所述第三区域。
  6. 根据权利要求4所述的显示基板，其中，所述第一区域在第二方向上的尺寸与所述第一显示区在所述第二方向上的尺寸的比例范围为1/5～1/2；和/或，
    所述第二区域在所述第一方向上的尺寸与所述第一显示区在所述第二方向上的尺 寸的比例范围为1/20～1/5；和/或，
    所述第三区域在所述第二方向上的尺寸与所述第一显示区在所述第二方向上的尺寸的比例范围为1/5～1/2，
    其中，所述第一方向与所述第二方向垂直。
  7. 根据权利要求4所述的显示基板，其中，连接所述第一显示区的子像素对应的像素电路、所述第二显示区的子像素对应的像素电路和所述第三显示区的子像素对应的像素电路的所述信号线在所述第二区域中改变延伸方向。
  8. 根据权利要求1所述的显示基板，其中，所述信号线包括数据线；
    所述数据线包括第一类数据线、第二类数据线和第三类数据线，
    与所述第一类数据线连接的像素电路为所述第一显示区的子像素对应的像素电路、所述第二显示区的子像素对应的像素电路及所述第三显示区的子像素对应的像素电路，
    与所述第二类数据线连接的像素电路为所述第二显示区的子像素对应的像素电路及所述第三显示区的子像素对应的像素电路，
    与所述第一类数据线连接的像素电路为所述第二显示区的子像素对应的像素电路。
  9. 根据权利要求1所述的显示基板，其中，所述第三显示区的透光率大于所述第二显示区的透光率。
  10. 根据权利要求1所述的显示基板，其中，所述第三显示区中子像素的密度小于所述第二显示区中子像素的密度，所述第一显示区中子像素的密度小于所述第二显示区中子像素的密度。
  11. 根据权利要求10所述的显示基板，其中，所述第三显示区中子像素的密度等于所述第一显示区中子像素的密度。
  12. 根据权利要求1所述的显示基板，其中，所述显示基板包括衬底，所述子像素位于所述衬底上；
    位于所述第一显示区的子像素包括第一电极、位于所述第一电极上的发光结构及位于所述发光结构上的第二电极，所述第一电极包括一个或多个电极块，
    当所述第一电极包括多个电极块时，相邻两个所述电极块电连接；所述发光结构包括位于所述电极块上的发光结构块；
    所述电极块在所述衬底上的投影包括一个第一图形单元或者多个第一图形单元；所述第一图形单元包括圆形、椭圆形、哑铃形、葫芦形或矩形。
  13. 根据权利要求12所述的显示基板，其中，所述发光结构块在所述衬底上的投影包括一个第二图形单元或者多个第二图形单元；所述第二图形单元包括圆形、椭圆形、 哑铃形、葫芦形或矩形。
  14. 一种显示面板，包括权利要求1所述的显示基板及封装结构；
    所述封装结构包括偏光片，所述偏光片覆盖所述第二显示区及第三显示区，且未覆盖所述第一显示区，或者所述偏光片覆盖所述第一显示区、所述第二显示区及所述第三显示区。
  15. 根据权利要求14所述的显示面板，其中，所述第一显示区为矩形，所述第一显示区与所述第三显示区总体形状为矩形。
  16. 根据权利要求15所述的显示面板，其中，
    所述第一显示区包括相对的第一边与第二边，所述第一边沿所述第一方向指向所述第二边，所述第二显示区包括第三边及与所述第三边相对的第四边，所述第三边沿所述第一方向指向所述第四边，所述第一边与所述第三边在同一直线上，
    所述第三显示区包括顺次相连的第一区域、第二区域及第三区域，所述第一区域与所述第三区域位于所述第一显示区的相对两侧，所述第二区域与所述第二边邻接；
    所述第一显示区的子像素对应的像素电路设置在所述第一区域与所述第三区域；所述第一区域、所述第二区域及所述第三区域均设有子像素及用于驱动该子像素的像素电路。
  17. 根据权利要求16所述的显示面板，其中，所述第一区域在第二方向上的尺寸与所述第一显示区在所述第二方向上的尺寸的比例范围为1/5～1/2；和/或，
    所述第二区域在所述第一方向上的尺寸与所述第一显示区在所述第二方向上的尺寸的比例范围为1/20～1/5；和/或，
    所述第三区域在所述第二方向上的尺寸与所述第一显示区在所述第二方向上的尺寸的比例范围为1/5～1/2；
    其中，所述第一方向与所述第二方向垂直。
  18. 根据权利要求14所述的显示面板，其中，其中，所述信号线包括数据线；
    所述数据线包括第一类数据线、第二类数据线和第三类数据线，
    与所述第一类数据线连接的像素电路为所述第一显示区的子像素对应的像素电路、所述第二显示区的子像素对应的像素电路及所述第三显示区的子像素对应的像素电路，
    与所述第二类数据线连接的像素电路为所述第二显示区的子像素对应的像素电路及所述第三显示区的子像素对应的像素电路，
    与所述第一类数据线连接的像素电路为所述第二显示区的子像素对应的像素电路。
  19. 根据权利要求15所述的显示面板，其中，所述第三显示区的透光率大于所述 第二显示区的透光率，和/或，所述第三显示区中子像素的密度小于所述第二显示区中子像素的密度，所述第一显示区中子像素的密度小于所述第二显示区中子像素的密度。
  20. 一种显示装置，包括：
    壳体，具有器件区；
    如权利要求14所述的显示面板，覆盖在所述壳体上；
    其中，所述器件区位于所述第一显示区下方，且所述器件区中设置有电子元件。
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