WO2021056301A1 - 跨导放大器和芯片 - Google Patents

跨导放大器和芯片 Download PDF

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Publication number
WO2021056301A1
WO2021056301A1 PCT/CN2019/108025 CN2019108025W WO2021056301A1 WO 2021056301 A1 WO2021056301 A1 WO 2021056301A1 CN 2019108025 W CN2019108025 W CN 2019108025W WO 2021056301 A1 WO2021056301 A1 WO 2021056301A1
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Prior art keywords
transistor
source
current
coupled
reference voltage
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PCT/CN2019/108025
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English (en)
French (fr)
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王文祺
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2019/108025 priority Critical patent/WO2021056301A1/zh
Priority to EP19932225.6A priority patent/EP3826174A4/en
Priority to CN201980002093.2A priority patent/CN110785925B/zh
Priority to KR1020207036919A priority patent/KR102531301B1/ko
Priority to US17/115,606 priority patent/US11456709B2/en
Publication of WO2021056301A1 publication Critical patent/WO2021056301A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0222—Continuous control by using a signal derived from the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • H03F3/45206—Folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/453—Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/91—Indexing scheme relating to amplifiers the amplifier has a current mode topology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45112—Indexing scheme relating to differential amplifiers the biasing of the differential amplifier being controlled from the input or the output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45156—At least one capacitor being added at the input of a dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45322—One or more current sources are added to the AAC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45626—Indexing scheme relating to differential amplifiers the LC comprising biasing means controlled by the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs

Definitions

  • This application relates to a transconductance amplifier and chip, and more particularly to a transconductance amplifier and chip that can improve the accuracy and linearity of the transconductance amplifier.
  • the conventional transconductance amplifier In the conventional transconductance amplifier, an AC voltage is applied between the gate and source of the transistor of the input stage, and the drain current generated will be affected by the transconductance of the transistor of the input stage. The transistors of the input stage will therefore cause errors in the transconductance amplifier. Moreover, due to the non-linearity of the transconductance of the transistors of the input stage, the linearity of the transconductance amplifier gradually deteriorates. In addition, the conventional transconductance amplifier also has room for further improvement in power consumption. In view of this, how to improve the above problems has become an important work item in this field.
  • One of the objectives of this application is to disclose a transconductance amplifier and chip to solve the above-mentioned problems.
  • An embodiment of the present application discloses a transconductance amplifier for generating output current according to a positive terminal input voltage and a negative terminal input voltage.
  • the transconductance amplifier includes an input stage that receives the positive terminal input voltage and the negative terminal input voltage.
  • the negative terminal inputs a voltage and generates a positive terminal output current and a negative terminal output current.
  • the input stage includes: a first transistor whose gate is coupled to the positive terminal input voltage; a second transistor whose gate is coupled to all The negative terminal input voltage; a first resistor, connected in series between the first transistor and the second transistor; a third transistor, the source of the third transistor is coupled to the first resistor and the Between the first transistor, the drain of the third transistor is used to output the positive terminal output current; and the fourth transistor, the source of the fourth transistor is coupled to the first resistor and the second resistor Between the transistors, the drain of the fourth transistor is used to output the negative terminal output current; and an output stage is used to generate the output current according to the positive terminal output current and the negative terminal output current.
  • An embodiment of the present application discloses a chip including the above-mentioned transconductance amplifier.
  • the embodiment of the present application improves the transconductance amplifier, which can improve accuracy and save power consumption.
  • FIG. 1 is a schematic diagram of the first embodiment of the transconductance amplifier of this application.
  • FIG. 2 is a schematic diagram of an embodiment of the input stage of the transconductance amplifier of FIG. 1.
  • Fig. 3 is a schematic diagram of an embodiment of the output stage of the transconductance amplifier of Fig. 1.
  • FIG. 4 is a schematic diagram of a second embodiment of the transconductance amplifier of this application.
  • FIG. 5 is a schematic diagram of an embodiment of the input stage of the transconductance amplifier of FIG. 4.
  • FIG. 6 is a schematic diagram of an embodiment of the bias current control circuit of the transconductance amplifier of FIG. 4.
  • FIG. 7 is a schematic diagram of the third embodiment of the transconductance amplifier of this application.
  • FIG. 8 is a schematic diagram of an embodiment of the output stage of the transconductance amplifier of FIG. 7.
  • V BP V BN reference voltage
  • first and second features are in direct contact with each other; and may also include additional components are formed between the above-mentioned first and second features, so that the first and second features may not be in direct contact.
  • content of the present invention may reuse component symbols and/or labels in multiple embodiments. Such repeated use is based on the purpose of brevity and clarity, and does not in itself represent the relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms here such as “below”, “below”, “below”, “above”, “above” and similar, may be used to facilitate the description of the drawing in the figure
  • the relationship between one component or feature relative to another component or feature is shown.
  • the original meaning of these spatially-relative vocabulary covers a variety of different orientations of the device in use or operation, in addition to the orientation shown in the figure.
  • the device may be placed in other orientations (for example, rotated 90 degrees or in other orientations), and these spatially-relative description vocabulary should be explained accordingly.
  • Transconductance amplifiers are used in many different circuits.
  • the input of the transconductance amplifier is voltage and the output is current.
  • the output current divided by the input voltage is defined as the transconductance of the transconductance amplifier.
  • an AC voltage is applied between the gate and source of the transistor of the input stage of the conventional transconductance amplifier, and the generated drain current will be affected by the transconductance of the transistor of the input stage, because the current will flow
  • the input stage transistor passes through, and the current directly affects the output current. Therefore, the transconductance of the input stage transistor will affect the output current of the conventional transconductance amplifier, causing errors.
  • the linearity of the conventional transconductance amplifier is subsequently affected.
  • a fixed amount of bias current is consumed. Therefore, the conventional transconductance amplifier has room for further improvement in power consumption.
  • the transconductance amplifier of the present application can improve the error and linearity of the transconductance amplifier by changing the transistor configuration of the input stage.
  • the power consumption of the transconductance amplifier can be improved.
  • FIG. 1 is a schematic diagram of the first embodiment of the transconductance amplifier of this application.
  • the transconductance amplifier 100 is used to generate the output current I OUT according to the positive terminal input voltage V IP and the negative terminal input voltage V IN .
  • the transconductance amplifier 100 includes an input stage 102 and an output stage 104.
  • the input stage 102 receives the positive terminal input voltage V IP and the negative terminal input voltage V IN and generates a positive terminal output current I OP and a negative terminal output current I ON .
  • the output stage 104 is based on the positive terminal output current I OP and the negative terminal output current I ON Generate output current I OUT .
  • the transconductance amplifier 100 is a rail-to-rail input/output transconductance amplifier.
  • FIG. 2 is a schematic diagram of an embodiment of the input stage of the transconductance amplifier of FIG. 1.
  • the input stage 102 of FIG. 2 includes a first transistor 110, a second transistor 120, a first resistor 109, a third transistor 114, a fourth transistor 124, a fifth transistor 116, a sixth transistor 126, a first current source, and a second current source.
  • the first transistor 110, the second transistor 120, the third transistor 114, and the fourth transistor 124 are P-type transistors; the fifth transistor 116 and the sixth transistor 126 are N-type transistors.
  • the present application is not limited to this.
  • the polarity of the transistors in the input stage 102 can also be changed, for example, the first transistor 110, the second transistor 120, and the third transistor 114 And the fourth transistor 124 are changed to P-type transistors; and the fifth transistor 116 and the sixth transistor 126 are changed to N-type transistors.
  • the transconductance amplifier 100 is a rail-to-rail input/output transconductance amplifier. Therefore, in the input stage 102 of FIG. 2, the first reference voltage V 1 is greater than the third reference voltage V 3 , and the third reference The voltage V 3 is greater than the second reference voltage V 2 . Specifically, the first reference voltage V 1 is twice the third reference voltage V 3 , and the second reference voltage V 2 is the ground voltage. But this application is not limited to this.
  • the gate of the first transistor 110 is coupled to the positive input voltage V IP
  • the gate of the second transistor 120 is coupled to the negative input voltage V IN
  • the first resistor 109 is connected in series to the first transistor Between 110 and the second transistor 120, there is a resistance value R 1.
  • one end of the first resistor 109 is coupled to the source of the first transistor 110
  • the other end of the first resistor 109 is coupled to the second transistor 120 Of the source.
  • the source of the third transistor 114 is coupled to the source of the first transistor 110, the drain of the third transistor 114 is used to output the positive terminal output current I OP ; the source of the fourth transistor 124 is coupled to the source of the second transistor 120 The source and the drain of the fourth transistor 124 are used to output the negative terminal output current I ON .
  • a first current source 111 is coupled between a source of the first transistor and the first reference voltage 110 V, for generating a first bias current source of the first electrode from the reference voltage V 1 is the flow through the first transistor 110;
  • the second current source 112 is coupled between the second reference voltage V 2 and the drain of the first transistor 110 to generate a second bias current from the drain of the first transistor 110 to the second reference voltage V 2 ;
  • the third current source 121 is coupled between the first reference voltage V 1 and the source of the second transistor 120 to generate a third bias current from the first reference voltage V 1 to the source of the second transistor 120;
  • the fourth current source 122 is coupled between the second reference voltage V 2 and the drain of the second transistor 120 to generate a fourth bias current from the drain of the second transistor 120 to the second reference voltage V 2 .
  • the first bias current is greater than the second bias current
  • the third bias current is greater than the fourth bias current.
  • the voltage difference between the positive terminal input voltage V IP and the negative terminal input voltage V IN does not affect the source-to-drain currents of the first transistor 110 and the second transistor 120. That is, the voltage difference between the source of the first transistor 110 and the source of the second transistor 120 (that is, the voltage difference between the two ends of the first resistor 109) and the difference between the positive terminal input voltage V IP and the negative terminal input voltage V IN.
  • the voltage difference is the same and will not be affected by the transconductance of the first transistor 110 and/or the transconductance of the second transistor 120, and the voltage difference between the source of the third transistor 114 and the source of the fourth transistor 124, It will also be the same as the voltage difference between the source of the first transistor 110 and the source of the second transistor 120.
  • the difference between the positive terminal output current I OP and the negative terminal output current I ON is locked at 2*(V IP -V IN )/R 1 .
  • the transconductance of the first transistor 110 and/or the transconductance of the second transistor 120 will not contribute errors to the output current I OUT of the transconductance amplifier 100, and the transconductance of the first transistor 110 and the transconductance of the second transistor 120 The poor linearity of the transconductance itself will not affect the linearity of the transconductance amplifier 100.
  • FIG. 2 also includes a fifth transistor 116, a sixth transistor 126, a seventh current source 115, an eighth current source 125, a first capacitor 117, and a second capacitor 127.
  • the fifth transistor 116 and the sixth transistor 126 are N-type transistors, but the application is not limited thereto.
  • the drain of the fifth transistor 116 is coupled to the gate of the third transistor 114, the source of the fifth transistor 116 is coupled to the second reference voltage V 2 , and the gate of the fifth transistor 116 is coupled to the gate of the first transistor 110 Drain; the drain of the sixth transistor 126 is coupled to the gate of the fourth transistor 124, the source of the sixth transistor 126 is coupled to the second reference voltage V 2 , the gate of the sixth transistor 126 is coupled to the second The drain of the transistor 120; the first capacitor 117 is coupled between the gate and the drain of the fifth transistor 116; the second capacitor 127 is coupled between the gate and the drain of the sixth transistor 126. The first capacitor 117 and the second capacitor 127 are used for loop compensation.
  • the seventh current source 115 is coupled between the third reference voltage V 3 and the drain of the fifth transistor 116; the eighth current source 125 is coupled between the third reference voltage V 3 and the drain of the sixth transistor 126.
  • Fig. 3 is a schematic diagram of an embodiment of the output stage of the transconductance amplifier of Fig. 1.
  • the output stage 104 of the transconductance amplifier 100 of FIG. 3 includes a seventh transistor 131, an eighth transistor 141, a ninth current source 134, a tenth current source 144, and transistors 132, 133, 142, and 143.
  • the seventh transistor 131 and the eighth transistor 141 are N-type transistors, and the transistors 132, 133, 142, and 143 are P-type transistors, but the application is not limited thereto.
  • the source of the seventh transistor 131 is coupled to the drain of the third transistor 114 of the input stage 102 of the transconductance amplifier 100 for receiving the positive output current I OP ; the source of the eighth transistor 141 is coupled to the transconductance amplifier The drain of the fourth transistor 124 of the input stage 102 of 100 is used to receive the negative terminal output current I ON .
  • the gate of the seventh transistor 131 is coupled to the gate of the eighth transistor 141 and is also coupled to the reference voltage V BN .
  • the ninth current source 134 is coupled between the source of the seventh transistor 131 and the second reference voltage V 2 for generating a ninth bias current; the tenth current source 144 is coupled to the source of the eighth transistor 141 and The second reference voltage V 2 is used to generate a tenth bias current.
  • the drain of the transistor 132 is coupled to the drain of the seventh transistor 131, the source of the transistor 132 is coupled to the drain of the transistor 133, the source of the transistor 133 is coupled to the third reference voltage V 3 , and the drain of the transistor 142 Is coupled to the drain of the eighth transistor 141, the source of the transistor 142 is coupled to the drain of the transistor 143, the source of the transistor 143 is coupled to the third reference voltage V 3 , and the gate of the transistor 132 is coupled to the transistor 142 , And coupled to the reference voltage V BP together .
  • the gate of the transistor 133 is coupled to the gate of the transistor 143 and also coupled to the drain of the transistor 132.
  • the transistor 133 and the transistor 143 constitute a current mirror circuit, and convert the positive-side output current I OP and the negative-side output current I ON into an output current I OUT that is output between the drain of the eighth transistor 141 and the drain of the transistor 142.
  • FIG. 4 is a schematic diagram of a second embodiment of the transconductance amplifier of this application.
  • the transconductance amplifier 200 is used to generate the output current I OUT according to the positive terminal input voltage V IP and the negative terminal input voltage V IN .
  • the difference from the transconductance amplifier 100 is that the transconductance amplifier 200 additionally includes a bias current control circuit 206, and in response to the addition of the bias current control circuit 206, the input stage 102 has also been changed to become the input stage 202, and the output stage 104 is also made The change becomes the input stage 304.
  • the input stage 202 receives the positive terminal input voltage V IP and the negative terminal input voltage V IN and generates a positive terminal output current I OP and a negative terminal output current I ON .
  • the output stage 104 is based on the positive terminal output current I OP and the negative terminal output current I ON The output current I ON is generated.
  • the bias current control circuit 206 generates a first control voltage V CTP according to the positive terminal input voltage V IP and the negative terminal input voltage V IN to adjust the bias current in the input stage 202.
  • the bias current control circuit 206 will determine the bias current of the input stage 202 according to the voltage difference between the positive terminal input voltage V IP and the negative terminal input voltage V IN .
  • the embodiment of FIG. 4 can help save the power consumption of the input stage 202.
  • the bias current control circuit 206 of the transconductance amplifier 200 generates a second control voltage V CTN according to the positive terminal input voltage V IP and the negative terminal input voltage V IN to adjust the bias current in the output stage 304, and accordingly
  • the output stage 104 has also been changed to become the input stage 304. Simply put, when the voltage difference between the positive terminal input voltage V IP and the negative terminal input voltage V IN is greater, the output current I OUT of the transconductance amplifier 200 is greater, and the output stage 304 also needs to use a greater bias.
  • the bias current control circuit 206 will determine the bias current of the output stage 304 according to the voltage difference between the positive terminal input voltage V IP and the negative terminal input voltage V IN, compared to not using a bias current control circuit In the case of 206, that is, regardless of the voltage difference between the positive terminal input voltage V IP and the negative terminal input voltage V IN , the output stage 104 requires a fixed bias current.
  • the embodiment of FIG. 4 can further help save the output stage 304. Power consumption.
  • FIG. 5 is a schematic diagram of an embodiment of the input stage 202 of the transconductance amplifier 200 of FIG. 4.
  • the difference between the input stage 202 and the input stage 102 of FIG. 2 lies in the addition of a transistor 118 and a transistor 128.
  • the transistor 118 and the transistor 128 are P-type transistors, but the application is not limited thereto.
  • the source of the transistor 118 is coupled to the first reference voltage V 1
  • the drain of the transistor 118 is coupled to the source of the third transistor 114
  • the source of the transistor 128 is coupled to the first reference voltage V 1
  • the drain of the transistor 128 The electrode is coupled to the source of the fourth transistor 124, and the gates of the transistor 118 and the transistor 128 are controlled by the first control voltage V CTP to adjust the magnitude of the fifth bias current and the sixth bias current to help save input Power consumption of level 202.
  • FIG. 6 is a schematic diagram of an embodiment of the bias current control circuit 206 of the transconductance amplifier 200 of FIG. 4.
  • the bias current control circuit 206 includes a ninth transistor 212, a tenth transistor 222, a second resistor 211, an eleventh current source 213, a twelfth current source 214, a thirteenth current source 223, a fourteenth current source 224, and Transistors 215, 216, 225, 226, 217, 227, 228.
  • the ninth transistor 212, the tenth transistor 222, the transistors 217 and 227 are P-type transistors
  • the transistors 215, 216, 225, 226, and 228 are N-type transistors, but the application is not limited thereto.
  • the gate of the ninth transistor 212 is coupled to the positive terminal input voltage V IP
  • the gate of the tenth transistor 222 is coupled to the negative terminal input voltage V IN
  • the second resistor 211 is connected in series to the ninth transistor Between 212 and the tenth transistor 222, there is a resistance value R 2.
  • one end of the second resistor 211 is coupled to the source of the ninth transistor 212
  • the other end of the second resistor 211 is coupled to the tenth transistor 222 Of the source.
  • the eleventh current source 213 is coupled between the first reference voltage V 1 and the source of the ninth transistor 212 for generating an eleventh bias current from the first reference voltage V 1 to the source of the ninth transistor 212
  • the twelfth current source 214 is coupled between the second reference voltage V 2 and the drain of the ninth transistor 212 to generate a twelfth bias current from the drain of the ninth transistor 212 to the second reference Voltage V 2
  • the thirteenth current source 223 is coupled between the first reference voltage V 1 and the source of the tenth transistor 222 to generate a thirteenth bias current flowing from the first reference voltage V 1 to the tenth
  • the fourteenth current source 224 is coupled between the second reference voltage V 2 and the drain of the tenth transistor 222 to generate a fourteenth bias current flowing from the drain of the tenth transistor 222 To the second reference voltage V 2 .
  • the eleventh bias current is greater than and the twelfth bias current, and the thirteenth bias current is greater than the
  • the source-to-drain currents of the ninth transistor 212 and the tenth transistor 222 in the bias current control circuit 206 are not locked, so the positive terminal input voltage V IP and the negative terminal The voltage difference between the input voltage V IN will be reflected in the twelfth bias current of the twelfth current source 214 and the fourteenth bias current of the fourteenth current source 224. Because the bias current control circuit 206 is only used to generate and control the first control voltage V CTP and not used as an input stage, the error caused by the transconductance of the ninth transistor 212 and the tenth transistor 222 does not affect the overall accuracy. hurt.
  • Transistors 215 and 216 form a first current mirror circuit
  • transistors 225 and 226 form a second current mirror circuit
  • transistor 217 and transistor 227 form a third current mirror circuit.
  • the gate voltage of the transistor 227 can be used as the first control voltage V CTP .
  • the gate voltage of the transistor 228 can be used as the second control voltage V CTN .
  • 7 is a schematic diagram of an embodiment of the output stage 304 of the transconductance amplifier 200 of FIG. 4.
  • the difference between the output stage 304 and the output stage 104 of FIG. 3 is that the ninth current source 134 and the tenth current source 144 of the output stage 104 of FIG. 3 are implemented by a transistor 334 and a transistor 344 respectively in the output stage 304 of FIG.
  • the transistor 334 and the transistor 344 are N-type transistors, but the application is not limited thereto.
  • the source of the transistor 334 is coupled to the second reference voltage V 2
  • the drain of the transistor 334 is coupled to the source of the seventh transistor 131
  • the source of the transistor 344 is coupled to the second reference voltage V 2
  • the drain of the transistor 344 The electrode is coupled to the source of the eighth transistor 141, and the gates of the transistor 334 and the transistor 344 are controlled by the second control voltage V CTN to adjust the magnitude of the ninth bias current and the tenth bias current, thereby further saving output Power consumption of level 304.
  • the application also provides a chip, which includes the above-mentioned transconductance amplifier 100/200.
  • the embodiments of the present application improve the conventional transconductance amplifier, and improve the error and linearity of the transconductance amplifier by changing the transistor configuration of the input stage.
  • the power consumption of the transconductance amplifier can be improved.

Abstract

本申请公开了一种跨导放大器以及相关芯片，所述种跨导放大器用来依据正端输入电压(V IP)与负端输入电压(V IN)产生输出电流，跨导放大器包括：输入级(102)，接收正端输入电压与负端输入电压并产生正端输出电流(I OP)与负端输出电流(I ON)，输入级包括：第一晶体管(110)，其闸极耦接至正端输入电压；第二晶体管(120)，其闸极耦接至负端输入电压；第一电阻(109)，串接于第一晶体管和第二晶体管之间；第三晶体管(114)，第三晶体管的源极耦接至第一电阻和第一晶体管之间，第三晶体管的漏极用以输出正端输出电流；以及第四晶体管(124)，第四晶体管的源极耦接至第一电阻和第二晶体管之间，第四晶体管的漏极用以输出负端输出电流。

Description

跨导放大器和芯片 技术领域
本申请涉及一种跨导放大器和芯片，尤其涉及一种利用能够改善跨导放大器的准确度和线性度的跨导放大器和芯片。
背景技术
习知的跨导放大器中，交流电压加于输入级的晶体管的闸极和源极之间，产生的漏极电流会受所述输入级的晶体管的跨导影响，由于电流会流过所述输入级的晶体管，因此会使所述跨导放大器产成误差。又，由于所述输入级的晶体管的跨导非线性，造成所述跨导放大器的线性度跟著变差，除此之外，习知的跨导放大器在功耗上也有进一步改善的空间。有鉴于此，如何改善上述问题，已成为本领域的一个重要的工作项目。
发明内容
本申请的目的之一在于公开一种跨导放大器和芯片，来解决上述问题。
本申请的一实施例公开了一种跨导放大器，用来依据正端输入电压与负端输入电压产生输出电流，所述跨导放大器包括：输入级，接收所述正端输入电压与所述负端输入电压并产生正端输出电流与负端输出电流，所述输入级包括：第一晶体管，其闸极耦接至所述正端输入电压；第二晶体管，其闸极耦接至所述负端输入电压；第一电阻，串接于所述第一晶体管和所述第二晶体管之间；第三晶体管，所述第三晶体管的源极耦接至所述第一电阻和所述第一晶体管之间，所述第三晶体管的漏极用以输出所述正端输出电流；以及第四晶体管，所述第四晶体管的源极耦接至所述第一电阻和所述第二 晶体管之间，所述第四晶体管的漏极用以输出所述负端输出电流；以及输出级，用来依据所述正端输出电流以及所述负端输出电流产生所述输出电流。
本申请的一实施例公开了一种芯片，包括上述的跨导放大器。
本申请实施例针对跨导放大器进行改良，可提高准确度并节省功耗。
附图说明
图1为本申请的跨导放大器的第一实施例的示意图。
图2为图1的跨导放大器的输入级的实施例的示意图。
图3为图1的跨导放大器的输出级的实施例的示意图。
图4为本申请的跨导放大器的第二实施例的示意图。
图5为图4的跨导放大器的输入级的实施例的示意图。
图6为图4的跨导放大器的偏置电流控制电路的实施例的示意图。
图7为本申请的跨导放大器的第三实施例的示意图。
图8为图7的跨导放大器的输出级的实施例的示意图。
其中，附图标记说明如下：
100、200                  跨导放大器
102、202                  输入级
104、304                  输出级
109                       第一电阻
110                       第一晶体管
111                       第一电流源
112                       第三电流源
114                       第三晶体管
115                       第七电流源
116                          第五晶体管
117                          第一电容
120                          第二晶体管
121                          第二电流源
122                          第四电流源
124                          第四晶体管
125                          第八电流源
126                          第六晶体管
127                          第二电容
131                          第七晶体管
134                          第九电流源
141                          第八晶体管
144                          第十电流源
132、133、142、143、334、344、  晶体管
118、128、215、216、225、226、
217、227、228、334、344
206                          偏置电流控制电路
211                          第二电阻
212                          第九晶体管
213                          第十一电流源
214                          第十二电流源
222                          第十晶体管
223                          第十三电流源
224                          第十四电流源
V IP                          正端输出电压
V IN                          负端输出电压
I OP                          正端输出电流
I ON                          负端输出电流
I OUT                         输出电流
V 1                           第一参考电压
V 2                        第二参考电压
V 3                        第三参考电压
V BP、V BN                  参考电压
V CTP                      第一控制电压
V CTN                      第二控制电压
具体实施方式
以下揭示内容提供了多种实施方式或示例，其能用以实现本发明内容的不同特征。下文所述之组件与配置的具体例子系用以简化本发明内容。当可想见，这些叙述仅为例示，其本意并非用于限制本发明内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本发明内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值 的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比率及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
跨导放大器应用在许多不同的电路中，跨导放大器的输入为电压，输出为电流。输出电流除以输入电压即定义为跨导放大器的跨导。具体来说，交流电压加于习知的跨导放大器的输入级的晶体管的闸极和源极之间，产生的漏极电流会受所述输入级的晶体管的跨导影响，由于电流会流过所述输入级的晶体管，且所述电流直接影响输出电流，因此所述输入级的晶体管的跨导会影响习知的跨导放大器的输出电流，产成误差。又，由于所述输入级的晶体管的跨导非线性，造成习知的跨导放大器的线性度跟著受到影响。除此之外，不管习知的跨导放大器的输出电流的大小，都要消耗固定大小的偏置电流，因此，习知的跨导放大器在功耗上也有进一步改善的空间。
本申请的跨导放大器能藉由改变输入级的晶体管配置来改善跨导放大器的误差并提升线性度。另外，藉由额外的偏置电流控制电路，可改善跨导放大器的功耗。
图1为本申请的跨导放大器的第一实施例的示意图。跨导放大器100用来依据正端输入电压V IP与负端输入电压V IN产生输出电流I OUT。跨导放大器100包括输入级102和输出级104。输入级102接收正端输入电压V IP与负端输入电压V IN并产生正端输出电流I OP与负端输出电流I ON，输出级104依据正端输出电流I OP以及负端输出电流I ON产生输出电流I OUT。在本实施例中，跨导放大器100为轨到轨输入/输出跨导放大器。
图2为图1的跨导放大器的输入级的实施例的示意图。图2的输入级102包括第一晶体管110、第二晶体管120、第一电阻109、第三晶体管114、第四晶体管124、第五晶体管116、第六晶体管126、第一电流源、第二电流源121、第三电流源112、第四电流源122、第七电流源115、第八电流源125、第一电容117以及第二电容127。
在本实施例及接下来的说明中，第一晶体管110、第二晶体管120、第三晶体管114和第四晶体管124为P型晶体管；第五晶体管116和第六晶体管126为N型晶体管。但本申请不以此为限，在某些实施例中，亦可通过对输入级102进行变化来改变其中的晶体管的极性，例如将第一晶体管110、第二晶体管120、第三晶体管114和第四晶体管124改变为P型晶体管；以及将第五晶体管116和第六晶体管126改变为N型晶体管。
在本实施例中，跨导放大器100为轨到轨输入/输出跨导放大器，因此，在图2的输入级102中，第一参考电压V 1大于第三参考电压V 3，以及第三参考电压V 3大于第二参考电压V 2。具体来说，第一参考电压V 1为第三参考电压V 3的两倍，第二参考电压V 2是接地电压。但本申请不以此为限。
如图2所示，第一晶体管110的闸极耦接至正端输入电压V IP，第二晶体管120的闸极耦接至负端输入电压V IN，第一电阻109串接于第一晶体管110和第二晶体管120之间，具有电阻值R 1，具体来说，第一电阻109的一端耦接于第一晶体管110的源极，第一电阻109的另一端耦接于第二晶体管120的源极。第三晶体管114的源极耦接至第一晶体管110的源极，第三晶体管114的漏极用以输出正端输出电流I OP；第四晶体管124的源极耦接至第二晶体管120的源极，第四晶体管124的漏极用以输出负端输出电流I ON。
第一电流源111耦接于第一参考电压V 1和第一晶体管110的源极之间，用来产生第一偏置电流从第一参考电压V 1流至第一晶体管110的源极；第二电流源112耦接于第二参考电压V 2和第一晶体管110的漏极之间，用来产生第二偏置电流从第一晶体管110的漏极 流至第二参考电压V 2；第三电流源121耦接于第一参考电压V 1和第二晶体管120的源极之间，用来产生第三偏置电流从第一参考电压V 1流至第二晶体管120的源极；第四电流源122耦接于第二参考电压V 2和第二晶体管120的漏极之间，用来产生第四偏置电流从第二晶体管120的漏极流至第二参考电压V 2。其中所述第一偏置电流大于和所述第二偏置电流，且所述第三偏置电流大于所述第四偏置电流。
本实施例中，正端输入电压V IP和负端输入电压V IN之间的电压差不会影响第一晶体管110和第二晶体管120的源极到漏极电流。也就是说，第一晶体管110的源极和第二晶体管120的源极之间的电压差(即第一电阻109的两端的电压差)和正端输入电压V IP与负端输入电压V IN的电压差相同，不会受跟第一晶体管110的跨导及/或第二晶体管120的跨导的影响，且第三晶体管114的源极和第四晶体管124的源极之间的电压差，也会和第一晶体管110的源极和第二晶体管120的源极之间的电压差相同。因此，正端输出电流I OP和负端输出电流I ON的差，即I OP-I ON被锁定在2*(V IP-V IN)/R 1。这样一来，第一晶体管110的跨导及/或第二晶体管120的跨导便不会对跨导放大器100的输出电流I OUT贡献误差，第一晶体管110的跨导和第二晶体管120的跨导本身具有的线性度不佳问题也就不会影响跨导放大器100的线性度。
图2中还包括第五晶体管116、第六晶体管126、第七电流源115、第八电流源125、第一电容117、第二电容127。在本实施例中，第五晶体管116和第六晶体管126为N型晶体管，但本申请不以此限。第五晶体管116的漏极耦接于第三晶体管114的闸极，第五晶体管116的源极耦接于第二参考电压V 2，第五晶体管116的闸极耦接于第一晶体管110的漏极；第六晶体管126的漏极耦接于第四晶体管124的闸极，第六晶体管126的源极耦接于第二参考电压V 2，第六晶体管126的闸极耦接于第二晶体管120的漏极；第一电容117耦接于第五晶体管116的闸极和漏极之间；第二电容127耦接于第六晶体管126的闸极和漏极之间。第一电容117和第二电容 127用作回路补偿。第七电流源115耦接于第三参考电压V 3和第五晶体管116的漏极之间；第八电流源125耦接于第三参考电压V 3和第六晶体管126的漏极之间。
图3为图1的跨导放大器的输出级的实施例的示意图。图3的跨导放大器100的输出级104包括第七晶体管131、第八晶体管141、第九电流源134、第十电流源144以及晶体管132、133、142、143。其中第七晶体管131和第八晶体管141为N型晶体管，晶体管132、133、142、143为P型晶体管，但本申请不以此限。
第七晶体管131的源极耦接至跨导放大器100的输入级102的第三晶体管114的漏极，用来接受正端输出电流I OP；第八晶体管141的源极耦接至跨导放大器100的输入级102的第四晶体管124的漏极，用来接受负端输出电流I ON。第七晶体管131的闸极耦接至第八晶体管141的闸极，并一同耦接至参考电压V BN。第九电流源134耦接于第七晶体管131的源极和第二参考电压V 2之间，用来产生第九偏置电流；第十电流源144耦接于第八晶体管141的源极和第二参考电压V 2之间，用来产生第十偏置电流。
晶体管132的漏极耦接至第七晶体管131的漏极，晶体管132的源极耦接至晶体管133的漏极，晶体管133的源极耦接至第三参考电压V 3，晶体管142的漏极耦接至第八晶体管141的漏极，晶体管142的源极耦接至晶体管143的漏极，晶体管143的源极耦接至第三参考电压V 3，晶体管132的闸极耦接至晶体管142的闸极，并一同耦接至参考电压V BP。晶体管133的闸极耦接至晶体管143的闸极，并一同耦接至晶体管132的漏极。晶体管133和晶体管143构成电流镜电路，并将正端输出电流I OP和负端输出电流I ON转换成输出电流I OUT从第八晶体管141的漏极和晶体管142的漏极之间输出。
图4为本申请的跨导放大器的第二实施例的示意图。跨导放大器200用来依据正端输入电压V IP与负端输入电压V IN产生输出电流I OUT。和跨导放大器100的差别在于，跨导放大器200另包括偏 置电流控制电路206，且因应偏置电流控制电路206的加入，输入级102也做了变化成为输入级202，输出级104也做了变化成为输入级304。输入级202接收正端输入电压V IP与负端输入电压V IN并产生正端输出电流I OP与负端输出电流I ON，输出级104依据正端输出电流I OP以及负端输出电流I ON产生输出电流I ON。偏置电流控制电路206依据正端输入电压V IP与负端输入电压V IN产生第一控制电压V CTP，用来调整输入级202中的偏压电流大小，简单来说，当正端输入电压V IP与负端输入电压V IN之间的电压差越大，跨导放大器200的输出电流I OUT越大，输入级202也就需要使用到越大的偏置电流，因此偏置电流控制电路206会依据正端输入电压V IP与负端输入电压V IN之间的电压差来决定输入级202的偏置电流，相较于不使用偏置电流控制电路206的情况，即无论正端输入电压V IP与负端输入电压V IN之间的电压差大小，输入级102都需要固定大小的偏置电流，图4的实施例可以帮助节省输入级202的功耗。
跨导放大器200的偏置电流控制电路206又依据正端输入电压V IP与负端输入电压V IN产生第二控制电压V CTN，用来调整输出级304中的偏压电流大小，且因应此变化，输出级104也做了变化成为输入级304。简单来说，当正端输入电压V IP与负端输入电压V IN之间的电压差越大，跨导放大器200的输出电流I OUT越大，输出级304也就需要使用到越大的偏置电流，因此偏置电流控制电路206会依据正端输入电压V IP与负端输入电压V IN之间的电压差来决定输出级304的偏置电流，相较于不使用偏置电流控制电路206的情况，即无论正端输入电压V IP与负端输入电压V IN之间的电压差大小，输出级104都需要固定大小的偏置电流，图4的实施例可以进一步帮助节省输出级304的功耗。
图5为图4的跨导放大器200的输入级202的实施例的示意图。输入级202和图2的输入级102的差异在于新增了晶体管118和晶体管128，在本实施例中，晶体管118和晶体管128为P型晶体管，但本申请不以此为限。晶体管118的源极耦接至第一参考电压V 1，晶体管118的漏极耦接至第三晶体管114的源极，晶体管128的源 极耦接至第一参考电压V 1，晶体管128的漏极耦接至第四晶体管124的源极，晶体管118和晶体管128的闸极受到第一控制电压V CTP的控制，以调整第五偏置电流和第六偏置电流的大小，藉以帮助节省输入级202的功耗。
图6为图4的跨导放大器200的偏置电流控制电路206的实施例的示意图。偏置电流控制电路206包括第九晶体管212、第十晶体管222、第二电阻211、第十一电流源213、第十二电流源214、第十三电流源223、第十四电流源224以及晶体管215、216、225、226、217、227、228。在本实施例中，第九晶体管212、第十晶体管222、晶体管217和227为P型晶体管，晶体管215、216、225、226和228为N型晶体管，但本申请不以此为限。
如图6所示，第九晶体管212的闸极耦接至正端输入电压V IP，第十晶体管222的闸极耦接至负端输入电压V IN，第二电阻211串接于第九晶体管212和第十晶体管222之间，具有电阻值R 2，具体来说，第二电阻211的一端耦接于第九晶体管212的源极，第二电阻211的另一端耦接于第十晶体管222的源极。
第十一电流源213耦接于第一参考电压V 1和第九晶体管212的源极之间，用来产生第十一偏置电流从第一参考电压V 1流至第九晶体管212的源极；第十二电流源214耦接于第二参考电压V 2和第九晶体管212的漏极之间，用来产生第十二偏置电流从第九晶体管212的漏极流至第二参考电压V 2；第十三电流源223耦接于第一参考电压V 1和第十晶体管222的源极之间，用来产生第十三偏置电流从第一参考电压V 1流至第十晶体管222的源极；第十四电流源224耦接于第二参考电压V 2和第十晶体管222的漏极之间，用来产生第十四偏置电流从第十晶体管222的漏极流至第二参考电压V 2。其中所述第十一偏置电流大于和所述第十二偏置电流，且所述第十三偏置电流大于所述第十四偏置电流。
不像输入级102或202的配置，偏置电流控制电路206中的第九晶体管212和第十晶体管222的源极到漏极电流并没有被锁住， 因此正端输入电压V IP和负端输入电压V IN之间的电压差会反应在第十二电流源214的所述第十二偏置电流和第十四电流源224的所述第十四偏置电流。因为偏置电流控制电路206仅用来产生控制第一控制电压V CTP而非用作输入级，因此第九晶体管212和第十晶体管222的跨导所造成的误差对整体准确度并不会造成伤害。晶体管215和216形成第一电流镜电路，晶体管225和226形成第二电流镜电路，晶体管217和晶体管227形成第三电流镜电路。通过所述第一电流镜电路和所述第二电流镜电路，第九晶体管212和第十晶体管222的漏极电流的电流差会反应在晶体管217的漏极电流。并通过所述形成第三电流镜电路反应到晶体管227的漏极电流。晶体管227的闸极电压即可用作第一控制电压V CTP。
以图4的偏置电流控制电路206来说，晶体管228的闸极电压即可用作第二控制电压V CTN。而图7为图4的跨导放大器200的输出级304的实施例的示意图。输出级304和图3的输出级104的差异在于，图3的输出级104的第九电流源134和第十电流源144在图8的输出级304中分别以晶体管334和晶体管344实现，在本实施例中，晶体管334和晶体管344为N型晶体管，但本申请不以此为限。晶体管334的源极耦接至第二参考电压V 2，晶体管334的漏极耦接至第七晶体管131的源极，晶体管344的源极耦接至第二参考电压V 2，晶体管344的漏极耦接至第八晶体管141的源极，晶体管334和晶体管344的闸极受到第二控制电压V CTN的控制，以调整第九偏置电流和第十偏置电流的大小，藉以进一步节省输出级304的功耗。
本申请还提供了一种芯片，其包括上述的跨导放大器100/200。
本申请实施例针对习知的跨导放大器进行改良，藉由改变输入级的晶体管配置来改善跨导放大器的误差并提升线性度。另外，藉由额外的偏置电流控制电路，可改善跨导放大器的功耗。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本 申请所属技术领域具有通常知识者能够更全面地理解本发明内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本发明内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本发明内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本发明内容之精神与范围。

Claims (15)

  1. 一种跨导放大器，用来依据正端输入电压与负端输入电压产生输出电流，其特征在于，所述跨导放大器包括：
    输入级，接收所述正端输入电压与所述负端输入电压并产生正端输出电流与负端输出电流，所述输入级包括：
    第一晶体管，其闸极耦接至所述正端输入电压；
    第二晶体管，其闸极耦接至所述负端输入电压；
    第一电阻，串接于所述第一晶体管和所述第二晶体管之间；
    第三晶体管，所述第三晶体管的源极耦接至所述第一电阻和所述第一晶体管之间，所述第三晶体管的漏极用以输出所述正端输出电流；以及
    第四晶体管，所述第四晶体管的源极耦接至所述第一电阻和所述第二晶体管之间，所述第四晶体管的漏极用以输出所述负端输出电流；以及
    输出级，用来依据所述正端输出电流以及所述负端输出电流产生所述输出电流。
  2. 如权利要求1所述的跨导放大器，其中所述输入级另包括：
    第一电流源，耦接于第一参考电压和所述第一晶体管的源极之间，用来产生第一偏置电流，所述第一偏置电流的方向是从所述第一参考电压流至所述第一晶体管的所述源极；
    第二电流源，耦接于第二参考电压和所述第一晶体管的漏极之间，用来产生第二偏置电流，所述第二偏置电流的方向是从所述第一晶体管的所述漏极流至所述第二参考电压；
    第三电流源，耦接于所述第一参考电压和所述第二晶体管的源极之间，用来产生第三偏置电流，所述第三偏置电流的方向是从所述第一参考电压流至所述第二晶体管的所述源极；以 及
    第四电流源，耦接于所述第二参考电压和所述第二晶体管的漏极之间，用来产生第四偏置电流，所述第四偏置电流的方向是从所述第二晶体管的所述漏极流至所述第二参考电压。
  3. 如权利要求2所述的跨导放大器，其中所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管均为P型晶体管。
  4. 如权利要求3所述的跨导放大器，其中所述输入级另包括：
    第五晶体管，耦接于所述第三晶体管的闸极和所述第二参考电压之间；以及
    第六晶体管，耦接于所述第四晶体管的闸极和所述第二参考电压之间。
  5. 如权利要求4所述的跨导放大器，其中所述输入级另包括：
    第一电容，耦接于所述第五晶体管的闸极和所述第五晶体管的漏极之间；以及
    第二电容，耦接于所述第六晶体管的闸极和所述第六晶体管的漏极之间。
  6. 如权利要求5所述的跨导放大器，其中所述输入级另包括：
    第七电流源，耦接于第三参考电压和所述第五晶体管的所述漏极之间；以及
    第八电流源，耦接于第三参考电压和所述第六晶体管的所述漏极之间；
    其中所述第三参考电压小于所述第一参考电压并大于所述第二参考电压。
  7. 如权利要求6所述的跨导放大器，其中所述第五晶体管和所述第六晶体管为N型晶体管。
  8. 如权利要求7所述的跨导放大器，其中所述输出级包括：
    第七晶体管，所述第七晶体管的源极耦接至所述第三晶体管的所述漏极；
    第八晶体管，所述第八晶体管的源极耦接至所述第四晶体管的所述漏极；
    第九电流源，耦接于所述第七晶体管的所述源极和所述第二参考电压之间，用来产生第九偏置电流；以及
    第十电流源，耦接于所述第八晶体管的所述源极和所述第二参考电压之间，用来产生第十偏置电流。
  9. 如权利要求8所述的跨导放大器，其中所述第七晶体管和所述第八晶体管为N型晶体管。
  10. 如权利要求9所述的跨导放大器，另包括：
    偏置电流控制电路，用来依据所述正端输入电压与所述负端输入电压产生第一控制电压，所述第一控制电压用来调整所述第五电流源产生的所述第五偏置电流和所述第六电流源产生的所述第六偏置电流的大小。
  11. 如权利要求10所述的跨导放大器，其中所述偏置电流控制电路另用来依据所述正端输入电压与所述负端输入电压产生第二控制电压，所述第二控制电压用来调整所述第九电流源产生的所述第九偏置电流和所述第十电流源产生的所述第十偏置电流的大小。
  12. 如权利要求11所述的跨导放大器，其中所述偏置电流控制电路包括：
    第九晶体管，其闸极耦接至所述正端输入电压；
    第十晶体管，其闸极耦接至所述负端输入电压；
    第二电阻，串接于所述第九晶体管和所述第十晶体管之间。
  13. 如权利要求12所述的跨导放大器，其中所述偏置电流控制电路 另包括：
    第十一电流源，耦接于第一参考电压和所述第九晶体管的源极之间，用来产生第十一偏置电流，所述第十一偏置电流的方向是从所述第一参考电压流至所述第九晶体管的所述源极；
    第十二电流源，耦接于第二参考电压和所述第九晶体管的漏极之间，用来产生第十二偏置电流，所述第十二偏置电流的方向是从所述第九晶体管的所述漏极流至所述第二参考电压；
    第十三电流源，耦接于所述第一参考电压和所述第十晶体管的源极之间，用来产生第十三偏置电流，所述第十三偏置电流的方向是从所述第一参考电压流至所述第十晶体管的所述源极；以及
    第十四电流源，耦接于所述第二参考电压和所述第十晶体管的漏极之间，用来产生第十四偏置电流，所述第十四偏置电流的方向是从所述第十晶体管的所述漏极流至所述第二参考电压；
    其中所述第十一偏置电流大于和所述第十二偏置电流，所述第十三偏置电流大于所述第十四偏置电流。
  14. 如权利要求13所述的跨导放大器，其中所述第九晶体管和所述第十晶体管为P型晶体管。
  15. 一种芯片，其特征在于，包括：
    如权利要求1-14中任一项所述的跨导放大器。
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CN116760368A (zh) * 2023-08-23 2023-09-15 苏州领慧立芯科技有限公司 低噪声比较器的预放大器电路及低噪声比较器
CN116760368B (zh) * 2023-08-23 2023-11-07 苏州领慧立芯科技有限公司 低噪声比较器的预放大器电路及低噪声比较器

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