WO2021051285A1 - Condensateur et son procédé de fabrication - Google Patents

Condensateur et son procédé de fabrication Download PDF

Info

Publication number
WO2021051285A1
WO2021051285A1 PCT/CN2019/106266 CN2019106266W WO2021051285A1 WO 2021051285 A1 WO2021051285 A1 WO 2021051285A1 CN 2019106266 W CN2019106266 W CN 2019106266W WO 2021051285 A1 WO2021051285 A1 WO 2021051285A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive
conductive layer
external electrode
electrically connected
Prior art date
Application number
PCT/CN2019/106266
Other languages
English (en)
Chinese (zh)
Inventor
陆斌
沈健
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2019/106266 priority Critical patent/WO2021051285A1/fr
Priority to CN201980001973.8A priority patent/CN110785840A/zh
Publication of WO2021051285A1 publication Critical patent/WO2021051285A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • This application relates to the field of capacitors, and more specifically, to capacitors and methods of making them.
  • Capacitors can play the role of bypassing, filtering, decoupling, etc. in the circuit, and are an indispensable part of ensuring the normal operation of the circuit.
  • MLCC Multi-layer Ceramic Capacitors
  • trench silicon prepared on silicon wafers Capacitors can reduce the volume of capacitors and increase the density of capacitance.
  • the cost of trench silicon capacitors based on silicon wafers is relatively high. How to prepare low-cost, small-volume, and high-capacity capacitors has become an urgent technical problem to be solved.
  • the embodiments of the present application provide a capacitor and a manufacturing method thereof, which can prepare a trench silicon capacitor based on a non-semiconductor substrate, so that a capacitor with a small volume and a high capacitance density can be manufactured while reducing the cost of the capacitor.
  • a capacitor including:
  • Non-semiconductor substrate
  • the first semiconductor layer is disposed above the non-semiconductor substrate, and at least one first trench array is formed on the first semiconductor layer;
  • At least one first stacked structure is disposed above the first semiconductor layer and fills the at least one first trench array, the first stacked structure includes an N-layer conductive layer and an M-layer dielectric layer, the The N-layer conductive layer and the M-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and N and M are positive integers;
  • At least one first external electrode the first external electrode electrically connected to all odd-numbered conductive layers in the N-layer conductive layer;
  • At least one second external electrode, and the second external electrode is electrically connected to all even-numbered conductive layers in the N-layer conductive layer.
  • the first semiconductor layer is disposed on a non-semiconductor substrate, and at least one first stacked structure is disposed above the first semiconductor layer and fills at least one first trench array, so that a trench type can be prepared.
  • Silicon capacitors can reduce the cost of capacitors while preparing capacitors with a small volume and high capacitance value density.
  • the preparation of silicon capacitors based on non-semiconductor substrates can be compatible with the current mature and low-cost large-size board-level processing technology, and can reduce the unit processing cost of silicon capacitors.
  • an interlayer insulating layer and/or an interlayer conductive layer are provided between the first semiconductor layer and the non-semiconductor substrate.
  • providing an interlayer insulating layer and/or an interlayer conductive layer between the first semiconductor layer and the non-semiconductor substrate can be used to strengthen the gap between the conductive layers at the bottom of the trenches in the first trench array.
  • the electrical connection can also be used as an etch stop layer to enhance the etching accuracy of the trenches in the first trench array, and can also be used to enhance the bonding force between the non-semiconductor substrate and the first semiconductor layer. It can play a role in protecting the first stacked structure in the first semiconductor layer.
  • the interlayer insulating layer and/or the interlayer conductive layer can also play some other roles.
  • the interlayer insulating layer and/or layer The inter-conductive layer can be used as a buffer layer.
  • the interlayer insulating layer and/or the interlayer conductive layer can achieve stress matching between the first semiconductor layer and the non-semiconductor substrate.
  • the interlayer insulating layer is disposed above the interlayer conductive layer, and the trenches in the first trench array penetrate the first semiconductor layer and the interlayer insulating layer
  • the interlayer conductive layer is connected to the conductive layers at the bottoms of different trenches in the first trench array.
  • a release layer is provided between the first semiconductor layer and the non-semiconductor substrate.
  • the release layer can release the non-semiconductor substrate. That is to say, in the embodiment of the present application, the non-semiconductor substrate may be released at the end, that is, the capacitor may not include the non-semiconductor substrate at the end.
  • the non-semiconductor substrate includes at least one of the following:
  • non-semiconductor materials such as glass or substrates as substrates, which can be used to subsequently integrate high-performance inductors to make integrated passive devices (IPD) or integrated IPD interposer boards. ), used in high-frequency applications such as the fifth-generation mobile communication technology (5-Generation, 5G).
  • 5G fifth-generation mobile communication technology
  • different first stacked structures in the at least one first stacked structure share the same first external electrode, and/or, different in the at least one first stacked structure
  • the first laminated structure shares the same second external electrode.
  • the capacitor further includes: a first electrode layer disposed above the at least one first laminated structure, and the first electrode layer includes at least one first conductive region and At least one second conductive region, the first conductive region forms the first external electrode, and the second conductive region forms the second external electrode.
  • the capacitor further includes: a first interconnection structure, the first interconnection structure including a first interlayer dielectric layer, at least one first conductive via structure, and at least one second conductive via structure , wherein the first interlayer dielectric layer covers the at least one first laminated structure, the first conductive via structure and the second conductive via structure penetrate the first interlayer dielectric layer, so The first external electrode is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer through the first conductive via structure, and the second external electrode is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer through the second conductive via structure All the even-numbered conductive layers in the N-layer conductive layer.
  • the capacitor further includes:
  • the first etch stop layer is disposed between the first interconnection structure and the first stack structure, and the first conductive via structure and the second conductive via structure penetrate through the first etch Stop the layer.
  • the capacitor further includes:
  • the second semiconductor layer is arranged above the second interlayer dielectric layer, and at least one second trench array is formed on the second semiconductor layer;
  • At least one second stacked structure is disposed above the second semiconductor layer and fills the at least one second trench array, the second stacked structure includes a P-layer conductive layer and a Q-layer dielectric layer, the The P-layer conductive layer and the Q-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and P and Q are positive integers;
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer
  • the second external electrode is electrically connected to all even-numbered conductive layers in the P-layer conductive layer
  • the first external electrode is electrically connected to all even-numbered conductive layers in the P-layer conductive layer
  • the second external electrode is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer.
  • the number of the at least one first trench array is the same as the number of the at least one second trench array.
  • the number of grooves in the first groove array is the same as the number of grooves in the second groove array, and/or the number of grooves in the first groove array
  • the dimensions of the grooves are the same as the dimensions of the grooves in the second groove array.
  • the at least one first trench array and the at least one second trench array completely overlap in the vertical direction.
  • the at least one first trench array and the at least one second trench array can be prepared by the same etching process, which simplifies the etching process.
  • the trenches in the second trench array penetrate the second semiconductor layer and the second interlayer dielectric layer, and the P-layer conductive layer and the N-layer conductive layer are Part of the conductive layer is electrically connected.
  • different second stacked structures in the at least one second stacked structure share the same first external electrode, and/or, in the at least one second stacked structure Different second laminated structures share the same second external electrode.
  • the capacitor further includes: a second electrode layer disposed above the at least one second laminated structure, and the second electrode layer includes at least one third conductive region and At least one fourth conductive region, the third conductive region forms the first external electrode, and the fourth conductive region forms the second external electrode.
  • the capacitor further includes: a second interconnection structure, the second interconnection structure including a third interlayer dielectric layer, at least one third conductive via structure, and at least one fourth conductive via structure ,
  • the third interlayer dielectric layer covers the at least one second laminated structure and the second interlayer dielectric layer, and the third conductive via structure and the fourth conductive via structure penetrate the first Three interlayer dielectric layers;
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the third conductive via structure
  • the second external electrode is electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure;
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the third conductive via structure, and the first conductive layer
  • the two external electrodes are electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure.
  • the capacitor further includes:
  • the second etch stop layer is disposed between the second interconnection structure and the second stack structure, and the third conductive via structure and the fourth conductive via structure penetrate through the second etch Stop the layer.
  • the first laminated structure includes a first conductive layer, a first dielectric layer, and a second conductive layer.
  • the first conductive layer is disposed above the first semiconductor layer and in the first trench array.
  • the second conductive layer is disposed above the first semiconductor layer and fills the first trench array, and the first dielectric layer is disposed between the first conductive layer and the second conductive layer to connect
  • the first conductive layer is isolated from the second conductive layer; and the second laminated structure includes a third conductive layer, a second dielectric layer, and a fourth conductive layer, and the third conductive layer is disposed on the first conductive layer.
  • the fourth conductive layer is disposed above the second semiconductor layer and fills the second trench array, and the second dielectric layer is disposed on the Between the third conductive layer and the fourth conductive layer to isolate the third conductive layer from the fourth conductive layer;
  • the trenches in the second trench array penetrate the second semiconductor layer and the second interlayer dielectric layer to expose the second conductive layer, the second conductive layer and the third
  • the conductive layer is electrically connected
  • the first external electrode is electrically connected to the first conductive layer and the fourth conductive layer
  • the second external electrode is electrically connected to the second conductive layer and the third conductive layer .
  • the second semiconductor layer is further formed with at least one trench, and the second semiconductor layer includes a conductive structure disposed in the at least one trench, and the at least one trench is self-contained
  • the upper surface of the second semiconductor layer penetrates the second semiconductor layer and the second interlayer dielectric layer downward to expose the first conductive layer, and the first external electrode is electrically connected through the conductive structure To the first conductive layer.
  • the size of the at least one trench is smaller than the size of the trenches in the at least one second trench array.
  • the size of the at least one trench is less than or equal to 2D, where D is the thickness of the third conductive layer.
  • the conductive layer includes at least one of the following:
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer, metal oxynitride layer.
  • a method for manufacturing a capacitor including:
  • At least one first stacked structure is prepared, the first stacked structure is disposed above the first semiconductor layer and fills the at least one first trench array, and the first stacked structure includes an N-layer conductive layer And an M dielectric layer, the N conductive layer and the M dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and N and M are positive integers;
  • At least one first external electrode and at least one second external electrode are prepared, wherein the first external electrode is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer, and the second external electrode is electrically connected to all the odd-numbered conductive layers in the n-layer conductive layer. All the even-numbered conductive layers in the n-layer conductive layer.
  • an interlayer insulating layer and/or an interlayer conductive layer are provided between the first semiconductor layer and the non-semiconductor substrate.
  • the interlayer insulating layer is disposed above the interlayer conductive layer, and the trenches in the first trench array penetrate the first semiconductor layer and the interlayer insulating layer
  • the interlayer conductive layer is connected to the conductive layers at the bottoms of different trenches in the first trench array.
  • a release layer is provided between the first semiconductor layer and the non-semiconductor substrate.
  • the non-semiconductor substrate includes at least one of the following:
  • different first stacked structures in the at least one first stacked structure share the same first external electrode, and/or, different in the at least one first stacked structure
  • the first laminated structure shares the same second external electrode.
  • the preparing at least one first external electrode and at least one second external electrode includes:
  • a first electrode layer is prepared above the at least one first laminated structure, and the first electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms the A first external electrode, and the second conductive area forms the second external electrode.
  • the method further includes:
  • a first interconnection structure is prepared.
  • the first interconnection structure includes a first interlayer dielectric layer, at least one first conductive via structure, and at least one second conductive via structure, wherein the first interlayer dielectric layer covers the The at least one first laminated structure, the first conductive via structure and the second conductive via structure penetrate the first interlayer dielectric layer, and the first external electrode passes through the first conductive via
  • the structure is electrically connected to all the odd-numbered conductive layers in the N-layer conductive layer, and the second external electrode is electrically connected to all the even-numbered conductive layers in the N-layer conductive layer through the second conductive via structure .
  • the method further includes:
  • a first etch stop layer is prepared, the first etch stop layer is disposed between the first interconnection structure and the first stack structure, and the first conductive via structure and the second conductive via The hole structure penetrates the first etch stop layer.
  • the method further includes:
  • the second semiconductor layer is disposed above the second interlayer dielectric layer, and at least one second trench array is formed on the second semiconductor layer;
  • At least one second stacked structure is prepared, the second stacked structure is disposed above the second semiconductor layer and fills the at least one second trench array, and the second stacked structure includes a P layer conductive A layer and a Q-layer dielectric layer, the P-layer conductive layer and the Q-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and P and Q are positive integers;
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer
  • the second external electrode is electrically connected to all even-numbered conductive layers in the P-layer conductive layer
  • the first external electrode is electrically connected to all even-numbered conductive layers in the P-layer conductive layer
  • the second external electrode is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer.
  • the number of the at least one first trench array is the same as the number of the at least one second trench array.
  • the number of grooves in the first groove array is the same as the number of grooves in the second groove array, and/or the number of grooves in the first groove array
  • the dimensions of the grooves are the same as the dimensions of the grooves in the second groove array.
  • the at least one first trench array and the at least one second trench array completely overlap in the vertical direction.
  • the trenches in the second trench array penetrate the second semiconductor layer and the second interlayer dielectric layer, and the P-layer conductive layer and the N-layer conductive layer are Part of the conductive layer is electrically connected.
  • different second stacked structures in the at least one second stacked structure share the same first external electrode, and/or, in the at least one second stacked structure Different second laminated structures share the same second external electrode.
  • the preparing at least one first external electrode and at least one second external electrode includes:
  • a second electrode layer is prepared above the at least one second laminated structure, and the second electrode layer includes at least one third conductive region and at least one fourth conductive region that are separated from each other, and the third conductive region forms the The first external electrode, and the fourth conductive area form the second external electrode.
  • the method further includes:
  • a second interconnection structure is prepared.
  • the second interconnection structure includes a third interlayer dielectric layer, at least one third conductive via structure and at least one fourth conductive via structure, and the third interlayer dielectric layer covers the at least A second laminated structure and the second interlayer dielectric layer, and the third conductive via structure and the fourth conductive via structure penetrate the third interlayer dielectric layer;
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the third conductive via structure
  • the second external electrode is electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure;
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the third conductive via structure, and the first conductive layer
  • the two external electrodes are electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure.
  • the method further includes:
  • a second etch stop layer is prepared, the second etch stop layer is disposed between the second interconnection structure and the second stack structure, and the third conductive via structure and the fourth conductive via The hole structure penetrates the second etch stop layer.
  • the first laminated structure includes a first conductive layer, a first dielectric layer, and a second conductive layer.
  • the first conductive layer is disposed above the first semiconductor layer and in the first trench array.
  • the second conductive layer is disposed above the first semiconductor layer and fills the first trench array, and the first dielectric layer is disposed between the first conductive layer and the second conductive layer to connect
  • the first conductive layer is isolated from the second conductive layer; and the second laminated structure includes a third conductive layer, a second dielectric layer, and a fourth conductive layer, and the third conductive layer is disposed on the first conductive layer.
  • the fourth conductive layer is disposed above the second semiconductor layer and fills the second trench array, and the second dielectric layer is disposed on the Between the third conductive layer and the fourth conductive layer to isolate the third conductive layer from the fourth conductive layer;
  • the trenches in the second trench array penetrate the second semiconductor layer and the second interlayer dielectric layer to expose the second conductive layer, the second conductive layer and the third
  • the conductive layer is electrically connected
  • the first external electrode is electrically connected to the first conductive layer and the fourth conductive layer
  • the second external electrode is electrically connected to the second conductive layer and the third conductive layer .
  • the second semiconductor layer is further formed with at least one trench, and the second semiconductor layer includes a conductive structure disposed in the at least one trench, and the at least one trench is self-contained
  • the upper surface of the second semiconductor layer penetrates the second semiconductor layer and the second interlayer dielectric layer downward to expose the first conductive layer, and the first external electrode is electrically connected through the conductive structure To the first conductive layer.
  • the size of the at least one trench is smaller than the size of the trenches in the at least one second trench array.
  • the size of the at least one trench is less than or equal to 2D, where D is the thickness of the third conductive layer.
  • the first semiconductor layer is disposed on a non-semiconductor substrate, and at least one first stacked structure is disposed above the first semiconductor layer and fills at least one first trench array, so that trenches can be prepared.
  • Trough silicon capacitors can reduce the cost of capacitors while preparing capacitors with a small volume and high capacitance value density.
  • the preparation of silicon capacitors based on non-semiconductor substrates can be compatible with the current mature and low-cost large-size board-level processing technology, and can reduce the unit processing cost of silicon capacitors.
  • Fig. 1 is a schematic structural diagram of a capacitor according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a trench array and laminated structure provided by the present application.
  • FIG. 3 is a schematic diagram of another trench array and laminated structure provided by the present application.
  • Fig. 4 is a schematic structural diagram of yet another capacitor according to an embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of yet another capacitor according to an embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 9 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of yet another semiconductor substrate according to an embodiment of the present application.
  • FIGS. 11a to 11h are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.
  • 12a to 12n are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.
  • capacitors in the embodiments of the present application can perform functions such as bypassing, filtering, and decoupling in the circuit.
  • the capacitor described in the embodiments of the present application may be a 3D silicon capacitor, which is a new type of capacitor based on semiconductor wafer processing technology. Compared with traditional MLCC (multilayer ceramic capacitors), 3D silicon capacitors have the advantages of small size, high precision, high stability, and long life.
  • the basic processing flow needs to process high-aspect-ratio deep holes (Via), trenches (Trench), pillars (Pillar), wall (Wall) and other 3D structures on the wafer or substrate first, and then in the 3D structure
  • An insulating film and a low-resistivity conductive material are deposited on the surface to make the lower electrode, the dielectric layer and the upper electrode of the capacitor in sequence.
  • the existing silicon capacitors generally adopt a multi-layer stacking technical solution.
  • a metal interconnection structure is used to connect multiple capacitors in parallel.
  • the cost of trench silicon capacitors based on silicon wafers is relatively high.
  • this application proposes a new type of capacitor structure and manufacturing method, which is based on a non-semiconductor substrate to prepare trench silicon capacitors, which can reduce the capacitance of the capacitors while preparing small-volume, high-capacitance-density capacitors. cost.
  • the capacitors in FIGS. 1 to 8 are only examples, and the number of first trench arrays formed in the first semiconductor layer and the number of trenches in the first trench array are not limited to those shown in FIGS. 1 to 8 As shown by the capacitor in Figure 8, it can be determined according to actual needs. In the same way, the number of the first stacked structure included in the capacitor, and the number of conductive layers and the number of dielectric layers included in the first stacked structure are merely examples, and are not limited to the capacitors shown in FIGS. 1 to 8. It can be flexibly set according to actual needs.
  • FIG. 1 is a possible structural diagram of a capacitor 100 according to an embodiment of the present application.
  • the capacitor 100 includes a non-semiconductor substrate 110, a first semiconductor layer 120, at least one stacked structure 130, at least one first external electrode 140, and at least one second external electrode 150.
  • the first semiconductor layer 120 is disposed above the non-semiconductor substrate 110, and the first semiconductor layer 120 is formed with at least one first trench array 10;
  • the first stacked structure 130 is disposed above the first semiconductor layer 120 and fills the at least one first trench array 10.
  • the first stacked structure 130 includes an N conductive layer and an M dielectric layer.
  • the N conductive layer Layer and the M dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and N and M are positive integers;
  • the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N conductive layer;
  • the two external electrodes 150 are electrically connected to all the even-numbered conductive layers in the N-layer conductive layer.
  • N two adjacent conductive layers in the N-layer conductive layer are electrically isolated.
  • the first semiconductor layer is disposed on the non-semiconductor substrate, and at least one first stacked structure is disposed above the first semiconductor layer and fills at least one first trench array, so that the trench type can be prepared.
  • Silicon capacitors can reduce the cost of capacitors while preparing capacitors with a small volume and high capacitance value density. That is, the laminated structure in which the conductive layer and the dielectric layer are alternately stacked can obtain a larger capacitance value in the case of a smaller device size, thereby improving the capacitance value density of the capacitor.
  • the preparation of silicon capacitors based on non-semiconductor substrates can be compatible with the current mature and low-cost large-scale board-level processing technology. For example, square plates with a size of several hundred centimeters can be processed, and silicon wafers with a diameter of 20-30 centimeters can be processed. In comparison, it has a greater cost advantage, that is, it can reduce the unit processing cost of silicon capacitors.
  • the order of the M dielectric layers may be: in the first trench array 10, the distance from the first semiconductor layer 120 is from small to large or from large to large. Small order.
  • the sequence of the N conductive layers can also be: in the first trench array 10, the distance from the first semiconductor layer 120 is ascending or descending.
  • the sequence of the M-layer dielectric layer and the N-layer conductive layer in the embodiment of the present application is illustrated by taking the order of the distance from the first semiconductor layer 120 in the first trench array 10 from small to large as an example.
  • the first trench array 10 may include one trench or multiple trenches, and the multiple trenches may be distributed in an array. As shown in FIG. 1, the first trench array 10 includes 2 grooves distributed in an array.
  • the depth and width of the grooves in the first groove array 10 can be flexibly set according to actual needs.
  • the grooves in the first groove array 10 have a high aspect ratio.
  • the grooves in the first groove array 10 may be holes with a small difference in length and width in cross section, or may be holes with a large difference in length and width.
  • the trench may also be a 3D structure such as Pillar or Wall.
  • the cross-section can be understood as a cross-section parallel to the surface of the non-semiconductor substrate 110, while in FIG. 1 it is a cross-section along the longitudinal direction of the non-semiconductor substrate 110.
  • external electrodes in the embodiments of the present application may also be referred to as pads or external pads.
  • one trench array corresponds to one laminated structure.
  • a first stacked structure 1 is provided in the first trench array A
  • a first stacked structure 2 is provided in the first trench array B
  • the first stacked structure 1 is connected to the first stacked structure.
  • the corresponding conductive layers in the layer structure 2 are connected, and the first stacked structure 1 and the corresponding dielectric layer in the first stacked structure 2 are connected.
  • FIG. 2 shows that, as shown in FIG.
  • a first stacked structure 3 is provided in the first trench array C
  • a first stacked structure 4 is provided in the first trench array D
  • the first stacked structure 3 is The corresponding conductive layers in the stacked structure 4 are connected, and the first stacked structure 3 is connected with the corresponding dielectric layer in the first stacked structure 4.
  • the corresponding conductive layers and/or dielectric layers in different first laminated structures may be isolated or connected together.
  • the non-semiconductor substrate 110 includes but is not limited to at least one of the following:
  • the non-semiconductor substrate 110 may include glass, quartz, ceramics, glass fiber and resin-containing substrates, carrier-like substrates, or other organic polymer substrates, or may be a lining made of a mixture of the above materials or laminated. bottom.
  • the non-semiconductor substrate 110 may be circular or square.
  • non-semiconductor materials such as glass or substrates as substrates, which can be used for subsequent integration of high-performance inductors, production of IPD or integrated IPD adapter boards, for high-frequency applications such as 5G.
  • the first semiconductor layer 120 may be a silicon layer or other semiconductor layers.
  • the silicon layer may be, for example, an amorphous silicon layer or a polysilicon layer.
  • the surface of the first semiconductor layer 120 may include one or more of an epitaxial layer, an oxide layer, a doped layer, and a bonding layer.
  • a low temperature or high temperature chemical vapor deposition (Chemical Vapor Deposition, CVD) process may be used to grow an amorphous silicon layer or a polysilicon layer on the upper surface of the non-semiconductor substrate 110.
  • CVD Chemical Vapor Deposition
  • a silicon layer with a thickness ranging from 1 ⁇ m to 15 ⁇ m is grown on the upper surface of the non-semiconductor substrate 110 as the first semiconductor layer 120.
  • a 2 ⁇ m thick silicon layer is grown on the upper surface of the non-semiconductor substrate 110 as the first semiconductor layer 120.
  • a bonding process may be used to bond the first semiconductor layer 120 on the upper surface of the non-semiconductor substrate 110.
  • the thickness of the first semiconductor layer 120 is less than a first threshold, for example, the first threshold is 40 ⁇ m.
  • the thickness of the non-semiconductor substrate 110 can also be flexibly set according to actual needs. For example, when the thickness of the non-semiconductor substrate 110 is too thick to meet the requirements, the thickness of the non-semiconductor substrate 110 can be adjusted The non-semiconductor substrate 110 is thinned.
  • the material of the first external electrode 140 and the second external electrode 150 may be metal, such as copper, aluminum, or the like.
  • the first external electrode 140 and the second external electrode 150 may also include low resistivity Ti, TiN, Ta, TaN layers as an adhesion layer and/or barrier layer; they may also include some metal layers on the surface of the external electrode, such as Ni, Pd (palladium), Au, Sn (tin), Ag are used for subsequent wire bonding or welding processes.
  • the conductive layer includes at least one of the following:
  • the material of the conductive layer described in the embodiments of the present application may be heavily doped polysilicon, carbon, aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), nickel (Ni) and other metals, tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), nitride Low-resistivity compounds such as tantalum silicon (TaSiN) and tantalum carbon nitride (TaCN), or a combination of the above-mentioned materials and a laminated structure.
  • the specific conductive material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the conductive layer described in the embodiment of the present application may also include some other conductive materials, which is not limited in the embodiment of the present application.
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer and metal oxynitride layer.
  • the material of the dielectric layer described in the embodiments of the present application may be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, or metal oxynitride.
  • SiO 2 , SiN, SiON, or high-k materials including Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , La 2 O 3 , HfSiO 4 , LaAlO 3 , SrTiO 3 , LaLuO 3 and so on.
  • the dielectric layer in the laminated structure 120 may be one layer or include multiple laminated layers, and may be one material or a combination or mixture of multiple materials.
  • the specific insulation material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the dielectric layer described in the embodiment of the present application may also include some other insulating materials, which is not limited in the embodiment of the present application.
  • first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer
  • second external electrode 150 is electrically connected to all even-numbered conductive layers in the N-layer conductive layer
  • the capacitor 100 includes a laminated structure, denoted as laminated structure 1, and includes two first external electrodes and two second external electrodes, and the two first external electrodes are respectively denoted as first external electrodes.
  • a and the first external electrode B, the two second external electrodes are respectively denoted as the second external electrode C and the second external electrode D
  • the laminated structure 1 includes 5 conductive layers, 4 dielectric layers, and 5 conductive layers They are denoted as conductive layer 1, conductive layer 2, conductive layer 3, conductive layer 4, and conductive layer 5, respectively.
  • the four dielectric layers are denoted as dielectric layer 1, dielectric layer 2, dielectric layer 3, and dielectric layer 4, respectively.
  • the first external electrode A is electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5, and the first external electrode B is also electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5.
  • the second external electrode C is electrically connected to the conductive layer 2 and the conductive layer 4, and the second external electrode D is also electrically connected to the conductive layer 2 and the conductive layer 4.
  • the capacitor corresponding to the electrode C, the conductive layer 1 and the conductive layer 2 form a capacitor 1, the capacitance value is denoted as C1, the conductive layer 2 and the conductive layer 3 form a capacitor 2, the capacitance value is denoted as C2, the conductive layer 3 and the The conductive layer 4 forms a capacitor 3, the capacitance value is denoted as C3, the conductive layer 4 and the conductive layer 5 form a capacitor 4, the capacitance value is denoted as C4, the capacitor 1, the capacitor 2, the capacitor 3 and the capacitor 4 are connected in parallel, and its equivalent capacitance i
  • the capacitance value is denoted as C1, the conductive layer 2 and the conductive layer 3 form a capacitor 2
  • the capacitance value is denoted as C
  • the capacitors corresponding to the first external electrode A and the second external electrode D can also be formed in a similar series-parallel structure, and the capacitors corresponding to the first external electrode B and the second external electrode C can also be formed similarly.
  • the series-parallel structure will not be repeated here.
  • different first stacked structures 130 in the at least one first stacked structure 130 share the same first external electrode 140, and/or, different first stacked structures 130 in the at least one first stacked structure 130
  • the stacked structure 130 shares the same second external electrode 150.
  • a first external electrode 140 may be electrically connected to a part or all of the first stacked structure 130 in the at least one first stacked structure 130, and similarly, a second external electrode 150 may also be electrically connected to a part or all of the first stacked structure 130 in the at least one first stacked structure 130.
  • the capacitor 100 includes two first stacked structures, a first external electrode P, a second external electrode Q, and a second external electrode Z, and the two first stacked structures are respectively denoted as the first stacked structure A and the first laminated structure B.
  • the first external electrode P is electrically connected to all the odd-numbered conductive layers of the first stacked structure A and all the odd-numbered conductive layers of the first stacked structure B
  • the second external electrode Q is electrically connected to the first stacked layer All the even-numbered conductive layers of the structure A
  • the second external electrode Z is electrically connected to all the even-numbered conductive layers of the first laminated structure B
  • the first external electrode P and the second external electrode Q form an equivalent capacitor 1
  • the capacitance is denoted as C1
  • the first external electrode P and the second external electrode Z form an equivalent capacitor 2
  • the capacitance is denoted as C2.
  • the first stacked structure 130 may include two conductive layers, such as the conductive layer 1301 and the conductive layer 1302 shown in FIG. 1, and one layer.
  • a dielectric layer such as the dielectric layer 1311 shown in FIG. 1.
  • the conductive layer 1301 is disposed on the upper surface of the first semiconductor layer 120 and the inner surface of the first trench array 10
  • the conductive layer 1302 is disposed on the first semiconductor layer 120 and fills the first trench array 10,
  • the dielectric layer 1311 is disposed between the conductive layer 1301 and the conductive layer 1302.
  • the corresponding conductive layers and dielectric layers in the two first stacked structures 130 are connected, that is, the two first stacked structures 130 share the same one.
  • the first stacked structure 130 may include three conductive layers, which are respectively denoted as conductive layer 1301, conductive layer 1302, and conductive layer 1302.
  • the conductive layer 1303 and the two dielectric layers are denoted as a dielectric layer 1311 and a dielectric layer 1312, respectively.
  • the conductive layer 1301 is disposed on the upper surface of the first semiconductor layer 120 and the inner surface of the first trench array 10
  • the conductive layer 1302 is disposed above the first semiconductor layer 120 and in the first trench array 10.
  • the dielectric layer 1311 is disposed between the conductive layer 1301 and the conductive layer 1302, the conductive layer 1303 is disposed above the first semiconductor layer 120 and fills the first trench array 10, and the dielectric layer 1312 is disposed on the conductive layer 1302 And the conductive layer 1303.
  • the two first stacked structures 130 respectively fill the two first trench arrays 10, and only the conductive layer 1301 of the two first stacked structures 130
  • the two first stacked structures 130 share the same first external electrode 140, and the two first stacked structures 130 are respectively provided with respective second external electrodes 150.
  • the first external electrode 140 and/or the second external electrode 150 are electrically connected to the conductive layer of the N-layer conductive layer through the first interconnection structure 160.
  • the first interconnection structure 160 includes a first interlayer dielectric layer 161, at least one first conductive via structure 162, and at least one second conductive via structure 163, wherein the The first interlayer dielectric layer 161 covers the at least one first stacked structure 130, the first conductive via structure 162 and the second conductive via structure 163 penetrate the first interlayer dielectric layer 161, and the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer through the first conductive via structure 162, and the second external electrode 150 is electrically connected to the N-layer conductive layer through the second conductive via structure 163 All even-numbered conductive layers in.
  • first interlayer dielectric layer 161 may also be referred to as an intermetal dielectric layer (IMD) or an insulating layer.
  • IMD intermetal dielectric layer
  • the first conductive via structure 162 and the second conductive via structure 163 may also be referred to as conductive channels.
  • the first interlayer dielectric layer 161 may be at least one insulating layer.
  • the first interlayer dielectric layer 161 covers the first laminated structure 130, that is, the first interlayer dielectric layer 161 can fill a cavity or gap formed on the upper surface of the first laminated structure 130 to improve The structural integrity and mechanical stability of the capacitor.
  • the material of the first interlayer dielectric layer 161 may be an organic polymer material, including polyimide, Parylene, benzocyclobutene (BCB), etc.; or Some inorganic materials, including spin-on glass (SOG), undoped silicon glass (USG), boro-silicate glass (BSG), phospho-silicate glass (phospho-silicate glass) , PSG), boro-phospho-silicate glass (BPSG), silicon oxide synthesized by tetraethoxysilane (Tetraethyl Orthosilicate, TEOS), silicon oxide, nitride, ceramic; it can also be the above Combinations or stacks of materials.
  • SOG spin-on glass
  • USG undoped silicon glass
  • BSG boro-silicate glass
  • phospho-silicate glass phospho-silicate glass
  • PSG boro-phospho-silicate glass
  • BPSG boro-phospho-silicate glass
  • the material of the first conductive via structure 162 and the second conductive via structure 163 may be made of a low-resistivity conductive material, such as heavily doped polysilicon, tungsten, Ti, TiN, Ta, TaN.
  • first conductive via structure 162 and the second conductive via structure 163 may be specifically determined according to the manufacturing process of the capacitor 100, which is not limited in the embodiment of the present application.
  • a first etch stop layer 170 may be provided between the first interconnect structure 160 and the first stacked structure 130, and the first conductive via structure in the first interconnect structure 160 162 and the second conductive via structure 163 penetrate the first etch stop layer 170.
  • the first etch stop layer 170 is more resistant to etching than the first interlayer dielectric layer 161.
  • the first conductive via structure 162 and the second conductive via structure 163 are etched, the The bottom of the via stays on the first etch stop layer 170 of different depths, and then a dry or wet process is used to remove part of the first etch stop layer 170 exposed at the bottom of the via, so that the first conductive via structure 162 and the second conductive via structure 163 penetrate the first etch stop layer 170.
  • the arrangement of the first etch stop layer 170 can ensure that the etching of the first conductive via structure 162 and the second conductive via structure 163 will not damage the conductive layer and/or the dielectric layer in the first stacked structure 130 .
  • the first etch stop layer 170 may be silicon oxide, silicon nitride, USG, BSG, PSG, BPSG) deposited by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process; it may also be atomic layer deposition. (Atomic layer deposition, ALD) deposited alumina; or sprayed or spin-coated SOG, polyimide, etc.; it can also be a combination of the above materials.
  • CVD chemical Vapor Deposition
  • the first stacked structure 130 is provided with a step structure, and the first conductive via structure 162 and the second conductive via structure 163 are provided on the step structure, so that The first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer through the first conductive via structure 162, and the second external electrode 150 is electrically connected to the N-layer through the second conductive via structure 163. All even-numbered conductive layers in the conductive layer are electrically connected.
  • step structure facilitates the connection and/or isolation between different conductive layers.
  • the first etch stop layer 170 provided on the stepped structure can enhance the electrical insulation between adjacent conductive layers in the first stacked structure 130, and at the same time, the stepped structure can facilitate the first interconnection structure 160.
  • the conductive layers in the first stacked structure 130 are connected.
  • the at least one first external electrode 140 and the at least one second external electrode 150 are disposed above the at least one first stacked structure 130.
  • the capacitor 100 further includes: a first electrode layer disposed above the at least one first laminated structure 130, and the first electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other. Area, the first conductive area forms the first external electrode 140, and the second conductive area forms the second external electrode 150.
  • the first electrode layer is disposed on the first interconnection structure. The upper surface of the first interlayer dielectric layer 161 in 160. That is, the at least one first external electrode 140 and the at least one second external electrode 150 can be formed by one etching, which reduces the etching steps.
  • an interlayer insulating layer 180 and/or an interlayer conductive layer 190 is provided between the first semiconductor layer 120 and the non-semiconductor substrate 110.
  • a bonding layer may also be provided between the first semiconductor layer 120 and the non-semiconductor substrate 110, so that the first semiconductor layer 120 can be disposed on the upper surface of the non-semiconductor substrate 110 through a bonding process.
  • an interlayer insulating layer 180 and/or an interlayer conductive layer 190 between the first semiconductor layer 120 and the non-semiconductor substrate 110 can be used to strengthen the bottom of the trenches in the first trench array 10.
  • the electrical connection between the conductive layers can also be used as an etch stop layer to enhance the etching accuracy of the trenches in the first trench array 10, and can also be used to strengthen the non-semiconductor substrate 110 and the first semiconductor layer.
  • the bonding force between 120 can also play a role in protecting the first stacked structure 130 in the first semiconductor layer 120.
  • the interlayer insulating layer 180 and/or the interlayer conductive layer 190 can also play some other functions.
  • the interlayer insulating layer 180 and/or the interlayer conductive layer 190 may serve as a buffer layer.
  • the interlayer insulating layer 180 and/or the interlayer conductive layer 190 may achieve stress matching between the first semiconductor layer 120 and the non-semiconductor substrate 110.
  • the interlayer insulating layer 180 is disposed above the interlayer conductive layer 190, the trenches in the first trench array 10 penetrate the first semiconductor layer 120 and the interlayer insulating layer 180, and the interlayer conductive layer 190 is connected to the conductive layers at the bottoms of different trenches in the first trench array 10.
  • the interlayer conductive layer 190 is disposed on the upper surface of the non-semiconductor substrate 110, the interlayer insulating layer 180 is disposed on the upper surface of the interlayer conductive layer 190, and the first trench
  • the trenches in the array 10 penetrate the first semiconductor layer 120 and the interlayer insulating layer 180, and the interlayer conductive layer 190 connects the conductive layers at the bottoms of different trenches in the first trench array 10.
  • a release layer 200 is provided between the first semiconductor layer 120 and the non-semiconductor substrate 110 to release the non-semiconductor substrate 110.
  • the non-semiconductor substrate 110 can be released at the end, that is, the capacitor 100 may not include the non-semiconductor substrate 110 at the end, so that the thickness of the capacitor 100 can be reduced.
  • the capacitor 100 further includes:
  • the second interlayer dielectric layer 210 covers the at least one first laminated structure 130;
  • the second semiconductor layer 220 is disposed above the second interlayer dielectric layer 210, and the second semiconductor layer 220 is formed with at least one second trench array 20;
  • At least one second stacked structure 230 is disposed above the second semiconductor layer 220 and fills the at least one second trench array 20.
  • the second stacked structure 230 includes a P-layer conductive layer and a Q-layer dielectric layer.
  • the P-layer conductive layer and the Q-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and P and Q are positive integers;
  • the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer, and the second external electrode 150 is electrically connected to all even-numbered conductive layers in the P-layer conductive layer; or, the first An external electrode 140 is electrically connected to all even-numbered conductive layers in the P-layer conductive layer, and the second external electrode 150 is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer.
  • the order of the Q-layer dielectric layers may be: in the second trench array 20, the distance from the second semiconductor layer 220 is from small to large or from large to large. Small order.
  • the order of the P-layer conductive layers may also be: in the second trench array 10, the distance from the second semiconductor layer 220 is ascending or descending.
  • the sequence of the Q-layer dielectric layer and the P-layer conductive layer in the embodiment of the present application is described by taking the order of the distance from the second semiconductor layer 220 in the second trench array 20 from small to large as an example.
  • the depth and width of the grooves in the second groove array 20 can be flexibly set according to actual needs.
  • the grooves in the second groove array 20 have a high aspect ratio.
  • the grooves in the second groove array 20 may be holes with a small difference in cross-sectional length and width, or may also be holes with a large difference in length and width.
  • the groove may also be a 3D structure such as a column or a wall.
  • the thickness of the second semiconductor layer 220 can be flexibly set according to actual needs.
  • the thickness of the second semiconductor layer 220 is less than or equal to the thickness of the first semiconductor layer 120.
  • the number of the at least one first trench array 10 is the same as the number of the at least one second trench array 20.
  • the number of grooves in the first groove array 10 is the same as the number of grooves in the second groove array 20, and/or the size of the grooves in the first groove array 10
  • the size of the grooves in the second groove array 20 is the same.
  • the at least one first groove array 10 and the at least one second groove array 20 completely overlap in the vertical direction.
  • the at least one first trench array and the at least one second trench array can be prepared by the same etching process, which simplifies the etching process.
  • the projected position and/or projected area of the at least one first trench array 10 and the at least one second trench array 20 on the non-semiconductor substrate 110 are the same.
  • the trenches in the second trench array 20 penetrate through the second semiconductor layer 220 and the second interlayer dielectric layer 210, between the P-layer conductive layer and part of the N-layer conductive layer Electric connection. Therefore, the first external electrode 140 and/or the second external electrode 150 can be electrically connected to the conductive layer in the N-layer conductive layer by electrically connecting the conductive layer in the P-layer conductive layer.
  • different second stacked structures 230 in the at least one second stacked structure 230 share the same first external electrode 140, and/or, different second stacked structures 230 in the at least one second stacked structure 230
  • the stacked structure 230 shares the same second external electrode 150.
  • one first external electrode 140 may be electrically connected to a part or all of the second stacked structure 230 in the at least one second stacked structure 230.
  • one second external electrode 150 may also be electrically connected to a part or all of the second stacked structure 230 in the at least one second stacked structure 230.
  • the first stacked structure 130 includes a first conductive layer, a first dielectric layer, and a second conductive layer.
  • the first conductive layer is disposed above the first semiconductor layer 120 and the first trench In the trench array 10
  • the second conductive layer is disposed above the first semiconductor layer 120 and fills the first trench array 10
  • the first dielectric layer is disposed between the first conductive layer and the second conductive layer ,
  • the second laminated structure 230 includes a third conductive layer, a second dielectric layer, and a fourth conductive layer.
  • the third conductive layer is disposed on the second conductive layer.
  • the fourth conductive layer is disposed above the second semiconductor layer 220 and fills the second trench array 20, and the second dielectric layer is disposed on the third conductive layer. Layer and the fourth conductive layer to isolate the third conductive layer from the fourth conductive layer;
  • the trenches in the second trench array 20 penetrate the second semiconductor layer 220 and the second interlayer dielectric layer 210 to expose the second conductive layer, and the second conductive layer is electrically connected to the third conductive layer.
  • the first external electrode 140 is electrically connected to the first conductive layer and the fourth conductive layer
  • the second external electrode 150 is electrically connected to the second conductive layer and the third conductive layer.
  • the second semiconductor layer 220 is further formed with at least one trench 30, and the second semiconductor layer 220 includes a conductive structure 40 disposed in the at least one trench, and the at least one trench 30 extends from the second The upper surface of the semiconductor layer 220 penetrates the second semiconductor layer 220 and the second interlayer dielectric layer 210 downward to expose the first conductive layer.
  • the first external electrode 140 is electrically connected to the first conductive layer through the conductive structure 40. Conductive layer.
  • the size of the at least one trench 30 is smaller than the size of the trenches in the at least one second trench array 20.
  • the size of the at least one trench 30 is less than or equal to 2D, where D is the thickness of the third conductive layer.
  • the conductive structure 40 and the third conductive layer have the same conductive material.
  • the first stacked structure 130 may include two conductive layers, which are respectively denoted as conductive layer 1301 and conductive layer 1301.
  • the layer 1302 and one dielectric layer are referred to as the dielectric layer 1311.
  • the conductive layer 1301 is disposed on the upper surface of the first semiconductor layer 120 and the inner surface of the first trench array 10
  • the conductive layer 1302 is disposed on the first semiconductor layer 120 and fills the first trench array 10
  • the dielectric layer 1311 is disposed between the conductive layer 1301 and the conductive layer 1302.
  • the second laminated structure 230 may include two conductive layers, denoted as a conductive layer 2301 and a conductive layer 2302 respectively, and a dielectric layer, denoted as a dielectric layer 2311.
  • the conductive layer 2301 is disposed on the upper surface of the second semiconductor layer 220 and the inner surface of the second trench array 20
  • the conductive layer 2302 is disposed on the second semiconductor layer 220 and fills the second trench array 20.
  • the dielectric layer 2311 is disposed between the conductive layer 2301 and the conductive layer 2302.
  • the at least one first trench array 10 and the at least one second trench array 20 completely overlap in the vertical direction, and the trenches in the second trench array 20 penetrate the second semiconductor layer 220 and the second interlayer dielectric layer 210 to expose the conductive layer 1302, the conductive layer 1302 is electrically connected to the conductive layer 2301, the first external electrode 140 is electrically connected to the conductive layer 1301 and the conductive layer 2302, the The second external electrode 150 is electrically connected to the conductive layer 1302 and the conductive layer 2301.
  • the second semiconductor layer 220 is further formed with at least one trench 30, and the second semiconductor layer 220 includes a conductive structure 40 disposed in the at least one trench, and the at least one trench 30 extends from the The upper surface of the second semiconductor layer 220 penetrates the second semiconductor layer 220 and the second interlayer dielectric layer 210 downward to expose the conductive layer 1301.
  • the first external electrode 140 is electrically connected to the conductive layer through the conductive structure 40. ⁇ 1301.
  • the conductive structure 40 and the conductive layer in the second stacked structure may be electrically isolated by some trenches penetrating the second semiconductor layer 220.
  • the conductive structure 40 and the conductive layer 2301 have the same conductive material, that is, the conductive structure 40 and the conductive layer 2301 can be deposited in the same step.
  • the size of the at least one trench 30 is less than or equal to 2D, where D is the thickness of the conductive layer 2301.
  • the first external electrode 140 and/or the second external electrode 150 are electrically connected to the conductive layer of the N-layer conductive layer and the P-layer conductive layer through the second interconnection structure 240 ⁇ conductive layer.
  • the second interconnection structure 240 includes a third interlayer dielectric layer 241, at least one third conductive via structure 242, and at least one fourth conductive via structure 243, and the third interlayer dielectric layer 241 covers the at least one The second stacked structure 230 and the second interlayer dielectric layer 210, the third conductive via structure 242 and the fourth conductive via structure 243 penetrate the third interlayer dielectric layer 241;
  • the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the third conductive via structure 242, and the second conductive layer
  • the external electrode 150 is electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure 243; or,
  • the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the third conductive via structure 242, and the second external electrode 150 is electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure 243.
  • the second interconnection structure 240 includes a third interlayer dielectric layer 241, at least one third conductive via structure 242, and at least one fourth conductive via structure 243.
  • the third interlayer dielectric layer 241 covers the at least one second stacked structure 230 and the second interlayer dielectric layer 210, and the third conductive via structure 242 and the fourth conductive via structure 243 penetrate the third interlayer dielectric layer 241.
  • the first external electrode 140 is electrically connected to the conductive layer 1301 in the N-layer conductive layer and the conductive layer 2302 in the P-layer conductive layer through the third conductive via structure 242, and the second external electrode 150 passes through
  • the fourth conductive via structure 243 is electrically connected to the conductive layer 1302 in the N-layer conductive layer and the conductive layer 2301 in the P-layer conductive layer.
  • the third conductive via structure 242 can be electrically connected to the conductive structure 40, and the conductive structure 40 is electrically connected to the conductive layer 1301, that is, the first external electrode 140 passes through
  • the third conductive via structure 242 is electrically connected to the conductive layer 1301 of the N-layer conductive layer.
  • the conductive layer 2301 in the P-layer conductive layer is in direct contact with the conductive layer 1302 in the N-layer conductive layer, that is, the second external electrode 150 is electrically connected to the conductive layer through the fourth conductive via structure 243
  • the conductive layer 2301 in the P-layer conductive layer can be electrically connected to the conductive layer 1302 in the N-layer conductive layer.
  • the third conductive via structure 242 penetrates the second semiconductor layer 220 and is electrically connected to the conductive layer 1301 of the N-layer conductive layer, that is, the first external electrode 140 is electrically connected through the third conductive layer.
  • the hole structure 242 is electrically connected to the conductive layer 1301 in the N-layer conductive layer and the conductive layer 2302 in the P-layer conductive layer.
  • the related description of the second interconnection structure 240 can refer to the above-mentioned first interconnection structure 160, which will not be repeated for the sake of brevity.
  • a second etch stop layer 250 may be disposed between the second interconnection structure 240 and the second stacked structure 230, and the third conductive via in the second interconnection structure 240 The structure 242 and the fourth conductive via structure 243 penetrate the second etch stop layer 250.
  • the second etch stop layer 250 is not shown in FIG. 7 or FIG. 8.
  • the specific arrangement of the second etch stop layer 250 can refer to the first etch stop in FIG. 4 or FIG.
  • the setting method of layer 170 will not be repeated.
  • the related description of the second etch stop layer 250 can refer to the above-mentioned first etch stop layer 170, which will not be repeated for the sake of brevity.
  • the second stacked structure 230 is provided with a step structure, and the third conductive via structure 242 and the fourth conductive via structure 243 are provided on the step structure, so that The first external electrode 140 is electrically connected to the conductive layer in the N-layer conductive layer and the conductive layer in the P-layer conductive layer through the third conductive via structure 242, and the second external electrode 150 is electrically connected through the fourth conductive layer.
  • the hole structure 243 is electrically connected to the conductive layer in the N-layer conductive layer and the conductive layer in the P-layer conductive layer.
  • step structure facilitates the connection and/or isolation between different conductive layers.
  • the second etch stop layer 250 provided on the stepped structure can enhance the electrical insulation between adjacent conductive layers in the second stacked structure 230, and at the same time, the stepped structure can facilitate the second interconnection structure 240.
  • the conductive layers in the second stacked structure 230 are connected.
  • the at least one first external electrode 140 and the at least one second external electrode 150 are disposed above the at least one second stacked structure 230.
  • the capacitor 100 further includes: a second electrode layer disposed above the at least one second laminated structure 230, and the second electrode layer includes at least one third conductive region and at least one fourth conductive region that are separated from each other. Area, the third conductive area forms the first external electrode 140, and the fourth conductive area forms the second external electrode 150.
  • the second electrode layer is disposed on the upper surface of the third interlayer dielectric layer 241 in the second interconnect structure 240. That is, the at least one first external electrode 140 and the at least one second external electrode 150 can be formed by one etching, which reduces the etching steps.
  • disposing the at least one second stacked structure 230 above the at least one first stacked structure 130 can further increase the capacitance of the capacitor.
  • the first semiconductor layer is disposed on a non-semiconductor substrate, and at least one first stacked structure is disposed above the first semiconductor layer and in at least one first trench array, so that trench silicon can be prepared.
  • the capacitor can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.
  • the preparation of silicon capacitors based on non-semiconductor substrates can be compatible with the current mature, low-cost large-size board-level processing technology, and can reduce the unit processing cost of silicon capacitors.
  • the capacitors according to the embodiments of the present application are described above, and the method for preparing the capacitors according to the embodiments of the present application is described below.
  • the method for preparing a capacitor of the embodiment of the present application can prepare the capacitor of the foregoing embodiment of the present application, and the following embodiments and related descriptions in the foregoing embodiments may refer to each other.
  • FIG. 9 is a schematic flowchart of a method for manufacturing a capacitor in an embodiment of the present application, but these steps or operations are only examples, and the embodiment of the present application may also perform other operations or modifications of each operation in FIG. 9.
  • FIG. 9 shows a schematic flowchart of a method 300 for manufacturing a capacitor according to an embodiment of the present application. As shown in FIG. 9, the manufacturing method 300 of the capacitor includes:
  • Step 310 preparing a first semiconductor layer over the non-semiconductor substrate, the first semiconductor layer being formed with at least one first trench array;
  • Step 320 prepare at least one first stacked structure, the first stacked structure is disposed above the first semiconductor layer and fills the at least one first trench array, the first stacked structure includes an N-layer conductive layer And an M dielectric layer, the N conductive layer and the M dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and N and M are positive integers;
  • Step 330 preparing at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer, and the second external electrode is electrically connected to the All the even-numbered conductive layers in the n-layer conductive layer.
  • steps 310-330 can be used to prepare capacitors as shown in FIGS. 1 to 8.
  • each material layer described in steps 310-330 refers to the surface substantially parallel to the upper surface of the non-semiconductor substrate, and the inner surface of each material layer refers to the material layer located in the trench.
  • the upper surface, the upper surface and the inner surface can be regarded as a whole.
  • the non-semiconductor substrate 110 includes but is not limited to at least one of the following:
  • the non-semiconductor substrate 110 may include glass, quartz, ceramics, glass fiber and resin-containing substrates, carrier-like substrates, or other organic polymer substrates, or may be a lining made of a mixture of the above materials or laminated. bottom.
  • the first semiconductor layer 120 may be a silicon layer, and the silicon layer may be, for example, an amorphous silicon layer or a polysilicon layer.
  • an interlayer insulating layer 180 and/or an interlayer conductive layer 190 is provided between the first semiconductor layer 120 and the non-semiconductor substrate 110.
  • the interlayer insulating layer 180 is disposed above the interlayer conductive layer 190, the trenches in the first trench array 10 penetrate the first semiconductor layer 120 and the interlayer insulating layer 180, and the interlayer
  • the conductive layer 190 is connected to the conductive layers at the bottom of different trenches in the first trench array 10, so that the capacitor as shown in FIG. 5 can be prepared based on the above steps S310 to S330.
  • a release layer 200 is provided between the first semiconductor layer 120 and the non-semiconductor substrate 110 to release the non-semiconductor substrate 110, so that the step shown in FIG. 6 is prepared based on the above steps S310 to S330. After the capacitor, the non-semiconductor substrate 110 can be released to prepare the capacitor as shown in FIG. 10.
  • different first stacked structures 130 in the at least one first stacked structure 130 share the same first external electrode 140, and/or, different first stacked structures 130 in the at least one first stacked structure 130
  • the stacked structure 130 shares the same second external electrode 150.
  • a first external electrode 140 can be electrically connected to a part or all of the first stacked structure 130 in the at least one first stacked structure 130.
  • a second external electrode 150 can also be electrically connected to the at least one first stacked structure 130. Part or all of the first stacked structure 130 in the at least one first stacked structure 130.
  • the foregoing step 330 may specifically be: preparing a first electrode layer above the at least one first stacked structure 130, the first electrode layer including at least one first conductive region and at least one second conductive region that are separated from each other , The first conductive area forms the first external electrode 140, and the second conductive area forms the second external electrode 150.
  • the method 300 further includes:
  • a first interconnection structure 160 is prepared.
  • the first interconnection structure 160 includes a first interlayer dielectric layer 161, at least one first conductive via structure 162, and at least one second conductive via structure 163, wherein the first interlayer dielectric
  • the layer 161 covers the at least one first stacked structure 130, the first conductive via structure 162 and the second conductive via structure 163 penetrate the first interlayer dielectric layer 161, and the first external electrode 140 passes through the first
  • the conductive via structure 162 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer, and the second external electrode 150 is electrically connected to all the even-numbered layers in the N-layer conductive layer through the second conductive via structure 163 Conductive layer.
  • the method 300 further includes:
  • a first etch stop layer 170 is prepared.
  • the first etch stop layer 170 is disposed between the first interconnect structure 160 and the first stacked structure 130, and the first conductive via in the first interconnect structure 160
  • the structure 162 and the second conductive via structure 163 penetrate the first etch stop layer 170.
  • the first etch stop layer 170 is more resistant to etching than the first interlayer dielectric layer 161.
  • the first conductive via structure 162 and the second conductive via structure 163 are etched, the The bottom of the via stays on the first etch stop layer 170 of different depths, and then a dry or wet process is used to remove part of the first etch stop layer 170 exposed at the bottom of the via, so that the first conductive via structure 162 and the second conductive via structure 163 penetrate the first etch stop layer 170.
  • the arrangement of the first etch stop layer 170 can ensure that the etching of the first conductive via structure 162 and the second conductive via structure 163 will not damage the conductive layer and/or the dielectric layer in the first stacked structure 130 .
  • the first stacked structure 130 may include two conductive layers, such as the conductive layer 1301 and the conductive layer 1302 shown in FIG. 1, and one layer.
  • a dielectric layer such as the dielectric layer 1311 shown in FIG. 1.
  • the conductive layer 1301 is disposed on the upper surface of the first semiconductor layer 120 and the inner surface of the first trench array 10
  • the conductive layer 1302 is disposed on the first semiconductor layer 120 and fills the first trench array 10
  • the dielectric layer 1311 is disposed between the conductive layer 1301 and the conductive layer 1302.
  • the above steps S310 to S330 may specifically be the preparation process shown in step 1a to step 1h (FIG. 11a to FIG.
  • Step 1a select fused silica glass as the non-semiconductor substrate 110, as shown in FIG. 11a;
  • Step 1b depositing amorphous silicon on the upper surface of the non-semiconductor substrate 110 as shown in FIG. 11a to form the first semiconductor layer 120, as shown in FIG. 11b;
  • Step 1c using patterning techniques such as photolithography, nanoimprinting, laser direct writing, etc., to form a mask layer of pattern A on the upper surface of the first semiconductor layer 120, and then use an etching process to prepare it on the first semiconductor layer 120
  • the first trench array 10 the depth of the trenches in the first trench array 10 is less than the thickness of the first semiconductor layer 120, as shown in FIG. 11c;
  • Step 1d depositing a conductive layer 1301 on the upper surface of the first semiconductor layer 120 and the inner surface (sidewall and bottom) of the trenches in the first trench array 10, as shown in FIG. 11d;
  • Step 1e deposit a dielectric layer 1311 on the upper surface of the conductive layer 1301 and the trenches in the first trench array 10, the dielectric layer 1311 is conformal to the conductive layer 1301, and on the upper surface of the dielectric layer 1311 And a conductive layer 1302 is deposited in the trenches in the first trench array 10, and the conductive layer 1302 fills the trenches in the first trench array, as shown in FIG. 11e;
  • Step 1f using a photolithography process to perform photolithography processing on the dielectric layer 1311 and the conductive layer 1302 to form a stepped structure on the upper surface of the conductive layer 1301, and obtain a first laminated structure 130, as shown in FIG. 11f ;
  • step 1g an insulating material is deposited on the upper surfaces of the conductive layer 1301 and the conductive layer 1302 to form a first interlayer dielectric layer 161, as shown in FIG. 11g, at least one first conductive via is prepared by etching and deposition processes.
  • the first conductive via structure 162 penetrates the first interlayer dielectric layer 161 and extends to the upper surface of the conductive layer 1301.
  • the second conductive via structure 163 penetrates the first interlayer dielectric layer 161 and extends to the upper surface of the conductive layer 1302, thereby preparing a first interconnect structure 160, as shown in FIG. 11h;
  • Step 1h prepare a first external electrode 140 and a second external electrode 150 above the first interconnect structure 160, wherein the first external electrode 140 is electrically connected to the N-layer conductive layer through the first conductive via structure 162
  • the second external electrode 150 is electrically connected to all the even-numbered conductive layers in the N-layer conductive layer through the second conductive via structure 163, as shown in FIG. 1.
  • the conductive layer 1301 in the first stacked structure 130 can also be prepared in the following manner:
  • the low resistivity characteristics of heavily doped silicon can be used to dope the entire first semiconductor layer 120 or the sidewalls of the trenches in the first trench array 10 to form conductive regions or conductive layers with low resistivity, thereby preparing the Conductive layer 1301.
  • a low-resistivity conductive layer is directly deposited on the inner walls of the trenches in the first trench array 10, such as heavily doped polysilicon deposited by a CVD process; it may also be physical vapor deposition (Physical Vapor Deposition, PVD), CVD, or atomic layer.
  • PVD Physical Vapor Deposition
  • CVD chemical vapor deposition
  • Other low-resistivity conductive materials deposited by an Atomic Layer Deposition (ALD) process are deposited to prepare the conductive layer 1301.
  • the method 300 further includes:
  • the second semiconductor layer 220 is disposed above the second interlayer dielectric layer 210, and the second semiconductor layer 220 is formed with at least one second trench array 20;
  • At least one second stacked structure 230 is prepared.
  • the second stacked structure 230 is disposed above the second semiconductor layer 220 and fills the at least one second trench array 20.
  • the second stacked structure 230 includes a P layer conductive A layer and a Q-layer dielectric layer, the P-layer conductive layer and the Q-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and P and Q are positive integers;
  • the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer, and the second external electrode 150 is electrically connected to all even-numbered conductive layers in the P-layer conductive layer; or, the first An external electrode 140 is electrically connected to all even-numbered conductive layers in the P-layer conductive layer, and the second external electrode 150 is electrically connected to all odd-numbered conductive layers in the P-layer conductive layer.
  • the number of the at least one first trench array 10 is the same as the number of the at least one second trench array 20.
  • the number of grooves in the first groove array 10 is the same as the number of grooves in the second groove array 20, and/or the size of the grooves in the first groove array 10
  • the size of the grooves in the second groove array 20 is the same.
  • the at least one first groove array 10 and the at least one second groove array 20 completely overlap in the vertical direction.
  • the trenches in the second trench array 20 penetrate through the second semiconductor layer 220 and the second interlayer dielectric layer 210, between the P-layer conductive layer and part of the N-layer conductive layer Electric connection.
  • different second stacked structures 230 in the at least one second stacked structure 230 share the same first external electrode 140, and/or, different second stacked structures 230 in the at least one second stacked structure 230 The stacked structure 230 shares the same second external electrode 150.
  • the foregoing step S330 may specifically be: preparing a second electrode layer above the at least one second stacked structure 230, and the second electrode layer includes at least one third conductive region and at least one fourth conductive region that are separated from each other. Area, the third conductive area forms the first external electrode 140, and the fourth conductive area forms the second external electrode 150.
  • the method 300 further includes:
  • a second interconnection structure 240 is prepared.
  • the second interconnection structure 240 includes a third interlayer dielectric layer 241, at least one third conductive via structure 242, and at least one fourth conductive via structure 243, and the third interlayer dielectric layer 241 Covering the at least one second stacked structure 230 and the second interlayer dielectric layer 210, the third conductive via structure 242 and the fourth conductive via structure 243 penetrate the third interlayer dielectric layer 241;
  • the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the third conductive via structure 242, and the second conductive layer
  • the external electrode 150 is electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure 243; or,
  • the first external electrode 140 is electrically connected to all odd-numbered conductive layers in the N-layer conductive layer and all even-numbered conductive layers in the P-layer conductive layer through the third conductive via structure 242, and the second external electrode 150 is electrically connected to all even-numbered conductive layers in the N-layer conductive layer and all odd-numbered conductive layers in the P-layer conductive layer through the fourth conductive via structure 243.
  • the method 300 further includes:
  • a second etch stop layer 250 is prepared.
  • the second etch stop layer 250 is disposed between the second interconnection structure 240 and the second stacked structure 230.
  • the third conductive via structure 242 and the fourth conductive via The hole structure 243 penetrates the second etch stop layer 250.
  • the first stacked structure 130 includes a first conductive layer, a first dielectric layer, and a second conductive layer, and the first conductive layer is disposed above the first semiconductor layer 120 and in the first trench array 10 , The second conductive layer is disposed above the first semiconductor layer 120 and fills the first trench array 10, and the first dielectric layer is disposed between the first conductive layer and the second conductive layer to The first conductive layer is isolated from the second conductive layer; and the second stacked structure 230 includes a third conductive layer, a second dielectric layer, and a fourth conductive layer, and the third conductive layer is disposed above the second semiconductor layer 220 And in the second trench array 20, the fourth conductive layer is disposed above the second semiconductor layer 220 and fills the second trench array 20, and the second dielectric layer is disposed on the third conductive layer and the first Between the four conductive layers to isolate the third conductive layer from the fourth conductive layer;
  • the trenches in the second trench array 20 penetrate the second semiconductor layer 220 and the second interlayer dielectric layer 210 to expose the second conductive layer, and the second conductive layer is electrically connected to the third conductive layer.
  • the first external electrode 140 is electrically connected to the first conductive layer and the fourth conductive layer
  • the second external electrode 150 is electrically connected to the second conductive layer and the third conductive layer.
  • the second semiconductor layer 220 is further formed with at least one trench 30, and the second semiconductor layer 220 includes a conductive structure 40 disposed in the at least one trench, and the at least one trench 30 extends from the second The upper surface of the semiconductor layer 220 penetrates the second semiconductor layer 220 and the second interlayer dielectric layer 210 downward to expose the first conductive layer.
  • the first external electrode 140 is electrically connected to the first conductive layer through the conductive structure 40. Conductive layer.
  • the size of the at least one trench 30 is smaller than the size of the trenches in the at least one second trench array 20.
  • the size of the at least one trench 30 is less than or equal to 2D, where D is the thickness of the third conductive layer.
  • the conductive structure 40 and the third conductive layer have the same conductive material.
  • the first stacked structure 130 may include two conductive layers, which are respectively denoted as conductive layer 1301 and conductive layer 1301.
  • the layer 1302 and one dielectric layer are referred to as the dielectric layer 1311.
  • the conductive layer 1301 is disposed on the upper surface of the first semiconductor layer 120 and the inner surface of the first trench array 10
  • the conductive layer 1302 is disposed on the first semiconductor layer 120 and fills the first trench array 10
  • the dielectric layer 1311 is disposed between the conductive layer 1301 and the conductive layer 1302.
  • the second laminated structure 230 may include two conductive layers, denoted as a conductive layer 2301 and a conductive layer 2302 respectively, and a dielectric layer, denoted as a dielectric layer 2311.
  • the conductive layer 2301 is disposed on the upper surface of the second semiconductor layer 220 and the inner surface of the second trench array 20
  • the conductive layer 2302 is disposed on the second semiconductor layer 220 and fills the second trench array 20.
  • the dielectric layer 2311 is disposed between the conductive layer 2301 and the conductive layer 2302.
  • the above steps S310 to S330 may specifically be the preparation process shown in step 2a to step 2o (FIG. 12a-FIG. 12n) to prepare the capacitor 100 as shown in FIG. 7.
  • the capacitor 100 as shown in FIG. 8 can also be prepared, which can refer to the capacitor preparation process shown in steps 2a to 2o (FIGS. 12a-12n).
  • FIG. 8 can also be prepared, which can refer to the capacitor preparation process shown in steps 2a to 2o (
  • Step 2a select fused silica glass as the non-semiconductor substrate 110, as shown in FIG. 12a;
  • Step 2b depositing amorphous silicon on the upper surface of the non-semiconductor substrate 110 as shown in FIG. 12a to form the first semiconductor layer 120, as shown in FIG. 12b;
  • Step 2c using patterning techniques such as photolithography, nanoimprinting, laser direct writing, etc., to form a mask layer of pattern A on the upper surface of the first semiconductor layer 120, and then use an etching process to prepare it on the first semiconductor layer 120
  • the first trench array 10 the depth of the trenches in the first trench array 10 is less than the thickness of the first semiconductor layer 120, as shown in FIG. 12c;
  • Step 2d depositing a conductive layer 1301 on the upper surface of the first semiconductor layer 120 and the inner surface (sidewall and bottom) of the trenches in the first trench array 10, as shown in FIG. 12d;
  • Step 2e deposit a dielectric layer 1311 on the upper surface of the conductive layer 1301 and the trenches in the first trench array 10, the dielectric layer 1311 is conformal to the conductive layer 1301, and on the upper surface of the dielectric layer 1311 And depositing a conductive layer 1302 in the trenches in the first trench array 10, and the conductive layer 1302 fills the trenches in the first trench array, as shown in FIG. 12e;
  • Step 2f Use a photolithography process to perform photolithography processing on the dielectric layer 1311 and the conductive layer 1302 to form a stepped structure on the upper surface of the conductive layer 1301, and obtain a first laminated structure 130, as shown in FIG. 12f ;
  • Step 2g deposit a second interlayer dielectric layer 210 on the upper surfaces of the conductive layer 1301 and the conductive layer 1302, that is, the second interlayer dielectric layer 210 covers the at least one first stacked structure 130, as shown in FIG. 12g Shown
  • Step 2h depositing amorphous silicon on the upper surface of the second interlayer dielectric layer 210 to form a second semiconductor layer 220, as shown in FIG. 12h;
  • Step 2i use patterning techniques such as photolithography, nanoimprinting, and laser direct writing to form a mask layer of pattern B on the upper surface of the second semiconductor layer 220, and then prepare it on the second semiconductor layer 220 by an etching process
  • the second trench array 20 and at least one trench 30 The trenches in the second trench array 20 enter the second semiconductor layer 220 downward from the upper surface of the second semiconductor layer 220 and extend to the second semiconductor layer 220.
  • the upper surface of the interlayer dielectric layer 210, and the at least one trench 30 enters the second semiconductor layer 220 downward from the upper surface of the second semiconductor layer 220, and extends to the upper surface of the second interlayer dielectric layer 210 , As shown in Figure 12i;
  • Step 2j removing the second interlayer dielectric layer 210 at the bottom of the trenches in the second trench array 20 to expose the conductive layer 1302, and removing the second interlayer dielectric layer at the bottom of the at least one trench 30 210 to expose the conductive layer 1301, as shown in FIG. 12j;
  • step 2k first, a conductive layer 2301 is deposited on the upper surface of the second semiconductor layer 220, the inner surfaces (sidewalls and bottoms) of the trenches in the second trench array 20, and the at least one trench 30; then , Deposit a dielectric layer 2311 on the upper surface of the conductive layer 2301 and the trenches in the second trench array 20; finally, on the upper surface of the dielectric layer 2311 and the trenches in the second trench array 20 Deposit a conductive layer 2302, as shown in FIG. 12k;
  • Step 21 Use a photolithography process to perform photolithography processing on the dielectric layer 2311 and the conductive layer 2302 to form a stepped structure on the upper surface of the conductive layer 2301, and obtain a second stacked structure 230 and a conductive structure 40, such as As shown in Figure 12l;
  • Step 2m using photolithography combined with a dry etching process to form at least one insulating trench 50, the insulating trench 50 penetrates the second semiconductor layer 220 to divide the second semiconductor layer 220 into at least two electrically isolated from each other Area, as shown in Figure 12m;
  • Step 2n firstly, a third interlayer dielectric layer 241 is deposited on the upper surface of the conductive layer 2301, the upper surface of the conductive layer 2302, and the insulating trench 50, that is, the third interlayer dielectric layer 241 covers the At least one second stacked structure 230 and the second interlayer dielectric layer 210; then, at least one third conductive via structure 242 and at least one fourth conductive via structure 243 are prepared by using an etching process and a deposition process.
  • the three conductive via structure 242 penetrates the third interlayer dielectric layer 241 and extends to the upper surface of the conductive layer 2302 and the conductive structure 40.
  • the fourth conductive via structure 243 penetrates the third interlayer dielectric layer 241, And extend to the upper surface of the conductive layer 2301, thereby preparing a second interconnection structure 240, as shown in FIG. 12n;
  • Step 2o prepare a first external electrode 140 and a second external electrode 150 above the second interconnection structure 240, wherein the first external electrode 140 is electrically connected to the N-layer conductive layer through the third conductive via structure 242
  • the conductive layer 2301 in the conductive layer is as shown in FIG. 7.
  • the conductive layer 1301 in the first stacked structure 130 can also be prepared in the following manner:
  • the low resistivity characteristics of heavily doped silicon can be used to dope the entire first semiconductor layer 120 or the sidewalls of the trenches in the first trench array 10 to form conductive regions or conductive layers with low resistivity, thereby preparing the Conductive layer 1301.
  • a low-resistivity conductive layer is deposited directly on the inner walls of the trenches in the first trench array 10, such as heavily doped polysilicon deposited by a CVD process; it can also be other low-resistivity conductive materials deposited by a PVD, CVD or ALD process, Thus, the conductive layer 1301 is prepared.
  • the first semiconductor layer is disposed on the non-semiconductor substrate, and at least one first stacked structure is disposed above the first semiconductor layer and in the at least one first trench array, so that trenches can be prepared.
  • Type silicon capacitors can reduce the cost of capacitors while preparing small-volume, high-capacitance-density capacitors.
  • the preparation of silicon capacitors based on non-semiconductor substrates can be compatible with the current mature and low-cost large-size board-level processing technology, and can reduce the unit processing cost of silicon capacitors.
  • a capacitor as shown in FIG. 1 is fabricated in the first embodiment.
  • the capacitor manufacturing method in the first embodiment can also be used to manufacture capacitors as shown in Figure 4, Figure 5 and Figure 6, except that the first stacked structure, the first trench array, the interlayer insulating layer, and the layer There are some differences between the conductive layer or the release layer and other parts, for the sake of brevity, it will not be repeated here.
  • a capacitor as shown in FIG. 7 was fabricated.
  • the capacitor manufacturing method in the second embodiment can also be used to manufacture the capacitor as shown in FIG. 8, but there are some differences in the conductive structure and the arrangement of the second interconnection structure. For the sake of brevity, it will not be repeated here.
  • Step 1 Choose fused silica glass as a non-semiconductor substrate.
  • Step 2 Using Plasma Enhanced Chemical Vapor Deposition (PECVD) process to deposit a 10-micron amorphous silicon layer on the non-semiconductor substrate as the first semiconductor layer.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • Step 3 First use patterning techniques such as photolithography, nanoimprinting, and laser direct writing to form a patterned mask layer on the upper surface of the first semiconductor layer, and then use a deep silicon etching process to form a second semiconductor layer on the first semiconductor layer. An array of grooves.
  • Step 4 Using an ALD process, deposit a layer of TiN as the first conductive layer on the sidewalls of the trenches in the first trench array. If the non-semiconductor substrate can withstand high temperatures, such as fused silica, a doping process can also be used in this step to form a low-resistivity conductive layer on the trench sidewalls in the first trench array.
  • Step 5 Using the ALD process, deposit a layer of Al 2 O 3 as the first dielectric layer; then, deposit a layer of TiN as the second conductive layer.
  • Step 6 Using a photolithography process, photolithography processing is performed on the first dielectric layer and the second conductive layer to form steps.
  • Step 7 Using a CVD process, deposit a layer of silicon nitride and a layer of silicon oxide as the first interlayer dielectric layer (ILD). Using a photolithography process, a number of via holes are opened, and the bottom of the via holes respectively expose the first conductive layer or the second conductive layer.
  • ILD interlayer dielectric
  • Step 8 Using a CVD process, TiN is deposited in the via hole and filled with W. A chemical mechanical polishing (CMP) process is used to remove excess conductive material on the surface to form conductive channels embedded in the ILD.
  • CMP chemical mechanical polishing
  • Step 9 Use the PVD process to deposit a layer of Ti/TiN and a layer of Al on the first interlayer dielectric layer (ILD), and use photolithography to form several pads or electrodes. At least one electrode is electrically connected to the first conductive layer through the conductive channel; at least one electrode is electrically connected to the second conductive layer through the conductive channel.
  • Step 1 Choose fused silica glass as a non-semiconductor substrate.
  • Step 2 Using the PECVD process, deposit an amorphous silicon layer of 10 microns on the non-semiconductor substrate as the first semiconductor layer.
  • Step 3 First use patterning techniques such as photolithography, nanoimprinting, and laser direct writing to form a patterned mask layer on the upper surface of the first semiconductor layer, and then use a deep silicon etching process on the first semiconductor layer A first trench array is formed.
  • patterning techniques such as photolithography, nanoimprinting, and laser direct writing to form a patterned mask layer on the upper surface of the first semiconductor layer, and then use a deep silicon etching process on the first semiconductor layer A first trench array is formed.
  • Step 4 Using an ALD process, deposit a layer of TiN as the first conductive layer on the sidewalls of the trenches in the first trench array. If the non-semiconductor substrate can withstand high temperatures, such as fused silica, a doping process can also be used in this step to form a low-resistivity conductive layer on the trench sidewalls in the first trench array.
  • Step 5 Using the ALD process, deposit a layer of Al 2 O 3 as the first dielectric layer; then, deposit a layer of TiN as the second conductive layer.
  • Step 6 Using a photolithography process, photolithography processing is performed on the first dielectric layer and the second conductive layer to form steps.
  • Step 7 Depositing a layer of silicon oxide as the second interlayer dielectric layer using a CVD process, and then depositing a layer of amorphous silicon as the second semiconductor layer on the upper surface of the second interlayer dielectric layer.
  • Step 8 First use patterning techniques such as photolithography, nanoimprinting, and laser direct writing to form a patterned mask layer on the upper surface of the second semiconductor layer, and then use a deep silicon etching process on the second semiconductor layer A second trench array and at least one trench are formed.
  • the width (or aperture) of the at least one trench is relatively small, and the width or aperture is less than or equal to twice the thickness of the third conductive layer. The depths of the trenches and the at least one trench in the second trench array reach the second interlayer dielectric layer.
  • Step 9 Use a dry method or a wet method to remove the second interlayer dielectric layer at the bottom of the groove.
  • the bottom of the trenches in the second trench array exposes the second conductive layer, and the bottom of the at least one trench exposes the first conductive layer.
  • Step 10 Using an ALD process, TiN is deposited as a third conductive layer on the upper surface of the second semiconductor layer and in the second trench array, and deposited on the upper surface of the second semiconductor layer and in the second trench array Al 2 O 3 is used as the second dielectric layer, TiN is deposited as the fourth conductive layer on the upper surface of the second semiconductor layer and the second trench array, and TiN is deposited in the at least one trench.
  • the second dielectric layer is located between the third conductive layer and the fourth conductive layer to isolate the third conductive layer from the fourth conductive layer, and the at least one trench is filled with TiN to form a conductive channel Connect the first conductive layer.
  • Step 11 Using a photolithography process, photolithography processing is performed on the second dielectric layer and the fourth conductive layer pattern to form steps.
  • Step twelve using photolithography combined with a dry etching process to fabricate at least one insulating trench to divide the second semiconductor layer into at least two regions that are electrically isolated from each other.
  • Step 13 Using a CVD process, a third interlayer dielectric layer is filled inside the insulating trench.
  • Step 14 Fabricate metal interconnections and electrodes in the third interlayer dielectric layer, and connect the capacitors formed in the first trench array and the capacitors formed in the second trench array in parallel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un condensateur (100) et son procédé de fabrication. Le condensateur (100) comprend un substrat non semi-conducteur (110) ; une première couche semi-conductrice (120) disposée au-dessus du substrat non semi-conducteur (110), au moins un premier réseau de tranchées (10) étant formé dans la première couche semi-conductrice (120) ; au moins une première structure stratifiée (130) disposée au-dessus de la première couche semi-conductrice (120) et à remplir ledit au moins un premier réseau de tranchées (10), la première structure stratifiée (130) comprenant N couches conductrices et M couches diélectriques, les N couches conductrices et les M couches diélectriques formant une structure dans laquelle les couches conductrices (1301, 1302, 1303) et les couches diélectriques (1311, 1312) sont adjacents les unes aux autres, et N et M sont des nombres entiers positifs ; au moins une première électrode externe (140) électriquement connectée à toutes les couches conductrices impaires (1301, 1303) dans les N couches conductrices ; et au moins une seconde électrode externe (150) connectée électriquement à toutes les couches conductrices paires (1302) dans les N couches conductrices.
PCT/CN2019/106266 2019-09-17 2019-09-17 Condensateur et son procédé de fabrication WO2021051285A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2019/106266 WO2021051285A1 (fr) 2019-09-17 2019-09-17 Condensateur et son procédé de fabrication
CN201980001973.8A CN110785840A (zh) 2019-09-17 2019-09-17 电容器及其制作方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/106266 WO2021051285A1 (fr) 2019-09-17 2019-09-17 Condensateur et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2021051285A1 true WO2021051285A1 (fr) 2021-03-25

Family

ID=69394835

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/106266 WO2021051285A1 (fr) 2019-09-17 2019-09-17 Condensateur et son procédé de fabrication

Country Status (2)

Country Link
CN (1) CN110785840A (fr)
WO (1) WO2021051285A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114566490A (zh) * 2022-04-15 2022-05-31 中国电子科技集团公司第十研究所 垂直布局msm电容结构及其制作方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021196018A1 (fr) * 2020-03-31 2021-10-07 深圳市汇顶科技股份有限公司 Condensateur et son procédé de fabrication
WO2021196016A1 (fr) * 2020-03-31 2021-10-07 深圳市汇顶科技股份有限公司 Condensateur, structure de condensateur et procédé de fabrication de condensateur
CN112151535B (zh) * 2020-08-17 2022-04-26 复旦大学 一种硅基纳米电容三维集成结构及其制备方法
CN112151537B (zh) * 2020-09-10 2022-04-29 复旦大学 一种高能量密度纳米电容三维集成结构及其制备方法
CN112652620B (zh) * 2020-12-22 2022-09-13 复旦大学 三维集成结构及其制造方法
CN112670285A (zh) * 2020-12-22 2021-04-16 复旦大学 三维集成结构及其制备方法
CN112908990B (zh) * 2021-01-26 2022-08-05 复旦大学 三维集成结构及其制造方法
CN112908993A (zh) * 2021-01-26 2021-06-04 复旦大学 三维集成结构及其制造方法
CN112908991B (zh) * 2021-01-26 2022-09-13 复旦大学 三维集成结构及其制造方法
CN112908992B (zh) * 2021-01-26 2022-10-21 复旦大学 三维集成结构及其制造方法
CN115250112A (zh) * 2021-04-09 2022-10-28 圣邦微电子（北京）股份有限公司 器件模块及其制造方法和电感电容阵列

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100087042A1 (en) * 2008-10-06 2010-04-08 Samsung Electronics Co., Ltd. Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein
CN102683318A (zh) * 2012-05-25 2012-09-19 无锡纳能科技有限公司 硅电容器内部多层电极连接结构及连接方法
US20160020267A1 (en) * 2012-11-26 2016-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Low impedance high density deep trench capacitor
CN106170858A (zh) * 2014-03-25 2016-11-30 Ipdia公司 电容器结构
CN108735719A (zh) * 2017-04-25 2018-11-02 三星电机株式会社 电容器及制造该电容器的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100087042A1 (en) * 2008-10-06 2010-04-08 Samsung Electronics Co., Ltd. Methods of Fabricating Three-Dimensional Capacitor Structures Having Planar Metal-Insulator-Metal and Vertical Capacitors Therein
CN102683318A (zh) * 2012-05-25 2012-09-19 无锡纳能科技有限公司 硅电容器内部多层电极连接结构及连接方法
US20160020267A1 (en) * 2012-11-26 2016-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Low impedance high density deep trench capacitor
CN106170858A (zh) * 2014-03-25 2016-11-30 Ipdia公司 电容器结构
CN108735719A (zh) * 2017-04-25 2018-11-02 三星电机株式会社 电容器及制造该电容器的方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114566490A (zh) * 2022-04-15 2022-05-31 中国电子科技集团公司第十研究所 垂直布局msm电容结构及其制作方法
CN114566490B (zh) * 2022-04-15 2023-06-27 中国电子科技集团公司第十研究所 垂直布局msm电容结构及其制作方法

Also Published As

Publication number Publication date
CN110785840A (zh) 2020-02-11

Similar Documents

Publication Publication Date Title
WO2021051285A1 (fr) Condensateur et son procédé de fabrication
CN112602191B (zh) 电容器及其制作方法
US11615921B2 (en) Capacitor and manufacturing method therefor
US11469168B2 (en) Capacitor and method for producing the same
US11276750B2 (en) Capacitor and method for fabricating the same
US11362171B2 (en) Capacitor and manufacturing method therefor
WO2021196009A1 (fr) Condensateur et son procédé de fabrication
US11462609B2 (en) Capacitor and manufacturing method therefor
US20210020737A1 (en) Capacitor and method for producing the same
US11063113B2 (en) Capacitor and method for fabricating the same
WO2021138839A1 (fr) Condensateur et son procédé de fabrication
CN113748508B (zh) 电容器、电容结构、电容器的制作方法
WO2021196018A1 (fr) Condensateur et son procédé de fabrication
CN211929311U (zh) 电容器
CN211208251U (zh) 电容器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19946024

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19946024

Country of ref document: EP

Kind code of ref document: A1