WO2021138839A1 - Condensateur et son procédé de fabrication - Google Patents

Condensateur et son procédé de fabrication Download PDF

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Publication number
WO2021138839A1
WO2021138839A1 PCT/CN2020/070928 CN2020070928W WO2021138839A1 WO 2021138839 A1 WO2021138839 A1 WO 2021138839A1 CN 2020070928 W CN2020070928 W CN 2020070928W WO 2021138839 A1 WO2021138839 A1 WO 2021138839A1
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layer
conductive
external electrode
capacitor
substrate
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PCT/CN2020/070928
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English (en)
Chinese (zh)
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陆斌
沈健
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深圳市汇顶科技股份有限公司
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Priority to CN202080001513.8A priority Critical patent/CN111788649A/zh
Priority to PCT/CN2020/070928 priority patent/WO2021138839A1/fr
Publication of WO2021138839A1 publication Critical patent/WO2021138839A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics

Definitions

  • This application relates to the field of capacitors, and more specifically, to capacitors and methods of making them.
  • Capacitors can play the role of bypassing, filtering, decoupling, etc. in the circuit, and are an indispensable part of ensuring the normal operation of the circuit.
  • silicon capacitors can usually be fabricated based on a three-dimensional structure with a high aspect ratio.
  • the high aspect ratio three-dimensional structure itself is difficult to process, and the production of conformal, uniform thickness and defect-free conductive layers and dielectric layers on this three-dimensional structure also requires an extremely high level of technology. How to prepare small-volume, high-capacity, and low-cost capacitors has become an urgent technical problem to be solved.
  • the embodiments of the present application provide a capacitor and a manufacturing method thereof, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.
  • a capacitor in a first aspect, includes:
  • the laminated structure includes an n-layer conductive layer and an m-layer dielectric layer, the n-layer conductive layer and the m-layer dielectric layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other, and the All odd-numbered conductive layers in the n-layer conductive layer form at least one first step structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second step structure, and m and n are positive integers;
  • At least one first external electrode the first external electrode is electrically connected to a part or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one first stepped structure;
  • At least one second external electrode and the second external electrode is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.
  • the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose the n-layer
  • the first external electrode is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of at least one first step structure, and the second external electrode is connected through at least one second conductive layer.
  • the step surface of the step structure is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.
  • a laminated structure can be fabricated on a flat substrate surface, and at least one first stepped structure and at least one second stepped structure can be formed on the laminated structure by using a photoresist trimming process, thereby avoiding the problems associated with preparing a 3D structure. Expensive processes such as etching and deposition, and the photoresist trimming process effectively reduces the number of photolithography and reduces the cost of the capacitor.
  • the at least one first step structure and the at least one second step structure are respectively located on different sides of the laminated structure.
  • the at least one first step structure and the at least one second step structure are located on the same side of the laminated structure.
  • the capacitor further includes a substrate, and the at least one stacked structure is disposed above the substrate.
  • the capacitor further includes: a first conductive material layer and a second conductive material layer,
  • the first conductive material layer is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through part or all of the stepped surfaces of the at least one first stepped structure, and the second conductive material layer passes through Part or all of the step surfaces of the at least one second step structure are electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the first conductive material layer covers part or all of the step surfaces of the at least one first step structure to electrically connect part or all of the odd-numbered conductive layers in the n-layer conductive layer
  • the second conductive material layer covers part or all of the step surfaces of the at least one second step structure to electrically connect part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the capacitor further includes: a first conductive via structure and a second conductive via structure,
  • the first external electrode is electrically connected to the first conductive material layer through the first conductive via structure
  • the second external electrode is electrically connected to the second conductive material layer through the second conductive via structure. Conductive material layer.
  • the capacitor further includes a sidewall structure formed of an insulating material, wherein the sidewall structure covers the vertical surface of the at least one first step structure, and is used to isolate the first conductive material.
  • the material layer is perpendicular to the vertical surface of the at least one first step structure, and the side wall structure covers the vertical surface of the at least one second step structure, and is used to isolate the second conductive material layer from the at least one first step structure.
  • the vertical plane of the two-step structure is used to isolate the first conductive material.
  • the capacitor further includes: a plurality of first conductive via structures and a plurality of second conductive via structures, wherein:
  • the first external electrode is electrically connected to the plurality of first conductive via structures, and the plurality of first conductive via structures are electrically connected to the at least one first stepped structure through a part or all of the stepped surfaces Part or all of the odd-numbered conductive layers in the n-layered conductive layer;
  • the second external electrode is electrically connected to the plurality of second conductive via structures, and the plurality of second conductive via structures are electrically connected to the step surface of the at least one second stepped structure. Part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the capacitor further includes: an etch stop layer covering the at least one first step structure and the at least one second step structure, and the plurality of first step structures The conductive via structure and the plurality of second conductive via structures penetrate the etch stop layer.
  • the capacitor further includes a substrate, the at least one stacked structure is disposed above the substrate, and the etch stop layer also covers the substrate.
  • the thickness of the conductive layer in the n-layer conductive layer ranges from 5 nm to 1 mm.
  • the thickness of the dielectric layer in the m-layer dielectric layer ranges from 1 nm to 10 um.
  • the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.
  • the capacitor further includes a substrate, the at least one stacked structure is disposed above the substrate, and the second external electrode is also electrically connected to the substrate.
  • the substrate is formed of a material with a resistivity less than a threshold, or a heavily doped conductive layer or a heavily doped conductive region is formed on the surface of the substrate.
  • the capacitor further includes: an electrode layer disposed above the laminated structure, the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, so The first conductive area forms the first external electrode, and the second conductive area forms the second external electrode.
  • different stacked structures in the at least one stacked structure share the same first external electrode, and/or different stacked structures share the same second external electrode.
  • the conductive layer in the n-layer conductive layer includes at least one of the following:
  • the dielectric layer in the m-layer dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer, metal oxynitride layer.
  • a method for manufacturing a capacitor including:
  • At least one laminated structure is prepared over the substrate, the laminated structure includes an n-layer conductive layer and an m-layer dielectric layer, and the n-layer conductive layer and the m-layer dielectric layer form the conductive layer and the dielectric layer adjacent to each other Structure, and all odd-numbered conductive layers in the n-layer conductive layer form at least one first stepped structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second stepped structure, and m and n are positive Integer
  • At least one first external electrode and at least one second external electrode are prepared, wherein the first external electrode is electrically connected to a part or all of the odd numbers in the n-layer conductive layer through the step surface of the at least one first step structure A conductive layer, and the second external electrode is electrically connected to some or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.
  • the preparing at least one laminated structure above the substrate includes:
  • the at least one first step structure and the at least one second step structure are formed on the stacked structure.
  • the at least one first step structure and the at least one second step structure are respectively located on different sides of the laminated structure.
  • the at least one first step structure and the at least one second step structure are located on the same side of the laminated structure.
  • the method further includes:
  • the first conductive material layer is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through part or all of the stepped surfaces of the at least one first stepped structure, and the second conductive material layer passes through Part or all of the step surfaces of the at least one second step structure are electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the first conductive material layer covers part or all of the step surfaces of the at least one first step structure to electrically connect part or all of the odd-numbered conductive layers in the n-layer conductive layer
  • the second conductive material layer covers part or all of the step surfaces of the at least one second step structure to electrically connect part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the method further includes:
  • the first external electrode is electrically connected to the first conductive material layer through the first conductive via structure
  • the second external electrode is electrically connected to the second conductive material layer through the second conductive via structure. Conductive material layer.
  • the method further includes:
  • the method further includes:
  • a plurality of first conductive via structures and a plurality of second conductive via structures are prepared, wherein,
  • the first external electrode is electrically connected to the plurality of first conductive via structures, and the plurality of first conductive via structures are electrically connected to the at least one first stepped structure through a part or all of the stepped surfaces Part or all of the odd-numbered conductive layers in the n-layered conductive layer;
  • the second external electrode is electrically connected to the plurality of second conductive via structures, and the plurality of second conductive via structures are electrically connected to the step surface of the at least one second stepped structure. Part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the method further includes:
  • An etch stop layer is prepared, the etch stop layer covers the at least one first step structure and the at least one second step structure, the plurality of first conductive via structures and the plurality of second conductive vias
  • the hole structure penetrates the etch stop layer.
  • the etch stop layer also covers the substrate.
  • the thickness of the conductive layer in the n-layer conductive layer ranges from 5 nm to 1 mm.
  • the thickness of the dielectric layer in the m-layer dielectric layer ranges from 1 nm to 10 um.
  • the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.
  • the second external electrode is also electrically connected to the substrate.
  • the substrate is formed of a material with a resistivity less than a threshold, or a heavily doped conductive layer or a heavily doped conductive region is formed on the surface of the substrate.
  • the preparing at least one first external electrode and at least one second external electrode includes:
  • the electrode layer is prepared above the laminated structure.
  • the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other.
  • the first conductive region forms the first external electrode
  • the first conductive region forms the first external electrode.
  • Two conductive regions form the second external electrode.
  • different stacked structures in the at least one stacked structure share the same first external electrode, and/or different stacked structures share the same second external electrode.
  • the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose
  • the first external electrode is electrically connected to some or all of the odd-numbered conductive layers in the n-layer conductive layer through at least one step surface of the first stepped structure, and the second external electrode passes through at least one
  • the step surface of the second step structure is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.
  • a laminated structure can be fabricated on a flat substrate surface, and at least one first stepped structure and at least one second stepped structure can be formed on the laminated structure by using a photoresist trimming process, thereby avoiding the problems associated with preparing a 3D structure. Expensive processes such as etching and deposition, and the photoresist trimming process effectively reduces the number of photolithography and reduces the cost of the capacitor.
  • Fig. 1 is a schematic structural diagram of a capacitor provided by the present application.
  • Fig. 2 is a schematic diagram of a photoresist trimming process according to an embodiment of the present application.
  • Fig. 3 is a top view of an external electrode according to an embodiment of the present application.
  • Fig. 4 is a top view of another external electrode according to an embodiment of the present application.
  • Fig. 5 is a schematic diagram of different laminated structures according to an embodiment of the present application.
  • Fig. 6 is a schematic three-dimensional structural diagram of a laminated structure according to an embodiment of the present application.
  • Fig. 7 is a schematic diagram of a three-dimensional preparation process of another laminated structure according to an embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of another capacitor according to an embodiment of the present application.
  • Fig. 9 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.
  • 10a to 10p are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.
  • capacitors in the embodiments of the present application can perform functions such as bypassing, filtering, and decoupling in the circuit.
  • this application proposes a new type of capacitor structure and manufacturing method, by fabricating multiple alternating layers of conductive films and dielectric films on a flat substrate surface, and finally realize the interconnection and interconnection of odd-numbered conductive layers. Interconnection of even-numbered conductive layers. Because expensive processes such as etching and deposition related to the 3D structure are avoided, and the photoresist trimming process is used to effectively reduce the number of photolithography, it is possible to reduce the capacitors while preparing small-volume, high-capacitance-density capacitors cost.
  • the capacitors in FIGS. 1 and 8 and the laminated structure included in the capacitor are merely examples, and the number of laminated structures and the number of conductive layers and the number of dielectric layers included in the laminated structure are merely examples.
  • the number of conductive layers and the number of dielectric layers included in the layer structure are not limited to those shown in the capacitors in FIGS. 1 and 8, and can be flexibly set according to actual needs.
  • FIG. 1 is a possible structural diagram of a capacitor 100 according to an embodiment of the present application.
  • the capacitor 100 includes at least one laminated structure 120, at least one first external electrode 130, and at least one second external electrode 140.
  • the laminated structure 120 includes an n-layer conductive layer and an m-layer dielectric layer, and the n-layer conductive layer and the m-layer dielectric layer form a conductive layer and a dielectric layer that are mutually opposite to each other.
  • Adjacent structure, and all odd-numbered conductive layers in the n-layer conductive layer form at least one first stepped structure 10, and all even-numbered conductive layers in the n-layer conductive layer form at least one second stepped structure 20, m, n Is a positive integer;
  • the first external electrode 130 is electrically connected to some or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one first stepped structure 10;
  • the second external electrode 140 is electrically connected through the at least one
  • the step surface of the second step structure 20 is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose the n-layer
  • the first external electrode is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through the step surface of at least one first step structure, and the second external electrode is connected through at least one second conductive layer.
  • the step surface of the step structure is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.
  • a laminated structure can be fabricated on a flat substrate surface, and at least one first stepped structure and at least one second stepped structure can be formed on the laminated structure by using a photoresist trimming process, thereby avoiding the problems associated with preparing a 3D structure. Expensive processes such as etching and deposition, and the photoresist trimming process effectively reduces the number of photolithography and reduces the cost of the capacitor.
  • all odd-numbered conductive layers in the n-layer conductive layer are dislocated to form at least one first step structure 10, and all even-numbered conductive layers in the n-layer conductive layer are dislocated to form at least one The second step structure 20.
  • a partial area of the upper surface of all odd-numbered conductive layers in the n-layer conductive layer forms the step surface of the first stepped structure 10, and a certain side surface of all odd-numbered conductive layers in the n-layer conductive layer Part or all of the area forms the vertical surface of the first step structure 10.
  • a partial area of the upper surface of all even-numbered conductive layers in the n-layer conductive layer forms the step surface of the second stepped structure 20, and a certain side surface of all even-numbered conductive layers in the n-layer conductive layer Part or all of the area forms the vertical surface of the second step structure 20.
  • the first stepped structure 10 is a whole composed of multiple steps, that is, as shown in FIG. 1, the first stepped structure 10 is a whole composed of 4 steps, in other words, the 4 are formed by odd-numbered conductive layers.
  • the steps constitute the first step structure 10.
  • the second step structure 20 is a whole composed of a plurality of steps, that is, as shown in FIG. 1, the second step structure 20 is a whole composed of three steps, in other words, three are formed by even-numbered conductive layers
  • the steps constitute the second step structure 20.
  • the capacitor 100 may further include a substrate 110, and the at least one stacked structure 120 is disposed above the substrate 110, as shown in FIG. 1.
  • FIG. 1 in the embodiment of the present application is a cross-sectional view along the longitudinal direction of the substrate.
  • two adjacent conductive layers in the n-layer conductive layer are electrically isolated by a dielectric layer, and the specific values of m and n can be flexibly configured according to actual needs.
  • the two adjacent conductive layers are electrically isolated.
  • a dielectric layer needs to be provided between the first conductive layer of the laminated structure 120 and the substrate 110 to isolate the first conductive layer.
  • n ⁇ 2 n ⁇ 2.
  • two adjacent conductive layers in the n-layer conductive layer are dislocated.
  • the external electrode in the embodiment of the present application may also be referred to as a pad or an external pad.
  • the photoresist trimming (PR trimming) process used in the embodiments of the present application refers to a process in which part of the photoresist is removed laterally by dry etching to expose the surface of the material to be etched.
  • PR trimming photoresist trimming
  • the two steps of the PR trimming process and the etch process are used alternately and cyclically, as shown in Figure 2, which can effectively reduce the number of photolithography and reduce the manufacturing cost.
  • the substrate 110 may be a silicon wafer, including monocrystalline silicon, polycrystalline silicon, and amorphous silicon.
  • the substrate 110 may also be other semiconductor substrates, including silicon-on-insulator (SOI) wafers, silicon carbide (SiC), gallium nitride (GaN), and gallium arsenide (GaAs) wafers.
  • SOI silicon-on-insulator
  • SiC silicon carbide
  • GaN gallium nitride
  • GaAs gallium arsenide
  • the substrate 110 may also be a non-semiconductor substrate, such as a glass substrate, an organic polymer substrate, or a ceramic substrate.
  • the surface of the substrate 110 includes an epitaxial layer, an oxide layer, a doped layer, a bonding layer, a low resistance region, and the like.
  • the thickness of the substrate 110 can also be flexibly set according to actual needs.
  • the substrate 110 can be The thinning process is performed, and even the substrate 110 is completely removed.
  • the material of the first external electrode 130 and the second external electrode 140 may be metal, such as copper, aluminum, or the like.
  • the first external electrode 130 and the second external electrode 140 may also include low resistivity Ti, TiN, Ta, TaN layers as adhesion layers and/or barrier layers; they may also include some metal layers on the surface of the external electrodes, such as Ni, Pd (palladium), Au, Sn (tin), Ag are used for subsequent wire bonding or welding processes.
  • the conductive layer in the n-layer conductive layer includes at least one of the following:
  • the material of the conductive layer in the n-layer conductive layer may be heavily doped polysilicon, carbon, aluminum (Al), tungsten (W), copper (Cu), titanium (Ti) ), tantalum (Ta), platinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh), nickel (Ni) and other metals, tantalum nitride (TaN), titanium nitride (TiN), nitride Low-resistivity compounds such as ruthenium (RuN), or the conductive layer in the n-layer conductive layer is a combination, laminate, or composite structure of the above-mentioned materials.
  • one conductive layer in the n-layer conductive layer may be one layer or multiple stacked layers, and a certain conductive layer in the n-layer conductive layer may be a single layer formed of a single material or multiple layers.
  • the materials and thicknesses of different conductive layers in the n-layer conductive layer may be the same or different.
  • the specific conductive material and layer thickness of the conductive layer in the n-layer conductive layer can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the conductive layer in the n-layer conductive layer may also include some other conductive materials, which is not limited in the embodiment of the present application.
  • the dielectric layer in the m-layer dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer and metal oxynitride layer.
  • the material of the dielectric layer in the m-layer dielectric layer may be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or metal nitride. , Metal oxynitride.
  • SiO 2 , SiN, SiON, or high-k materials including Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 O 3 , La 2 O 3 , HfSiO 4 , LaAlO 3 , SrTiO 3 , LaLuO 3 and so on.
  • One dielectric layer in the m-layer dielectric layer may be one layer or a plurality of stacked layers, and one dielectric layer in the m-layer dielectric layer may be one material or a combination or mixture of multiple materials.
  • the materials and thicknesses of different dielectric layers in the m-layer dielectric layer may be the same or different.
  • the specific insulating material and layer thickness of the dielectric layer in the m-layer dielectric layer can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the dielectric layer in the m-layer dielectric layer may also include some other insulating materials, which is not limited in the embodiment of the present application.
  • the order of the m-layer dielectric layer is: on the substrate 110, the distance from the substrate 110 is ascending.
  • the order of the n-layer conductive layer is: on the substrate 110, the distance from the substrate 110 is ascending order.
  • the thickness of the conductive layer in the n-layer conductive layer ranges from 5 nm to 1 mm.
  • the thickness of the dielectric layer in the m-layer dielectric layer ranges from 1 nm to 10 um.
  • the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.
  • different stacked structures in the at least one stacked structure 120 share the same first external electrode 130, and/or different stacked structures share the same second external electrode 140 .
  • one first external electrode 130 may be electrically connected to some or all of the plurality of stacked structures 120.
  • one second external electrode 140 may also be electrically connected to at most A part or all of the stacked structure 120 is a stacked structure 120.
  • the capacitor 100 includes two stacked structures 120, two first external electrodes 130, and one second external electrode 140.
  • the two stacked structures 120 are respectively denoted as a stacked structure 120a and a stacked structure 120b.
  • the external electrodes 130 are respectively denoted as the first external electrode 130a and the first external electrode 130b, wherein the top view of the first external electrode 130a, the first external electrode 130b, and the second external electrode 140 can be as shown in FIG. 3, the laminated structure 120a And laminated structure 120b not shown in FIG.
  • the first external electrode 130a and the second external electrode 140 are electrically connected to the laminated structure 120a, and the first external electrode 130b and the second external electrode 140 are electrically connected to the laminated structure 120b, namely The layer structure 120a and the stacked structure 120b share a second external electrode 140.
  • the stacked structure 120a and the stacked structure 120b can share one first external electrode while sharing one second external electrode 140.
  • the capacitor 100 includes two stacked structures 120, a first external electrode 130, and two second external electrodes 140.
  • the two stacked structures 120 are respectively denoted as a stacked structure 120a and a stacked structure 120b.
  • the two external electrodes 140 are respectively denoted as the second external electrode 140a and the second external electrode 140b.
  • the top view of the first external electrode 130, the second external electrode 140a and the second external electrode 140b can be as shown in FIG. 120a and the laminated structure 120b are not shown in FIG.
  • the first external electrode 130 and the second external electrode 140a are electrically connected to the laminated structure 120a
  • the first external electrode 130 and the second external electrode 140b are electrically connected to the laminated structure 120b, namely The stacked structure 120a and the stacked structure 120b share a first external electrode 130.
  • the stacked structure 120a and the stacked structure 120b may share a second external electrode while sharing one first external electrode 130.
  • the first external electrode 130 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer
  • the second external electrode 140 is electrically connected to all even-numbered layers in the n-layer conductive layer
  • the capacitance of the capacitor 100 is the largest, that is, in this case, the effect of the laminated structure of increasing the capacitance density of the capacitor can be fully exerted.
  • the capacitors in the embodiments of the present application are not restricted by 3D structures such as grooves and bosses during the process of stacking conductive layers, and can stack more conductive layers. It is possible to form a capacitor with a higher capacitance density.
  • a capacitor may include one laminated structure or multiple laminated structures.
  • the capacitor 100 includes two stacked structures 120, which are respectively denoted as stacked structure 120a and stacked structure 120b.
  • the stacked structure 120a and the stacked structure 120b are two on the substrate 110. There are independent capacitors with different projection positions.
  • a capacitor A can be formed; if only the first external electrode 130 and the second external electrode 140 are electrically connected to the stacked structure 120b, the capacitor B can be formed; if the first external electrode 130 and the second external electrode 140 are electrically connected to the stacked structure 120a and the stacked structure 120b, an equivalent capacitor C can be formed, wherein the capacitance of the capacitor C The value is the sum of the capacitance of capacitor A and the capacitance of capacitor B.
  • both the stacked structure 120a and the stacked structure 120b include 7 conductive layers, and there is a connected conductive layer between the stacked structure 120a and the stacked structure 120b.
  • the stacked structure 120a and the stacked structure 120b can also be completely isolated.
  • the laminated structure 120a and the laminated structure 120b have the same conductive layer, so that the laminated structure 120a and the laminated structure 120b can be simultaneously prepared and formed using the same parameters. Of course, more laminated structures are being prepared. The same applies when.
  • different laminated structures of the at least one laminated structure 120 included in the capacitor 100 may have different conductive layers, which is not limited in the embodiment of the present application.
  • the at least one first step structure 10 and the at least one second step structure 20 are respectively located on different sides of the laminated structure 120.
  • the at least one first stepped structure 10 and the at least one second stepped structure 20 are respectively located on both sides of the stacked structure 120.
  • the three-dimensional structure of the stacked structure 120 may be as shown in FIG. Shown.
  • the at least one first stepped structure 10 and the at least one second stepped structure 20 are located on the same side of the stacked structure 120, and the three-dimensional structure of the stacked structure 120 may be based on FIG. 7 Prepared by the procedure shown. It should be noted that the mask layer in FIG. 7 can be removed later.
  • the capacitor 100 further includes: a first conductive material layer 150 and a second conductive material layer 160, wherein the first conductive material layer 150 passes through the steps of the at least one first step structure 10
  • the surface is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer
  • the second conductive material layer 160 is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second step structure 20 Layer conductive layer.
  • the first conductive material layer 150 is electrically connected to all odd-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one first stepped structure 10, and the second conductive material layer 160 passes through The step surface of the at least one second step structure 20 is electrically connected to all the even-numbered conductive layers in the n-layer conductive layer.
  • the first conductive material layer 150 covers part or all of the stepped surfaces of the at least one first stepped structure 10 to electrically connect part or all of the odd-numbered conductive layers in the n-layer conductive layer and the second conductive layer.
  • the material layer 160 covers part or all of the step surface of the at least one second step structure 20 to electrically connect part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the first conductive material layer 150 covers all the step surfaces of the at least one first step structure 10 to electrically connect all odd-numbered conductive layers in the n-layer conductive layer and the second conductive layer.
  • the material layer 160 covers all the step surfaces of the at least one second step structure 20 to electrically connect all the even-numbered conductive layers in the n-layer conductive layer.
  • the capacitor 100 further includes: a first conductive via structure 170 and a second conductive via structure 180, wherein the first external electrode 130 is electrically connected to the first conductive via structure 170 through the first conductive via structure 170
  • the material layer 150, the second external electrode 140 is electrically connected to the second conductive material layer 160 through the second conductive via structure 180, for example, as shown in FIG. 1.
  • the capacitor 100 further includes a sidewall structure 190 formed of an insulating material, wherein the sidewall structure 190 covers the vertical surface of the at least one first step structure 10, and is used to isolate the first conductive material layer 150 from The vertical surface of the at least one first step structure 10, and the side wall structure 190 covers the vertical surface of the at least one second step structure 20, and is used to isolate the second conductive material layer 160 from the at least one second step structure 20 The vertical plane.
  • a sidewall structure 190 formed of an insulating material, wherein the sidewall structure 190 covers the vertical surface of the at least one first step structure 10, and is used to isolate the first conductive material layer 150 from The vertical surface of the at least one first step structure 10, and the side wall structure 190 covers the vertical surface of the at least one second step structure 20, and is used to isolate the second conductive material layer 160 from the at least one second step structure 20 The vertical plane.
  • a stepped step may form a step surface and a vertical surface, and the step surface and the vertical surface may be perpendicular or approximately perpendicular.
  • the arrangement of the side wall structure 190 can also strengthen the electrical insulation between adjacent conductive layers.
  • the first conductive material layer 150 covers the at least one first stepped structure 10 to electrically connect all odd-numbered conductive layers on the step surface of the at least one first stepped structure 10 (four stepped steps), and the second
  • the conductive material layer 160 covers the at least one second step structure 20 to electrically connect all the even-numbered conductive layers on the step surface of the at least one second step structure 20 (three steps of steps).
  • the side wall structure 190 covers the vertical surface of the at least one first stepped structure 10 to isolate the first conductive material layer 150 from the vertical surface of the at least one first stepped structure 10, and the side wall structure 190 covers the at least one vertical surface.
  • the vertical surface of a second step structure 20 is used to isolate the second conductive material layer 160 from the vertical surface of the at least one second step structure 20.
  • the capacitor 100 further includes: a plurality of first conductive via structures 170 and a plurality of second conductive via structures 180, wherein,
  • the first external electrode 130 is electrically connected to the plurality of first conductive via structures 170, and the plurality of first conductive via structures 170 are electrically connected to the n through a part or all of the step surfaces of the at least one first step structure 10 Part or all of the odd-numbered conductive layers in the conductive layers;
  • the second external electrode 140 is electrically connected to the plurality of second conductive via structures 180, and the plurality of second conductive via structures 180 are electrically connected to the n through a part or all of the step surfaces of the at least one second step structure 20 Part or all of the even-numbered conductive layers in the conductive layer.
  • the capacitor 100 further includes an etch stop layer 200 covering the at least one first step structure 10 and the at least one second step structure 20, and the plurality of first conductive via structures 170 and the plurality of second conductive via structures 180 penetrate the etch stop layer 200.
  • the etching stop layer 200 also covers the substrate 110.
  • the arrangement of the etch stop layer 200 can also strengthen the electrical insulation between adjacent conductive layers.
  • the etch stop layer 200 can also strengthen the electrical insulation between the laminated structure 120 and the substrate 110.
  • the etch stop layer 200 is more resistant to etching than the conductive layer and the dielectric layer in the stacked structure 120.
  • the etch stop layer 200 is processed by other processes, so that the conductive via structure is connected to the conductive layer without destroying the integrity of the conductive layer.
  • the etch stop structure 200 can effectively prevent the first conductive via structure 170 and the second conductive via structure 180 from damaging the integrity of the conductive layer, thereby preventing the first conductive via structure 170 and the second conductive via structure 170 from damaging the integrity of the conductive layer.
  • the arrangement of the via structure 180 affects the performance of the capacitor 100.
  • the etching stop layer 200 may be silicon oxide, silicon nitride, silicon-containing glass (Undoped Silicon Glass (Undoped Silicon Glass, USG), Borosilicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG)); it can also be atomic layer deposition (ALD) ) Deposited alumina; or sprayed or spin-coated spin-on glass (SOG), polyimide (Polyimide), etc.; it can also be a combination of the above materials.
  • silicon oxide silicon nitride
  • silicon-containing glass Undoped Silicon Glass (Undoped Silicon Glass, USG), Borosilicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG)
  • ALD atomic layer deposition
  • SOG spin-coated spin-on glass
  • Polyimide Polyimide
  • the laminated structure 120 may include 7 conductive layers, for example, adjacent conductive layers shown in FIG. 8 are electrically isolated by a dielectric layer,
  • the four first conductive via structures 170 are respectively electrically connected to all the odd-numbered conductive layers on the step surface of the at least one first step structure 10 (four stepped steps), and the three second conductive via structures 180 are respectively electrically connected All the even-numbered conductive layers on the step surface of the at least one second step structure 20 (3 stepped steps) are connected.
  • the etch stop layer 200 covers the at least one first step structure 10 and the at least one second step structure 20, and the plurality of first conductive via structures 170 and the plurality of second conductive via structures 180 penetrate the etch Stop layer 200.
  • the substrate 110 is made of a material with a resistivity less than a threshold, or the surface of the substrate 110 is provided with a heavily doped conductive layer or a heavily doped conductive layer with a resistivity less than the threshold.
  • Conductive area That is, the substrate 110 is conductive, or the area of the substrate 110 in contact with the laminated structure 120 is conductive.
  • a material with a resistivity less than the threshold value can be regarded as a conductive material.
  • the substrate 110 is a heavily doped substrate
  • the substrate 110 may also be doped to form a p++-type or n++-type low-resistivity conductive layer or conductive region.
  • a low-resistivity conductive material is deposited on the surface of the substrate 110, such as using a PVD or ALD process to deposit TiN and/or TaN and/or Pt and other metals, or using a CVD process to deposit heavily doped polysilicon, metal tungsten, Carbon material.
  • the substrate 110 is formed of a material with a resistivity less than the threshold, it can be considered that the substrate 110 is a heavily doped low-resistivity substrate; the surface of the substrate 110 is formed with a heavily doped resistivity less than the threshold.
  • the conductive layer of the substrate 110 can be considered to be a heavily doped low-resistivity conductive layer formed on the surface of the substrate 110; the surface of the substrate 110 is formed with a heavily doped conductive region with a resistivity less than the threshold, which can be considered to be the substrate 110 A heavily doped low-resistivity conductive area is formed on the surface.
  • the second external electrode 140 may also be electrically connected to the substrate 110.
  • the second conductive material layer 160 also covers the substrate 110 to electrically connect all the even-numbered conductive layers on the step surface of the at least one second step structure 20
  • the second external electrode 140 is electrically connected to the second conductive material layer 160 through the second conductive via structure 180, so that the second external electrode 140 is electrically connected to all even-numbered conductive layers and the substrate.
  • the purpose of the bottom 110 For another example, the second external electrode 140 may also be electrically connected to the substrate 110 through a second conductive via structure 180 connected to the substrate 110.
  • the capacitor 100 further includes at least one insulating layer 210.
  • the at least one insulating layer 210 covers the laminated structure 120, and the first conductive via structure 170 and the second conductive via structure 180 penetrate the at least one insulating layer 210.
  • the at least one insulating layer 210 may also be referred to as an intermetal dielectric layer (IMD) or an interlayer dielectric layer (ILD).
  • IMD intermetal dielectric layer
  • ILD interlayer dielectric layer
  • the first conductive via structure 170 and the second conductive via structure 180 may also be referred to as conductive channels.
  • the at least one insulating layer 210 covers the laminated structure 120, and the at least one insulating layer 210 can fill a cavity or gap formed on the upper surface of the laminated structure 120 to improve the structural integrity of the capacitor And mechanical stability.
  • the material and preparation process of the at least one insulating layer 210 may be the same as the above-mentioned etch stop layer 200, and for the sake of brevity, it will not be repeated here.
  • the material of the first conductive via structure 170 and the second conductive via structure 180 may be made of a low-resistivity conductive material, such as heavily doped polysilicon, tungsten, Ti, TiN, Ta, TaN.
  • first conductive via structure 170 and the second conductive via structure 180 may be specifically determined according to the manufacturing process of the capacitor 100, which is not limited in the embodiment of the present application.
  • the at least one first external electrode 130 and the at least one second external electrode 140 are disposed above the laminated structure 120.
  • the capacitor 100 further includes: an electrode layer disposed above the laminated structure 120, the electrode layer including at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms The first external electrode 130 and the second conductive area form the second external electrode 140, as shown in FIGS. 1 and 8 in detail. That is, the at least one first external electrode 130 and the at least one second external electrode 140 can be formed by one etching, which reduces the etching steps. Specifically, as shown in FIGS. 1 and 8, the electrode layer is disposed above the at least one insulating layer 210.
  • the capacitors of the embodiments of the present application are described above, and the method for preparing the capacitors of the embodiments of the present application is described below.
  • the method for preparing a capacitor of the embodiment of the present application can prepare the capacitor of the foregoing embodiment of the present application, and the following embodiment and the related description in the foregoing embodiment can be referred to each other.
  • FIG. 9 is a schematic flowchart of a method for manufacturing a capacitor in an embodiment of the present application, but these steps or operations are only examples, and the embodiment of the present application may also perform other operations or modifications of each operation in FIG. 9.
  • FIG. 9 shows a schematic flowchart of a method 300 for manufacturing a capacitor according to an embodiment of the present application. As shown in FIG. 9, the manufacturing method 300 of the capacitor includes:
  • Step 310 prepare at least one laminated structure over the substrate, the laminated structure including an n-layer conductive layer and an m-layer dielectric layer, the n-layer conductive layer and the m-layer dielectric layer form the conductive layer and the dielectric layer adjacent to each other Structure, and all odd-numbered conductive layers in the n-layer conductive layer form at least one first stepped structure, and all even-numbered conductive layers in the n-layer conductive layer form at least one second stepped structure, and m and n are positive integers;
  • Step 320 prepare at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to a part or all of the odd number of the n-layer conductive layer through the step surface of the at least one first step structure A conductive layer, and the second external electrode is electrically connected to a part or all of the even-numbered conductive layers in the n-layer conductive layer through the step surface of the at least one second stepped structure.
  • the capacitor as shown in FIG. 1 and FIG. 8 can be prepared based on the above steps 310-320.
  • each material layer described in steps 310-320 refers to the surface of the material layer that is substantially parallel to the upper surface of the substrate.
  • the at least one first step structure 10 and the at least one second step structure 20 are respectively located on different sides of the laminated structure 120.
  • the at least one first step structure 10 and the at least one second step structure 20 are located on the same side of the laminated structure 120.
  • the thickness of the conductive layer in the n-layer conductive layer ranges from 5 nm to 1 mm.
  • the thickness of the dielectric layer in the m-layer dielectric layer ranges from 1 nm to 10 um.
  • the thickness of the conductive layer in the n-layer conductive layer is greater than the thickness of the dielectric layer in the m-layer dielectric layer.
  • the second external electrode 140 is also electrically connected to the substrate 110. That is, the substrate 110 is conductive, or some specific areas in the substrate 110 are conductive, so that the substrate 110 can serve as a conductive layer of the capacitor 100.
  • the substrate 110 is formed of a material with a resistivity less than a threshold value, or a heavily doped conductive layer or a heavily doped conductive region is formed on the surface of the substrate 110.
  • the foregoing step 310 may specifically be:
  • the at least one first step structure 10 and the at least one second step structure 20 are formed on the laminated structure 120 by using a photoresist trimming process.
  • the method 300 further includes:
  • the first conductive material layer 150 is electrically connected to some or all of the odd-numbered conductive layers in the n-layer conductive layer through part or all of the stepped surfaces of the at least one first stepped structure 10, and the second conductive material layer 160 passes through the Part or all of the step surfaces of the at least one second step structure 20 are electrically connected to some or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the first conductive material layer 150 covers part or all of the stepped surfaces of the at least one first stepped structure 10 to electrically connect part or all of the odd-numbered conductive layers in the n-layer conductive layer and the second conductive layer.
  • the material layer 160 covers part or all of the step surface of the at least one second step structure 20 to electrically connect part or all of the even-numbered conductive layers in the n-layer conductive layer.
  • the method 300 further includes:
  • first external electrode 130 is electrically connected to the first conductive material layer 150 through the first conductive via structure 170
  • second external electrode 140 is electrically connected to the second conductive material layer through the second conductive via structure 180.
  • Material layer 160 is electrically connected to the first conductive material layer 150 through the first conductive via structure 170
  • second external electrode 140 is electrically connected to the second conductive material layer through the second conductive via structure 180.
  • the method 300 further includes:
  • a sidewall structure 190 formed of an insulating material wherein the sidewall structure 190 covers the vertical surface of the at least one first step structure 10 and is used to isolate the first conductive material layer 150 from the at least one first step structure 10
  • the side wall structure 190 covers the vertical surface of the at least one second step structure 20 to isolate the second conductive material layer 160 from the vertical surface of the at least one second step structure 20.
  • the method 300 further includes:
  • a plurality of first conductive via structures 170 and a plurality of second conductive via structures 180 are prepared, wherein,
  • the first external electrode 130 is electrically connected to the plurality of first conductive via structures 170, and the plurality of first conductive via structures 170 are electrically connected to the n through a part or all of the step surfaces of the at least one first step structure 10 Part or all of the odd-numbered conductive layers in the conductive layers;
  • the second external electrode 140 is electrically connected to the plurality of second conductive via structures 180, and the plurality of second conductive via structures 180 are electrically connected to the n through a part or all of the step surfaces of the at least one second step structure 20 Part or all of the even-numbered conductive layers in the conductive layer.
  • the method 300 further includes:
  • An etch stop layer 200 is prepared, the etch stop layer 200 covers the at least one first step structure 10 and the at least one second step structure 20, the plurality of first conductive via structures 170 and the plurality of second conductive vias
  • the hole structure 180 penetrates the etch stop layer 200.
  • the etch stop layer 200 also covers the substrate 110.
  • the foregoing step 320 may specifically be:
  • the electrode layer is prepared above the laminated structure 120.
  • the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other.
  • the first conductive region forms the first external electrode 130, and the second conductive region
  • the second external electrode 140 is formed.
  • different stacked structures in the at least one stacked structure 120 share the same first external electrode 130, and/or different stacked structures share the same second external electrode 140.
  • the laminated structure 120 includes 7 conductive layers and 7 dielectric layers.
  • the above-mentioned steps 310 and 320 may specifically be the preparation process shown in step a to step 1 (FIGS. 10a-10p), and the capacitor 100 shown in FIG. 1 may be prepared.
  • the capacitor 100 as shown in FIG. 8 can also be prepared, which can refer to the capacitor preparation process shown in step a to step 1 (FIGS. 10a-10p). For the sake of brevity, the details are not repeated here.
  • Step a select the substrate 110, and deposit an alternating stack of 7 conductive layers and 7 dielectric layers on the upper surface of the substrate 110, as shown in FIG. 10a;
  • Step b using photolithography combined with an etching process to pattern the outermost conductive layer to expose the next conductive layer of the outermost conductive layer in a part of the area, as shown in FIG. 10b;
  • Step c coating a layer of photoresist on the surface of the structure as shown in FIG. 10b, and obtaining a photoresist pattern as shown in FIG. 10c after exposure and development;
  • Step d dry etching is performed using photoresist as a mask to remove two conductive layers and two dielectric layers, as shown in FIG. 10d;
  • Step e using a photoresist trimming process to remove part of the photoresist by lateral retreat, as shown in FIG. 10e, and then dry etching to remove two conductive layers and two dielectric layers, as shown in FIG. 10f;
  • Step f using a photoresist trimming process to remove part of the photoresist by laterally retracting, as shown in FIG. 10g; then, dry etching removes two conductive layers and two dielectric layers, exposing the substrate 110 and the first layer The conductive layer (the conductive layer in contact with the substrate 110), as shown in FIG. 10h;
  • step g the remaining photoresist is removed to obtain a first step structure 10 and a second step structure 20. All odd-numbered conductive layers are exposed on the first stepped structure 10, and all even-numbered conductive layers are exposed on the second stepped structure 20, such as As shown in Figure 10i;
  • Step h using a CVD or ALD process to deposit a layer of insulating material on the surface of the structure (including the vertical surface of the step) as shown in FIG. 10i, as shown in FIG. 10j, the insulating material may be silicon oxide, silicon nitride, or aluminum oxide.
  • the insulating material may be silicon oxide, silicon nitride, or aluminum oxide.
  • dry etching is used to remove the insulating material on the horizontal surface, and an insulating spacer 190 is formed on the vertical surface of the step, as shown in FIG. 10k;
  • Step i depositing a layer of conductive material on the structure shown in FIG. 10k, and patterning the first conductive material layer 150 and the second conductive material layer 160, as shown in FIG. 10l;
  • Step j deposit a layer of insulating material on the structure shown in FIG. 10l and planarize it to form an insulating layer 210 (or an interlayer dielectric layer (ILD)), as shown in FIG. 10m;
  • ILD interlayer dielectric layer
  • Step k using photolithography combined with an etching process to form two through holes in the insulating layer 210, and the bottoms of the two through holes respectively expose the first conductive material layer 150 and the second conductive material layer 160, as shown in FIG. 10n ;
  • Step 1 Fill the two through holes with conductive material to form a first conductive through hole structure 170 and a second conductive through hole structure 180, and prepare the first external electrode 130 and the second external electrode 140, so as to prepare as shown in FIG. 10o Or the capacitor shown in Figure 10p.
  • the following method 1 and method 2 can be used to fill conductive materials and fabricate electrodes.
  • Method 1 when the size of the through hole is large, you can directly use the PVD process to form a metal layer on the sidewall of the through hole and the surface of the ILD; finally, use photolithography to pattern the metal layer on the surface of the ILD to obtain independent electrodes, such as Shown in Figure 10o. That is, the first conductive via structure 170 and the second conductive via structure 180 may have the same material as the first external electrode 130 and the second external electrode 140.
  • Method 2 when the size of the through hole is small, first use PVD to deposit one or more layers of Ti/TiN/TaN as the adhesion layer and/or barrier layer on the sidewall of the through hole, and then fill the hole with metal tungsten by CVD. Then, an etchback process or a surface planarization process is used to remove the excess conductive material on the surface of the ILD layer. Finally, the PVD process is used to deposit Ti/TiN and metal again on the surface of the ILD, and then patterned by photolithography to obtain individual electrodes, as shown in Figure 10p. That is, the first conductive via structure 170 and the second conductive via structure 180 may have different materials from the first external electrode 130 and the second external electrode 140.
  • the stacked structure is formed with at least one first step structure to expose all odd-numbered conductive layers in the n-layer conductive layer, and the stacked structure is formed with at least one second step structure to expose All the even-numbered conductive layers in the n-layer conductive layer, the first external electrode is electrically connected to part or all of the odd-numbered conductive layers in the n-layer conductive layer through at least one first step structure, and the second external electrode is through at least one second step structure
  • the step surface is electrically connected to part or all of the even-numbered conductive layers in the n-layer conductive layer, so that a three-dimensional silicon capacitor can be prepared, which can reduce the cost of the capacitor while preparing a capacitor with a small volume and a high capacitance value density.
  • a laminated structure can be fabricated on a flat substrate surface, and at least one first stepped structure and at least one second stepped structure can be formed on the laminated structure by using a photoresist trimming process, thereby avoiding the problems associated with preparing a 3D structure. Expensive processes such as etching and deposition, and the photoresist trimming process effectively reduces the number of photolithography and reduces the cost of the capacitor.

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Abstract

L'invention concerne un condensateur (100) et son procédé de fabrication permettant de fabriquer un condensateur (100) à faible coût. Le condensateur (100) comprend : au moins une structure d'empilement (120) comprenant n couches électriquement conductrices et m couches diélectriques, les n couches électriquement conductrices et les m couches diélectriques formant une structure dans laquelle les couches électriquement conductrices et les couches diélectriques sont adjacentes les unes aux autres, toutes les couches électriquement conductrices impaires dans les n couches électriquement conductrices formant au moins une première structure étagée (10), toutes les couches électriquement conductrices paires dans les n couches électriquement conductrices formant au moins une deuxième structure étagée (20), et chacun de m et n étant un nombre entier positif ; au moins une première électrode externe (130) électriquement connectée à une partie ou à la totalité des couches électriquement conductrices impaires dans les n couches électriquement conductrices au moyen d'une surface d'étage de la première structure étagée (10) ; et au moins une seconde électrode externe (140) électriquement connectée à une partie ou à la totalité des couches électriquement conductrices paires dans les n couches électriquement conductrices au moyen d'une surface d'étage de la seconde structure étagée (20).
PCT/CN2020/070928 2020-01-08 2020-01-08 Condensateur et son procédé de fabrication WO2021138839A1 (fr)

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