WO2021042500A1 - 一种显示面板及其制备方法 - Google Patents

一种显示面板及其制备方法 Download PDF

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Publication number
WO2021042500A1
WO2021042500A1 PCT/CN2019/116107 CN2019116107W WO2021042500A1 WO 2021042500 A1 WO2021042500 A1 WO 2021042500A1 CN 2019116107 W CN2019116107 W CN 2019116107W WO 2021042500 A1 WO2021042500 A1 WO 2021042500A1
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Prior art keywords
layer
metal
active
display panel
dielectric layer
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PCT/CN2019/116107
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English (en)
French (fr)
Inventor
肖辉
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/625,722 priority Critical patent/US11309341B2/en
Publication of WO2021042500A1 publication Critical patent/WO2021042500A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/385—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel and a preparation method thereof.
  • part of the semiconductor layer made of IGZO indium gallium zinc oxide
  • IGZO indium gallium zinc oxide
  • the conductive part of the semiconductor layer has a technical problem of increased impedance.
  • a display panel which includes:
  • a light-shielding layer provided on the substrate
  • a buffer layer disposed on the substrate and covering the light shielding layer
  • An active layer disposed on the buffer layer
  • a gate insulating layer and a gate metal layer stacked on the active layer
  • An interlayer dielectric layer disposed on the buffer layer and covering the gate metal layer;
  • An anode metal layer, a light-emitting layer and a cathode metal layer which are stacked on the flat layer;
  • the flat layer is further provided with a pixel definition layer, the pixel definition layer is provided with a pixel opening, the light-emitting layer is located in the pixel opening;
  • the active layer includes an active island, the active The island includes a conductor layer and a semiconductor layer corresponding to and in contact with the gate insulating layer, a protective layer is provided on the conductor layer, and the source and drain metal layers pass through the protective layer and are in contact with the conductor layer.
  • a protective layer covering the gate metal layer is also provided on the gate metal layer.
  • the light shielding layer includes a first metal plate
  • the active layer further includes a dielectric layer independent of the active island, and the position of the dielectric layer is opposite to the first metal plate.
  • the second metal layer further includes a second metal electrode plate disposed on the dielectric layer and independent of the source and drain metal layers.
  • a protective layer covering the dielectric layer is also provided on the dielectric layer.
  • an opening is provided on the interlayer dielectric layer, and the second metal electrode plate is located in the opening.
  • the protective layer is an aluminum oxide protective layer.
  • a display panel which includes:
  • a light-shielding layer provided on the substrate
  • a buffer layer disposed on the substrate and covering the light shielding layer
  • An active layer disposed on the buffer layer
  • a gate insulating layer and a gate metal layer stacked on the active layer
  • An interlayer dielectric layer disposed on the buffer layer and covering the gate metal layer;
  • An anode metal layer, a light-emitting layer and a cathode metal layer which are stacked on the flat layer;
  • the active layer includes an active island, the active island includes a conductor layer and a semiconductor layer corresponding to and in contact with the gate insulating layer, a protective layer is provided on the conductor layer, and the source and drain metals The layer penetrates the protective layer and is in contact with the conductor layer.
  • a protective layer covering the gate metal layer is also provided on the gate metal layer.
  • the light shielding layer includes a first metal plate
  • the active layer further includes a dielectric layer independent of the active island, and the position of the dielectric layer is opposite to the first metal plate.
  • the second metal layer further includes a second metal electrode plate disposed on the dielectric layer and independent of the source and drain metal layers.
  • a protective layer covering the dielectric layer is also provided on the dielectric layer.
  • an opening is provided on the interlayer dielectric layer, and the second metal electrode plate is located in the opening.
  • the protective layer is an aluminum oxide protective layer.
  • the present invention also provides a method for manufacturing a display panel, including the following steps:
  • the active layer includes an active island and a dielectric layer independent of the active island. Corresponding to a metal plate;
  • S80 Laminating and forming an anode metal layer, a light emitting layer and a cathode metal layer in sequence on the flat layer.
  • step S40 includes:
  • a protective layer is formed on the conductor layer, a protective layer is also formed on the gate metal layer and the dielectric layer.
  • step S60 includes:
  • the indium gallium zinc oxide is transformed from a semiconductor into a conductor, thereby forming a conductor layer, and at the same time, a dense structure of the two oxides is generated on the surface of the conductor layer.
  • the aluminum protective layer protects the conductor layer after the conductorization and prevents the conductor layer from being affected by the subsequent manufacturing process.
  • aluminum oxide has the characteristics of high resistance, which can effectively increase the capacitance per unit area of the storage capacitor and meet the high resolution requirements.
  • FIG. 1 is a schematic diagram of the structure of a display panel in a specific embodiment of the present invention.
  • FIG. 2 is a schematic diagram of the manufacturing steps of the display panel in the specific embodiment of the present invention.
  • 3 to 7 are schematic diagrams of the manufacturing process of the display panel in the specific embodiment of the present invention.
  • the present invention addresses the technical problem of increased impedance in the conductive part of the semiconductor layer in the existing display panel when the subsequent thermal process time increases.
  • the present invention can solve the above-mentioned problems.
  • a display panel as shown in FIG. 1, includes a substrate 10, a light shielding layer provided on the substrate 10, a buffer layer 30 provided on the substrate 10 and covering the light shielding layer, and a buffer layer 30 provided on the buffer layer.
  • the active layer 40 on the 30, the gate insulating layer 50 and the gate metal layer 60 stacked on the active layer 40, the layer that is provided on the buffer layer 30 and covers the gate metal layer 60
  • a pixel definition layer 106 is further provided on the flat layer 102, a pixel opening is provided on the pixel definition layer 106, and the light-emitting layer 104 is located in the pixel opening.
  • the active layer 40 includes an active island 41, the active island 41 includes a conductive layer 411 and a semiconductor layer 411 corresponding to and in contact with the gate insulating layer 50, and a surface of the conductive layer 411 is provided There is a protective layer 107 covering the conductor layer 411; the second metal layer includes a source-drain metal layer 81, and the source-drain metal layer 81 passes through the protective layer 107 and is in contact with the conductor layer 411.
  • the conductive layer 411 is covered by the protective layer 107, which plays a role of heat insulation, prevents the subsequent thermal process from increasing the impedance of the conductive layer 411, protects the conductive layer 411 from the subsequent thermal process, and improves the thermal stability of the conductive layer 411 Sex.
  • the light-shielding layer includes a first metal plate 21, the active layer 40 also includes a dielectric layer 42 independent of the active island 41, and the position of the dielectric layer 42 is the same as that of the first metal plate.
  • a metal electrode plate 21 corresponds to the second metal layer.
  • the second metal layer also includes a second metal electrode plate 82 that is disposed on the dielectric layer 42 and is independent of the source and drain metal layer 81.
  • the first metal plate 21 and the second metal plate 82 form a storage capacitor, and a portion of the active layer 40 is used as a dielectric material of the storage capacitor.
  • the surface of the gate metal layer 60 and the surface of the dielectric layer 42 are both covered with a protective layer 107.
  • the protective layer 107 is used to protect the gate metal layer 60, and the protective layer 107 and the active layer 40 are used as the dielectric material of the storage capacitor at the same time, which effectively increases the capacitance per unit area of the storage capacitor, thereby meeting the demand for high resolution.
  • the active layer 40 is made of indium gallium zinc oxide
  • the protective layer 107 is an aluminum oxide protective layer 107.
  • the densely structured aluminum oxide protective layer 107 can protect the conductive layer 411 from the influence of subsequent manufacturing processes, and improve the stability of the conductive layer 411. At the same time, aluminum oxide has the characteristics of high resistance. It can effectively increase the capacitance per unit area of the storage capacitor to meet high-resolution requirements.
  • the interlayer dielectric layer 70 is provided with an opening 71, and the second metal electrode plate 82 is located in the opening 71.
  • the present invention also provides a method for manufacturing a display panel, as shown in FIG. 2, including the following steps:
  • a patterned active layer 40 is formed on the buffer layer 30.
  • the active layer 40 includes an active island 41 and a dielectric layer 42 independent of the active island 41.
  • the dielectric layer The position of 42 corresponds to the first metal plate 21;
  • a second metal layer is formed on the interlayer dielectric layer 70 and the dielectric layer 42, and the second metal layer is patterned to form a source and drain connected to the conductor layer 411.
  • the metal layer 81 and the second metal electrode plate 82 independent of the source and drain metal layer 81, the second metal electrode plate 82 is disposed on the dielectric layer 42 so as to be in contact with the first metal electrode plate 21 Form a storage capacitor;
  • the step S40 includes:
  • the protective layer 107 is an aluminum oxide protective layer 107.
  • the active layer 40 is made of indium gallium zinc oxide, which utilizes the mutual diffusion of aluminum atoms and oxygen atoms in indium gallium zinc oxide to transform indium gallium zinc oxide from a semiconductor into a conductor, thereby forming a conductor
  • the layer 411, and the densely structured aluminum oxide protective layer 107 formed on the surface of the conductive layer 411 at the same time, can protect the conductive layer 411 after conductorization and protect the conductive layer 411 from subsequent thermal processes.
  • the protective layer 107 is formed on the conductor layer 411, the protective layer 107 is also formed on the gate metal layer 60 and the dielectric layer 42.
  • the step S60 includes:
  • Aluminum oxide has the characteristics of high resistance, which can effectively increase the capacitance per unit area of the storage capacitor and meet the high resolution requirements.
  • FIGS. 3 to 7 are schematic diagrams of the manufacturing process of the display panel.
  • the light-shielding layer is patterned to form the first metal plate 21, and then a buffer layer 30 covering the light-shielding layer is formed.
  • an active layer 40 is formed on the buffer layer 30, and the active layer 40 is patterned to form an active island 41 and a position corresponding to the first metal plate 21 After the dielectric layer 42 is independent of the active island 41, a gate insulating layer 50 and a gate metal layer 60 are sequentially stacked on the active island 41.
  • a silicon oxide material is used to form an interlayer dielectric layer 70 covering the active layer 40 and the gate metal layer 60.
  • a hole for connecting the source-drain metal layer 81 and the conductor layer 411 is formed on the interlayer dielectric layer 70, and the protective layer 107 at the position corresponding to the hole is removed to facilitate the source-drain metal layer 81 It is connected to the conductor layer 411, and at the same time, an opening 71 is formed on the interlayer dielectric layer 70 to expose the dielectric layer 42.
  • a second metal layer filled with holes and openings 71 is formed on the interlayer dielectric layer 70, and the second metal layer is patterned to form a source and drain connected to the conductor layer 411.
  • the metal layer 81 and the second metal electrode plate 82 independent of the source and drain metal layers 81 are mutually independent.
  • a passivation layer 101 covering the second metal layer is formed on the interlayer dielectric layer 70, and a flat layer 102 is formed on the passivation layer 101.
  • a pixel defining layer 106 and an anode metal layer 103 connected in contact with the drain in the source-drain metal layer 81 are formed on the flat layer 102, and then a light-emitting layer 104 and a cathode metal layer are formed on the anode metal layer 103. 105.
  • the beneficial effect of the present invention is that the mutual diffusion effect of aluminum atoms and oxygen atoms in indium gallium zinc oxide is used to achieve the transformation of indium gallium zinc oxide from a semiconductor into a conductor, thereby forming a conductor layer 411, and at the same time in the conductor layer 411
  • the densely structured aluminum oxide protective layer 107 formed on the surface protects the conductor layer 411 after conductorization and prevents the conductive layer 411 from being affected by subsequent manufacturing processes.
  • aluminum oxide has high resistance characteristics, which can effectively improve storage
  • the capacitance per unit area of the capacitor meets the requirements of high resolution.

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Abstract

本发明提供一种显示面板及其制备方法，显示面板包括基板、设置于基板上的有源层、层叠设置于有源层上的栅极绝缘层以及栅极金属层；其中，有源层包括有源岛，有源岛包括导体层以及与栅极绝缘层对应并接触的半导体层，导体层上设置有保护层。

Description

一种显示面板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及其制备方法。
 背景技术
在显示面板行业，目前Oxide TFT（氧化物薄膜晶体管）中，由IGZO（indium gallium zinc oxide，铟镓锌氧化物）制成的半导体层的部分被导体化，当后续热制程时间增加时，半导体层中被导体化的部分有阻抗升高的问题。
 技术问题
由IGZO制成的半导体层的部分被导体化的过程中，当后续热制程时间增加时，半导体层中被导体化的部分有阻抗升高的技术问题。
 技术解决方案
一种显示面板，其包括：
基板；
设置于所述基板上的遮光层；
设置于所述基板上且覆盖所述遮光层的缓冲层；
设置于所述缓冲层上的有源层；
层叠设置于所述有源层上的栅极绝缘层以及栅极金属层；
设置于所述缓冲层上且覆盖所述栅极金属层的层间介质层；
设置于所述层间介质层上的第二金属层，所述第二金属层包括源漏金属层；
层叠设置于所述层间介质层上的钝化层和平坦层；
层叠设置于所述平坦层上的阳极金属层、发光层和阴极金属层；
其中，所述平坦层上还设置有像素定义层，所述像素定义层上设置有像素开口，所述发光层位于所述像素开口中；所述有源层包括有源岛，所述有源岛包括导体层以及与所述栅极绝缘层对应并接触的半导体层，所述导体层上设置有保护层，所述源漏金属层穿过所述保护层与所述导体层接触连接。
进一步的，所述栅极金属层上也设置有覆盖所述栅极金属层的保护层。
进一步的，所述遮光层包括第一金属极板，所述有源层还包括与所述有源岛相互独立的介电层，所述介电层的位置与所述第一金属极板相对应，所述第二金属层还包括设置在所述介电层上且与所述源漏金属层相互独立的第二金属极板。
进一步的，所述介电层上也设置有覆盖所述介电层的保护层。
进一步的，所述层间介质层上设置有开孔，所述第二金属极板位于所述开孔中。
进一步的，所述保护层为三氧化二铝保护层。
一种显示面板，其包括：
基板；
设置于所述基板上的遮光层；
设置于所述基板上且覆盖所述遮光层的缓冲层；
设置于所述缓冲层上的有源层；
层叠设置于所述有源层上的栅极绝缘层以及栅极金属层；
设置于所述缓冲层上且覆盖所述栅极金属层的层间介质层；
设置于所述层间介质层上的第二金属层，所述第二金属层包括源漏金属层；
层叠设置于所述层间介质层上的钝化层和平坦层；
层叠设置于所述平坦层上的阳极金属层、发光层和阴极金属层；
其中，所述有源层包括有源岛，所述有源岛包括导体层以及与所述栅极绝缘层对应并接触的半导体层，所述导体层上设置有保护层，所述源漏金属层穿过所述保护层与所述导体层接触连接。
进一步的，所述栅极金属层上也设置有覆盖所述栅极金属层的保护层。
进一步的，所述遮光层包括第一金属极板，所述有源层还包括与所述有源岛相互独立的介电层，所述介电层的位置与所述第一金属极板相对应，所述第二金属层还包括设置在所述介电层上且与所述源漏金属层相互独立的第二金属极板。
进一步的，所述介电层上也设置有覆盖所述介电层的保护层。
进一步的，所述层间介质层上设置有开孔，所述第二金属极板位于所述开孔中。
进一步的，所述保护层为三氧化二铝保护层。
本发明还提供一种显示面板的制备方法，包括以下步骤：
S10、在基板上形成遮光层以及覆盖所述遮光层的缓冲层，所述遮光层包括第一金属极板；
S20、在所述缓冲层上形成图案化的有源层，所述有源层包括有源岛和与所述有源岛相互独立的介电层，所述介电层的位置与所述第一金属极板相对应；
S30、在所述有源岛上依次层叠形成栅极绝缘层和栅极金属层；
S40、对所述有源岛露出所述栅极绝缘层的部分进行导体化，形成导体层，并形成覆盖所述导体层的保护层；
S50、形成覆盖所述有源层以及所述栅极金属层的层间介质层；
S60、在所述层间介质层和所述介电层上形成第二金属层，并对所述第二金属层进行图案化处理，以形成与所述导体层接触连接的源漏金属层以及与所述源漏金属层相互独立的第二金属极板，所述第二金属极板设置在所述介电层上，以与所述第一金属极板形成存储电容；
S70、在所述层间介质层上层叠形成钝化层以及平坦层；
S80、在所述平坦层上依次层叠形成阳极金属层、发光层和阴极金属层。
进一步的，所述步骤S40包括：
S41、在所述有源岛露出所述栅极绝缘层的部分上由铝或/和氧化铝形成薄膜；
S42、在有氧的环境中对薄膜进行热退火，使铝分子扩散到所述有源岛露出所述栅极绝缘层的部分中，以使有源岛露出所述栅极绝缘层的部分形成导体层，同时有源岛中的氧原子扩散到薄膜中，以在所述导体层上形成保护层，所述保护层为三氧化二铝保护层。
进一步的，在所述导体层上形成保护层的同时，在所述栅极金属层和所述介电层上也形成保护层。
进一步的，所述步骤S60包括：
S61、在所述层间介质层上与所述第一金属极板对应的位置处形成开孔，以露出所述介电层；
S62、在所述层间介质层和所述介电层上形成第二金属层；
S63、对所述第二金属层进行图案化处理，以形成与所述导体层接触连接的源漏金属层以及与所述源漏金属层相互独立的第二金属极板，所述第二金属极板设置在所述介电层上，以与所述第一金属极板形成存储电容。
 有益效果
利用铝原子与铟镓锌氧化物中的氧原子的相互扩散作用，达到使铟镓锌氧化物由半导体变成导体，从而形成导体层，同时在导体层的表面生成的结构致密的三氧化二铝保护层，保护导体化后的导体层，使导体层免受后续制程的影响；同时三氧化二铝具有高阻值的特性，可有效提高存储电容的单位面积电容，满足高解析度要求。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明具体实施方式中显示面板的结构示意图；
图2为本发明具体实施方式中显示面板的制备步骤示意图；
图3至图7为本发明具体实施方式中显示面板的制备流程示意图。
附图标记：
10、基板；21、第一金属极板；30、缓冲层；40、有源层；41、有源岛；411、导体层；42、介电层；50、栅极绝缘层；60、栅极金属层；70、层间介质层；71、开孔；81、源漏金属层；82、第二金属极板；101、钝化层；102、平坦层；103、阳极金属层；104、发光层；105、阴极金属层；106、像素定义层；107、保护层。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有的显示面板中，当后续热制程时间增加时，半导体层中被导体化的部分有阻抗升高的技术问题。本发明可以解决上述问题。
一种显示面板，如图1所示，包括基板10、设置于所述基板10上的遮光层、设置于所述基板10上且覆盖所述遮光层的缓冲层30、设置于所述缓冲层30上的有源层40、层叠设置于所述有源层40上的栅极绝缘层50以及栅极金属层60、设置于所述缓冲层30上且覆盖所述栅极金属层60的层间介质层70、设置于所述层间介质层70上的第二金属层、层叠设置于所述层间介质层70上的钝化层101和平坦层102，以及，层叠设置于所述平坦层102上的阳极金属层103、发光层104和阴极金属层105。
其中，所述平坦层102上还设置有像素定义层106，所述像素定义层106上设置有像素开口，所述发光层104位于所述像素开口中。
其中，所述有源层40包括有源岛41，所述有源岛41包括导体层411以及与所述栅极绝缘层50对应并接触的半导体层411，所述导体层411的表面上设置有覆盖所述导体层411的保护层107；所述第二金属层包括源漏金属层81，所述源漏金属层81穿过所述保护层107与所述导体层411接触连接。
通过保护层107覆盖所述导体层411，起到隔热的作用，防止后续热制程使导体层411的阻抗升高，使导体层411免受后续热制程的影响，提高导体层411的热稳定性。
具体的，所述遮光层包括第一金属极板21，所述有源层40还包括与所述有源岛41相互独立的介电层42，所述介电层42的位置与所述第一金属极板21相对应，所述第二金属层还包括设置在所述介电层42上且与所述源漏金属层81相互独立的第二金属极板82。
所述第一金属极板21与所述第二金属极板82形成存储电容，利用有源层40的部分充当存储电容的介电材料。
进一步的，所述栅极金属层60的表面和所述介电层42的表面均覆盖有保护层107。
利用保护层107保护栅极金属层60，同时利用保护层107和有源层40同时充当存储电容的介电材料，有效提升存储电容的单位面积电容，进而满足高解析度的需求。
具体的，所述有源层40的制成材料为铟镓锌氧化物，所述保护层107为三氧化二铝保护层107。
利用结构致密的三氧化二铝保护层107可以保护导体化后的导体层411，使其免受后制程的影响，提高导体层411的稳定性，同时三氧化二铝具有高阻值的特性，可有效提高存储电容的单位面积电容，满足高解析度要求。
具体的，所述层间介质层70上设置有开孔71，所述第二金属极板82位于所述开孔71中。
根据上述显示面板，本发明还提供一种显示面板的制备方法，如图2所示，包括以下步骤：
S10、在基板10上形成遮光层以及覆盖所述遮光层的缓冲层30，所述遮光层包括第一金属极板21；
S20、在所述缓冲层30上形成图案化的有源层40，所述有源层40包括有源岛41和与所述有源岛41相互独立的介电层42，所述介电层42的位置与所述第一金属极板21相对应；
S30、在所述有源岛41上依次层叠形成栅极绝缘层50和栅极金属层60；
S40、对所述有源岛41露出所述栅极绝缘层50的部分进行导体化，形成导体层411，并形成覆盖所述导体层411的保护层107；
S50、形成覆盖所述有源层40以及所述栅极金属层60的层间介质层70；
S60、在所述层间介质层70和所述介电层42上形成第二金属层，并对所述第二金属层进行图案化处理，以形成与所述导体层411接触连接的源漏金属层81以及与所述源漏金属层81相互独立的第二金属极板82，所述第二金属极板82设置在所述介电层42上，以与所述第一金属极板21形成存储电容；
S70、在所述层间介质层70上层叠形成钝化层101以及平坦层102；
S80、在所述平坦层102上依次层叠形成阳极金属层103、发光层104和阴极金属层105。
具体的，所述步骤S40包括：
S41、在所述有源岛41露出所述栅极绝缘层50的部分上由铝或/和氧化铝形成薄膜；
S42、在有氧的环境中对薄膜进行热退火，使铝分子扩散到所述有源岛41露出所述栅极绝缘层50的部分中，以使有源岛41露出所述栅极绝缘层50的部分形成导体层411，同时有源岛41中的氧原子扩散到薄膜中，以在所述导体层411上形成保护层107，所述保护层107为三氧化二铝保护层107。
所述有源层40的制成材料为铟镓锌氧化物，利用铝原子与铟镓锌氧化物中氧原子的相互扩散作用，达到使铟镓锌氧化物由半导体变成导体，从而形成导体层411，同时在导体层411的表面生成的结构致密的三氧化二铝保护层107，可以保护导体化后的导体层411，使导体层411免受后续热制程的影响。
进一步的，在所述导体层411上形成保护层107的同时，在所述栅极金属层60和所述介电层42上也形成保护层107。
具体的，所述步骤S60包括：
S61、在所述层间介质层70上与所述第一金属极板21对应的位置处形成开孔71，以露出所述介电层42；
S62、在所述层间介质层70和所述介电层42上形成第二金属层；
S63、对所述第二金属层进行图案化处理，以形成与所述导体层411接触连接的源漏金属层81以及与所述源漏金属层81相互独立的第二金属极板82，所述第二金属极板82设置在所述介电层42上，以与所述第一金属极板21形成存储电容。
三氧化二铝具有高阻值的特性，可有效提高存储电容的单位面积电容，满足高解析度要求。
参见图3至图7，图3至图7为显示面板的制备流程示意图。
如图3所示，在基板10上形成遮光层后，对所述遮光层进行图案化处理，形成第一金属极板21后，形成覆盖所述遮光层的缓冲层30。
如图4所示，在所述缓冲层30上形成有源层40，并对所述有源层40进行图案化处理，形成有源岛41以及位置与所述第一金属极板21相对应并与所述有源岛41相互独立的介电层42后，在所述有源岛41上依次层叠形成栅极绝缘层50和栅极金属层60。
如图5所示，利用铝或/和氧化铝靶材用溅射的方式，或者利用ALD机台形成覆盖有源层40以及栅极金属层60的薄膜，并在有氧环境下进行热褪火，使铝原子扩散到有源层40中，形成导体层411，同时有源层40中的氧原子扩散到薄膜中，形成三氧化二铝保护层107。
如图6所示，利用氧化硅材料形成覆盖所述有源层40以及所述栅极金属层60的层间介质层70。
如图7所示，在层间介质层70上形成用于源漏金属层81与导体层411连接的孔洞，并去除与所述孔洞对应位置处的保护层107，以便于源漏金属层81与导体层411连接，同时在层间介质层70上形成开孔71，以露出所述介电层42。
随后，在所述层间介质层70上形成填充孔洞和开孔71的第二金属层，并对所述第二金属层进行图案化处理，以形成与所述导体层411接触连接的源漏金属层81以及与所述源漏金属层81相互独立的第二金属极板82。
随后，在所述层间介质层70上形成覆盖第二金属层的钝化层101，在所述钝化层101上形成平坦层102。
随后，在所述平坦层102上形成像素定义层106和与所述源漏金属层81中的漏极接触连接的阳极金属层103后，在阳极金属层103上形成发光层104和阴极金属层105。
本发明的有益效果为：利用铝原子与铟镓锌氧化物中的氧原子的相互扩散作用，达到使铟镓锌氧化物由半导体变成导体，从而形成导体层411，同时在导体层411的表面生成的结构致密的三氧化二铝保护层107，保护导体化后的导体层411，使导体层411免受后续制程的影响；同时三氧化二铝具有高阻值的特性，可有效提高存储电容的单位面积电容，满足高解析度要求。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种显示面板，其中，包括：
    基板；
    设置于所述基板上的遮光层；
    设置于所述基板上且覆盖所述遮光层的缓冲层；
    设置于所述缓冲层上的有源层；
    层叠设置于所述有源层上的栅极绝缘层以及栅极金属层；
    设置于所述缓冲层上且覆盖所述栅极金属层的层间介质层；
    设置于所述层间介质层上的第二金属层，所述第二金属层包括源漏金属层；
    层叠设置于所述层间介质层上的钝化层和平坦层；
    层叠设置于所述平坦层上的阳极金属层、发光层和阴极金属层；
    其中，所述平坦层上还设置有像素定义层，所述像素定义层上设置有像素开口，所述发光层位于所述像素开口中；所述有源层包括有源岛，所述有源岛包括导体层以及与所述栅极绝缘层对应并接触的半导体层，所述导体层上设置有保护层，所述源漏金属层穿过所述保护层与所述导体层接触连接。
  2. 根据权利要求1所述的显示面板，其中，所述栅极金属层上也设置有覆盖所述栅极金属层的保护层。
  3. 根据权利要求1所述的显示面板，其中，所述遮光层包括第一金属极板，所述有源层还包括与所述有源岛相互独立的介电层，所述介电层的位置与所述第一金属极板相对应，所述第二金属层还包括设置在所述介电层上且与所述源漏金属层相互独立的第二金属极板。
  4. 根据权利要求3所述的显示面板，其中，所述介电层上也设置有覆盖所述介电层的保护层。
  5. 根据权利要求3所述的显示面板，其中，所述层间介质层上设置有开孔，所述第二金属极板位于所述开孔中。
  6. 根据权利要求1所述的显示面板，其中，所述保护层为三氧化二铝保护层。
  7. 一种显示面板，其中，包括：
    基板；
    设置于所述基板上的遮光层；
    设置于所述基板上且覆盖所述遮光层的缓冲层；
    设置于所述缓冲层上的有源层；
    层叠设置于所述有源层上的栅极绝缘层以及栅极金属层；
    设置于所述缓冲层上且覆盖所述栅极金属层的层间介质层；
    设置于所述层间介质层上的第二金属层，所述第二金属层包括源漏金属层；
    层叠设置于所述层间介质层上的钝化层和平坦层；
    层叠设置于所述平坦层上的阳极金属层、发光层和阴极金属层；
    其中，所述有源层包括有源岛，所述有源岛包括导体层以及与所述栅极绝缘层对应并接触的半导体层，所述导体层上设置有保护层，所述源漏金属层穿过所述保护层与所述导体层接触连接。
  8. 根据权利要求7所述的显示面板，其中，所述栅极金属层上也设置有覆盖所述栅极金属层的保护层。
  9. 根据权利要求7所述的显示面板，其中，所述遮光层包括第一金属极板，所述有源层还包括与所述有源岛相互独立的介电层，所述介电层的位置与所述第一金属极板相对应，所述第二金属层还包括设置在所述介电层上且与所述源漏金属层相互独立的第二金属极板。
  10. 根据权利要求9所述的显示面板，其中，所述介电层上也设置有覆盖所述介电层的保护层。
  11. 根据权利要求9所述的显示面板，其中，所述层间介质层上设置有开孔，所述第二金属极板位于所述开孔中。
  12. 根据权利要求7所述的显示面板，其中，所述保护层为三氧化二铝保护层。
  13. 一种显示面板的制备方法，其中，包括以下步骤：
    S10、在基板上形成遮光层以及覆盖所述遮光层的缓冲层，所述遮光层包括第一金属极板；
    S20、在所述缓冲层上形成图案化的有源层，所述有源层包括有源岛和与所述有源岛相互独立的介电层，所述介电层的位置与所述第一金属极板相对应；
    S30、在所述有源岛上依次层叠形成栅极绝缘层和栅极金属层；
    S40、对所述有源岛露出所述栅极绝缘层的部分进行导体化，形成导体层，并形成覆盖所述导体层的保护层；
    S50、形成覆盖所述有源层以及所述栅极金属层的层间介质层；
    S60、在所述层间介质层和所述介电层上形成第二金属层，并对所述第二金属层进行图案化处理，以形成与所述导体层接触连接的源漏金属层以及与所述源漏金属层相互独立的第二金属极板，所述第二金属极板设置在所述介电层上，以与所述第一金属极板形成存储电容；
    S70、在所述层间介质层上层叠形成钝化层以及平坦层；
    S80、在所述平坦层上依次层叠形成阳极金属层、发光层和阴极金属层。
  14. 根据权利要求13所述的显示面板的制备方法，其中，所述步骤S40包括：
    S41、在所述有源岛露出所述栅极绝缘层的部分上由铝或/和氧化铝形成薄膜；
    S42、在有氧的环境中对薄膜进行热退火，使铝分子扩散到所述有源岛露出所述栅极绝缘层的部分中，以使有源岛露出所述栅极绝缘层的部分形成导体层，同时有源岛中的氧原子扩散到薄膜中，以在所述导体层上形成保护层，所述保护层为三氧化二铝保护层。
  15. 根据权利要求14所述的显示面板的制备方法，其中，在所述导体层上形成保护层的同时，在所述栅极金属层和所述介电层上也形成保护层。
  16. 根据权利要求15所述的显示面板的制备方法，其中，所述步骤S60包括：
    S61、在所述层间介质层上与所述第一金属极板对应的位置处形成开孔，以露出所述介电层；
    S62、在所述层间介质层和所述介电层上形成第二金属层；
    S63、对所述第二金属层进行图案化处理，以形成与所述导体层接触连接的源漏金属层以及与所述源漏金属层相互独立的第二金属极板，所述第二金属极板设置在所述介电层上，以与所述第一金属极板形成存储电容。
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