WO2021164569A1 - 显示基板及其制备方法、显示面板 - Google Patents

显示基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021164569A1
WO2021164569A1 PCT/CN2021/075319 CN2021075319W WO2021164569A1 WO 2021164569 A1 WO2021164569 A1 WO 2021164569A1 CN 2021075319 W CN2021075319 W CN 2021075319W WO 2021164569 A1 WO2021164569 A1 WO 2021164569A1
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electrode
light
capacitor electrode
gate
emitting area
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PCT/CN2021/075319
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English (en)
French (fr)
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刘宁
王庆贺
倪柳松
孙涛
周斌
闫梁臣
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US17/432,217 priority Critical patent/US20230148287A1/en
Publication of WO2021164569A1 publication Critical patent/WO2021164569A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a preparation method thereof, and a display panel.
  • the top-gate thin film transistor has the characteristics of a short channel, and its on-state current can be effectively increased, thereby significantly improving the display effect and effectively reducing power consumption.
  • the overlap area between the gate and the source and drain of the top-gate TFT is small, and the resulting parasitic capacitance is small. Therefore, the possibility of defects such as short-circuiting of the gate and the drain is effectively reduced. Because the top-gate TFT has the above-mentioned significant advantages, it has attracted more and more attention.
  • the 3T1C structure is often used. Specifically, an indium tin oxide (Indium Tin Oxide, ITO) electrode and a Cst electrode are used to form a storage capacitor.
  • ITO Indium Tin Oxide
  • the ITO electrode is the part of the ITO anode that extends to the non-light emitting area.
  • the Cst electrode and the metal layer of the source and drain (SD) of the TFT are arranged in the same layer, and are located at the source (S) metal electrode and the drain (D). Between metal electrodes.
  • the storage capacitor In order to make the storage capacitor large enough to ensure that the emitting layer (EL) has a long enough light emitting time, it is necessary to have a very large facing area between the ITO electrode and the Cst electrode.
  • the embodiments of the present disclosure provide a display substrate and a preparation method thereof, and a display panel.
  • the display substrate provides a storage capacitor design structure.
  • a display substrate including a display area, the display area including a plurality of light-emitting areas arranged in an array and a non-light-emitting area located between adjacent light-emitting areas;
  • the display substrate further includes:
  • a first capacitor electrode, at least a part of the first capacitor electrode is located in the light-emitting area
  • a buffer layer which covers the first capacitor electrode and is located in the light-emitting area and the non-light-emitting area;
  • the second capacitor electrode and the active layer are disposed on the buffer layer without overlapping each other, and the active layer is located in the non-light emitting area;
  • the first capacitor electrode, the buffer layer and the second capacitor electrode form a storage capacitor.
  • the display substrate further includes:
  • the anode is located above the second capacitor electrode and the gate, and is insulated from the second capacitor electrode and the gate, at least a part of the anode is located in the light-emitting area, and the first capacitor electrode, The active layer and the anode are electrically connected.
  • the first capacitor electrode is also located in the non-light-emitting area
  • the second capacitor electrode is located in the light-emitting area
  • the anode is also located in the non-light-emitting area
  • the material of the active layer is metal Oxide
  • the display substrate further includes:
  • An interlayer dielectric layer located between the second capacitor electrode and the anode, the interlayer dielectric layer is located in the light-emitting area and the non-light-emitting area, and covers the second capacitor electrode and the gate And the active layer.
  • the display substrate further includes:
  • the connecting electrode is electrically connected, and the second capacitor electrode and the gate are electrically connected through the second connecting electrode.
  • At least a part of the first connection electrode is located in the non-light-emitting area
  • the display substrate further includes:
  • An insulating layer located between the anode and the interlayer dielectric layer, the insulating layer is located in the light-emitting area and the non-light-emitting area, and covers at least the interlayer dielectric layer, the first connecting electrode and The second connection electrode.
  • the display substrate further includes:
  • a first via hole, the first via hole penetrates the interlayer dielectric layer and the buffer layer, and the first connection electrode is electrically connected to the first capacitor electrode through the first via hole;
  • a second via hole, the second via hole penetrates the interlayer dielectric layer, and the first connection electrode is electrically connected to the active layer through the second via hole;
  • the thickness of the portion of the buffer layer used to form the storage capacitor is smaller than the thickness of the portion of the interlayer dielectric layer used to cover the storage capacitor.
  • the second connection electrode is located in the light-emitting area and the non-light-emitting area;
  • the display substrate further includes:
  • a fourth via, the fourth via penetrates the interlayer dielectric layer, and the second connection electrode is electrically connected to the gate through the fourth via;
  • a fifth via hole, the fifth via hole penetrates the interlayer dielectric layer, and the second connection electrode is electrically connected to the second capacitor electrode through the fifth via hole.
  • the fourth via hole is disposed above the side of the gate close to the second connection electrode, and the fifth via hole is disposed on the second capacitor electrode close to the second connection electrode. Above the side.
  • the display substrate further includes:
  • the source electrode and the drain electrode located between the interlayer dielectric layer and the anode, the source electrode, the drain electrode, the first connection electrode and the second connection electrode are arranged in the same layer and do not cross each other Stacked, the source electrode and the drain electrode are both located in the non-light-emitting area, and are electrically connected to the active layer, respectively.
  • the first capacitor electrode is also located in the non-light-emitting area
  • the display substrate further includes:
  • the embodiment of the present disclosure provides a display substrate, the display substrate includes a display area, the display area includes a plurality of light-emitting areas arranged in an array and a non-light-emitting area located between adjacent light-emitting areas; the display The substrate further includes: a first capacitor electrode, at least a part of the first capacitor electrode is located in the light-emitting area; a buffer layer, the buffer layer covering the first capacitor electrode and located in the light-emitting area and the non-light-emitting area
  • the second capacitor electrode and the active layer are arranged on the buffer layer without overlapping each other, and the active layer is located in the non-light emitting area; wherein, the first capacitor electrode, the buffer layer and the The second capacitor electrode forms a storage capacitor.
  • a display panel which includes the above-mentioned display substrate.
  • the display substrate includes a display area, the display area includes a plurality of light-emitting areas arranged in an array and is located between adjacent light-emitting areas.
  • the method includes:
  • the first capacitor electrode, the buffer layer and the second capacitor electrode form a storage capacitor.
  • the method further includes:
  • the gate is located on the active layer and in the non-light-emitting area, and the second capacitor electrode is electrically connected to the gate;
  • An anode is formed, the anode is located on the second capacitor electrode and the gate and at least a part is located in the light-emitting area, and the first capacitor electrode, the active layer and the anode are electrically connected.
  • the second capacitor electrode is located in the light-emitting area, and the material of the active layer is metal oxide;
  • the forming the second capacitor electrode and the active layer that do not overlap each other on the buffer layer includes:
  • a patterning process is used to form a non-overlapping second capacitor electrode to be conductorized and an active layer to be conductorized on the buffer layer.
  • the active layer to be conductorized includes a semiconductor part and is located on the buffer layer. The portions to be conductorized on both sides of the semiconductor portion and connected to the semiconductor portion;
  • the display substrate further includes: a gate insulating layer located between the active layer and the gate;
  • the method further includes:
  • the forming the gate insulating layer includes:
  • a gate insulating film is formed.
  • the forming the gate includes:
  • the gate insulating film and the gate metal film are exposed, developed, and etched using the same mask to form the gate insulating layer and the gate.
  • the second capacitor electrode to be conductorized and the conductor to be conductor are performed The step of conducting the conduction by the chemical department;
  • the forming the gate further includes:
  • the photoresist on the gate is stripped.
  • the anode is also located in the non-light-emitting area
  • the display substrate further includes: a first connection electrode and a second connection electrode that are located between the second capacitor electrode and the anode and do not overlap each other , Source and drain;
  • the method further includes:
  • a patterning process is used to form the first connection electrode, the second connection electrode, the source electrode and the drain electrode that do not overlap each other.
  • the display substrate further includes: an interlayer dielectric layer located between the second capacitor electrode and the anode;
  • the method further includes:
  • the interlayer dielectric layer is located in the light-emitting area and the non-light-emitting area, and covers the second capacitor electrode, the gate and the active layer;
  • the first connection electrode is electrically connected to the first capacitor electrode through the first via hole
  • the first connection electrode is electrically connected to the active layer through the second via hole
  • the first connection electrode is electrically connected to the active layer through the second via hole.
  • the two connection electrodes are electrically connected to the gate through the fourth via hole
  • the second connection electrode is electrically connected to the second capacitor electrode through the fifth via hole.
  • the display substrate further includes: an insulating layer located between the anode and the interlayer dielectric layer;
  • the method further includes:
  • Forming the insulating layer which is located in the light-emitting area and the non-light-emitting area and covers at least the interlayer dielectric layer, the first connection electrode and the second connection electrode;
  • a third via hole penetrating the insulating layer is formed.
  • the forming the anode includes:
  • the anode is formed on the first insulating layer; wherein the anode is connected to the first connection electrode through the third via hole.
  • FIG. 1 is a schematic diagram of the structure of a display substrate provided by the related art
  • FIG. 2 is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of a 3T1C circuit provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic flow chart of a method for manufacturing a display substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram of yet another display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another display substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • words such as “first”, “second”, ... “fifth” are used to distinguish the same items or similar items that have substantially the same function and effect, and are only used to clearly describe the embodiments of the present disclosure.
  • the technical solution cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.
  • the array substrate of the top-gate AMOLED includes a substrate 10, a light shield 11, a buffer layer 12, and indium gallium zinc oxide (Indium Gallium Zinc Oxide) on the substrate 10 in sequence.
  • the Cst electrode 19 located between the source 17 and the drain 18 covers the insulating layer (PVX layer) 20 of the source 17, the drain 18 and the Cst electrode 19, and the ITO electrode 21 located on the PVX layer 20.
  • the Cst electrode and the ITO electrode are the two electrodes of the storage capacitor, and the PVX layer is the insulating medium between the two electrode plates.
  • the Cst electrode is located between the source and drain.
  • a very large facing area between the ITO electrode and the Cst electrode is required, which will inevitably lead to a larger area occupied by the TFT, that is, non-luminous
  • the occupied area of the area is increased, thereby reducing the occupied area of the light-emitting area, thereby greatly reducing the aperture ratio and affecting the display quality.
  • the active layer 13 includes a semiconductor portion 130 and a conductive portion 131 located on both sides of the semiconductor portion 130; of course, the array substrate also includes a color filter 22, a resin layer (Resin) 23 and other film structures, I won't repeat it here.
  • the array substrate also includes a color filter 22, a resin layer (Resin) 23 and other film structures, I won't repeat it here.
  • An embodiment of the present disclosure provides a display substrate, which includes a display area, and the display area includes a plurality of light-emitting areas arranged in an array and a non-light-emitting area located between adjacent light-emitting areas.
  • the display substrate further includes:
  • the first capacitor electrode 32 at least a part of the first capacitor electrode 32 is located in the light-emitting area (not marked in FIG. 2).
  • the buffer layer 33 covers the first capacitor electrode 32 and is located in the light-emitting area and the non-light-emitting area (not marked in FIG. 2).
  • the second capacitor electrode 34 and the active layer 35 are disposed on the buffer layer 33 without overlapping each other, and the active layer 35 is located in the non-light emitting area.
  • the first capacitor electrode 32, the buffer layer 33 and the second capacitor electrode 34 form a storage capacitor.
  • the above-mentioned display substrates are mainly used in self-luminous organic light emitting diode (OLED) display panels, which can be applied to top-emitting OLED display panels or bottom-emitting OLEDs
  • OLED organic light emitting diode
  • the display panel is not limited here. If it is applied to a bottom-emitting OLED display panel, the materials of the first capacitor electrode, the buffer layer, and the second capacitor electrode are all light-transmitting materials. If it is applied to a top-emission OLED display panel, the transparency of the first capacitor electrode, the buffer layer, and the second capacitor electrode is not required.
  • the active area (AA) of the above-mentioned display substrate refers to the area used to realize display; the light-emitting area (also called the pixel opening area) refers to the area where the OLED unit is arranged.
  • the OLED unit includes the anode (Anode). ), organic light-emitting functional layer and cathode (Cathode); the non-light-emitting area refers to the area in the display area other than the light-emitting area.
  • a pixel defining layer and a pixel circuit unit can be provided, and the pixel circuit unit can include a thin film transistor ( Thin Film Transistor, TFT), gate line, data line, etc.
  • TFT Thin Film Transistor
  • the material of the above-mentioned first capacitor electrode may be metal or metal oxide (for example: ITO), etc.; due to the good light transmittance of ITO, the first capacitor electrode made of ITO can be used in bottom-emission OLED display panels.
  • the material of the buffer layer may be insulating oxide, nitride or oxynitride, which is not limited here.
  • the material of the above-mentioned second capacitor electrode is also not limited, and it is specifically determined according to actual conditions.
  • the above-mentioned buffer layer may include an insulating layer, and may also include multiple insulating layers, which need to be determined according to a specific process, which is not limited here.
  • the embodiments of the present disclosure and the drawings are described by taking the buffer layer including an insulating layer as an example.
  • the above-mentioned second capacitor electrode may all be located in the light-emitting area; or a part of it may be located in the light-emitting area and the other part in the non-light-emitting area, that is, the part of the second capacitor electrode located in the light-emitting area can extend to the non-light-emitting area.
  • the part of the second capacitor electrode located in the light-emitting area can extend to the non-light-emitting area.
  • the embodiments of the present disclosure and the drawings are all described by taking as an example that the second capacitor electrodes are all located in the light-emitting area.
  • the above-mentioned second capacitor electrode and the active layer can be formed by one patterning process (that is, arranged in the same layer), or can be formed by other methods (for example, printing), which is not limited here. In view of reducing the manufacturing cost, the former can be selected. At this time, the material of the second capacitor electrode and the material of the active layer are the same.
  • the embodiments of the present disclosure and the drawings are all described by taking this as an example.
  • the non-overlapping of the second capacitor electrode and the active layer means that the orthographic projection of the second capacitor electrode on the substrate of the display substrate and the orthographic projection of the active layer on the substrate of the display substrate have no overlapping area.
  • the material of the active layer is not limited here, it can be a metal oxide semiconductor, for example: IGZO, zinc oxide (ZnO) or zinc oxynitride (ZnON), etc. Among them, IGZO has better performance and is more widely used;
  • the material of the active layer may also be monocrystalline silicon, polycrystalline silicon, etc., which is not limited here, and specific needs are determined according to actual requirements.
  • the embodiments of the present disclosure and the drawings are all illustrated by taking the material of the active layer as a metal oxide as an example.
  • the metal oxide active layer generally includes a semiconductor part and a conductive part located on both sides of the semiconductor part and connected to the semiconductor part. In FIG.
  • the active layer 35 includes a semiconductor portion 350 (also called an Act portion), a conductive portion 351 (also called a conductive Act portion) located on the left side of the semiconductor portion 350, and a conductive portion 351 located on the right side of the semiconductor portion 350 (Also called the conductive Act part), at this time, the second capacitor electrode is a conductive metal oxide.
  • the display substrate further includes:
  • the gate 37 is located on the active layer 35 and insulated from the active layer 35 and is located in the non-light emitting area.
  • the second capacitor electrode 34 is electrically connected to the gate 37.
  • the anode 42 is located on the second capacitor electrode 34 and the gate 37 and insulated from the second capacitor electrode 34 and the gate 37. At least a part of the anode 42 is located in the light-emitting area.
  • the first capacitor electrode 32, the active layer 35 and the anode 42 The three are electrically connected.
  • the material of the above-mentioned gate is also not limited, and can be made of metals or metal alloys, for example: Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • the material of the above anode is also not limited, and it is generally made of ITO.
  • the first capacitor electrode and the second capacitor electrode respectively serve as two electrodes of the storage capacitor
  • the buffer layer serves as an insulating medium between the two electrode plates, and the three together form the storage capacitor.
  • the second capacitor electrode and the active layer do not overlap each other.
  • the second capacitor electrode is located in the light-emitting area and arranged outside the thin film transistor, which reduces the area occupied by the thin film transistor and thereby reduces the non-light-emitting area The area, thereby increasing the aperture ratio.
  • the relative area of the second capacitor electrode and the first capacitor electrode is proportional to the capacitance value of the storage capacitor. Therefore, to increase the capacitance value of the storage capacitor, it can be achieved by increasing the relative area of the second capacitor electrode and the first capacitor electrode, specifically by increasing the area of the second capacitor electrode in the light-emitting area. That is, increasing the capacitance value of the storage capacitor will not increase the area of the non-light-emitting area, thereby further increasing the aperture ratio.
  • the above-mentioned display substrate provides a storage capacitor design structure. While ensuring that the storage capacitor is large enough, the occupied area of the TFT is reduced as much as possible, thereby reducing the area of the non-light-emitting area, thereby significantly increasing the aperture ratio. Significantly improve the display quality of the product.
  • the first capacitor electrode is also located in the non-light-emitting area
  • the second capacitor electrode is located in the light-emitting area
  • the anode is also located in the non-light-emitting area
  • the material of the active layer is metal oxide, such as: IGZO, zinc oxide (ZnO) or Zinc oxynitride (ZnON) and so on.
  • the above-mentioned display substrate further includes:
  • the interlayer dielectric layer 38 is located between the second capacitor electrode 34 and the anode 42.
  • the interlayer dielectric layer 38 is located in the light-emitting area and the non-light-emitting area, and covers the second capacitor electrode 34, the gate 37 and the active layer 35.
  • the first connecting electrode 40 and the second connecting electrode 39 are located between the interlayer dielectric layer 38 and the anode 42 and do not overlap each other.
  • the first capacitor electrode 32, the active layer 35 and the anode 42 are electrically connected by the first connecting electrode 40
  • the second capacitor electrode 34 and the gate 37 are electrically connected through the second connection electrode 39.
  • the above-mentioned interlayer dielectric layer is an inorganic insulating layer, which can insulate and protect the gate and the active layer.
  • the material is not limited, and may be oxide, nitride, or oxynitride.
  • first connection electrode and second connection electrode do not overlap each other means that the orthographic projection of the first connection electrode on the substrate of the display substrate and the orthographic projection of the second connection electrode on the substrate of the display substrate have no overlapping area. There are no restrictions on the shape, material, and position distribution of the first connection electrode and the second connection electrode.
  • the above-mentioned display substrate realizes the electrical connection of the first capacitor electrode, the active layer and the anode by arranging the first connection electrode, and realizes the electric connection between the second capacitor electrode and the gate electrode by arranging the second connection electrode.
  • This structure is simple and easy to realize.
  • the display substrate further includes:
  • the insulating layer (PVX layer) 41 located between the anode 42 and the interlayer dielectric layer 38.
  • the insulating layer 41 is located in the light-emitting area and the non-light-emitting area, and covers at least the interlayer dielectric layer 38, the first connecting electrode 40 and the second connecting electrode 39.
  • the first via hole (CNT via hole, not marked in FIG. 2), the first via hole penetrates the interlayer dielectric layer 38 and the buffer layer 33, and the first connection electrode 40 is electrically connected to the first capacitor electrode 32 through the first via hole.
  • the second via hole (not marked in FIG. 2), the second via hole penetrates the interlayer dielectric layer 38, and the first connection electrode 40 is electrically connected to the active layer 35 through the second via hole.
  • the third via hole (PVX via hole, not marked in FIG. 2), the third via hole penetrates the insulating layer, and the first connection electrode is electrically connected to the anode through the third via hole.
  • the above-mentioned second via hole only penetrates the interlayer dielectric layer and belongs to an ILD via hole.
  • At least a part of the first connection electrode is located in the non-light-emitting area means that the first connection electrode may be all located in the non-light-emitting area; Part of the area may extend to the light-emitting area.
  • the first connection electrode may be all located in the non-light-emitting area; Part of the area may extend to the light-emitting area.
  • the specific positions of the first via hole, the second via hole and the third via hole are not limited here. If the first connection electrode is located in the non-light-emitting area, in order to simplify the structure, the first via hole, the second via hole, and the third via hole are arranged in the non-light-emitting area as an example for drawing; in this case, the first connection electrode The first via hole is in direct contact with the portion of the first capacitor electrode in the non-light-emitting area, thereby achieving electrical connection between the first connection electrode and the first capacitor electrode; the first connection electrode is conductive to the active layer through the second via hole
  • the part located on the right side of the semiconductor part) is in direct contact to realize the electrical connection between the first connection electrode and the active layer; Connect the electrical connection of the electrode and the anode. It should be noted that, FIG. 2 shows an example in which the material of the active layer is a metal oxide.
  • the above-mentioned insulating layer also covers the source and drain.
  • the above-mentioned display substrate realizes the electrical connection between the first connection electrode and the first capacitor electrode, the electrical connection between the first connection electrode and the active layer, the first connection electrode and the The anode is electrically connected, thereby realizing the electrical connection of the first capacitor electrode, the active layer and the anode.
  • the structure design is simple and easy to implement.
  • the thickness of the part used to form the storage capacitor in the buffer layer is smaller than the thickness of the part used to cover the storage capacitor in the interlayer dielectric layer.
  • the buffer layer is located between the first capacitor electrode and the second capacitor electrode. Since the buffer layer has less influence on the yield, the thickness of the film can be made smaller; and the capacitance value of the storage capacitor is the distance between the two electrodes ( That is, the thickness of the part used to form the storage capacitor in the buffer layer is negatively correlated. Therefore, thinning the thickness of the part used to form the storage capacitor in the buffer layer can significantly improve the storage capacity of the capacitor, which is more conducive to the display effect. promote.
  • the gate and gate wiring are arranged on the same layer, the data wiring and the source and drain are arranged on the same layer, and the interlayer dielectric layer is located between the two layers; in order to prevent the gate wiring (Gate wiring) and There is a risk of short circuits between data traces (Data traces), and the interlayer dielectric layer needs to be made particularly thick.
  • the second connecting electrode is located in the light-emitting area and the non-light-emitting area; the display substrate further includes:
  • the fourth via hole (not marked in FIG. 2), the fourth via hole penetrates the interlayer dielectric layer 38, and the second connection electrode 39 is electrically connected to the gate 37 through the fourth via hole.
  • the fifth via hole (not marked in FIG. 2), the fifth via hole penetrates the interlayer dielectric layer 38, and the second connection electrode 39 is electrically connected to the second capacitor electrode 34 through the fifth via hole.
  • the fourth via and the fifth via only penetrate the interlayer dielectric layer, and both belong to ILD vias.
  • the specific positions of the fourth via hole and the fifth via hole are not limited here.
  • the fourth via hole in FIG. 2 is arranged above the side of the gate close to the second connection electrode, and the fifth via hole is arranged on the second capacitor electrode close to the first connection electrode. 2. Connect the upper side of the electrode.
  • the above-mentioned display substrate is provided with a fourth via hole and a fifth via hole to realize electrical connection between the second connection electrode and the gate electrode, and the second connection electrode and the second capacitor electrode respectively, thereby realizing the electrical connection between the second connection electrode and the gate electrode.
  • This kind of structure design is simple and easy to realize.
  • the display substrate further includes:
  • the source and drain are located between the interlayer dielectric layer and the anode.
  • the source, the drain, the first connection electrode and the second connection electrode are arranged in the same layer and do not overlap each other, and the source and drain are both located in the non-luminous area , And are respectively electrically connected to the active layer.
  • the source electrode and the drain electrode are respectively electrically connected to the active layer.
  • the active layer is a metal oxide active layer
  • the source electrode and the drain electrode can be electrically connected to the conductive part of the respective active layer through the via hole penetrating the interlayer dielectric layer; at this time, the gate, The source electrode, the drain electrode and the active layer form a top-gate metal oxide thin film transistor.
  • the source electrode, the drain electrode, the first connection electrode and the second connection electrode in the same layer means that the source electrode, the drain electrode, the first connection electrode and the second connection electrode are formed by one patterning process.
  • the above-mentioned source, drain, first connection electrode and second connection electrode do not overlap each other means that the source, drain, first connection electrode and second connection electrode respectively have the same orthographic projections on the substrate of the display substrate. There is no overlapping area.
  • the 3T1C structure used in the circuit design of the above display substrate can be referred to as shown in FIG.
  • the storage capacitor, the first capacitor electrode and the second capacitor electrode are used as the two electrodes of the storage capacitor, and the buffer layer is used as the insulating medium between the two electrode plates, and the above-mentioned thin film transistor can be used as a T3 drive tube.
  • the first capacitor electrode is also located in the non-light-emitting area; the display substrate further includes:
  • the light shielding layer can block external light from irradiating the active layer, thereby protecting the active layer and extending the life of the thin film transistor.
  • the light-shielding layer is arranged between the substrate and the first capacitor electrode, and the part of the first capacitor electrode located in the non-light-emitting area can protect the light-shielding layer to avoid damage to the light-shielding layer caused by subsequent etching processes, which greatly improves The process suitability is improved.
  • the embodiments of the present disclosure provide a display panel, which includes the display substrate provided in the above-mentioned embodiments.
  • the display panel has a high aperture ratio, good display effect, and high product quality.
  • the display panel can be a display device such as an OLED display, and any product or component with a display function, such as a TV, a digital camera, a mobile phone, a tablet computer, and the like including these display devices.
  • the embodiments of the present disclosure provide a method for preparing a display substrate as in the above embodiments.
  • the display substrate includes a display area, and the display area includes a plurality of light-emitting areas arranged in an array and a non-light-emitting area located between adjacent light-emitting areas.
  • the method includes:
  • a first capacitor electrode is formed, and at least a part of the first capacitor electrode is located in the light-emitting area.
  • a patterning process may be used to form the first capacitor electrode on the substrate.
  • the material of the first capacitor electrode may be metal or metal oxide (for example: ITO) or the like.
  • a buffer layer is formed.
  • the buffer layer covers the first capacitor electrode and is located in the light-emitting area and the non-light-emitting area.
  • the material of the buffer layer may be insulating oxide, nitride or oxynitride, which is not limited here.
  • a second capacitor electrode and an active layer that do not overlap each other are formed on the buffer layer, the second capacitor electrode is located in the light-emitting area, and the active layer is located in the non-light-emitting area.
  • the second capacitor electrode and the active layer can be formed on the buffer layer by one patterning process; of course, other methods (such as printing) can also be used for manufacturing, which is not limited here.
  • the first capacitor electrode, the buffer layer and the second capacitor electrode form a storage capacitor.
  • the method further includes:
  • a gate is formed, the gate is located on the active layer and in the non-light emitting area, and the second capacitor electrode is electrically connected to the gate.
  • the material of the gate can be made of metal or metal alloy, for example: Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • An anode is formed.
  • the anode is located on the second capacitor electrode and the gate and at least a part is located in the light-emitting area, and the first capacitor electrode, the active layer and the anode are electrically connected.
  • the first capacitor electrode and the second capacitor electrode respectively serve as the two electrodes of the storage capacitor
  • the buffer layer serves as the insulating medium between the two electrode plates, and the three together form the storage capacitor.
  • the second capacitor electrode and the active layer do not overlap each other.
  • the second capacitor electrode is located in the light-emitting area and arranged outside the thin film transistor, which reduces the area occupied by the thin film transistor and thereby reduces the non-light-emitting area The area, thereby increasing the aperture ratio.
  • the embodiments of the present disclosure provide a method for preparing a display substrate.
  • the display substrate formed by the method provides a storage capacitor design structure, which reduces the occupied area of the TFT as much as possible while ensuring that the storage capacitor is large enough , Thereby significantly improving the aperture ratio, and thus greatly improving the display quality of the product.
  • the preparation method is simple and easy to realize.
  • the material of the above-mentioned active layer is a metal oxide, for example: IGZO, zinc oxide (ZnO) or zinc oxynitride (ZnON), etc.; then, S03, a second non-overlapping second layer is formed on the buffer layer
  • the capacitor electrode and the active layer include:
  • the active layer to be conductive includes a semiconductor part and is located on both sides of the semiconductor part. And the part to be conductorized connected to the semiconductor part.
  • S302 Conducting the second capacitor electrode to be conductorized and the portion to be conductorized to form a second capacitor electrode and an active layer. Conduction refers to the use of particles such as H and He to bombard the part to be conductive.
  • the above display substrate further includes: a gate insulating layer located between the active layer and the gate; then, before S04, forming the gate, the above method further includes:
  • a gate insulating layer is formed, and the gate insulating layer is located on the active layer.
  • Forming a gate insulating layer includes: forming a gate insulating film.
  • a plasma-enhanced chemical vapor deposition (PECVD) method may be used to deposit a gate insulating film on the active layer, and the material of the gate insulating film may be oxide, nitride, or oxynitride.
  • PECVD plasma-enhanced chemical vapor deposition
  • Forming a gate includes:
  • the gate insulating layer and the gate By manufacturing the gate insulating layer and the gate by the above method, a mask can be saved, the number of patterning can be reduced, and the cost and production time can be reduced. It should be noted that when fabricating the gate insulating layer and the gate, the gate insulating layer and the gate can also be etched by a self-aligned process to improve the fabrication accuracy.
  • the second capacitor electrode to be conductorized and the portion to be conductorized are conductorized A step of.
  • the semiconductor part of the active layer is protected from influence due to the protective effect of the gate insulating layer and the gate.
  • Forming a gate further includes:
  • the second capacitor electrode to be conductorized and the portion to be conductorized are conductorized, S404, the photoresist on the gate is stripped. In this way, when conducting conductorization, the gate is protected from influence due to the protective effect of the photoresist.
  • the anode is also located in the non-light-emitting area
  • the display substrate further includes: a first connection electrode, a second connection electrode, a source electrode and a drain electrode that are located between the second capacitor electrode and the anode and do not overlap each other.
  • the above method further includes:
  • a patterning process is used to form a first connection electrode, a second connection electrode, a source electrode and a drain electrode that do not overlap each other. This can reduce the number of composition and reduce costs.
  • the display substrate further includes: an interlayer dielectric layer located between the second capacitor electrode and the anode.
  • the above method further includes:
  • the interlayer dielectric layer is located in the light-emitting area and the non-light-emitting area, and covers the second capacitor electrode, the gate electrode and the active layer.
  • the material of the interlayer dielectric layer is not limited, and it may be oxide, nitride, or oxynitride compound.
  • the first connection electrode is electrically connected to the first capacitor electrode through the first via hole
  • the first connection electrode is electrically connected to the active layer through the second via hole
  • the second connection electrode is electrically connected to the gate electrode through the fourth via hole.
  • the second connection electrode is electrically connected to the second capacitor electrode through the fifth via hole.
  • the display substrate formed by the above preparation method can realize the electrical connection between the first capacitor electrode and the active layer, and the electrical connection between the second capacitor electrode and the gate. This method is simple and easy to implement.
  • the display substrate further includes: an insulating layer located between the anode and the interlayer dielectric layer.
  • the above method further includes:
  • An insulating layer is formed.
  • the insulating layer is located in the light-emitting area and the non-light-emitting area and covers at least the interlayer dielectric layer, the first connection electrode and the second connection electrode. It should be noted that the source electrode, the drain electrode, the first connection electrode and the second connection electrode are arranged in the same layer, and the insulating layer also covers the source electrode and the drain electrode.
  • Forming the anode includes:
  • An anode is formed on the first insulating layer; wherein the anode is connected to the first connection electrode through a third via hole.
  • the display substrate formed by the above preparation method can further realize the connection between the anode and the first connection electrode, thereby realizing the electrical connection of the first capacitor electrode, the active layer and the anode. This method is simple and easy to implement.
  • the active layer of the display substrate is a metal oxide active layer, which includes a semiconductor portion, a conductive portion located on the left side of the semiconductor portion, and a conductive portion located on the right side of the semiconductor portion.
  • the display substrate shown in FIG. 2 is applied to a bottom emission display panel.
  • the preparation method includes:
  • a substrate is formed, and the substrate is a light-transmissive material, such as glass and other materials.
  • a light-shielding layer is formed on the substrate, and the light-shielding layer is located in a non-light-emitting area.
  • the active layer to be conductive includes a semiconductor part and is located on both sides of the semiconductor part. And the part to be conductorized connected to the semiconductor part. Wherein, the projection of the active layer on the substrate is within the projection of the light shielding layer on the substrate.
  • the second capacitor electrode to be conductive and the portion to be conductive are conductive.
  • An interlayer dielectric layer is formed.
  • the interlayer dielectric layer is located in the light-emitting area and the non-light-emitting area, and covers the second capacitor electrode, the gate electrode and the active layer.
  • the first connection electrode is electrically connected to the first capacitor electrode through the first via hole
  • the first connection electrode is electrically connected to the active layer through the second via hole
  • the second connection electrode is electrically connected to the gate through the fourth via hole
  • the second The connection electrode is electrically connected to the second capacitor electrode through the fifth via hole.
  • An insulating layer is formed.
  • the insulating layer is located in the light-emitting area and the non-light-emitting area and covers the interlayer dielectric layer, the first connection electrode, the second connection electrode, the source electrode and the drain electrode.
  • An anode is formed on the insulating layer, the anode is located in the light-emitting area and the non-light-emitting area, and is connected to the first connection electrode through the third via hole.
  • the display substrate as shown in FIG. 2 is formed.
  • the above preparation method further includes:
  • any reference signs placed between parentheses should not be constructed as a limitation to the claims.
  • the word “comprising” does not exclude the presence of elements or steps not listed in the claims.
  • the word “a” or “an” preceding an element does not exclude the presence of multiple such elements.
  • the present disclosure can be realized by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims listing several devices, several of these devices may be embodied in the same hardware item. The use of the words first, second, and third, etc. do not indicate any order. These words can be interpreted as names.

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Abstract

显示基板及其制备方法、显示面板。显示基板包括：第一电容电极，至少一部分位于发光区；缓冲层，覆盖第一电容电极；第二电容电极和有源层,互不交叠设置于缓冲层之上，有源层位于非发光区；其中，第一电容电极、缓冲层和第二电容电极形成存储电容。

Description

显示基板及其制备方法、显示面板
相关申请的交叉引用
本公开要求在2020年02月17日提交中国专利局、申请号为202010097583.X、名称为“一种显示基板及其制备方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示面板。
背景技术
顶栅型薄膜晶体管(Thin Film Transistor，TFT)具有短沟道的特点，其开态电流得以有效提升，从而显著提高显示效果并且能有效降低功耗。另外，顶栅型TFT的栅极与源漏极重叠面积小，因而产生的寄生电容较小，所以发生栅极和漏极短路等不良的可能性也有效降低。由于顶栅型TFT具有上述显著优点，所以越来越受到人们的关注。
在顶栅型有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)产品电路设计中，经常采用3T1C结构。具体的，采用氧化铟锡(Indium Tin Oxide，ITO)电极和Cst电极形成存储电容。其中，ITO电极为ITO阳极延伸到非发光区的部分，Cst电极与TFT的源漏极(SD极)金属层同层设置、且位于源极(S极)金属电极和漏极(D极)金属电极之间。而为了使得存储电容足够大以确保发光层(Emitting layer，EL)有足够长的发光时间，需要ITO电极和Cst电极之间有非常大的正对面积。
概述
本公开的实施例提供一种显示基板及其制备方法、显示面板，该显示基板提供了一种存储电容设计结构。
为达到上述目的，本公开的实施例采用如下技术方案：
一方面，提供了一种显示基板，包括显示区，所述显示区包括阵列排布的多个发光区和位于相邻所述发光区之间的非发光区；
所述显示基板还包括：
第一电容电极，所述第一电容电极至少一部分位于所述发光区；
缓冲层，所述缓冲层覆盖所述第一电容电极、且位于所述发光区和所述非发光区；
第二电容电极和有源层,互不交叠设置于所述缓冲层之上，所述有源层位于所述非发光区；
其中，所述第一电容电极、所述缓冲层和所述第二电容电极形成存储电容。
可选地，所述显示基板还包括：
栅极，位于所述有源层之上与所述有源层绝缘、且位于所述非发光区，所述第二电容电极与所述栅极电连接；
阳极，位于所述第二电容电极和所述栅极之上、且与所述第二电容电极及所述栅极绝缘，所述阳极至少一部分位于所述发光区，所述第一电容电极、所述有源层和所述阳极三者电连接。
可选地，所述第一电容电极还位于所述非发光区，所述第二电容电极位于所述发光区，所述阳极还位于所述非发光区，所述有源层的材料为金属氧化物；
所述显示基板还包括：
位于所述第二电容电极和所述阳极之间的层间介质层，所述层间介质层位于所述发光区和所述非发光区，且覆盖所述第二电容电极、所述栅极和所述有源层。
可选地，所述显示基板还包括：
位于所述层间介质层和所述阳极之间且互不交叠的第一连接电极和第二连接电极，所述第一电容电极、所述有源层和所述阳极通过所述第一连接电极电连接，所述第二电容电极和所述栅极通过所述第二连接电极电连接。
可选地，所述第一连接电极至少一部分位于所述非发光区；
所述显示基板还包括：
位于所述阳极和所述层间介质层之间的绝缘层，所述绝缘层位于所述发光区和所述非发光区，且至少覆盖所述层间介质层、所述第一连接电极和所述第二连接电极。
可选地，所述显示基板还包括：
第一过孔，所述第一过孔贯穿所述层间介质层和所述缓冲层，所述第一连接电极通过所述第一过孔与所述第一电容电极电连接；
第二过孔，所述第二过孔贯穿所述层间介质层，所述第一连接电极通过所述第二过孔与所述有源层电连接；
第三过孔，所述第三过孔贯穿所述绝缘层，所述第一连接电极通过所述第三过孔与所述阳极电连接。
可选地，所述缓冲层中用于形成所述存储电容的部分的厚度小于所述层间介质层中用于覆盖所述存储电容的部分的厚度。
可选地，所述第二连接电极位于所述发光区和所述非发光区；
所述显示基板还包括：
第四过孔，所述第四过孔贯穿所述层间介质层，所述第二连接电极通过所 述第四过孔与所述栅极电连接；
第五过孔，所述第五过孔贯穿所述层间介质层，所述第二连接电极通过所述第五过孔与所述第二电容电极电连接。
可选地，所述第四过孔设置于所述栅极靠近所述第二连接电极一侧的上方，所述第五过孔设置于所述第二电容电极靠近所述第二连接电极一侧的上方。
可选地，所述显示基板还包括：
位于所述层间介质层和所述阳极之间的源极和漏极，所述源极、所述漏极、所述第一连接电极和所述第二连接电极同层设置且互不交叠，所述源极和所述漏极均位于所述非发光区、且分别与所述有源层电连接。
可选地，所述第一电容电极还位于所述非发光区；
所述显示基板还包括：
衬底；
位于所述衬底和所述第一电容电极之间的遮光层，所述遮光层位于非发光区，所述有源层在所述衬底上的投影位于所述遮光层在所述衬底上的投影以内，且所述第一电容电极覆盖所述遮光层。
本公开的实施例提供了一种显示基板，该显示基板包括显示区，所述显示区包括阵列排布的多个发光区和位于相邻所述发光区之间的非发光区；所述显示基板还包括：第一电容电极，所述第一电容电极至少一部分位于所述发光区；缓冲层，所述缓冲层覆盖所述第一电容电极、且位于所述发光区和所述非发光区；第二电容电极和有源层,互不交叠设置于所述缓冲层之上，所述有源层位于所述非发光区；其中，所述第一电容电极、所述缓冲层和所述第二电容电极形成存储电容。
相关技术另一方面，提供了一种显示面板，包括上述所述的显示基板。
再一方面，提供了一种如上述所述的显示基板的制备方法，所述显示基板包括显示区，所述显示区包括阵列排布的多个发光区和位于相邻所述发光区之间的非发光区；
所述方法包括：
形成第一电容电极，所述第一电容电极至少一部分位于所述发光区；
形成缓冲层，所述缓冲层覆盖所述第一电容电极、且位于所述发光区和所述非发光区；
在所述缓冲层之上形成互不交叠的第二电容电极和有源层，所述有源层位于所述非发光区；
其中，所述第一电容电极、所述缓冲层和所述第二电容电极形成存储电容。
可选地，所述方法还包括：
形成栅极，所述栅极位于所述有源层之上、且位于所述非发光区，所述第 二电容电极与所述栅极电连接；
形成阳极，所述阳极位于所述第二电容电极和所述栅极之上且至少一部分位于所述发光区，所述第一电容电极、所述有源层和所述阳极三者电连接。
可选地，所述第二电容电极位于所述发光区，所述有源层的材料为金属氧化物；
所述在所述缓冲层之上形成互不交叠的第二电容电极和有源层包括：
采用一次构图工艺在所述缓冲层之上形成互不交叠的待导体化的第二电容电极和待导体化的有源层，所述待导体化的有源层包括半导体部、位于所述半导体部两侧且与所述半导体部相接的待导体化部；
对所述待导体化的第二电容电极和所述待导体化部进行导体化，形成所述第二电容电极和所述有源层。
可选地，所述显示基板还包括：位于所述有源层和所述栅极之间的栅绝缘层；
在所述形成栅极之前，所述方法还包括：
形成栅绝缘层，所述栅绝缘层位于所述有源层之上；
所述形成栅绝缘层包括：
形成栅绝缘薄膜。
可选地，所述形成所述栅极包括：
在所述栅绝缘薄膜之上形成栅金属薄膜；
在所述栅金属薄膜之上涂覆光刻胶；
采用同一掩膜板对所述栅绝缘薄膜和所述栅金属薄膜进行曝光、显影、刻蚀，形成所述栅绝缘层和所述栅极。
可选地，在采用同一掩膜板对所述栅绝缘薄膜和所述栅金属薄膜进行曝光、显影、刻蚀的步骤之后，执行对所述待导体化的第二电容电极和所述待导体化部进行导体化的步骤；
所述形成所述栅极还包括：
在对所述待导体化的第二电容电极和所述待导体化部进行导体化之后，剥离所述栅极上的光刻胶。
可选地，所述阳极还位于所述非发光区，所述显示基板还包括：位于所述第二电容电极和所述阳极之间且互不交叠的第一连接电极、第二连接电极、源极和漏极；
在形成所述栅极之后、且在形成所述阳极之前，所述方法还包括：
采用一次构图工艺形成互不交叠的所述第一连接电极、所述第二连接电极、所述源极和所述漏极。
可选地，所述显示基板还包括：位于所述第二电容电极和所述阳极之间的层间介质层；
在形成所述栅极之后、且在形成所述第一连接电极和所述第二连接电极之前，所述方法还包括：
形成所述层间介质层，所述层间介质层位于所述发光区和所述非发光区，且覆盖所述第二电容电极、所述栅极和所述有源层；
形成贯穿所述层间介质层和所述缓冲层的第一过孔,以及贯穿所述层间介质层的第二过孔、第四过孔和第五过孔；
其中，所述第一连接电极通过所述第一过孔与所述第一电容电极电连接，所述第一连接电极通过所述第二过孔与所述有源层电连接，所述第二连接电极通过所述第四过孔与所述栅极电连接，所述第二连接电极通过所述第五过孔与所述第二电容电极电连接。
可选地，所述显示基板还包括：位于所述阳极和所述层间介质层之间的绝缘层；
在形成所述第一连接电极和所述第二连接电极之后、且在形成所述阳极之前，所述方法还包括：
形成所述绝缘层，所述绝缘层位于所述发光区和所述非发光区，且至少覆盖所述层间介质层、所述第一连接电极和所述第二连接电极；
形成贯穿所述绝缘层的第三过孔。
可选地，所述形成阳极包括：
在所述第一绝缘层之上形成所述阳极；其中，所述阳极通过所述第三过孔与所述第一连接电极连接。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术提供的一种显示基板的结构示意图；
图2为本公开实施例提供的一种显示基板的结构示意图；
图3为本公开实施例提供的一种3T1C的电路示意图；
图4为本公开实施例提供的一种显示基板的制备方法的流程示意图；
图5为本公开实施例提供的又一种显示基板的结构示意图；
图6为本公开实施例提供的另一种显示基板的结构示意图；并且
图7为本公开实施例提供的再一种显示基板的结构示意图。
详细描述
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的实施例中，采用“第一”、“第二”、……“第五”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本公开实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
相关技术中，参考图1所示，顶栅型AMOLED的阵列基板包括衬底10，依次位于衬底10之上的遮光层(Light Shield)11、缓冲层12、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)有源层13、栅绝缘层14、栅极15、层间介质层16，在层间介质层16之上的源极(S极)17、漏极(D极)18、位于源极17和漏极18之间的Cst电极19，覆盖源极17、漏极18、Cst电极19的绝缘层(PVX层)20，位于PVX层20之上的ITO电极21。其中，Cst电极和ITO电极分别为存储电容的两个电极、PVX层为两极板间的绝缘介质。Cst电极位于源极和漏极之间，若要提高存储电容的电容值，则需要ITO电极和Cst电极之间有非常大的正对面积，这必然导致TFT的占用面积变大，即非发光区的占用面积增大，从而减小了发光区的占用面积，进而极大降低了开口率，影响显示质量。图1中,有源层13包括半导体部130和位于半导体部130两侧的导体化部131；当然，该阵列基板还包括彩色滤光片22、树脂层(Resin)23等其它膜层结构，这里不再赘述。
本公开实施例提供了一种显示基板，该显示基板包括显示区，所述显示区包括阵列排布的多个发光区和位于相邻发光区之间的非发光区。
参考图2所示，显示基板还包括：
第一电容电极32，第一电容电极32至少一部分位于发光区(图2未标记)。
缓冲层33，缓冲层33覆盖第一电容电极32、且位于发光区和非发光区(图2未标记)。
第二电容电极34和有源层35,互不交叠设置于缓冲层33之上，有源层位35于非发光区。
其中，第一电容电极32、缓冲层33和第二电容电极34形成存储电容。
上述显示基板(还可称阵列基板)主要应用于自发光的有机发光二极管(Organic Light Emitting Diode，OLED)显示面板中，其可以应用在顶发射的OLED显示面板，也可以应用在底发射的OLED显示面板，这里不做限定。 若应用在底发射的OLED显示面板，则要求第一电容电极、缓冲层、第二电容电极的材料均为透光材料。若应用在顶发射的OLED显示面板，则对第一电容电极、缓冲层、第二电容电极的透光性不做要求。
上述显示基板的显示区(Active Area，AA)是指用于实现显示的区域；发光区(又称像素开口区)是指设置有OLED单元的区域，根据相关技术可知，OLED单元包括阳极(Anode)、有机发光功能层和阴极(Cathode)；非发光区是指显示区中除发光区以外的区域，在该区域，可以设置像素界定层、像素电路单元，该像素电路单元可以包括薄膜晶体管(Thin Film Transistor，TFT)、栅线、数据线等。
上述第一电容电极的材料可以是金属或者金属氧化物(例如：ITO)等；由于ITO透光性好，采用ITO制作的第一电容电极可应用在底发射的OLED显示面板中。上述缓冲层的材料可以是绝缘的氧化物、氮化物或者氧氮化合物，这里不做限定。上述第二电容电极的材料也不做限定，具体根据实际而定。
上述缓冲层可以包括一层绝缘层，还可以包括多层绝缘层，具体需要根据具体工艺确定，这里不做限定。本公开实施例以及附图均以缓冲层包括一层绝缘层为例进行说明。
上述第二电容电极可以全部位于发光区；也可以一部分位于发光区，另一部分位于非发光区，即第二电容电极位于发光区的部分可延伸至非发光区。这里不做限定，具体可以根据实际设置。本公开实施例以及附图均以第二电容电极全部位于发光区为例进行说明。
上述第二电容电极和有源层可以通过一次构图工艺形成(即同层设置)，也可以采用其它方式(例如：打印)形成，这里不做限定。考虑到降低制作成本，可以选择前者，此时，第二电容电极的材料和有源层的材料相同，本公开实施例以及附图均以此为例进行说明。第二电容电极和有源层互不交叠是指第二电容电极在显示基板的衬底上的正投影和有源层在显示基板的衬底上的正投影没有重叠区域。
这里对有源层的材料不做限定，其可以是金属氧化物半导体，例如：IGZO、氧化锌(ZnO)或氮氧化锌(ZnON)等，其中，IGZO的性能较好，应用更为广泛；有源层的材料还可以是单晶硅、多晶硅等，这里不做限定，具体需要根据实际要求而定。本公开实施例以及附图均以有源层的材料为金属氧化物为例进行绘示。金属氧化物有源层一般包括半导体部、位于半导体部两侧且与半导体部相接的导体化部。图2中，有源层35包括半导体部350(又称Act部)、位于半导体部350左侧的导体化部351(又称导体化Act部)和位于半导体部350右侧的导体化部351(又称导体化Act部)，此时，第二电容电极为导体化的金属氧化物。
可选地，所述显示基板还包括：
栅极37，位于有源层35之上与有源层35绝缘、且位于非发光区，第二电容电极34与栅极37电连接。
阳极42，位于第二电容电极34和栅极37之上、且与第二电容电极34及栅极37绝缘，阳极42至少一部分位于发光区，第一电容电极32、有源层35和阳极42三者电连接。
上述栅极的材料也不做限定，可采用金属或者金属合金制作，例如：Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。上述阳极的材料也不做限定，一般采用ITO制作。
上述显示基板中，第一电容电极、第二电容电极分别作为存储电容的两个电极，缓冲层作为两极板间的绝缘介质，三者共同形成存储电容。第二电容电极与有源层互不交叠，相较于相关技术，第二电容电极位于发光区且设置在薄膜晶体管的外部，减小了薄膜晶体管的占用面积，进而减小了非发光区的面积，从而提高了开口率。
另外，由于第二电容电极和第一电容电极的相对面积与存储电容的电容值呈正比。因此，若要增大存储电容的电容值，可以通过增大第二电容电极和第一电容电极的相对面积实现，具体可以通过增加第二电容电极位于发光区的面积来实现。即增大存储电容的电容值不会增大非发光区的面积，从而进一步提高了开口率。
综上，上述显示基板提供了一种存储电容设计结构，在保证存储电容足够大的同时，尽可能地减小TFT的占用面积，从而减小非发光区的面积，进而显著提升了开口率，大幅提升了产品的显示质量。
可选地，上述第一电容电极还位于非发光区，第二电容电极位于发光区，阳极还位于非发光区，有源层的材料为金属氧化物，例如：IGZO、氧化锌(ZnO)或氮氧化锌(ZnON)等。
参考图2所示，上述显示基板还包括：
位于第二电容电极34和阳极42之间的层间介质层38，层间介质层38位于发光区和非发光区，且覆盖第二电容电极34、栅极37和有源层35。
位于层间介质层38和阳极42之间且互不交叠的第一连接电极40和第二连接电极39，第一电容电极32、有源层35和阳极42通过第一连接电极40电连接，第二电容电极34和栅极37通过第二连接电极39电连接。
上述层间介质层(ILD层)属于无机绝缘层，可以起到绝缘和保护栅极、有源层的作用，其材料不做限定，可以是氧化物、氮化物或者氧氮化合物等。
上述第一连接电极和第二连接电极互不交叠是指第一连接电极在显示基板的衬底上的正投影和第二连接电极在显示基板的衬底上的正投影没有重叠区域。这里对于第一连接电极和第二连接电极的形状、材料、位置分布均不作限定。
上述显示基板通过设置第一连接电极实现第一电容电极、有源层和阳极三者电连接，通过设置第二连接电极实现第二电容电极与栅极电连接，该种结构简单易实现。
可选地，参考图2所示，第一连接电极至少一部分位于非发光区；该显示基板还包括：
位于阳极42和层间介质层38之间的绝缘层(PVX层)41，绝缘层41位于发光区和非发光区，且至少覆盖层间介质层38、第一连接电极40和第二连接电极39。
第一过孔(CNT过孔，图2未标记)，第一过孔贯穿层间介质层38和缓冲层33，第一连接电极40通过第一过孔与第一电容电极32电连接。
第二过孔(图2未标记)，第二过孔贯穿层间介质层38，第一连接电极40通过第二过孔与有源层35电连接。
第三过孔(PVX过孔，图2未标记)，第三过孔贯穿绝缘层，第一连接电极通过第三过孔与阳极电连接。
上述第二过孔仅贯穿层间介质层，属于ILD过孔。
上述第一连接电极至少一部分位于非发光区是指：上述第一连接电极可以是全部位于非发光区；也可以是一部分位于非发光区、另一部分位于发光区，即第一连接电极位于非发光区的部分可延伸至发光区。这里不做限定，具体可以根据实际设置。本公开实施例以及附图均以第一连接电极全部位于非发光区为例进行说明。
这里对于第一过孔、第二过孔和第三过孔的具体位置不做限定。若第一连接电极位于非发光区，为了简化结构，图2中以第一过孔、第二过孔和第三过孔设置在非发光区为例进行绘示；此时，第一连接电极通过第一过孔与第一电容电极位于非发光区的部分直接接触，进而实现第一连接电极和第一电容电极的电连接；第一连接电极通过第二过孔与有源层的导体化部(位于半导体部的右侧)直接接触，进而实现第一连接电极和有源层的电连接；第一连接电极通过第三过孔与阳极位于非发光区的部分直接接触，进而实现第一连接电极和阳极的电连接。需要说明的是，图2是以有源层的材料为金属氧化物为例进行绘示。
需要说明的是，若第一连接电极、第二连接电极、薄膜晶体管的源极和漏极同层设置且互不交叠，则上述绝缘层还覆盖源极和漏极。
上述显示基板通过设置第一过孔、第二过孔、第三过孔，分别实现第一连接电极和第一电容电极电连接、第一连接电极和有源层电连接、第一连接电极和阳极电连接，进而实现第一电容电极、有源层和阳极三者电连接，该种结构设计简单且容易实现。
可选地，缓冲层中用于形成存储电容的部分的厚度小于层间介质层中用 于覆盖存储电容的部分的厚度。缓冲层位于第一电容电极和第二电容电极之间，由于缓冲层对于良率的影响较小，因此膜层厚度可以做的较小；而存储电容的电容值跟两电极之间的距离(即缓冲层中用于形成存储电容的部分的厚度)呈负相关，因此，将缓冲层中用于形成存储电容的部分的厚度做薄，可以显著提升电容器的储电能力，更利于显示效果的提升。为了减少构图次数，栅极和栅极走线同层设置，数据走线和源漏极同层设置，而层间介质层位于两层之间；为了防止栅极走线(Gate走线)和数据走线(Data走线)之间短路风险，需要将层间介质层做的特别厚。
可选地，参考图2所示，第二连接电极位于发光区和非发光区；该显示基板还包括：
第四过孔(图2未标记)，第四过孔贯穿层间介质层38，第二连接电极39通过第四过孔与栅极37电连接。
第五过孔(图2未标记)，第五过孔贯穿层间介质层38，第二连接电极39通过第五过孔与第二电容电极34电连接。
上述第四过孔、第五过孔均仅贯穿层间介质层，均属于ILD过孔。这里对于第四过孔、第五过孔的具体位置不做限定。考虑到减小第二连接电极的占用面积以节约空间和成本，图2中第四过孔设置在栅极靠近第二连接电极一侧的上方、第五过孔设置在第二电容电极靠近第二连接电极一侧的上方。
上述显示基板通过设置第四过孔、第五过孔，分别实现第二连接电极与栅极电连接、第二连接电极与第二电容电极电连接，进而实现第二连接电极和栅极电连接。该种结构设计简单且容易实现。
可选地，该显示基板还包括：
位于层间介质层和阳极之间的源极和漏极，源极、漏极、第一连接电极和第二连接电极同层设置且互不交叠，源极和漏极均位于非发光区、且分别与有源层电连接。
这里对于源极、漏极分别与有源层电连接的方式不做限定。若该有源层为金属氧化物有源层，则源极、漏极可以分别通过贯穿层间介质层的过孔与各自对应的有源层的导体化部电连接；此时，栅极、源极、漏极以及有源层形成顶栅型金属氧化物薄膜晶体管。当然，根据有源层的不同，还可以形成其它类型的薄膜晶体管，这里不再赘述。上述源极、漏极、第一连接电极和第二连接电极同层设置是指采用一次构图工艺形成源极、漏极、第一连接电极和第二连接电极。
上述源极、漏极、第一连接电极和第二连接电极互不交叠是指：源极、漏极、第一连接电极和第二连接电极分别在显示基板的衬底上的正投影均没有重叠区域。
需要说明的是，上述显示基板的电路设计采用的3T1C结构可以参考图 3所示，3T1C结构包括3个薄膜晶体管，T1为开关薄膜晶体管、T2为补偿薄膜晶体管、T3为驱动薄膜晶体管，Cst为存储电容，第一电容电极和第二电容电极作为存储电容的两个电极、缓冲层作为两极板间的绝缘介质，上述薄膜晶体管可以作为T3驱动管。
可选地，参考图2所示，第一电容电极还位于非发光区；显示基板还包括：
衬底30；位于衬底30和第一电容电极32之间的遮光层31，遮光层31位于非发光区，有源层35在衬底30上的投影位于遮光层31在衬底30上的投影以内，且第一电容电极32覆盖遮光层31。
将上述显示基板应用于底发射型的OLED显示面板中，遮光层可以阻挡外界光线照射到有源层上，从而对有源层起到保护作用，进而延长薄膜晶体管的寿命。另外，遮光层设置在衬底和第一电容电极之间，第一电容电极位于非发光区的部分对遮光层可以起到保护作用，避免后续的刻蚀工艺对遮光层造成损害，极大提高了工艺适用性。
本公开实施例提供了一种显示面板，包括上述实施例提供的显示基板。该显示面板的开口率高，显示效果佳，产品质量高。该显示面板可以是OLED显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
本公开实施例提供了一种如上述实施例的显示基板的制备方法，显示基板包括显示区，显示区包括阵列排布的多个发光区和位于相邻发光区之间的非发光区。
参考图4所示，该方法包括：
S01、形成第一电容电极，第一电容电极至少一部分位于发光区。
示例的，可以采用构图工艺在衬底之上形成第一电容电极。第一电容电极的材料可以是金属或者金属氧化物(例如：ITO)等。
S02、形成缓冲层，缓冲层覆盖第一电容电极、且位于发光区和非发光区。
该缓冲层的材料可以是绝缘的氧化物、氮化物或者氧氮化合物，这里不做限定。
S03、在缓冲层之上形成互不交叠的第二电容电极和有源层，第二电容电极位于发光区，有源层位于非发光区。
考虑到节省制作成本，可以采用一次构图工艺在缓冲层上形成第二电容电极和有源层；当然也可以采用其它方式(例如：打印)制作，这里不做限定。
其中，第一电容电极、缓冲层和第二电容电极形成存储电容。
可选地，该方法还包括：
S04、形成栅极，栅极位于有源层之上、且位于非发光区，第二电容电极与栅极电连接。
该栅极的材料可以是金属或者金属合金制作，例如：Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。
S05、形成阳极，阳极位于第二电容电极和栅极之上且至少一部分位于发光区，第一电容电极、有源层和阳极三者电连接。
采用上述方法制作的显示基板，第一电容电极、第二电容电极分别作为存储电容的两个电极，缓冲层作为两极板间的绝缘介质，三者共同形成存储电容。第二电容电极与有源层互不交叠，相较于相关技术，第二电容电极位于发光区且设置在薄膜晶体管的外部，减小了薄膜晶体管的占用面积，进而减小了非发光区的面积，从而提高了开口率。
本公开的实施例提供了一种显示基板的制备方法，通过该制备方法形成的显示基板提供了一种存储电容设计结构，在保证存储电容足够大的同时，尽可能地减小TFT的占用面积，从而显著提升了开口率，进而大幅提升了产品的显示质量。该制备方法简单、容易实现。
可选地，上述有源层的材料为金属氧化物，例如：IGZO、氧化锌(ZnO)或氮氧化锌(ZnON)等；那么，S03、在缓冲层之上形成互不交叠的第二电容电极和有源层包括：
S301、采用一次构图工艺在缓冲层之上形成互不交叠的待导体化的第二电容电极和待导体化的有源层，待导体化的有源层包括半导体部、位于半导体部两侧且与半导体部相接的待导体化部。
S302、对待导体化的第二电容电极和待导体化部进行导体化，形成第二电容电极和有源层。导体化是指采用H、He等粒子轰击待导体化的部位。
可选地，上述显示基板还包括：位于有源层和栅极之间的栅绝缘层；则在S04、形成栅极之前，上述方法还包括：
S06、形成栅绝缘层，栅绝缘层位于有源层之上。
S06、形成栅绝缘层包括：形成栅绝缘薄膜。
示例的，可以采用等离子体增强化学气相沉积(PECVD)方法在有源层之上沉积一层栅绝缘薄膜，该栅绝缘薄膜的材料可以是氧化物、氮化物或者氧氮化合物。
S04、形成栅极包括：
S401、在栅绝缘薄膜之上形成栅金属薄膜。
S402、在栅金属薄膜之上涂覆光刻胶。
S403、采用同一掩膜板对栅绝缘薄膜和栅金属薄膜进行曝光、显影、刻蚀，形成栅绝缘层和栅极。
通过上述方法制作栅绝缘层和栅极，可以节省一张掩膜板，减少构图次数，从而降低成本节约生产时间。需要说明的是，在制作栅绝缘层和栅极时，还可以采用自对准工艺对栅绝缘层和栅极进行刻蚀，以提高制作精度。
可选地，在S403、采用同一掩膜板对栅绝缘薄膜和栅金属薄膜进行曝光、显影、刻蚀的步骤之后，执行S302、对待导体化的第二电容电极和待导体化部进行导体化的步骤。这样，在进行导体化时，由于栅绝缘层和栅极的保护作用，使得有源层的半导体部免受影响。
S04、形成栅极还包括：
在S302、对待导体化的第二电容电极和待导体化部进行导体化之后，S404、剥离栅极上的光刻胶。这样，在进行导体化时，由于光刻胶的保护作用，使得栅极免受影响。
可选地，阳极还位于非发光区，显示基板还包括：位于第二电容电极和阳极之间且互不交叠的第一连接电极、第二连接电极、源极和漏极。
在S04、形成栅极之后、且在S05、形成阳极之前，上述方法还包括：
S07、采用一次构图工艺形成互不交叠的第一连接电极、第二连接电极、源极和漏极。这样可以减少构图次数，降低成本。
可选地，显示基板还包括：位于第二电容电极和阳极之间的层间介质层。
那么，在S04、形成栅极之后，且在S07、形成第一连接电极和第二连接电极之前，上述方法还包括：
S08、形成层间介质层，层间介质层位于发光区和非发光区，且覆盖第二电容电极、栅极和有源层。这里层间介质层的材料不做限定，可以是氧化物、氮化物或者氧氮化合物等。
S09、形成贯穿层间介质层和缓冲层的第一过孔,以及贯穿层间介质层的第二过孔、第四过孔和第五过孔。
其中，第一连接电极通过第一过孔与第一电容电极电连接，第一连接电极通过第二过孔与有源层电连接，第二连接电极通过第四过孔与栅极电连接，第二连接电极通过第五过孔与第二电容电极电连接。
通过上述制备方法形成的显示基板，可以实现第一电容电极和有源层电连接，以及第二电容电极与栅极电连接。该种方法简单易实现。
可选地，显示基板还包括：位于阳极和层间介质层之间的绝缘层。
那么，在S07、形成第一连接电极和第二连接电极之后、且在S05、形成阳极之前，上述方法还包括：
S10、形成绝缘层，绝缘层位于发光区和非发光区，且至少覆盖层间介质层、第一连接电极和第二连接电极。需要说明的是，源极、漏极、第一连接电极和第二连接电极同层设置，绝缘层还覆盖源极、漏极。
S11、形成贯穿绝缘层的第三过孔。
S05、形成阳极包括：
在第一绝缘层之上形成阳极；其中，阳极通过第三过孔与第一连接电极连接。
通过上述制备方法形成的显示基板，可以进一步实现阳极与第一连接电极连接，从而实现第一电容电极、有源层和阳极三者电连接。该种方法简单易实现。
下面以图2所示的显示基板的结构为例，具体说明其制备方法。图2中，显示基板的有源层为金属氧化物有源层，包括半导体部、位于半导体部左侧的导体化部和位于半导体部右侧的导体化部。图2所示的显示基板应用于底发射的显示面板中。
该制备方法包括：
S100、形成衬底，该衬底为可透光材料，例如：玻璃等材料。
S101、在衬底之上形成遮光层，遮光层位于非发光区。
S102、在衬底之上形成第一电容电极，第一电容电极覆盖遮光层、且位于发光区和非发光区。
S103、形成缓冲层，缓冲层覆盖第一电容电极和遮光层、且位于发光区和非发光区。
S104、采用一次构图工艺在缓冲层之上形成互不交叠的待导体化的第二电容电极和待导体化的有源层，待导体化的有源层包括半导体部、位于半导体部两侧且与半导体部相接的待导体化部。其中，有源层在衬底上的投影位于遮光层在衬底上的投影以内。
S105、在有源层之上形成栅绝缘薄膜。
S106、在栅绝缘薄膜之上形成栅金属薄膜。
S107、在栅金属薄膜之上涂覆光刻胶。
S108、采用同一掩膜板对栅绝缘薄膜和栅金属薄膜进行曝光、显影、刻蚀。
S109、对待导体化的第二电容电极和待导体化部进行导体化。
S110、剥离栅极上的光刻胶；从而形成如图5的显示基板。
S111、形成层间介质层，层间介质层位于发光区和非发光区，且覆盖第二电容电极、栅极和有源层。
S112、形成贯穿层间介质层和缓冲层的第一过孔,以及贯穿层间介质层的第二过孔、第四过孔和第五过孔。
S113、采用一次构图工艺形成互不交叠的第一连接电极和第二连接电极、源极和漏极；源极和漏极均位于非发光区、且分别与有源层电连接。第一连接电极通过第一过孔与第一电容电极电连接，第一连接电极通过第二过孔与有源层电连接，第二连接电极通过第四过孔与栅极电连接，第二连接电极通过第五过孔与第二电容电极电连接。从而形成如图6所示的显示基板，图6中未绘示源极和漏极。
S114、形成绝缘层，绝缘层位于发光区和非发光区，且覆盖层间介质层、第一连接电极、第二连接电极、源极和漏极。
S115、形成贯穿绝缘层的第三过孔。
S116、在绝缘层之上形成阳极，阳极位于发光区和非发光区，通过第三过孔与第一连接电极连接。从而形成如图2所示的显示基板。
需要说明的是，若上述显示基板的OLED发光单元采用的是WOLED结构(即每个OLED发光单元发出的光为白色)，则在S114、形成绝缘层之后，且在S116、在绝缘层之上形成阳极之前，上述制备方法还包括：
S117、在绝缘层之上依次形成彩膜层(图7中标记43)、覆盖彩膜层的树脂绝缘层(Resin层，图7中标记44)。OLED发光单元发出的白光经过彩膜层后，可以转换成彩色，例如：红色、绿色或者蓝色。上述阳极通过贯穿树脂绝缘层和绝缘层的过孔与第一连接电极连接。该种显示基板的结构如图7所示。
本公开实施例中涉及的各膜层的结构、材料等相关内容可以参考上述实施例，此处不再赘述。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本公开的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本公开的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本公开可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种显示基板，包括显示区，所述显示区包括阵列排布的多个发光区和位于相邻所述发光区之间的非发光区；
    所述显示基板还包括：
    第一电容电极，所述第一电容电极至少一部分位于所述发光区；
    缓冲层，所述缓冲层覆盖所述第一电容电极、且位于所述发光区和所述非发光区；
    第二电容电极和有源层，互不交叠设置于所述缓冲层之上，所述有源层位于所述非发光区；
    其中，所述第一电容电极、所述缓冲层和所述第二电容电极形成存储电容。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    栅极，位于所述有源层之上与所述有源层绝缘、且位于所述非发光区，所述第二电容电极与所述栅极电连接；
    阳极，位于所述第二电容电极和所述栅极之上、且与所述第二电容电极及所述栅极绝缘，所述阳极至少一部分位于所述发光区，所述第一电容电极、所述有源层和所述阳极三者电连接。
  3. 根据权利要求2所述的显示基板，其中，所述第一电容电极还位于所述非发光区，所述第二电容电极位于所述发光区，所述阳极还位于所述非发光区，所述有源层的材料为金属氧化物；
    所述显示基板还包括：
    位于所述第二电容电极和所述阳极之间的层间介质层，所述层间介质层位于所述发光区和所述非发光区，且覆盖所述第二电容电极、所述栅极和所述有源层。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板还包括：
    位于所述层间介质层和所述阳极之间，且互不交叠的第一连接电极和第二连接电极；所述第一电容电极、所述有源层和所述阳极通过所述第一连接电极电连接，所述第二电容电极和所述栅极通过所述第二连接电极电连接。
  5. 根据权利要求4所述的显示基板，其中，所述第一连接电极至少一部分位于所述非发光区；
    所述显示基板还包括：
    位于所述阳极和所述层间介质层之间的绝缘层，所述绝缘层位于所述发光区和所述非发光区，且至少覆盖所述层间介质层、所述第一连接电极和所述第二连接电极。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括：
    第一过孔，所述第一过孔贯穿所述层间介质层和所述缓冲层，所述第一连 接电极通过所述第一过孔与所述第一电容电极电连接；
    第二过孔，所述第二过孔贯穿所述层间介质层，所述第一连接电极通过所述第二过孔与所述有源层电连接；以及
    第三过孔，所述第三过孔贯穿所述绝缘层，所述第一连接电极通过所述第三过孔与所述阳极电连接。
  7. 根据权利要求3所述的显示基板，其中，所述缓冲层中用于形成所述存储电容的部分的厚度小于所述层间介质层中用于覆盖所述存储电容的部分的厚度。
  8. 根据权利要求4所述的显示基板，其中，所述第二连接电极位于所述发光区和所述非发光区；
    所述显示基板还包括：
    第四过孔，所述第四过孔贯穿所述层间介质层，所述第二连接电极通过所述第四过孔与所述栅极电连接；以及
    第五过孔，所述第五过孔贯穿所述层间介质层，所述第二连接电极通过所述第五过孔与所述第二电容电极电连接。
  9. 根据权利要求8所述的显示基板，其中，所述第四过孔设置于所述栅极靠近所述第二连接电极一侧的上方，所述第五过孔设置于所述第二电容电极靠近所述第二连接电极一侧的上方。
  10. 根据权利要求4所述的显示基板，其中，所述显示基板还包括：
    位于所述层间介质层和所述阳极之间的源极和漏极，所述源极、所述漏极、所述第一连接电极和所述第二连接电极同层设置且互不交叠，所述源极和所述漏极均位于所述非发光区、且分别与所述有源层电连接。
  11. 根据权利要求1-10任一项所述的显示基板，其中，所述第一电容电极还位于所述非发光区；
    所述显示基板还包括：
    衬底；以及
    位于所述衬底和所述第一电容电极之间的遮光层，所述遮光层位于非发光区，所述有源层在所述衬底上的投影位于所述遮光层在所述衬底上的投影以内，且所述第一电容电极覆盖所述遮光层。
  12. 一种显示面板，其中，包括权利要求1-11任一项所述的显示基板。
  13. 一种如权利要求1-11任一项所述的显示基板的制备方法，其中，所述显示基板包括显示区，所述显示区包括阵列排布的多个发光区和位于相邻所述发光区之间的非发光区；
    所述方法包括：
    形成第一电容电极，所述第一电容电极至少一部分位于所述发光区；
    形成缓冲层，所述缓冲层覆盖所述第一电容电极、且位于所述发光区和所 述非发光区；
    在所述缓冲层之上形成互不交叠的第二电容电极和有源层，所述有源层位于所述非发光区；
    其中，所述第一电容电极、所述缓冲层和所述第二电容电极形成存储电容。
  14. 根据权利要求13所述的制备方法，其中，所述方法还包括：
    形成栅极，所述栅极位于所述有源层之上、且位于所述非发光区，所述第二电容电极与所述栅极电连接；
    形成阳极，所述阳极位于所述第二电容电极和所述栅极之上且至少一部分位于所述发光区，所述第一电容电极、所述有源层和所述阳极三者电连接。
  15. 根据权利要求14所述的制备方法，其中，所述第二电容电极位于所述发光区，所述有源层的材料为金属氧化物；
    所述在所述缓冲层之上形成互不交叠的第二电容电极和有源层包括：
    采用一次构图工艺在所述缓冲层之上形成互不交叠的待导体化的第二电容电极和待导体化的有源层，所述待导体化的有源层包括半导体部、位于所述半导体部两侧且与所述半导体部相接的待导体化部；以及
    对所述待导体化的第二电容电极和所述待导体化部进行导体化，形成所述第二电容电极和所述有源层。
  16. 根据权利要求15所述的制备方法，其中，所述显示基板还包括：位于所述有源层和所述栅极之间的栅绝缘层；
    在所述形成栅极之前，所述方法还包括：
    形成栅绝缘层，所述栅绝缘层位于所述有源层之上；
    所述形成栅绝缘层包括：
    形成栅绝缘薄膜。
  17. 根据权利要求16所述的制备方法，其中，所述形成所述栅极包括：
    在所述栅绝缘薄膜之上形成栅金属薄膜；
    在所述栅金属薄膜之上涂覆光刻胶；以及
    采用同一掩膜板对所述栅绝缘薄膜和所述栅金属薄膜进行曝光、显影、刻蚀，形成所述栅绝缘层和所述栅极。
  18. 根据权利要求17所述的制备方法，其中，
    在采用同一掩膜板对所述栅绝缘薄膜和所述栅金属薄膜进行曝光、显影、刻蚀的步骤之后，执行对所述待导体化的第二电容电极和所述待导体化部进行导体化的步骤；
    所述形成所述栅极还包括：
    在对所述待导体化的第二电容电极和所述待导体化部进行导体化之后，剥离所述栅极上的光刻胶。
  19. 根据权利要求14所述的制备方法，其中，所述阳极还位于所述非发 光区，所述显示基板还包括：位于所述第二电容电极和所述阳极之间且互不交叠的第一连接电极、第二连接电极、源极和漏极；
    在形成所述栅极之后、且在形成所述阳极之前，所述方法还包括：
    采用一次构图工艺形成互不交叠的所述第一连接电极、所述第二连接电极、所述源极和所述漏极。
  20. 根据权利要求19所述的制备方法，其中，所述显示基板还包括：位于所述第二电容电极和所述阳极之间的层间介质层；
    在形成所述栅极之后、且在形成所述第一连接电极和所述第二连接电极之前，所述方法还包括：
    形成所述层间介质层，所述层间介质层位于所述发光区和所述非发光区，且覆盖所述第二电容电极、所述栅极和所述有源层；
    形成贯穿所述层间介质层和所述缓冲层的第一过孔,以及贯穿所述层间介质层的第二过孔、第四过孔和第五过孔；以及
    其中，所述第一连接电极通过所述第一过孔与所述第一电容电极电连接，所述第一连接电极通过所述第二过孔与所述有源层电连接，所述第二连接电极通过所述第四过孔与所述栅极电连接，所述第二连接电极通过所述第五过孔与所述第二电容电极电连接。
  21. 根据权利要求20所述的制备方法，其中，所述显示基板还包括：位于所述阳极和所述层间介质层之间的绝缘层；
    在形成所述第一连接电极和所述第二连接电极之后、且在形成所述阳极之前，所述方法还包括：
    形成所述绝缘层，所述绝缘层位于所述发光区和所述非发光区，且至少覆盖所述层间介质层、所述第一连接电极和所述第二连接电极；
    形成贯穿所述绝缘层的第三过孔。
  22. 根据权利要求21所述的制备方法，其中，所述形成阳极包括：
    在所述第一绝缘层之上形成所述阳极；其中，所述阳极通过所述第三过孔与所述第一连接电极连接。
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