WO2021026872A1 - 一种半导体薄膜层的转移方法及复合晶圆的制备方法 - Google Patents

一种半导体薄膜层的转移方法及复合晶圆的制备方法 Download PDF

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WO2021026872A1
WO2021026872A1 PCT/CN2019/100757 CN2019100757W WO2021026872A1 WO 2021026872 A1 WO2021026872 A1 WO 2021026872A1 CN 2019100757 W CN2019100757 W CN 2019100757W WO 2021026872 A1 WO2021026872 A1 WO 2021026872A1
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semiconductor substrate
layer
film layer
substrate
semiconductor
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French (fr)
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王智勇
代京京
兰天
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北京工业大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off

Definitions

  • the invention relates to the technical field of semiconductor device integration, in particular to a method for transferring a semiconductor thin film layer and a method for preparing a composite wafer.
  • microelectronics, optoelectronic devices and smart microsystems will continue to develop in the direction of miniaturization, integration and intelligence, and the required microsystem chip functions will become more complex, diversified and compatible.
  • This development trend puts forward a huge demand for heterogeneous integration technology.
  • Heterogeneous integration will also open up a new path for the development of microelectronics in the post-Moore era; on the basis of maintaining the original device and process size, the development of heterogeneous
  • the integrated integration technology of materials and multiple functional devices realizes the diversification of the functions of a single chip, especially the single chip integration of optoelectronics, micro energy, analog, radio frequency, passive devices, and MEMS devices.
  • heterogeneous integration technology must first solve the problem of heterogeneous fusion of different semiconductor materials and functional films, which will provide an important material basis for the monolithic integration of devices and systems in the future.
  • traditional epitaxial growth methods such as molecular beam epitaxy, metal organic chemical vapor phase epitaxy, chemical vapor deposition, physical vapor phase epitaxy and magnetron sputtering, have lattice mismatch, crystal mismatch, Problems such as interdiffusion and reverse domain seriously affect the quality of the film and the flexibility of heterogeneous integration.
  • seeking a high-quality compound semiconductor single crystal film is a transfer method, which is a development direction of future heterogeneous integration technology.
  • the present invention provides a method for transferring a semiconductor thin film layer and a method for preparing a composite wafer.
  • the invention discloses a method for transferring a semiconductor thin film layer, including:
  • An external force is applied to the metal film layer on the lower surface of the first semiconductor substrate to cause the first semiconductor substrate to laterally crystallize at the trench, and the semiconductor film layer after crystallization is transferred to the second semiconductor substrate Bottom.
  • the first semiconductor substrate includes one of a single crystal GaAs substrate, a single crystal Ge substrate, a single crystal Si substrate, a single crystal GaN substrate, and a single crystal InP substrate;
  • a buffer layer is provided between the metal film layer and the first semiconductor substrate, and the metal film layer includes one of a Ni layer and a Cr layer.
  • the second semiconductor substrate includes one of Si substrate, Ge substrate and SiC substrate;
  • the first dielectric layer or the second dielectric layer includes one or more of Si 3 N 4 layer, SiO 2 layer, Al 2 O 3 layer, and AlN layer, and the second dielectric layer serves as the second semiconductor
  • the buried oxide layer of the substrate includes one or more of Si 3 N 4 layer, SiO 2 layer, Al 2 O 3 layer, and AlN layer, and the second dielectric layer serves as the second semiconductor
  • the buried oxide layer of the substrate includes one or more of Si 3 N 4 layer, SiO 2 layer, Al 2 O 3 layer, and AlN layer, and the second dielectric layer serves as the second semiconductor
  • the buried oxide layer of the substrate
  • the first medium layer and the second medium layer are selected from the same medium layer or contain elements of the same group.
  • the method further includes:
  • a metal film layer is prepared on the surface of the composite crystal where there is no metal film layer.
  • the trench is a microcrack or a microhole
  • the tip of the microcrack or microhole penetrates deeply into the side surface of the first semiconductor substrate and is on the first semiconductor substrate.
  • a few nanometer nicks are formed on the side surface of the, and the semiconductor substrate between the tip of the microcrack or the microhole and the upper surface of the first semiconductor substrate is the semiconductor thin film layer after crystal cracking.
  • the applying external force to the metal film layer on the lower surface of the first semiconductor substrate to cause the first semiconductor substrate to laterally crystallize at the trench including:
  • the vacuum suction pulling force causes the first semiconductor substrate to laterally crystallize at the trench.
  • the present invention also provides a method for preparing a composite wafer based on the above transfer method, including:
  • the first semiconductor substrate is laterally crystallized at the microcracks or microcavities, and the semiconductor thin film layer after crystallization is transferred to the second semiconductor substrate with a buried oxygen layer, A single crystal XOI composite wafer is obtained; the structure of the single crystal XOI composite wafer is a second semiconductor substrate, a buried oxygen layer and a semiconductor thin film layer in order.
  • the thickness of the semiconductor thin film layer is 100-500 nm, and the thickness of the first dielectric layer and the second dielectric layer are 50-400 nm.
  • the remaining first semiconductor substrate and metal film layer can repeat the above-mentioned preparation method and be divided into multiple semiconductor thin film layers for preparing multiple XOIs.
  • the metal layer on the surface of the XOI is polished and removed by grinding and polishing.
  • the invention can form a semiconductor thin film layer on a semiconductor substrate in a crystal cracking manner, and the surface of the semiconductor thin film layer after crystal cracking is flat, and transferred to another substrate (Si-based or SiC-based substrate) by means of dielectric layer bonding. ), to achieve the preparation of high-quality, large-area, and low-cost compound semiconductor single crystal thin film layers on XOI substrates; since semiconductor substrates are generally more expensive, for example, a high-quality 2-inch single crystal GaN substrate costs For thousands of dollars, the transfer method of the present invention can separate the multilayer semiconductor film layer from the semiconductor substrate, which greatly saves the manufacturing cost of the semiconductor industry, thereby promoting the industrial application of semiconductor devices on XOI. Compared with the traditional smartcut, through crystal The surface of the crystal plane obtained by cracking is flat, and it can be directly epitaxially grown or chip manufacturing process on it, without polishing and grinding process.
  • FIG. 1 is a flowchart of a method for transferring a semiconductor thin film layer disclosed in an embodiment of the present invention
  • FIG. 2 is a structure and preparation flow chart of the first type A wafer disclosed in an embodiment of the present invention.
  • FIG. 3 is a structure and preparation flow chart of a second type A wafer disclosed in an embodiment of the present invention.
  • FIG. 5 is a structure and preparation flow chart of a second type of B wafer disclosed in an embodiment of the present invention.
  • FIG. 6 is a structure and preparation flow chart of the first composite wafer disclosed in an embodiment of the present invention.
  • FIG. 7 is a structure and preparation flow chart of a second composite wafer disclosed in two embodiments of the present invention.
  • FIG. 8 is a structure and preparation flow chart of a third composite wafer disclosed in three embodiments of the present invention.
  • FIG. 9 is a structure and preparation flow chart of a fourth composite wafer disclosed in four embodiments of the present invention.
  • a wafer 11. First semiconductor substrate; 12. First dielectric layer; 13. Metal film layer; 14. GeO 2 buffer layer;
  • connection should be understood in a broad sense, unless otherwise clearly defined and limited.
  • they may be fixed connections or alternatively.
  • Detachable connection, or integral connection it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • connection should be understood in specific situations.
  • the film layer transfer technology of the present invention can peel a thin film with a thickness of nanometer scale from any single crystal substrate and combine it with heterogeneous materials. This method will break through the physical limit of heteroepitaxial growth, and can be used in amorphous,
  • the integration of high-quality single-crystal films on polycrystalline or even flexible substrates provides a simple and efficient means for realizing high-quality heterogeneous integrated materials. Smartcut has achieved great success first in the preparation of silicon-on-insulator (SOI) materials.
  • SOI silicon-on-insulator
  • This single-crystal film transfer technology can directly obtain high-quality mirror film layers by crystal cracking without subsequent surface grinding and polishing.
  • the film layer transfer technology of the present invention can be further applied to the film layer transfer of laser crystals.
  • the present invention provides a method for transferring a semiconductor thin film layer, including:
  • a first dielectric layer is prepared on the upper surface of the first semiconductor substrate, and a metal film layer is prepared on the lower surface;
  • the first dielectric layer and the metal film layer of the present invention cover the first semiconductor substrate, as shown in the structure of A wafer in FIG. 2;
  • the first semiconductor substrate of the present invention is a single crystal GaAs substrate, a single crystal GaN substrate or a single crystal InP substrate, etc.
  • the present invention is also applicable to the transfer of other crystal film layers, such as laser crystals;
  • the first dielectric layer of the present invention is a Si 3 N 4 layer, a SiO 2 layer, an Al 2 O 3 layer or an AlN layer.
  • the selection criterion of the first dielectric layer is: it is necessary to ensure that the distance between the first dielectric layer and the first semiconductor substrate The bonding force of the first semiconductor substrate is greater than the crystal cracking force of the first semiconductor substrate at the trench;
  • the metal film layer of the present invention is a Ni or Cr metal layer, etc.
  • the selection criteria of the metal film layer are: the thermal expansion rate is quite different from the compound, the ductility is poor, and it is easy to prepare.
  • a GeO 2 buffer layer may be provided between the metal film layer and the first semiconductor substrate, as shown in the structure of the A wafer in FIG. 3; the preparation method is:
  • Magnetron sputtering can be used to prepare a metal film on the GeO 2 buffer layer.
  • the second semiconductor substrate is a semiconductor substrate such as a Si substrate, a Ge substrate, and a SiC substrate;
  • the second dielectric layer is Si 3 N 4 layer, SiO 2 layer, Al 2 O 3 layer or AlN layer.
  • the second dielectric layer serves as the buried oxygen layer of the second semiconductor substrate; both the first dielectric layer and the second dielectric layer are selected The same dielectric layer, or contains elements of the same group;
  • the trench is a microcrack or microhole.
  • the tip of the microcrack or microhole penetrates into the side surface of the semiconductor substrate and forms a few nanometer nicks on the side surface of the semiconductor substrate.
  • the tip of the microcrack or microhole The semiconductor substrate between the upper surface of the semiconductor substrate and the semiconductor substrate is a semiconductor thin film layer after crystal cracking;
  • S7 can be added between S3 and S4; that is, a metal film is plated on the position of the composite wafer where the metal film is not plated.
  • the metal film layer can effectively protect the bonding interface, so that cracks will not appear in the bonding interface under the action of tensile force.
  • the present invention provides a method for preparing a composite wafer (single crystal XOI composite wafer) based on the above transfer method, including: preparing A wafer, preparing B wafer and preparing single crystal XOI composite wafer; wherein:
  • the A wafer 10 of the present invention includes a first semiconductor substrate 11, a first dielectric layer 12, and a metal film layer 13.
  • the preparation method is as follows:
  • a first dielectric layer 12 is prepared on the upper surface of the first semiconductor substrate 11 as the buried oxygen layer of the single crystal XOI composite wafer; specifically: according to different dielectric layer materials, PECVD or thermal oxidation or magnetron sputtering is used Preparation by shooting method. These are mature processes, and the thickness of the first dielectric layer 12 is 100-400 nm;
  • a metal film layer 13 is prepared on the lower surface of the first semiconductor substrate 11; specifically, the metal film layer 13 is prepared by a magnetron sputtering method, and the thickness of the metal film layer 13 is 500-5000 nm.
  • the A wafer 10 of the present invention includes a first semiconductor substrate 11, a first dielectric layer 12, a metal film layer 13, and a GeO 2 buffer layer 14.
  • the preparation method is as follows:
  • a first dielectric layer 12 is prepared on the upper surface of the first semiconductor substrate 11 as the buried oxygen layer of the single crystal XOI composite wafer; specifically: according to different dielectric layer materials, PECVD or thermal oxidation or magnetron sputtering is used Preparation by shooting method. These are mature processes, and the thickness of the first dielectric layer 12 is 100-400 nm;
  • a GeO 2 buffer layer 14 is prepared on the lower surface of the first semiconductor substrate 11, and a metal film layer 13 is prepared on the GeO 2 buffer layer 14; specifically: 99.99% GeO 2 powder is sintered at a high temperature of 1500 to 1600°C.
  • GeO 2 was deposited on the substrate by radio frequency magnetron sputtering in an Ar/H 2 (about 10%) mixed atmosphere. Control the sputtering pressure from 25 to 55 Pa, the substrate temperature from 100 to 800°C, the sputtering power from 70 to 100 W, and the thickness of the GeO 2 film is about 200 to 300 nm.
  • the metal film layer 13 is prepared on the GeO 2 buffer layer 12 by a magnetron sputtering method, and the thickness of the metal film layer 13 is 500-5000 nm.
  • the B wafer 20 of the present invention includes: a Si substrate 21, a Ge substrate or a SiC substrate, etc., and a second dielectric layer 23; its preparation method is as follows:
  • a second dielectric layer 23 is prepared on the surface of the Si substrate 12 as a buried oxygen layer; the specific preparation method is as follows:
  • the reaction gas Several gases among N 2 , SiH 4 , NH 3 , HCl 4 , and H 2 Cl 2 are used as the reaction gas, and the second dielectric layer 23 is prepared in the range of 300-500° C. by using the PECVD method.
  • the B wafer 20 of the present invention includes: a Si substrate 21, an SiO 2 layer 22 and a second dielectric layer 23; its preparation method is as follows:
  • a SiO 2 layer 22 is prepared on the surface of the Si substrate 12, and a second dielectric layer 23 is prepared on the surface of the SiO 2 layer 22; further, the thickness of the second dielectric layer is 100-400 nm.
  • the single crystal XOI composite wafer of the present invention includes a Si substrate 31, a dielectric layer 33, and a semiconductor thin film layer 34, which are based on the A wafer as shown in FIG. 2 and the B crystal as shown in FIG.
  • the specific preparation method is as follows:
  • Etch micro cracks or micro holes in the metal film on the side of the A wafer Etch micro cracks or micro holes in the metal film on the side of the A wafer
  • a metal strip is prepared on the metal film layer on the lower surface of the A wafer; further, the metal strip can be prepared by laser welding or the like.
  • a single crystal XOI composite wafer is obtained; the structure of a single crystal XOI composite wafer is a Si substrate, a Ge substrate, a SiC substrate and other semiconductor substrates, a buried oxygen layer, and a semiconductor thin film layer.
  • the thickness of the semiconductor thin film layer is 100-500 nm.
  • the semiconductor film When choosing to prepare a metal film on the surface of the composite wafer without a metal film, after removing part of the semiconductor substrate and metal film with a metal strip, the semiconductor film needs to be removed by chemical etching and mechanical polishing. The layer is ground, and the remaining metal film layer is corroded to obtain a high-quality XOI single crystal film layer surface.
  • the single crystal XOI composite wafer of the present invention includes a Si substrate 31, a dielectric layer 33, and a semiconductor thin film layer 34, which are based on the A wafer as shown in FIG. 3 and the B crystal as shown in FIG.
  • the preparation method is the same as above.
  • the single-crystal XOI composite wafer of the present invention includes a Si substrate 31, an SiO 2 layer 22, a dielectric layer 33, and a semiconductor thin film layer 34, which are based on the A wafer shown in FIG. 2 and FIG.
  • the B wafer shown is prepared, and the specific preparation method is the same as above.
  • the single crystal XOI composite wafer of the present invention includes a Si substrate 31, an SiO 2 layer 22, a dielectric layer 33, and a semiconductor thin film layer 34, which are based on the A wafer shown in FIG. 3 and The B wafer shown is prepared, and the specific preparation method is the same as above.
  • the present invention can form a semiconductor thin film layer on the semiconductor substrate in the manner of crystal cracking, and the semiconductor thin film layer after the crystal cracking is transferred to another substrate (Si-based or SiC-based substrate) by means of dielectric layer bonding.
  • another substrate Si-based or SiC-based substrate
  • the transfer method of the present invention can separate the multilayer semiconductor film layer from the semiconductor substrate, which greatly saves the manufacturing cost of the semiconductor industry, thereby promoting the industrial application of semiconductor devices on XOI.
  • it is obtained by crystal cracking.
  • the surface of the crystal plane is flat, and epitaxial growth or chip manufacturing can be carried out directly on it, without polishing and grinding processes.
  • the present invention takes into account the actual requirements of both structure and device performance.
  • the thickness of each layer and manufacturing process can be adjusted within a certain range according to specific materials and device indicators; under the premise that the corresponding process can be achieved, the compound semiconductor film can be achieved Transfer and composite wafer preparation.
  • the GeO 2 of the present invention can prevent Ni ions from diffusing into the semiconductor substrate.
  • Ni or Cr metal is selected as the metal film is that Ni or Cr metal film is prepared at high temperature due to Ni or Cr metal.
  • the coefficient of thermal expansion is quite different from that of compound semiconductors and the extensibility is general. Therefore, when cooled to room temperature, a tensile force will be generated at the interface between the metal layer and the semiconductor substrate. When a trench defect occurs, it is easy to Lateral crystal cracks from the trench.
  • the semiconductor substrate is relatively brittle and the metal layer is relatively hard, the metal layer is attached to the semiconductor layer, which will protect the semiconductor substrate and the bonding interface. When pulled, the peeled semiconductor substrate will not be longitudinally cracked. Into pieces.
  • the same dielectric layer or a dielectric layer with elements of the same group is used because the elements of the same group are bonded by interatomic force, which can make the prepared composite wafer withstand thousands of degrees of high temperature during the subsequent epitaxy process.

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Abstract

本发明公开了一种半导体薄膜层的转移方法及复合晶圆的制备方法，包括：在半导体衬底的上表面上制备第一介质层、下表面上制备金属膜层；在第二半导体衬底上制备第二介质层；将第一介质层和第二介质层键合，使第一半导体衬底和第二半导体衬底相结合；在第一半导体衬底的侧面刻蚀沟槽；对第一半导体衬底的下表面金属膜层施加外力，使第一半导体衬底在沟槽处横向晶裂，晶裂后的半导体薄膜层转移到第二半导体衬底上。本发明可实现高质量、大面积、低成本的半导体单晶薄膜层在XOI衬底上的制备；同时，此方法可以重复利用剩余的第一半导体衬底，从第一半导体衬底上分离出多层半导体薄膜层，用于制备多个XOI，大大节约了工业制造成本。

Description

一种半导体薄膜层的转移方法及复合晶圆的制备方法 技术领域
本发明涉及半导体器件集成技术领域，具体涉及一种半导体薄膜层的转移方法及复合晶圆的制备方法。
背景技术
未来微电子、光电子器件及智能微系统将继续沿着小型化、集成化和智能化的方向发展，所需的微系统芯片功能更加复杂化、多样化和兼容一体化。这种发展趋势对异质集成技术提出了巨大的需求，异质集成也将为后摩尔时代微电子技术的发展开辟一条全新的道路；在保持原有器件和工艺尺寸的基础上，发展异质材料与多种功能器件的一体化集成技术，从而实现单一芯片的功能多样化，特别是实现光电、微能源、模拟、射频、无源器件、MEMS器件的单芯片集成。
发展异质集成技术首先要解决不同半导体材料及功能薄膜的异质融合问题，这将为今后实现器件及系统的单片式集成提供重要的材料基础。在材料异质集成方面，传统的外延生长方法，如分子束外延、金属有机化学气相外延、化学气相沉积、物理气相外延和磁控溅射等，存在着晶格失配、晶型失配、互扩散与反向畴等问题，严重影响了薄膜质量和异质集成的灵活性。
因此寻求一种高质量化合物半导体单晶膜层是转移方法，是未来异质集成技术的一个发展方向。
发明内容
针对上述问题中存在的不足之处，本发明提供一种半导体薄膜层的转移方法及复合晶圆的制备方法。
本发明公开了一种半导体薄膜层的转移方法，包括：
在第一半导体衬底的上表面上制备第一介质层、下表面上制备金属膜层；
在第二半导体衬底上制备第二介质层；
将所述第一介质层和第二介质层键合，使所述第一半导体衬底和第二半导体衬底相结合；
在所述第一半导体衬底的侧面刻蚀沟槽；
对所述第一半导体衬底的下表面金属膜层施加外力，使所述第一半导体衬底在所述沟槽处横向晶裂，晶裂后的半导体薄膜层转移到所述第二半导体衬底上。
作为本发明的进一步改进，所述第一半导体衬底包括单晶GaAs衬底、单晶Ge衬底、单晶Si衬底、单晶GaN衬底和单晶InP衬底中的一种；
所述金属膜层与第一半导体衬底之间设有缓冲层，所述金属膜层包括Ni层和Cr层中的一种。
作为本发明的进一步改进，所述第二半导体衬底包括Si衬底、Ge衬底和SiC衬底中的一种；
所述第一介质层或第二介质层包括Si 3N 4层、SiO 2层、Al 2O 3层和AlN层中的一种或多种，所述第二介质层作为所述第二半导体衬底的埋氧层；
所述第一介质层和第二介质层选用相同的介质层，或者含有同族元素。
作为本发明的进一步改进，在第一介质层和第二介质层键合之后、在所述第一半导体衬底的侧面刻蚀沟槽之前，还包括：
在复合晶体的表面没有金属膜层的部分制备一层金属膜层。
作为本发明的进一步改进，所述沟槽为微裂纹或微孔洞，所述微裂纹或微孔洞的尖端深入至所述第一半导体衬底的侧面上且在所述第一半导体衬底的侧面形成数纳米的刻痕，所述微裂纹或微孔洞的尖端与所述第一半导体衬底的上表面之间的半导体衬底为晶裂后的所述半导体薄膜层。
作为本发明的进一步改进，所述对所述第一半导体衬底的下表面金属膜层施加外力，使所述第一半导体衬底在所述沟槽处横向晶裂；包括：
在所述第一半导体衬底的下表面金属膜层上制备一个金属带；
拉动所述金属带，使所述第一半导体衬底在所述沟槽处横向晶裂；
或者，
在所述第一半导体衬底的下表面金属膜层上施加一个真空吸附拉力；
通过所述真空吸附拉力，使所述第一半导体衬底在所述沟槽处横向晶裂。
本发明还提供一种基于上述转移方法的复合晶圆的制备方法，包括：
制备A晶圆：
在第一半导体衬底的上表面上制备第一介质层，作为单晶XOI复合晶圆 的埋氧层；
在第一半导体衬底的下表面上制备金属膜层；
制备B晶圆：
在第二半导体衬底的表面上制备第二介质层，作为单晶XOI复合晶圆的埋氧层；
制备单晶XOI复合晶圆：
将A晶圆、B晶圆上顶层的第一介质层与第二介质层之间进行键合，使A晶圆、B晶圆紧密结合；
在A晶圆的侧面刻蚀微裂纹或微孔洞；
在A晶圆下表面的金属膜层上制备金属带或采用真空吸附的方法施加横向拉力；
在横向拉力的作用下使所述第一半导体衬底在所述微裂纹或微孔洞处横向晶裂，晶裂后的半导体薄膜层转移到带有埋氧层的第二半导体衬底上，得到单晶XOI复合晶圆；所述单晶XOI复合晶圆的结构依次为第二半导体衬底、埋氧层和半导体薄膜层。
作为本发明的进一步改进，所述半导体薄膜层的厚度为100-500nm，所述第一介质层、第二介质层的厚度为50-400nm。
作为本发明的进一步改进，在剥离去除半导体薄膜层后，剩余的第一半导体衬底和金属膜层可重复上述制备方法，分为多个半导体薄膜层用于制备成为多个XOI。
作为本发明的进一步改进，当在复合晶圆的表面没有金属膜层的部分制备一层金属膜层时：
在使用剥离去除部分半导体衬底和金属膜层后，采用磨抛法将所述XOI表面的金属层研磨去除。
与现有技术相比，本发明的有益效果为：
本发明可将半导体衬底以晶裂的方式形成一层半导体薄膜层，晶裂后的半导体薄膜层表面平整，通过介质层键合的方式转移到另一衬底(Si基或SiC基衬底)上，实现高质量、大面积、低成本化合物半导体单晶薄膜层在XOI衬底上的制备；由于半导体衬底一般都比较贵，例如，一个高品质的2寸单晶GaN衬底价格为数千美元，采用本发明的转移方法可以从半导体衬底上分 离出多层半导体薄膜层，大大节约半导体工业制造成本，从而促进XOI上半导体器件的工业应用，与传统的smartcut相比，通过晶裂得到的晶面表面平整，可以直接在上面进行外延生长或者进行芯片制程，无须抛光研磨工序。
附图说明
图1为本发明一种实施例公开的半导体薄膜层的转移方法的流程图；
图2为本发明一种实施例公开的第一种A晶圆的结构及制备流程图；
图3为本发明一种实施例公开的第二种A晶圆的结构及制备流程图；
图4为本发明一种实施例公开的第一种B晶圆的结构及制备流程图；
图5为本发明一种实施例公开的第二种B晶圆的结构及制备流程图；
图6为本发明一种实施例公开的第一种复合晶圆的结构及制备流程图；
图7为本发明二种实施例公开的第二种复合晶圆的结构及制备流程图；
图8为本发明三种实施例公开的第三种复合晶圆的结构及制备流程图；
图9为本发明四种实施例公开的第四种复合晶圆的结构及制备流程图。
图中：
10、A晶圆；11、第一半导体衬底；12、第一介质层；13、金属膜层；14、GeO 2缓冲层；
20、B晶圆；21、Si衬底；22、SiO 2层；23、第二介质层；
30、单晶XOI复合晶圆；31、Si衬底；32、SiO 2层；33、介质层；34、半导体薄膜层。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指 的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本发明的描述中，还需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
本发明的膜层转移技术可以从任意单晶衬底上剥离厚度在纳米尺度的薄膜，并将其与异质材料进行组合，该方法将突破异质外延生长的物理极限，能够在非晶、多晶甚至柔性衬底上集成高质量的单晶薄膜，为实现高质量异质集成材料提供了简单、高效的手段。smartcut首先在制备绝缘体上的硅(SOI)材料方面已经取得巨大的成功，此项单晶膜层转移技术可以直接通过晶裂的方式得到高质量的镜面膜层，无需后续对表面研磨抛光。本发明的膜层转移技术可以进一步应用于激光晶体的膜层转移上。
下面结合附图对本发明做进一步的详细描述：
如图1所示，本发明提供一种半导体薄膜层的转移方法，包括：
S1、在第一半导体衬底的上表面上制备第一介质层、下表面上制备金属膜层；其中：
本发明的第一介质层和金属膜层覆盖第一半导体衬底，如图2所示的A晶圆的结构；
本发明的第一半导体衬底为单晶GaAs衬底、单晶GaN衬底或单晶InP衬底等，本发明也同样适用于其他晶体膜层的转移，如激光晶体等；
本发明的第一介质层为Si 3N 4层、SiO 2层、Al 2O 3层或AlN层，第一介质层的选择标准为：需保证第一介质层与第一半导体衬底之间的结合力大于第一半导体衬底在沟槽处晶裂的晶裂力；
本发明的金属膜层为Ni或Cr金属层等，金属膜层的选择标准为：热膨胀率与化合物相差较大，延展性较差，容易制备。
进一步，本发明还可在金属膜层与第一半导体衬底之间设有GeO 2缓冲层， 如图3所示的A晶圆的结构；制备方法为：
在第一半导体衬底上采用磁控溅射的方法沉积一层GeO 2缓冲层；
在GeO 2缓冲层上可以采用磁控溅射的方法制备金属膜层。
S2、在第二半导体衬底上制备第二介质层；其中：
第二半导体衬底为Si衬底、Ge衬底、SiC衬底等半导体衬底；
第二介质层为Si 3N 4层、SiO 2层、Al 2O 3层或AlN层，第二介质层作为第二半导体衬底的埋氧层；第一介质层和第二介质层均选用相同的介质层，或者含有同族元素；
S3、将第一介质层和第二介质层键合，使第一半导体衬底和第二半导体衬底相结合；
S4、在第一半导体衬底的侧面上刻蚀沟槽；其中：
沟槽为微裂纹或微孔洞，微裂纹或微孔洞的尖端深入至半导体衬底的侧面上且在所述半导体衬底的侧面形成数纳米的刻痕，微裂纹或微孔洞的尖端与半导体衬底的上表面之间的半导体衬底为晶裂后的半导体薄膜层；
S5、对第一半导体衬底的下表面金属膜层施加外力，使第一半导体衬底在沟槽处横向晶裂，晶裂后的半导体薄膜层转移到第二半导体衬底上；其中：
在第一半导体衬底的下表面金属膜层上制备金属带；在金属带上施加拉力，使第一半导体衬底在沟槽处横向晶裂，晶裂后的半导体薄膜层转移到第二半导体衬底上。
S6、重复上述制备方法，可以利用将半导体衬底多次制备薄膜转移到XOI晶圆上。
进一步，本发明还可在S3与S4之间增加S7；即，在复合晶圆未镀金属膜的位置镀一层金属膜。可以使得金属膜层有效保护键合界面，使得在拉力作用下，键合界面不会出现裂缝。
本发明提供一种基于上述转移方法的复合晶圆(单晶XOI复合晶圆)的制备方法，包括：制备A晶圆、制备B晶圆和制备单晶XOI复合晶圆；其中：
如图2所示，本发明的A晶圆10包括第一半导体衬底11、第一介质层12和金属膜层13，其制备方法为：
在第一半导体衬底11上表面上制备第一介质层12，作为单晶XOI复合晶圆的埋氧层；具体为：根据不同的介质层材料，采用PECVD法或热氧化法 或磁控溅射法制备。这些是成熟工艺，第一介质层12的厚度为100-400nm；
在第一半导体衬底11的下表面上制备金属膜层13；具体为：采用磁控溅射法制备金属膜层13，金属膜层13的厚度为500-5000nm。
如图3所示，本发明的A晶圆10包括第一半导体衬底11、第一介质层12和金属膜层13和GeO 2缓冲层14，其制备方法为：
在第一半导体衬底11上表面上制备第一介质层12，作为单晶XOI复合晶圆的埋氧层；具体为：根据不同的介质层材料，采用PECVD法或热氧化法或磁控溅射法制备。这些是成熟工艺，第一介质层12的厚度为100-400nm；
在第一半导体衬底11的下表面上制备GeO 2缓冲层14，在GeO 2缓冲层14上制备金属膜层13；具体为：采用99.99％的GeO 2粉在1500～1600℃高温下烧结而成圆片。在Ar/H 2(约10％)混合气氛中用射频磁控溅射的方法将GeO 2沉积在基片上。控制溅射气压25～55Pa,基片温度100～800℃，溅射功率70～100W，GeO 2膜厚度约200～300nm。在GeO 2缓冲层12上采用磁控溅射法制备金属膜层13，金属膜层13的厚度为500-5000nm。
如图4所示，本发明的B晶圆20包括：Si衬底21、Ge衬底或SiC衬底等，第二介质层23；其制备方法为：
在Si衬底12表面制备第二介质层23作为埋氧层；具体的制备方法为：
采用N 2、SiH 4、NH 3、HCl 4、H 2Cl 2中的几种气体作为反应气体，采用PECVD法在300-500℃范围内制备出第二介质层23。
如图5所示，本发明的B晶圆20包括：Si衬底21、SiO 2层22和第二介质层23；其制备方法为：
在Si衬底12表面制备SiO 2层22，在SiO 2层22表面制备第二介质层23；进一步，第二介质层的厚度为100-400nm。
如图6所示，本发明的单晶XOI复合晶圆包括Si衬底31、介质层33、半导体薄膜层34，其基于如图2所示的A晶圆和如图4所示的B晶圆制得，具体制备方法为：
将A晶圆、B晶圆上顶层的第一介质层与第二介质层之间进行键合，使A晶圆、B晶圆紧密结合；
在复合晶圆的表面没有金属膜层的部分制备一层金属膜层，该步骤可选也可不选；
在A晶圆侧面的金属膜层处刻蚀微裂纹或微孔洞；
在A晶圆下表面的金属膜层上制备一个金属带；进一步，金属带的制备方法可以采用激光焊接等方式。
拉动金属带或使用真空吸附的方法，使半导体衬底在微裂纹或微孔洞处横向晶裂，晶裂后的半导体薄膜层转移到带有埋氧层的Si衬底、Ge衬底、SiC衬底等半导体衬底上，得到单晶XOI复合晶圆；单晶XOI复合晶圆的结构依次为Si衬底、Ge衬底、SiC衬底等半导体衬底、埋氧层和半导体薄膜层，半导体薄膜层的厚度为100-500nm。
当选择在复合晶圆的表面没有金属膜层的部分制备一层金属膜层时，在使用金属带剥离去除部分半导体衬底和金属膜层后，需通过化学腐蚀和机械磨抛法将半导体薄膜层进行研磨，并将残留的金属膜层腐蚀掉，得到高质量的XOI单晶薄膜层表面。
如图7所示，本发明的单晶XOI复合晶圆包括Si衬底31、介质层33、半导体薄膜层34，其基于如图3所示的A晶圆和如图4所示的B晶圆制得，具体制备方法同上。
如图8所示，本发明的单晶XOI复合晶圆包括Si衬底31、SiO 2层22、介质层33、半导体薄膜层34，其基于如图2所示的A晶圆和如图5所示的B晶圆制得，具体制备方法同上。
如图9所示，本发明的单晶XOI复合晶圆包括Si衬底31、SiO 2层22、介质层33、半导体薄膜层34，其基于如图3所示的A晶圆和如图5所示的B晶圆制得，具体制备方法同上。
本发明的优点为：
本发明可将半导体衬底以晶裂的方式形成一层半导体薄膜层，晶裂后的半导体薄膜层通过介质层键合的方式转移到另一衬底(Si基或SiC基衬底)上，实现高质量、大面积、低成本化合物半导体单晶薄膜层在XOI衬底上的制备；由于半导体衬底一般都比较贵，例如，一个高品质的2寸单晶GaN衬底价格为数千美元，采用本发明的转移方法可以从半导体衬底上分离出多层半导体薄膜层，大大节约半导体工业制造成本，从而促进XOI上半导体器件的工业应用，与传统的smartcut相比，通过晶裂得到的晶面表面平整，可以直接在上面进行外延生长或者进行芯片制程，无须抛光研磨工序。
本发明考虑到结构和器件性能两方面的实际要求，各层厚度、制造工艺可在一定范围内，根据具体材料和器件指标进行调整；在满足相应工艺可实现的前提下，实现化合物半导体薄膜的转移及复合晶圆制备。
本发明的GeO 2可以防止Ni离子扩散入半导体衬底中，选择Ni或则Cr金属作为金属薄膜的原因为Ni或则Cr金属薄膜在制备过程中，是在高温下，由于Ni或则Cr金属的热膨胀系数与化合物半导体差距较大，且延伸性一般，因此冷却到室温时，会在金属层与半导体衬底界面处产生一个拉力，当出现一个沟槽的缺陷时，在外界拉力下，容易从沟槽处横向晶裂。同时由于半导体衬底比较脆，金属层比较坚硬，金属层附着在半导体层上，会对半导体衬底及键合界面起到一个保护作用，当拉动时，不会使剥离的半导体衬底纵向裂成碎片。
本发明中采用相同的介质层或者具有同族元素的介质层是因为同族元素间以原子间力的方式键合，可以使得所制备的复合晶圆在后续外延工艺过程中的承受上千度高温。
以上仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种半导体薄膜层的转移方法，其特征在于，包括：
    在第一半导体衬底的上表面上制备第一介质层、下表面上制备金属膜层；
    在第二半导体衬底上制备第二介质层；
    将所述第一介质层和第二介质层键合，使所述第一半导体衬底和第二半导体衬底相结合；
    在所述第一半导体衬底的侧面刻蚀沟槽；
    对所述第一半导体衬底的下表面金属膜层施加外力，使所述第一半导体衬底在所述沟槽处横向晶裂，晶裂后的半导体薄膜层转移到所述第二半导体衬底上。
  2. 如权利要求1所述的转移方法，其特征在于，所述第一半导体衬底包括单晶GaAs衬底、单晶Ge衬底、单晶Si衬底、单晶GaN衬底和单晶InP衬底中的一种；
    所述金属膜层与第一半导体衬底之间设有缓冲层，所述金属膜层包括Ni层和Cr层中的一种。
  3. 如权利要求1所述的转移方法，其特征在于，所述第二半导体衬底包括Si衬底、Ge衬底和SiC衬底中的一种；
    所述第一介质层或第二介质层包括Si 3N 4层、SiO 2层、Al 2O 3层和AlN层中的一种或多种，所述第二介质层作为所述第二半导体衬底的埋氧层；
    所述第一介质层和第二介质层选用相同的介质层，或者含有同族元素。
  4. 如权利要求1所述的转移方法，其特征在于，在第一介质层和第二介质层键合之后、在所述第一半导体衬底的侧面刻蚀沟槽之前，还包括：
    在复合晶体的表面没有金属膜层的部分制备一层金属膜层。
  5. 如权利要求1所述的转移方法，其特征在于，所述沟槽为微裂纹或微孔洞，所述微裂纹或微孔洞的尖端深入至所述第一半导体衬底的侧面上且在所述第一半导体衬底的侧面形成数纳米的刻痕，所述微裂纹或微孔洞的尖端与所述第一半导体衬底的上表面之间的半导体衬底为晶裂后的所述半导体薄膜层。
  6. 如权利要求1所述的转移方法，其特征在于，所述对所述第一半导体衬底的下表面金属膜层施加外力，使所述第一半导体衬底在所述沟槽处横向晶裂；包括：
    在所述第一半导体衬底的下表面金属膜层上制备一个金属带；
    拉动所述金属带，使所述第一半导体衬底在所述沟槽处横向晶裂；
    或者，
    在所述第一半导体衬底的下表面金属膜层上施加一个真空吸附拉力；
    通过所述真空吸附拉力，使所述第一半导体衬底在所述沟槽处横向晶裂。
  7. 一种基于如权利要求1-6中任一项所述的转移方法的复合晶圆的制备方法，其特征在于，包括：
    制备A晶圆：
    在第一半导体衬底的上表面上制备第一介质层，作为单晶XOI复合晶圆的埋氧层；
    在第一半导体衬底的下表面上制备金属膜层；
    制备B晶圆：
    在第二半导体衬底的表面上制备第二介质层，作为单晶XOI复合晶圆的埋氧层；
    制备单晶XOI复合晶圆：
    将A晶圆、B晶圆上顶层的第一介质层与第二介质层之间进行键合，使A晶圆、B晶圆紧密结合；
    在A晶圆的侧面刻蚀微裂纹或微孔洞；
    在A晶圆下表面的金属膜层上制备金属带或采用真空吸附的方法施加横向拉力；
    在横向拉力的作用下使所述第一半导体衬底在所述微裂纹或微孔洞处横向晶裂，晶裂后的半导体薄膜层转移到带有埋氧层的第二半导体衬底上，得到单晶XOI复合晶圆；所述单晶XOI复合晶圆的结构依次为第二半导体衬底、埋氧层和半导体薄膜层。
  8. 如权利要求7所述的制备方法，其特征在于，所述半导体薄膜层的厚度为100-500nm，所述第一介质层、第二介质层的厚度为50-400nm。
  9. 如权利要求7所述的制备方法，其特征在于，在剥离去除半导体薄膜层后，剩余的第一半导体衬底和金属膜层可重复上述制备方法，分为多个半导体薄膜层用于制备成为多个XOI。
  10. 如权利要求7所述的制备方法，其特征在于，当在复合晶圆的表面 没有金属膜层的部分制备一层金属膜层时：
    在使用剥离去除部分半导体衬底和金属膜层后，采用磨抛法将所述XOI表面的金属层研磨去除。
PCT/CN2019/100757 2019-08-13 2019-08-15 一种半导体薄膜层的转移方法及复合晶圆的制备方法 WO2021026872A1 (zh)

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