CN107768347A - GaN与Si异质键合结构 - Google Patents

GaN与Si异质键合结构 Download PDF

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CN107768347A
CN107768347A CN201711066953.8A CN201711066953A CN107768347A CN 107768347 A CN107768347 A CN 107768347A CN 201711066953 A CN201711066953 A CN 201711066953A CN 107768347 A CN107768347 A CN 107768347A
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gan
gaox
films
bonding structures
heterogeneous bonding
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王鑫华
黄森
魏珂
刘新宇
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Recrystallisation Techniques (AREA)

Abstract

一种GaN与Si异质键合结构，包括：GaN材料层，设置在衬底上；Si材料层；以及辅助键合层，设置在所述GaN材料层和Si材料层之间，用于GaN材料层和Si材料层的异质键合，所述辅助键合层为GaOx薄膜。

Description

GaN与Si异质键合结构
技术领域
本发明涉及半导体器件领域，具体涉及一种GaN与Si异质键合结构。
背景技术
当前业界认为化合物电子的未来不在于代替硅，而在于通过硅基技术实现与化合物半导体的异质集成进而发挥二者的组合优势，其中兼容CMOS工艺的GaN-to-Si异质集成是重要技术途径。目前传统的GaN与Si异质键合方案面临兼容CMOS工艺的新挑战，其主要难点在于：1、需承受CMOS线高温工艺(～1000℃)，且无高温污染风险；2、异质材料光刻平面高度差H小于1.5μm。由于GaN与Si较大的晶格失配和热膨胀失配，且抛光后难以获得足够光滑的表面，使得GaN难以直接键合于Si材料。
发明内容
鉴于上述技术问题，为了克服上述现有技术的不足，本发明提出了GaN与Si异质键合结构及制作方法。
根据本发明的一个方面，提供了一种GaN与Si异质键合结构，包括：GaN材料层，设置在衬底上；Si材料层；以及辅助键合层，设置在所述GaN材料层和Si材料层之间，用于GaN材料层和Si材料层的异质键合，所述辅助键合层为GaOx薄膜。
在一些实施例中，GaOx薄膜中1≤X≤1.7。
在一些实施例中，GaOx薄膜为单晶、多晶或非晶态。
在一些实施例中，GaOx薄膜键合表面的表面粗糙度Rq满足：0.3nm≤Rq≤0.8nm。
在一些实施例中，GaOx薄膜厚度tw满足：10nm≤tw≤500nm。
在一些实施例中，GaOx薄膜的生长温度T满足：400℃≤T≤800℃。
从上述技术方案可以看出，本发明具有以下有益效果：
采用GaOx作为辅助层用于满足键合辅助层材料耐超高温和无污染的需求，可部分补偿GaN晶圆曲翘，缓解热应力失配，降低了传统键合工艺对材料表面的粗糙度要求，满足GaN与Si异质集成中兼容CMOS工艺需求。
附图说明
图1为本发明实施例中GaN与Si异质键合结构的截面示意图；
图2为本发明图1中GaN与Si异质键合结构的制作流程图。
具体实施方式
本发明某些实施例于后方将参照所附附图做更全面性地描述，其中一些但并非全部的实施例将被示出。实际上，本发明的各种实施例可以许多不同形式实现，而不应被解释为限于此数所阐述的实施例；相对地，提供这些实施例使得本发明满足适用的法律要求。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
鉴于GaN难以直接键合于Si材料，本发明采用中间介质辅助的方式实现异质键合，经研究发现辅助键合层采用PdIn3、AuGe、NiAu、ZnSSe、HSQ-SiO2、CVD-SiO2等均可实现GaN和Si的键合，但采用该些材料介质时，其或不能承受CMOS线高温工艺，或存在金属和气体污染风险。而采用GaOx作为辅助键合层可以获得较好的键合效果的同时辅助键合层材料耐超高温和无污染的需求。
图1示出了本发明实施例中GaN与Si异质键合结构的结构的截面示意图，如图1所示，GaN与Si异质键合结构100包括GaN材料层30、Si材料层10以及设置在它们之间的GaOx薄膜20。
GaOx薄膜20作为辅助键合层，用于GaN材料层和Si材料层的异质键合。其中GaOx薄膜中1≤X≤1.7，例如可以采用Ga2O3薄膜。
其中，GaOx薄膜20键合表面的表面粗糙度Rq满足：0≤Rq≤0.8nm，所述GaOx薄膜厚度tw满足：10nm≤tw≤500nm。采用其他辅助键合层来进行GaN与Si的键合时，设置在GaN材料层上的其他辅助键合层的键合表面的表面粗糙度需要小于0.3nm，工艺条件要求苛刻，而采用GaOx薄膜作为辅助键合层时，其键合表面粗糙度要求不高，只要不超过0.8nm即能实现键合。
以Ga2O3薄膜作为辅助键合层为例，结合如下表1，介绍采用GaOx薄膜作为辅助键合层具有以下优势。
满足兼容CMOS工艺的耐高温要求，Ga2O3熔点大于1000℃，所含元素为系统本征元素，无污染风险；
GaN晶格常数小于Ga2O3和Si，Ga2O3薄膜作为辅助键合层可以部分补偿GaN晶圆曲翘；
Ga2O3硬度较GaN低，且为两性氧化物，易腐蚀，容易实施CMP(化学机械抛光)；
Ga2O3热膨胀系数介于Si与GaN之间，可以缓解热应力失配，为使用较薄Ga2O3辅助键合层(应力释放层)提供应力余量和可能性；
Ga2O3为羟基“-OH”提供足够的氧悬挂键，易亲水性活化；
Ga2O3薄膜作为辅助键合层可以改善散热(相比SiO2辅助层而言)。
表1 GaN、Si、Ga2O3、SiO2材料的部分可比参数
在一些实施例中，GaN与Si异质键合结构还可以包括衬底40，用于支持GaN材料层30。
本发明另一实施例提供一种GaN与Si异质键合结构的制作方法，图2示出了本发明另一实施例的一种GaN与Si异质键合结构的制作流程图。如图2所示，该制作方法包括以下步骤：
S100在衬底40上外延生长GaN材料层30；
衬底40可以选用绝缘衬底或半导体衬底，例如为Si衬底，SOI衬底等。
S200在GaN材料层30上生长GaOx薄膜20，例如为Ga2O3薄膜。
GaOx薄膜可以采用金属化学气相沉积或溅射方式生长而成，其的生长温度T满足：400℃≤T≤800℃，GaOx薄膜为单晶、多晶或非晶态。
S300对GaOx薄膜20表面依次进行CMP(化学机械抛光)和表面活化处理；
该表面活化处理为亲水性处理，采用酸性溶液或碱性溶液来处理。
经上述处理后，GaOx薄膜20的表面粗糙度Rq满足：0.3nm≤Rq≤0.8nm，所述GaOx薄膜厚度tw满足：10nm≤tw≤500nm。
S400将Si材料层10键合在所述GaOx薄膜20经过处理的表面上。
具体可以包括加压键合及退火的步骤。由此获得GaN与Si异质键合结构。
应注意，附图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本发明实施例的内容。
实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本发明的保护范围。并且上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用，即不同实施例中的技术特征可以自由组合形成更多的实施例。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

1.一种GaN与Si异质键合结构，其特征在于，包括：
GaN材料层，设置在衬底上；
Si材料层；以及
辅助键合层，设置在所述GaN材料层和Si材料层之间，用于GaN材料层和Si材料层的异质键合，
所述辅助键合层为GaOx薄膜。
2.根据权利要求1所述的GaN与Si异质键合结构，其中，所述GaOx薄膜中1≤X≤1.7。
3.根据权利要求1或2所述的GaN与Si异质键合结构，其中，所述GaOx薄膜为单晶、多晶或非晶态。
4.根据权利要求1或2所述的GaN与Si异质键合结构，其中，所述GaOx薄膜键合表面的表面粗糙度Rq满足：0.3nm≤Rq≤0.8nm。
5.根据权利要求1或2所述的GaN与Si异质键合结构，其中，所述GaOx薄膜厚度tw满足：10nm≤tw≤500nm。
6.根据权利要求1或2所述的GaN与Si异质键合结构，其中，所述GaOx薄膜的生长温度T满足：400℃≤T≤800℃。
CN201711066953.8A 2017-10-31 2017-10-31 GaN与Si异质键合结构 Pending CN107768347A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111962155A (zh) * 2020-08-06 2020-11-20 济南量子技术研究院 一种介质层辅助的厚片周期极化铁电晶体制备方法

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CN101997068A (zh) * 2010-08-25 2011-03-30 山东华光光电子有限公司 一种制备GaN基LED的方法
JP2011176093A (ja) * 2010-02-24 2011-09-08 Sumitomo Electric Ind Ltd 発光素子用基板および発光素子
KR20130038703A (ko) * 2011-10-10 2013-04-18 삼성코닝정밀소재 주식회사 수직형 반도체 소자용 기판 및 이의 제조방법
US20140159090A1 (en) * 2012-12-07 2014-06-12 Epistar Corporation light emitting device
US9666677B1 (en) * 2014-12-23 2017-05-30 Soraa Laser Diode, Inc. Manufacturable thin film gallium and nitrogen containing devices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011176093A (ja) * 2010-02-24 2011-09-08 Sumitomo Electric Ind Ltd 発光素子用基板および発光素子
CN101997068A (zh) * 2010-08-25 2011-03-30 山东华光光电子有限公司 一种制备GaN基LED的方法
KR20130038703A (ko) * 2011-10-10 2013-04-18 삼성코닝정밀소재 주식회사 수직형 반도체 소자용 기판 및 이의 제조방법
US20140159090A1 (en) * 2012-12-07 2014-06-12 Epistar Corporation light emitting device
US9666677B1 (en) * 2014-12-23 2017-05-30 Soraa Laser Diode, Inc. Manufacturable thin film gallium and nitrogen containing devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111962155A (zh) * 2020-08-06 2020-11-20 济南量子技术研究院 一种介质层辅助的厚片周期极化铁电晶体制备方法

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Application publication date: 20180306