WO2021022757A1 - 字线驱动电路及存储单元 - Google Patents

字线驱动电路及存储单元 Download PDF

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Publication number
WO2021022757A1
WO2021022757A1 PCT/CN2019/126394 CN2019126394W WO2021022757A1 WO 2021022757 A1 WO2021022757 A1 WO 2021022757A1 CN 2019126394 W CN2019126394 W CN 2019126394W WO 2021022757 A1 WO2021022757 A1 WO 2021022757A1
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WO
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Prior art keywords
terminal
word line
drive circuit
line drive
signal terminal
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PCT/CN2019/126394
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English (en)
French (fr)
Inventor
刘志拯
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP19940798.2A priority Critical patent/EP3933838B1/en
Priority to US17/086,476 priority patent/US20210057017A1/en
Publication of WO2021022757A1 publication Critical patent/WO2021022757A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Definitions

  • the present disclosure relates to the field of storage technology, and in particular to a word line drive circuit and a storage unit.
  • the memory cell generally includes a word line drive circuit, and the word line drive circuit is used to output a high level or a low level to the word line of the memory cell, so as to realize that the memory cell stores logic "1" or logic "0".
  • the word line drive circuit generally includes a P-type transistor T1 and an N-type transistor T2.
  • the first terminal of the P-type transistor T1 is connected to the driving voltage terminal LWL
  • the control terminal is connected to the control signal terminal GWL
  • the second terminal is connected to the word line.
  • the line signal terminal WL is connected
  • the first terminal of the N-type transistor T2 is connected to the low level signal terminal NBS
  • the control terminal is connected to the control signal terminal GWL
  • the second terminal is connected to the word line signal terminal WL.
  • the P-type transistor T1 When the control signal terminal GWL outputs a low level signal, the P-type transistor T1 is turned on, and the word line drive circuit outputs a high level signal to the word line signal terminal WL.
  • the N type transistor The transistor T2 When the control signal terminal GWL outputs a high level signal, the N type transistor The transistor T2 is turned on, and the word line driving circuit outputs a low level signal to the word line signal terminal WL.
  • the thickness of the gate oxide layer of the N-type transistor T2 in the memory cell is becoming thinner and thinner.
  • the word line signal terminal WL is in a high level state for a long time, which will cause the N-type transistor
  • the GIDL phenomenon of transistor T2 Gate Induced Drain Leakage, gate induced drain leakage current, that is, N-type transistor T2 will have leakage current in the direction of the arrow in Figure 1), which will affect the reliability and life of T2, and ultimately affect storage The reliability and life of the unit.
  • a word line drive circuit including a switch transistor and a ring oscillator, a control terminal of the switch transistor is connected to a first control signal terminal, and a first terminal of the switch transistor Connected to the driving voltage terminal, the second terminal of the switching transistor is connected to the word line signal terminal; the power terminal of the ring oscillator is connected to the word line signal terminal, and the ground terminal of the ring oscillator is the word line driving circuit The ground terminal.
  • the ring oscillator includes a plurality of inverters, and the number of the inverters is greater than or equal to 3 and an odd number.
  • the ring oscillator further includes a transmission gate located between the two inverters.
  • the adjacent inverters include a first inverter and a second inverter
  • the transmission gate includes a first N-type transistor and a first P-type transistor
  • the control terminal of the first N-type transistor is connected to the high-level signal terminal, the first terminal is connected to the output terminal of the first inverter, and the second terminal is connected to the input terminal of the second inverter;
  • the control terminal of the type transistor is connected to the low-level signal terminal, the first terminal is connected to the output terminal of the first inverter, and the second terminal is connected to the input terminal of the second inverter.
  • the switch transistor is a PMOS transistor.
  • the word line driving circuit further includes a second N-type transistor, the control terminal of the second N-type transistor is connected to the second control signal terminal, and the first terminal is connected to the word line signal terminal , The second terminal is connected to the ground terminal; wherein the signals of the second control signal terminal and the driving voltage terminal are inverted.
  • the ring oscillator further includes a delay unit, and the delay unit is located between two inverters.
  • the delay unit includes a resistor and a capacitor, and the resistor and the capacitor constitute an RC delay.
  • the word line driving circuit further includes a third N-type transistor, a first terminal of the third N-type transistor is connected to a ground terminal, a control terminal is connected to the first control signal terminal, and a The two ends are connected to the word line signal end.
  • a memory cell including the above-mentioned word line driving circuit.
  • Fig. 1 is a circuit structure diagram of a word line drive circuit in the related art
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of a word line driving circuit of the present disclosure
  • FIG. 3 shows the level state of the word line signal output terminal in the related art
  • FIG. 4 shows the level state of the word line signal terminal in an exemplary embodiment of the word line driving circuit of the present disclosure
  • FIG. 5 is a timing diagram of a ring oscillator transmitting signal in an exemplary embodiment of the word line drive circuit of the present disclosure
  • FIG. 6 is a schematic structural diagram of another exemplary embodiment of the word line drive circuit of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of the word line driving circuit of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another exemplary embodiment of the word line driving circuit of the present disclosure.
  • the word line drive circuit includes a switching transistor T5 and a ring oscillator 1.
  • the control terminal of the switching transistor T5 is connected to the first control signal terminal VCN1, the first terminal of the switching transistor T5 is connected to the driving voltage terminal LWL, and the second terminal of the switching transistor T5 is connected to the word line signal terminal WL; the ring oscillator
  • the power terminal of is connected to the word line signal terminal WL, and the ground terminal GND of the ring oscillator is the ground terminal of the word line drive circuit.
  • the switch transistor may be a PMOS transistor.
  • the ring oscillator 1 may be composed of a plurality of inverters 11 connected end to end, and the number of inverters is an odd number. It should be understood that in other exemplary embodiments, the odd number of inverters may also include other numbers of inverters, for example, 5, 7, 9, etc. Among them, the number of inverters can determine the high-level pulsation frequency and pulsation amplitude of the word line signal terminal WL. For example, the more the number of inverters, the smaller the pulsation frequency and the greater the pulsation amplitude, and vice versa.
  • the present disclosure proposes a word line driving circuit.
  • the word line driving circuit includes a switching transistor and a ring oscillator.
  • the control terminal of the switching transistor is connected to a first control signal terminal, and the first terminal of the switching transistor is connected to a driving voltage terminal.
  • the second terminal of the switch transistor is connected to the word line signal terminal; the power terminal of the ring oscillator is connected to the word line signal terminal, and the ground terminal of the ring oscillator is the ground terminal of the word line drive circuit.
  • the switching transistor T5 When the switching transistor T5 is turned on, the driving voltage terminal LWL outputs a high-level signal to the word line signal terminal WL; when the switching transistor T5 is turned off, the signal output and input of each inverter 11 in the ring oscillator is in the logic
  • the transition between the level "1" and the logic level “0" does not change instantaneously, and the transition has an excessive process.
  • the second N-type transistor T3 and the second N-type transistor T4 have different conduction states, and they have different resistances between the word line signal terminal WL and the ground terminal GND. As a result, the resistance formed by the ring oscillator changes periodically. Therefore, the ring oscillator can pull the high level of the word line signal terminal WL low.
  • the word line drive circuit provided by the present disclosure can fundamentally solve the leakage phenomenon of the N-type transistor T2 in the related art.
  • the inverter may include an N-type transistor T4 and a P-type transistor T3.
  • the control terminal of the N-type transistor T4 forms the input terminal of the inverter, and the first terminal The ground terminal of the ring oscillator is formed, the second terminal forms the output terminal of the inverter;
  • the control terminal of the P-type transistor T3 is connected to the control terminal of the N-type transistor T4, and the first terminal is connected to the word line signal terminal WL ,
  • the second terminal is connected to the second terminal of the N-type transistor T4.
  • FIG. 3 is the level state of the word line signal terminal in the related art
  • FIG. 4 is the level state of the word line signal terminal in an exemplary embodiment of the word line driving circuit of the present disclosure.
  • the control signal terminal GWL outputs a low level signal
  • the transistor T1 is turned on
  • the word line signal terminal WL continues to be a stable high level.
  • the first control signal terminal VCN1 outputs a low-level signal transistor T5 is turned on. Because the resistance formed by the ring oscillator changes periodically, the word line signal terminal WL is periodic Changing high level signal.
  • the resistance between the word line signal terminal WL and the ground terminal GND is the smallest, corresponding to the low level part of the time period T, when the three inverters When the inverters are turned off at the same time, it corresponds to the high level part of the T part.
  • the flip of the three inverters is not necessarily ideal to be turned on or off at the same time, so the corresponding time period T may be a square wave, a sawtooth wave, a triangle wave, etc., but the waveform of the time period T must appear It is periodic and has a low level and a high level.
  • the size of the high level is equal to the size of the word line signal terminal WL, and the size of the low level is smaller than the size of the word line signal terminal WL.
  • the specific value of the low level can be reversed
  • the level switching time of the phase inverter, the number of inverters, the size of the transistor in the inverter, the delay of the connection line, etc. are set. Comparing FIG. 3 and FIG. 4, it can be seen that when the word line signal terminal WL is at a high level, it changes from a constant signal to a square wave signal. Comparing Figure 1 and Figure 2, the function of the ring oscillator in Figure 2 is similar to that of T2 in Figure 1. It can not only realize the conversion of the word line signal terminal WL from low level to high level and then to low level, but also avoid When the word line signal terminal WL continues to be high, the transistor reliability problem is caused.
  • FIG. 5 it is a timing diagram of a ring oscillator transmitting signal in an exemplary embodiment of the word line driving circuit of the present disclosure.
  • the pulse signal transmitted by the ring oscillator has positive and negative overshoot phenomena.
  • the position pointed by the P arrow is the positive overshoot position
  • the position pointed by the N arrow is the negative overshoot position.
  • the word line driving circuit may further include a transmission gate 2, which is arranged between adjacent inverters.
  • the adjacent inverters include a first inverter and a second inverter
  • the transmission gate may include a first N-type transistor T8 and a first P-type transistor T9, and the first N-type transistor T8
  • the control terminal is connected to the high-level signal terminal VDD, the first terminal is connected to the output terminal of the first inverter, and the second terminal is connected to the input terminal of the second inverter; the control of the first P-type transistor T9
  • the terminal is connected to the low-level signal terminal VSS, the first terminal is connected to the output terminal of the first inverter, and the second terminal is connected to the input terminal of the second inverter.
  • the first N-type transistor T8 and the first P-type transistor T9 can form a filter structure, thereby avoiding the positive overshoot and negative overshoot in Figure 6, and at the same time, by setting the size of T8 and T9, the oscillator can be controlled to generate The period of the pulse signal.
  • the first N-type transistor has no voltage drop to the high level
  • the first P-type transistor has no voltage drop to the low level, thereby avoiding signal attenuation in the ring oscillator.
  • the ring oscillator may further include a delay unit, the delay unit is located between two adjacent inverters, the delay unit includes a resistor and a capacitor, the resistor and the capacitor form an RC delay.
  • the adjacent inverters include a first inverter and a second inverter, the output terminal of the first inverter is connected to the input terminal of the second inverter, and the RC filter circuit may It includes a resistor R and a capacitor C.
  • the resistor R is connected in series between the first inverter and the second inverter; the capacitor C is connected between the input terminal of the second inverter and the ground terminal. This setting can also avoid the occurrence of positive overshoot and negative overshoot in Figure 5.
  • the word line driving circuit may further include a second N-type transistor T7.
  • the control terminal of the second N-type transistor T7 is connected to the second control signal terminal LWLB, the first terminal is connected to the word line signal terminal WL, and the second terminal is connected to ground. Terminal GND; wherein the signals of the second control signal terminal LWLB and the driving voltage terminal LWL are inverted.
  • the second N-type transistor T7 is turned on in response to the high level of the second control signal terminal LWLB to set the word line signal terminal WL to a low level.
  • the T7 tube will be closed, and the T7 tube will control the initial working state of the word line signal terminal WL.
  • the word line drive circuit further includes a third N-type transistor T6.
  • the first terminal of the third N-type transistor T6 is connected to the ground terminal GND, and the control terminal is connected to the first terminal GND.
  • the signal terminal VCN1 is controlled, and the second terminal is connected to the word line signal terminal WL.
  • the first control signal terminal VCN1 turns to a high level.
  • the third N-type transistor T6 is turned on under the action of the first control signal terminal VCN1, so that the word line signal terminal WL is connected to the ground terminal GND, thereby increasing the zero setting speed of the word line signal terminal WL.
  • the word line driving circuit can reduce the GIDL phenomenon generated on the N-type transistor T6 by periodically reducing the voltage of the word line signal terminal WL, thereby Improve the reliability and life of N-type transistor T6.
  • This exemplary embodiment also provides a memory cell including the above-mentioned word line driving circuit.
  • the memory cell provided by this exemplary embodiment has the same technical features and working principles as the above-mentioned word line driving circuit, and the above content has been described in detail, and will not be repeated here.

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Abstract

涉及存储技术领域，提出一种字线驱动电路，该字线驱动电路包括开关晶体管（T5）和环形振荡器（1），所述开关晶体管（T5）的控制端连接第一控制信号端（VCN1），所述开关晶体管（T5）的第一端连接驱动电压端（LWL），所述开关晶体管（T5）的第二端连接字线信号端（WL）；所述环形振荡器的电源端接所述字线信号端（WL），所述环形振荡器（1）的接地端（GND）为所述字线驱动电路的接地端。提供的字线驱动电路可以增强其器件可靠性和寿命。

Description

字线驱动电路及存储单元
交叉引用
本公开要求于2019年8月6日提交的申请号为201910720182.2、名称为“字线驱动电路及存储单元”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及存储技术领域，尤其涉及一种字线驱动电路及存储单元。
背景技术
存储单元一般包括有字线驱动电路，字线驱动电路用于向存储单元的字线输出高电平或者低电平，从而实现存储单元存储逻辑“1”或者逻辑“0”。
相关技术中，如图1所示，为相关技术中字线驱动电路的一种电路结构图。相关技术中，字线驱动电路一般包括有P型晶体管T1和N型晶体管T2，P型晶体管T1的第一端与驱动电压端LWL连接，控制端与控制信号端GWL连接，第二端与字线信号端WL连接，N型晶体管T2的第一端与低电平信号端NBS连接，控制端与控制信号端GWL连接，第二端与字线信号端WL连接。当控制信号端GWL输出低电平信号时，P型晶体管T1导通，该字线驱动电路向字线信号端WL输出高电平信号，当控制信号端GWL输出高电平信号时，N型晶体管T2导通，该字线驱动电路向字线信号端WL输出低电平信号。
然而，随着储存单元尺寸的小型化，存储单元中N型晶体管T2的栅氧化层厚度也越来越薄，同时由于字线信号端WL长期处于较高的电平状态，从而会引起N型晶体管T2的GIDL现象(Gate Induced Drain Leakage，栅诱导漏极泄漏电流，即N型晶体管T2会出现沿图1中箭头方向的漏电流)，进而会影响T2的可靠性和寿命，进而最终影响存储单元的可靠性和寿命。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种字线驱动电路，该字线驱动电路包括开关晶体管和环形振荡器，所述开关晶体管的控制端连接第一控制信号端，所述开关晶体管的第一端连接驱动电压端，所述开关晶体管的第二端连接字线信号端；所述环形振荡器的电源端接所述字线信号端，所述环形振荡器的接地端为所述字线驱动电路的接地端。
本公开的一种示例性实施例中，所述环形振荡器包括多个反相器，所述反相器的个数大于等于3且为奇数。
本公开的一种示例性实施例中，所述环形振荡器还包括传输门，所述传输门位于两个反相器之间。
本公开的一种示例性实施例中，相邻的所述反相器包括第一反相器和第二反相器，所述传输门包括：第一N型晶体管和第一P型晶体管，第一N型晶体管的控制端连接高电平信号端，第一端与所述第一反相器的输出端连接，第二端与所述第二反相器的输入端连接；第一P型晶体管的控制端连接低电平信号端，第一端与所述第一反相器的输出端连接，第二端与所述第二反相器的输入端连接。
本公开的一种示例性实施例中，所述开关晶体管为PMOS晶体管。
本公开的一种示例性实施例中，所述字线驱动电路还包括第二N型晶体管，第二N型晶体管的控制端连接第二控制信号端，第一端连接所述字线信号端，第二端连接接地端；其中，所述第二控制信号端和所述驱动电压端的的信号反相。
本公开的一种示例性实施例中，所述环形振荡器还包括延迟单元，所述延迟单元位于两个反相器之间。
本公开的一种示例性实施例中，所述延迟单元包括电阻和电容，所述电阻和所述电容构成RC延迟。
本公开的一种示例性实施例中，所述字线驱动电路还包括第三N型晶体管，第三N型晶体管的第一端连接接地端，控制端连接所述第一控制信号端，第二端连接所述字线信号端。
根据本公开的一个方面，提供一种存储单元，该存储单元包括上述的字线驱动电路。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中字线驱动电路的一种电路结构图；
图2为本公开字线驱动电路一种示例性实施例的结构示意图；
图3为相关技术中字线信号输出端的电平状态；
图4为本公开字线驱动电路一种示例性实施例中字线信号端的电平状态；
图5为本公开字线驱动电路一种示例性实施例中环形振荡器传输信号的时序图；
图6为本公开字线驱动电路另一种示例性实施例的结构示意图；
图7为本公开字线驱动电路另一种示例性实施例的结构示意图；
图8为本公开字线驱动电路另一种示例性实施例的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例首先提供一种字线驱动电路，如图2所示，为本公开一种示例性实施例的结构示意图，该字线驱动电路包括开关晶体管T5和环形振荡器1，所述开关晶体管T5的控制端连接第一控制信号端VCN1，所述开关晶体管T5的第一端连接驱动电压端LWL，所述开关晶体管T5的第二端连接字线信号端WL；所述环形振荡器的电源端接所述字线信号端WL，所述环形振荡器的接地端GND为所述字线驱动电路的接地端。其中，所述开关晶体管可以为PMOS晶体管。
本示例性实施例中，如图2所示，环形振荡器1可以由多个首尾相连的反相器11组成，且反相器的数量为奇数个。应该理解的是，在其他示例性实施例中，奇数个所述反相器还可以包括其他数量的反相器，例如，5个、7个、9个等。其中，反相器的数量可以决定字线信号端WL上高电平的脉动频率和脉动幅度，例如反相器的数量越多，脉动频率越小，脉动幅度越大，反之亦然。
本公开提出一种字线驱动电路该字线驱动电路包括开关晶体管和环形振荡器，所述 开关晶体管的控制端连接第一控制信号端，所述开关晶体管的第一端连接驱动电压端，所述开关晶体管的第二端连接字线信号端；所述环形振荡器的电源端接所述字线信号端，所述环形振荡器的接地端为所述字线驱动电路的接地端。当开关晶体管T5导通时，驱动电压端LWL向字线信号端WL输出高电平信号；当开关晶体管T5关断时，由于环形振荡器中每个反相器11输出和输入的信号在逻辑电平“1”与逻辑电平“0”之间的转变并不是瞬间变化的，其转变具有一个过度过程。反相器在不同电位作用下，第二N型晶体管T3和第二N型晶体管T4具有不同的导通状态，其在字线信号端WL和接地端GND之间具有不同电阻。从而使得环形振荡器所形成的电阻会发生周期性变化。因此，环形振荡器可以将字线信号端WL的高电平拉低。本公开提供的字线驱动电路可以从根本上解决相关技术中N型晶体管T2漏电现象。
本示例性实施例中，如图2所示，所述反相器可以包括N型晶体管T4和P型晶体管T3，N型晶体管T4的控制端形成所述反相器的输入端，第一端形成环形振荡器的接地端，第二端形成所述反相器的输出端；P型晶体管T3的控制端连接所述N型晶体管T4的控制端，第一端连接所述字线信号端WL，第二端连接所述N型晶体管T4的第二端。
如图3、4所示，图3为相关技术中字线信号端的电平状态，图4为本公开字线驱动电路一种示例性实施例中字线信号端的电平状态。图1、3中，在时间段T，控制信号端GWL输出低电平信号晶体管T1导通，字线信号端WL持续为稳定的高电平。在图2、4中，在时间段T，第一控制信号端VCN1输出低电平信号晶体管T5导通，由于环形振荡器形成的电阻发生周期性变化，因此，字线信号端WL为周期性变化的高电平信号。具体的，参考图2和图4，当3个反相器同时导通时，字线信号端WL到接地端GND之间的电阻最小，对应时间段T部分的低电平部分，当3个反相器同时关断时，对应时间段T部分的高电平部分。实际电路中，3个反相器的翻转并不一定是理想的同时开或同时关，因此对应时间段T部分有可能是方波、锯齿波、三角波等，但时间段T部分的波形一定呈现周期性，且有一低电平和一高电平，高电平的大小等于字线信号端WL的大小，低电平的大小小于字线信号端WL的大小，低电平的具体值可以通过反相器的电平翻转时间、反相器的个数、反相器中晶体管的尺寸、连接线的延迟等来设置。对比图3和图4可以看出，字线信号端WL为高电平时，由一个恒定信号变为了一个方波信号。对比图1和图2，图2中环形振荡器的作用类似图1中T2的作用，既能实现字线信号端WL的低电平到高电平再到低电平的转换，又避免了字线信号端WL持续为高时带来的晶体管可靠性问题。
本示例性实施例中，如图5所示，为本公开字线驱动电路一种示例性实施例中环形 振荡器传输信号的时序图。环形振荡器传输的脉冲信号存在正向过冲和负向过冲现象。如图5所示，P箭头所指位置即为正向过冲位置，N箭头所指位置即为负向过冲位置。正向过冲和负向过冲位置存在过冲电压，从而影响字线驱动电路工作的稳定性。
如图6所示，为本公开字线驱动电路另一种示例性实施例的结构示意图。本示例性实施例中，该字线驱动电路还可以包括传输门2，传输门2设置于相邻反相器之间。其中，相邻的所述反相器包括第一反相器和第二反相器，所述传输门可以包括第一N型晶体管T8和第一P型晶体管T9，第一N型晶体管T8的控制端连接高电平信号端VDD，第一端与所述第一反相器的输出端连接，第二端与所述第二反相器的输入端连接；第一P型晶体管T9的控制端连接低电平信号端VSS，第一端与所述第一反相器的输出端连接，第二端与所述第二反相器的输入端连接。第一N型晶体管T8和第一P型晶体管T9可以形成滤波器结构，从而避免图6中正向过冲和负向过冲现象发生，同时通过对T8和T9尺寸的设置，可以控制振荡器产生的脉冲信号的周期。同时，第一N型晶体管对高电平没有压降，第一P型晶体管对低电平没有压降，从而可以避免了环形振荡器中信号的衰减。
如图7所示，为本公开字线驱动电路另一种示例性实施例的结构示意图。本示例性实施例中，该环形振荡器还可以包括延迟单元，所述延迟单元位于两个相邻反相器之间，所述延迟单元包括电阻和电容，所述电阻和所述电容构成RC延迟。相邻的所述反相器包括第一反相器和第二反相器，所述第一反相器的输出端与所述第二反相器的输入端连接，所述RC滤波电路可以包括电阻R和电容C，电阻R串联于所述第一反相器与所述第二反相器之间；电容C连接于所述第二反相器输入端与接地端之间。该设置同样可以避免图5中正向过冲和负向过冲现象发生。
本示例性实施例中，如图8所示，为本公开字线驱动电路另一种示例性实施例的结构示意图。所述字线驱动电路还可以包括第二N型晶体管T7，第二N型晶体管T7的控制端连接第二控制信号端LWLB，第一端连接所述字线信号端WL，第二端连接接地端GND；其中，所述第二控制信号端LWLB和所述驱动电压端LWL的信号反相。第二N型晶体管T7在驱动电压端LWL启动前，响应于第二控制信号端LWLB的高电平导通以将字线信号端WL置为低电平，当驱动电压端LWL为高时，T7管将被关闭，T7管起到控制字线信号端WL初始工作状态的作用。
本示例性实施例中，如图8所示，所述字线驱动电路还包括第三N型晶体管T6，第三N型晶体管T6的第一端连接接地端GND，控制端连接所述第一控制信号端VCN1，第二端连接所述字线信号端WL。当字线信号端WL需要输出低电平信号时，第一控制信号端VCN1转为高电平。此时，第三N型晶体管T6在第一控制信号端VCN1作用下 导通，以使字线信号端WL与接地端GND连接，从而增加字线信号端WL的置零速度。同时，由于字线信号端WL的电压会发生周期性减小，该字线驱动电路可以通过周期性减小字线信号端WL的电压，从而减小对N型晶体管T6产生的GIDL现象，从而提高N型晶体管T6的可靠性和寿命。
本示例性实施例还提供一种存储单元，该存储单元包括上述的字线驱动电路。
本示例性实施例提供的存储单元与上述的字线驱动电路具有相同的技术特征和工作原理，上述内容已经做出详细说明，此处不再赘述。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (10)

  1. 一种字线驱动电路，其中，包括：
    开关晶体管，所述开关晶体管的控制端连接第一控制信号端，所述开关晶体管的第一端连接驱动电压端，所述开关晶体管的第二端连接字线信号端；
    环形振荡器，所述环形振荡器的电源端接所述字线信号端，所述环形振荡器的接地端为所述字线驱动电路的接地端。
  2. 根据权利要求1所述的字线驱动电路，其中，所述环形振荡器包括多个反相器，所述反相器的个数大于等于3且为奇数。
  3. 根据权利要求2所述的字线驱动电路，其中，所述环形振荡器还包括传输门，所述传输门位于两个相邻反相器之间。
  4. 根据权利要求3所述的字线驱动电路，其中，相邻的所述反相器包括第一反相器和第二反相器，所述传输门包括：
    第一N型晶体管，控制端连接高电平信号端，第一端与所述第一反相器的输出端连接，第二端与所述第二反相器的输入端连接；
    第一P型晶体管，控制端连接低电平信号端，第一端与所述第一反相器的输出端连接，第二端与所述第二反相器的输入端连接。
  5. 根据权利要求1所述的字线驱动电路，其中，所述开关晶体管为PMOS晶体管。
  6. 根据权利要求1所述的字线驱动电路，其中，所述字线驱动电路还包括：
    第二N型晶体管，控制端连接第二控制信号端，第一端连接所述字线信号端，第二端连接接地端；
    其中，所述第二控制信号端和所述驱动电压端的信号反相。
  7. 根据权利要求2所述的字线驱动电路，其中，所述环形振荡器还包括延迟单元，所述延迟单元位于两个相邻反相器之间。
  8. 根据权利要求7所述的字线驱动电路，其中，所述延迟单元包括电阻和电容，所述电阻和所述电容构成RC延迟。
  9. 根据权利要求1所述的字线驱动电路，其中，所述字线驱动电路还包括：
    第三N型晶体管，第一端连接接地端，控制端连接所述第一控制信号端，第二端连接所述字线信号端。
  10. 一种存储单元，其中，包括权利要求1-9任一项所述的字线驱动电路。
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