WO2021017206A1 - 电磁屏蔽封装结构及其封装方法 - Google Patents

电磁屏蔽封装结构及其封装方法 Download PDF

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Publication number
WO2021017206A1
WO2021017206A1 PCT/CN2019/113021 CN2019113021W WO2021017206A1 WO 2021017206 A1 WO2021017206 A1 WO 2021017206A1 CN 2019113021 W CN2019113021 W CN 2019113021W WO 2021017206 A1 WO2021017206 A1 WO 2021017206A1
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layer
packaging
electromagnetic shielding
electroplating
base plate
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PCT/CN2019/113021
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English (en)
French (fr)
Inventor
鲍漫
刘怡
龚臻
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江苏长电科技股份有限公司
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Priority to US17/613,054 priority Critical patent/US12033955B2/en
Publication of WO2021017206A1 publication Critical patent/WO2021017206A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention belongs to the field of semiconductor manufacturing, and particularly relates to an electromagnetic shielding packaging structure and a packaging method.
  • the prior art In order to solve the problem of electromagnetic interference, the prior art often pastes a metal cover or plating a metal layer on the outer surface of the package to shield the emission and reception of electromagnetic waves.
  • the substrate processing technology uses a copper clad laminate as a carrier. After exposure, development, electroplating, etching, etc.
  • the functional line is reserved within the cutting line, and the grounding line extends beyond the cutting line to achieve electromagnetic shielding effect.
  • the cost of using a substrate to achieve the shielding effect is very high, and its cost is about 10 times higher than the cost of packaging on a copper base material; in addition, using a substrate as a carrier has low reliability and poor thermal conductivity; the reason is The raw material used for the substrate contains core material and ink. Compared with the package body encapsulated on the base plate of copper material, the reliability is poor, and it can only pass MSL3, and the thermal conductivity is also relatively poor.
  • the purpose of the present invention is to provide an electromagnetic shielding packaging structure and packaging method that solve the above technical problems.
  • an embodiment of the present invention provides an electromagnetic shielding packaging structure packaging method, the method includes: S1, providing a base plate made of copper raw material;
  • electroplating is performed on the electroplating area of the base plate to form an electroplating layer on the base plate;
  • the transition layer includes: a pin, one end is connected to the pin, the other end is a conductive rib extending to the single cutting line, and the etching
  • the electroplating layer, the pins include: function pins and ground pins;
  • the conductive connecting ribs connected to the functional pins are etched from the back of the transition layer to form several grooves at the positions corresponding to the conductive connecting ribs etched away, so that the transition layer excluding the electroplating layer forms a circuit layer;
  • the circuit layer includes: Function pins, ground pins, and conductive ribs respectively connected to each ground pin;
  • step S9 Perform secondary encapsulation from the back of the circuit layer, and the encapsulation area at least includes the groove formed in step S8;
  • step S10 cutting the semi-molded package formed in step S9 from the monomer cutting line to form several monomer packages;
  • step S1 specifically includes:
  • step S2 specifically includes:
  • step S3 specifically includes:
  • the method further includes: using a punch mold or router method to divide the transition layer formed in step S3 into strips.
  • step S7 further includes: using a chemical agent to remove the adhesive layer remaining on the back of the circuit due to the removal of the protective film.
  • the method further includes: the area of the secondary encapsulation further includes: an unplasticized area between the electroplated layers on the back of the circuit layer.
  • the metal protective layer sputtered on the plastic cover of the monomer package is sequentially from the inside to the outside: an inner stainless steel layer, a copper layer, and an outer stainless steel layer.
  • an embodiment of the present invention provides an electromagnetic shielding package structure.
  • the electromagnetic shielding package structure includes a circuit layer made of copper.
  • the circuit layer includes functional pins, ground pins, and respective Conductive ribs that are connected to each ground pin and extend toward the side of the electromagnetic shielding package structure;
  • a shielding cover arranged on the front surface of the circuit layer and forming a cavity between the circuit layer, and the sidewall of the shielding cover extends to the side surface of the circuit layer and is connected to each of the conductive ribs;
  • Electroplating layers on the front and back of the circuit layer are Electroplating layers on the front and back of the circuit layer
  • a chip arranged in the cavity and electrically connected to the functional pin
  • the side wall of the shielding cover extends to the electroplating layer
  • the molding compound is also used to fill the gaps between the electroplating layers.
  • the electromagnetic shielding packaging structure and packaging method of the present invention directly form a transition layer on the base plate of copper raw material, and complete the first encapsulation of the transition layer, and use an etching process to remove and functional pins.
  • the connected conductive connecting ribs are encapsulated and flattened the grooves of the conductive connecting ribs a second time, so that the functional pins are wrapped in the plastic compound, and the grounding pins are electrically connected to the shielding cover on the outer wall of the plastic package through the conductive connecting ribs.
  • the ground pin inside the plastic package body is connected with the shielding metal to realize shielding; the performance of the package body is improved, and the manufacturing cost and the use cost are saved.
  • FIG. 1 is a schematic flowchart of a packaging method of an electromagnetic shielding packaging structure provided by an embodiment of the present invention
  • Figure 2 corresponds to a schematic diagram of the steps of the packaging method shown in Figure 1 of the present invention
  • 3 and 4 are respectively structural schematic diagrams of the connection relationship between conductive ribs and pins during the formation of the electromagnetic shielding package structure of the present invention
  • Figure 5 is a schematic diagram of the structure of a WB package product
  • Figure 6 is a schematic diagram of the structure of FC-type packaged products
  • Figure 7 is a schematic diagram of the structure of SMT packaged products
  • FIG. 8 is a partial structural diagram of the electromagnetic shielding package structure in the forming process in another embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of an electromagnetic shielding packaging structure packaged by the packaging method described in FIG. 8;
  • Fig. 10 is a schematic structural diagram of an electromagnetic shielding package structure packaged by the package method described in Fig. 2.
  • an embodiment of the present invention provides an electromagnetic shielding packaging structure packaging method, the method includes:
  • electroplating is performed on the electroplating area of the base plate 10 to form an electroplating layer 20 on the base plate 10;
  • FIG. 3 mainly shows the conductive ribs in the transition layer; the transition layer at least includes: pins 31. One end is connected to the pin 31, the other end extends to the conductive rib 33 of the single cutting line, and the etched electroplating layer 20; the pin 31 includes: a functional pin 31a and a ground pin 31b;
  • FIG. 4 mainly shows the conductive ribs in the circuit layer formed after the transition layer is processed; the circuit layer 30 at least includes: a functional pin 31a, a ground pin 31b, and connect each ground The conductive connecting rib 33 of the pin 31b;
  • step S10 cutting the semi-molded package formed in step S9 from the monomer cutting line to form several monomer packages;
  • step S1 specifically includes: S1-1, providing copper coil raw materials; the thickness of the copper coil raw materials provided can be selected according to the thickness of the product, because the copper raw materials are made of metal alloys, so it can be improved It is the reliability and heat dissipation of the encapsulated product of the carrier board; S1-2, pickling or alkaline washing pretreatment is performed on the copper surface to clean the copper surface to obtain the base plate 10.
  • This step S1 is to remove lipids and other substances on the copper surface to achieve the purpose of cleaning the copper surface.
  • step S2 specifically includes: S21, pasting a photoresist film on the base plate 10; the photoresist film is usually pasted on the front and back sides of the base plate 10; the photoresist film may be a dry photoresist film or Wet photoresist film; S22, remove part of the photoresist film through the exposure machine and the developing machine to expose the electroplating area on the base plate 10; in this step, pattern exposure, development and partial photoresist removal are performed on the position where the photoresist film is pasted After filming, the copper surface of the base plate 10 is exposed; S23, electroplating nickel, palladium, gold or silver in the electroplating area of the base plate 10; S24, peeling off the remaining photoresist film on the base plate 10.
  • the remaining photoresist film on the base plate 10 can be stripped off with the help of a stripping liquid.
  • the purpose of providing the conductive rib 33 in the present invention is to connect the ground pin 31b and the shielding cover 70 through the conductive rib 33 to achieve shielding.
  • the conductive connecting rib 33 connected to 31a needs to be etched away in the subsequent part.
  • the conductive connecting rib 33 connected to the functional pin 31a is excluded from the electroplating area, that is, the conductive connection connected to the functional pin 31a during electroplating
  • the rib 33 does not need to be electroplated, but the conductive connecting rib connected to the ground pin 31b needs to be electroplated when it is divided into a plating area.
  • step S3 specifically includes: S31. Pasting a photoresist film on the base plate 10 on which the electroplating layer 20 is formed; the photoresist film can also It is dry and wet photoresist film or wet photoresist film; S32, through the exposure machine and developing machine to remove part of the photoresist film to expose the etching area; in this step, pattern exposure, development and removal of part of the photoresist film are performed on the position of the photoresist film.
  • the transition layer may also include the base island 35; it will be described in the following content.
  • step S3 and step S4 the method further includes: using a punch mold or router method to divide the transition layer formed in step S3 into strips to facilitate subsequent cutting.
  • the components may be connected to each other or disconnected.
  • a high temperature resistant protective film 40 is pasted on the back of the transition layer, and the high temperature resistant protective film 40 is pasted on the back of the transition layer, and The gaps between the electroplating layers 20 on the back of the transition layer are filled.
  • the various parts are connected through the protective film to facilitate subsequent encapsulation.
  • step S5 as shown in FIG. 5, for WB packaged products, the chip 50 is installed on the front surface of the base island 35 by bonding glue, and then the chip 50 is electrically connected to the functional pin 31a by means of the bonding wire 51.
  • the chip 50 is electrically connected to the pins through the bump 53.
  • the chip 50 here is a passive component such as an inductor, a capacitor, a resistor, or a sensor, which is directly soldered on the functional pin 31a.
  • step S6 the first encapsulation is performed from the front side of the transition layer, which can be molded with epoxy resin on the front side of the transition layer, and the molding compound 60 fills all the gaps above the high temperature resistant protective film 40.
  • Step S7 corresponds to step S5. After the first encapsulation is completed, the temporarily pasted high-temperature resistant protective film 40 needs to be removed to facilitate the second encapsulation.
  • step S7 further includes: using a chemical agent to remove the adhesive layer remaining on the back of the circuit due to the removal of the protective film.
  • the chemical agents such as potassium hydroxide and organic amine, are mixed with alkaline lotion.
  • step S8 on the back of the transition layer, the conductive connecting rib 33 connected to the functional pin 31a has not been electroplated, and is still a copper surface.
  • the conductive connecting rib 33 at this position can be etched away with an etching solution, and the grounding pin 31b is retained
  • the connected conductive ribs 33 in this way, the truncated functional pin 31a is connected to the side wall, and only the grounding pin 31b is connected to the side wall through the conductive rib 33 to form the circuit layer 30; in this step, the corresponding position is etched away
  • a number of grooves 62 are formed on the back of the product that is not finally formed in step S7 and corresponding to the positions of the conductive ribs that have been etched away.
  • the bottom of each groove 62 exposes the plastic molding compound 60 encapsulated for the first time, and At least one side wall of each groove 62 exposes the functional pin 31a.
  • step S9 the secondary encapsulation is performed from the back surface of the circuit layer 30, and there are two encapsulation methods.
  • all the gaps above the back surface of the circuit layer 30 are filled with a plastic molding compound 60.
  • the filled area includes each groove 62 formed in step S8 and the area between the back of the circuit layer 30 and the electroplating layer 20 that is not covered with the molding compound 60.
  • pass The epoxy resin plastic encapsulation prevents the sidewall surface of the chip 50 package from being exposed, so as to facilitate subsequent metal shielding.
  • the filled area only includes each groove 62 formed in step S8, and the unplasticized area between the electroplated layer 20 on the back of the circuit layer 30 is not re-molded.
  • the epoxy resin plastic encapsulation can also prevent the sidewall surface of the chip 50 package from being exposed, so as to facilitate subsequent metal shielding.
  • Step S10 use a cutting machine to cut the product into individual pieces from the strip arrangement.
  • the side wall of the single product is blocked by the plastic packaging material to prevent the functional pin 31a from being electrically connected to the side wall, and the conductive rib 33
  • the conductive connecting rib 33 extends to the side wall of a single product to ensure that the ground pin 31 b is electrically connected to the side wall, so that the subsequent ground pin 31 b is connected to the metal shield 70.
  • the method further includes cleaning the monomer package to remove foreign matter and/or grease on the surface of the monomer package.
  • the cleaning methods include alcohol soaking and ultrasonic cleaning.
  • the plastic cover of the product includes 5 surfaces except the back surface.
  • the metal protective layer includes 3 layers, which are successively from the inside to the outside. :Inner stainless steel layer, copper layer and outer stainless steel layer; the purpose of sputtering the inner stainless steel layer is to increase the bonding force with the molding compound, the thickness of this layer is usually 0.1um, and the purpose of sputtering the outer stainless steel layer is to protect
  • the middle copper layer is not oxidized; the thickness of the middle copper layer is usually 5-9um, and the thickness of the outer stainless steel layer is usually 0.1-0.3um; after the metal protective layer is sputtered on the outer wall of the single package, it is connected to ground
  • the conductive connecting ribs 33 of the pins 31b extend to the sidewall surface, so that the functional pins 31b can be electrically connected to the shielding cover 70 made of metal through the conductive connecting ribs 33.
  • an embodiment of the present invention provides an electromagnetic shielding package structure manufactured by the method described above;
  • the electromagnetic shielding package structure includes: a circuit layer made of copper 30.
  • the circuit layer includes functional pins 31a, ground pins 31b, and conductive ribs 33 respectively connected to each ground pin 31b and extending toward the side of the electromagnetic shielding package structure;
  • a shielding cover 70 with a cavity is formed between the circuit layers 30.
  • the side walls of the shielding cover 70 extend to the side of the circuit layer 30 and connect each of the conductive ribs 33;
  • the material 60 isolates the shielding cover 70 from contacting the functional pins 31a.
  • the sidewall of the shielding cover 70 extends to the electroplating layer 20; the molding compound 60 is also used to fill the gaps between the electroplating layers 20.
  • the transition layer is directly formed on the base plate of copper raw material, the transition layer is encapsulated for the first time, and the etching process is used to remove the contact with the functional pins.
  • Conductive connecting ribs and then encapsulate and flatten the grooves of the conductive connecting ribs, so that the functional pins are wrapped in the plastic compound, and the grounding pins are electrically connected to the shielding cover on the outer wall of the plastic package through the conductive connecting ribs, thereby making the plastic package body
  • the internal grounding pin is connected with the shielding metal to realize shielding; improve the performance of the package body, save manufacturing cost and use cost.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明揭示了一种电磁屏蔽封装结构及封装方法，电磁屏蔽封装结构的封装方法包括：提供铜原材质的基础板材，经过两次光阻膜作业后形成过渡层，过渡层中包括连接功能引脚至外侧壁的导电连筋，之后贴装芯片进行一次包封，并在其后蚀刻掉连接功能引脚至外侧壁的导电连筋，再对蚀刻部位进行二次包封，在切割形成单体后，通过塑封料阻隔功能引脚与外侧壁连接，仅保留接地引脚与外侧壁通过导电连筋连接；如此，在溅镀金属保护层后，仅使得导电连筋与屏蔽罩导通，形成电磁屏蔽封装结构。本发明提升封装体的性能、节约制造成本及使用成本。

Description

电磁屏蔽封装结构及其封装方法
本申请要求了申请日为2019年7月26日，申请号为201910681409.7，发明名称为“电磁屏蔽封装结构及其封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于半导体制造领域，尤其涉及一种电磁屏蔽封装结构及封装方法。
背景技术
随着电子产品多功能化和小型化的潮流，高密度微电子组装技术在新一代电子产品上逐渐成为主流。为了配合新一代电子产品的发展，尤其是智能手机、掌上电脑、超级本等产品的发展，使得集成电路封装也向微小化、高密度、高功率、高速度的方向发展。而随着电子部件变得更小、并且在工作频率更高，由于高频芯片在运输和传输是会产生很强的电磁波，往往会对封装内的其他芯片或者封装外的电子部件的造成不期望的干扰或噪声。加上电子部件的密度过高，电子部件之间的信号传输线路的距离越来越近，使得来自集成电路封装外部或内部的芯片之间的电磁干扰情形也日益严重。同时也会降低集成电路封的电性品质和散热效能。
为解决电磁干扰问题，现有技术往往会在封装体外表面粘贴金属盖或是镀上金属层来屏蔽电磁波的发射和接收。现有的带有屏蔽罩的封装体的成型工艺中，以基板封装实现其功能居多；主要是因为基板加工工艺是采用覆铜板作为载板，经过曝光，显影，电镀，蚀刻等制程可以把有功能性的线预留在切割线以内，接地线延伸至切割线以外，以实现电磁屏蔽效应。采用基板实现屏蔽效应的成本非常高，其成本比在铜原材质的基础板材上进行封装的 成本约高10倍以上；另外，以基板为载板，其可靠性能低，导热差；其原因在于基板使用原材料里含有core材及油墨，其与铜原材质的基础板材上进行封装的封装体相比，可靠性较差，仅可通过MSL3，同时导热性能也比较差。
因此，需要提出一种以铜原材质的基础板材为载板，并在其上进行封装、屏蔽的技术及封装体，以提升封装体的性能及节约制造成本。
发明内容
本发明的目的在于提供一种解决上述技术问题的电磁屏蔽封装结构及封装方法。
为了实现上述发明目的之一，本发明一实施方式提供一种电磁屏蔽封装结构的封装方法，所述方法包括：S1、提供铜原材质的基础板材；
S2、在基础板材的电镀区域进行电镀，以在基础板材上形成电镀层；
S3、在形成有电镀层的基础板材上进行蚀刻使其整体形成过渡层，所述过渡层包括：引脚，一端连接引脚、另一端延伸至单体切割线的导电连筋，以及蚀刻后的电镀层，所述引脚包括：功能引脚和接地引脚；
S4、在过渡层背面粘贴耐高温保护膜；
S5、在过渡层正面贴装芯片，并使芯片电性连接功能引脚；
S6、在过渡层的正面进行第一次包封；
S7、剥离过渡层背面覆盖的耐高温保护膜；
S8、自过渡层背面蚀刻掉与功能引脚连接的导电连筋，以在对应蚀刻掉导电连筋的位置形成若干凹槽，使得排除电镀层的过渡层形成线路层；所述线路层包括：功能引脚、接地引脚，以及分别连接每一接地引脚的导电连筋；
S9、自线路层背面进行二次包封，所述包封区域至少包括步骤S8形成的凹槽；
S10、自单体切割线对步骤S9形成的半成型封装体进行切割，形成若干单体封装体；
S11、在单体封装体的塑封面上均匀溅射金属保护层形成屏蔽罩，并使得导电连筋与屏蔽罩导通，形成电磁屏蔽封装结构。
作为本发明一实施方式的进一步改进，步骤S1具体包括：
S1-1、提供卷铜原材料；
S1-2、在铜表面进行酸洗或碱洗预处理，以清洁铜表面获得基础板材。
作为本发明一实施方式的进一步改进，步骤S2具体包括：
S21、在基础板材上粘贴光阻膜；
S22、通过曝光机台和显影机台去除部分光阻膜以在基础板材上曝露电镀区域；
S23、在基础板材的电镀区域内电镀镍钯金或镀银；
S24、剥离基础板材上剩余的光阻膜。
作为本发明一实施方式的进一步改进，步骤S3具体包括：
S31、在形成有电镀层的基础板材上粘贴光阻膜；
S32、通过曝光机台和显影机台去除部分光阻膜曝露蚀刻区域；
S33、蚀刻掉蚀刻区域的基础板材，以保留粘贴有光阻膜的过渡层；
S34、剥离剩余的光阻膜形成过渡层。
作为本发明一实施方式的进一步改进，步骤S3和步骤S4之间，所述方法还包括：使用punch模具或者router方式将步骤S3形成的过渡层分割为条状。
作为本发明一实施方式的进一步改进，步骤S7还包括：采用化学药剂去除线路背面因去除保护膜而残留的黏胶层。
作为本发明一实施方式的进一步改进，所述方法还包括：二次包封的区域还包括：线路层背面电镀层之间未塑封的区域。
作为本发明一实施方式的进一步改进，在单体封装体的塑封面上溅射的金属保护层自内向外依次为：内层不锈钢层、铜层以及外层不锈钢层。
为了实现上述发明目的另一，本发明一实施方式提供一种电磁屏蔽封装 结构，所述电磁屏蔽封装结构包括：铜材质的线路层，所述线路层包括功能引脚、接地引脚，以及分别连接每一接地引脚，并朝向电磁屏蔽封装结构侧面延伸的导电连筋；
设置于线路层正面且与所述线路层之间形成空腔的屏蔽罩，所述屏蔽罩的侧壁延伸至线路层的侧面，且连接每一所述导电连筋；
设置于线路层正面和背面的电镀层；
设置于所述空腔内、且与所述功能引脚电性连接的芯片；
以及填充所述空腔及所述线路层之间空隙的塑封料，所述塑封料隔离所述屏蔽罩和所述功能引脚接触。
作为本发明一实施方式的进一步改进，所述屏蔽罩的侧壁延伸至所述电镀层；
所述塑封料还用于填充电镀层之间的空隙。
与现有技术相比，本发明的电磁屏蔽封装结构及其封装方法，在铜原材质的基础板材直接形成过渡层，对过渡层进行第一次包封完成，采用蚀刻工艺去除与功能引脚连接的导电连筋，再二次包封补平导电连筋的凹槽，使功能引脚包裹在塑封料里面，接地引脚通过导电连筋电性连接塑封体外壁面上的屏蔽罩，进而使塑封体内部的接地引脚与屏蔽金属相连接，实现屏蔽；提升封装体的性能、节约制造成本及使用成本。
附图说明
图1为本发明一实施方式提供的电磁屏蔽封装结构的封装方法的流程示意图；
图2对应本发明图1所示封装方法的步骤示意图；
图3、图4分别为本发明电磁屏蔽封装结构形成过程中导电连筋与引脚连接关系的结构示意图；
图5为WB类封装产品的结构示意图；
图6为FC类封装产品的结构示意图；
图7为SMT类封装产品的结构示意图；
图8为本发明另一实施方式中电磁屏蔽封装结构在形成过程中的部分结构示意图；
图9是采用图8所述封装方法封装出的电磁屏蔽封装结构的结构示意图；
图10是采用图2所述封装方法封装出的电磁屏蔽封装结构的结构示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
结合图1、图2所示，本发明一实施方式提供一种电磁屏蔽封装结构的封装方法，所述方法包括：
S1、提供铜原材质的基础板材10；
S2、在基础板材10的电镀区域进行电镀，以在基础板材10上形成电镀层20；
S3、在形成有电镀层20的基础板材10上进行蚀刻使其整体形成过渡层，结合图3所示，图3主要示出过渡层中的导电连筋；所述过渡层至少包括：引脚31，一端连接引脚31、另一端延伸至单体切割线的导电连筋33，以及蚀刻后的电镀层20；所述引脚31包括：功能引脚31a和接地引脚31b；
S4、在过渡层背面覆盖耐高温保护膜40；
S5、在过渡层正面贴装芯片50，并使芯片50电性连接功能性引脚31a；
S6、在过渡层的正面进行第一次包封；
S7、剥离过渡层背面覆盖的耐高温保护膜40；
S8、自过渡层背面蚀刻掉与功能引脚31a连接的导电连筋33，以在对应 蚀刻掉导电连筋的位置形成若干凹槽62，使得排除电镀层20的过渡层形成线路层30；结合图4所示，图4中主要示出对过渡层处理后形成的线路层中的导电连筋；所述线路层30至少包括：功能引脚31a、接地引脚31b，以及分别连接每一接地引脚31b的导电连筋33；
S9、自线路层30背面进行二次包封，所述包封区域至少包括步骤S8形成的凹槽62；
S10、自单体切割线对步骤S9形成的半成型封装体进行切割，形成若干单体封装体；
S11、在单体封装体的塑封面上均匀溅射金属保护层形成屏蔽罩70，并使得导电连筋33与屏蔽罩70导通，形成电磁屏蔽封装结构。
本发明一具体实施方式中，步骤S1具体包括：S1-1、提供卷铜原材料；提供的卷铜原材料的厚度可以依据产品的厚度进行选择，因铜原材料为金属合金材质，如此，可提升以其为载板的包封产品的可靠性及散热性；S1-2、在铜表面进行酸洗或碱洗预处理，以清洁铜表面获得基础板材10。该步骤S1在于去除铜表面脂类等物质，以起到清洁铜面的目的。
本发明一具体实施方式中，在步骤S2进行第一次贴膜作业，以为了后续电镀。具体的，步骤S2具体包括：S21、在基础板材10上粘贴光阻膜；光阻膜通常粘贴在基础板材10的正、反两面；所述光阻膜可以是干式光阻膜也可以是湿式光阻膜；S22、通过曝光机台和显影机台去除部分光阻膜以在基础板材10上曝露电镀区域；该步骤中对粘贴光阻膜的位置进行图形曝光、显影以及去除部分光阻膜后，曝露出基础板材10的铜面；S23、在基础板材10的电镀区域内电镀镍钯金或镀银；S24、剥离基础板材10上剩余的光阻膜。该步骤可以借助剥膜液剥除基础板材10上剩余的光阻膜。需要说明的是，本发明设置导电连筋33的目的在于，通过导电连筋33连接接地引脚31b和屏蔽罩70，以实现屏蔽，如此，在该具体实施方式中，由于与功能引脚连接31a连接的导电连筋33，在后续部分需要被蚀刻掉，如此，与功能引脚31a连接的 导电连筋33被排除在电镀区域外，即在电镀时，与功能引脚31a连接的导电连筋33无需电镀，但与接地引脚31b连接的导电连筋在被划分为电镀区域时，需要电镀。
本发明一具体实施方式中，在步骤S3进行第二次贴膜作业，具体的，步骤S3具体包括：S31、在形成有电镀层20的基础板材10上粘贴光阻膜；该光阻膜同样可为干湿光阻膜或湿式光阻膜；S32、通过曝光机台和显影机台去除部分光阻膜曝露蚀刻区域；该步骤中对粘贴光阻膜的位置进行图形曝光、显影以及去除部分光阻膜后，曝露出基础板材10的铜面；S33、蚀刻掉蚀刻区域的基础板材10，以保留粘贴有光阻膜的过渡层；该步骤中，保留的光阻膜覆盖的基础板材10以及电镀层即为需要保留的线路；S34、剥离剩余的光阻膜形成过渡层。根据封装类型的不同，所述过渡层上除引脚31及导电连筋33外，还可能包括基岛35；以下内容中还会描述。
步骤S3和步骤S4之间，所述方法还包括：使用punch模具或者router方式将步骤S3形成的过渡层分割为条状，以便于后续切割。
对于步骤S4形成的过渡层，各零部件之间可能相互连接，也可能会断开，如此，在其背面粘贴耐高温保护膜40，所述耐高温保护膜40粘贴于过渡层的背面，并填充位于过渡层背面的电镀层20之间的空隙，如此，通过保护膜连接各个零部件，便于后续包封使用。
对于步骤S5，结合图5所示，对于WB类封装产品，在基岛35正面通过粘结胶装置芯片50，之后借助焊线51使芯片50电性连接功能引脚31a。
结合图6所示，对于FC类封装产品，芯片50通过Bump53与引脚电性连接。
结合图7所示，对于SMT类封装产品，该处的芯片50为电感、电容、电阻或传感器等被动元器件，其直接焊接在功能引脚31a上。
对于步骤S6，自过渡层的正面对其进行第一次包封，其可在过渡层的正面进行环氧树脂塑封，塑封料60填充耐高温保护膜40以上的所有间隙。
步骤S7对应于步骤S5，在第一次包封完成后，需要撕除临时粘贴的耐高温保护膜40，并利于第二次包封。
本发明较佳实施方式中，步骤S7还包括：采用化学药剂去除线路背面因去除保护膜而残留的黏胶层。所述化学药剂例如氢氧化钾和有机胺等混合碱洗药液。
步骤S8中，在过渡层背面，与功能引脚31a连接的导电连筋33未进行电镀，依然为铜面，采用蚀刻药水可蚀刻掉该位置的导电连筋33，并保留与接地引脚31b连接的导电连筋33，如此，截断功能引脚31a与侧壁连接，仅保留接地引脚31b通过导电连筋33与侧壁连接，形成线路层30；该步骤中，蚀刻掉对应位置处的导电连筋33后，在步骤S7未最终成型的产品背面、且对应蚀刻掉的导电连筋位置形成若干凹槽62，每一凹槽62的底部曝露第一次包封的塑封料60，且每一凹槽62的至少一个边壁曝露功能引脚31a。
步骤S9中，自线路层30的背面进行二次包封，其包封方式具有两种，图2所示示例中，通过塑封料60填充线路层30背面以上的所有间隙，该实施方式中，使用环氧树脂胶填充线路层30背面，填充的区域包括步骤S8中形成的每一凹槽62，以及位于线路层30背面、电镀层20之间未覆盖塑封料60的区域，此时，通过环氧树脂胶塑封阻挡芯片50封装体的侧壁面外露，以便于后续做金属屏蔽。
结合图8所示，二次包封时，填充的区域仅包括步骤S8中形成的每一凹槽62，而未对线路层30背面电镀层20之间未塑封的区域进行二次塑封，此时，通过环氧树脂胶塑封同样可以阻挡芯片50封装体的侧壁面外露，以便于后续做金属屏蔽。
步骤S10，使用切割机台使产品由条排布切成单颗，此时，单颗产品的侧壁由塑封料阻隔，防止功能引脚31a电性连接至侧壁，而在导电连筋33作用下，导电连筋33延伸到单个产品的侧壁，以保证接地引脚31b电性连接至侧壁，便于后续接地引脚31b与金属屏蔽罩70相连。
步骤S10后，所述方法还包括：清洗单体封装体，以去除单体封装体表面的异物和/或油脂。其清洗的方式例如：酒精浸泡、超声波清洗。
步骤S11中，结合图2及图8所示，产品的塑封面包括除背面之外的5个面，本发明较佳实施方式中，所述金属保护层包括3层，其自内向外依次为：内层不锈钢层、铜层以及外层不锈钢层；溅射内层不锈钢层的目的在于增加与塑封料的结合力，该层的厚度通常为0.1um，溅射外层不锈钢层的目的是保护中间的铜层不被氧化；中间铜层的厚度通常为5～9um，外层不锈钢层的厚度通常为0.1～0.3um；在单体封装体的外壁面溅射金属保护层后，由于连接接地引脚31b的导电连筋33延伸至侧壁面，如此，可通过导电连筋33使功能引脚31b电性连接金属材质的屏蔽罩70。
结合参照图9所示，并参照上述方法相关的图示，本发明一实施方式提供一种通过如上所述方法制造形成的电磁屏蔽封装结构；所述电磁屏蔽封装结构包括：铜材质的线路层30，所述线路层包括功能引脚31a、接地引脚31b，以及分别连接每一接地引脚31b，并朝向电磁屏蔽封装结构侧面延伸的导电连筋33；设置于线路层30正面且与所述线路层30之间形成空腔的屏蔽罩70，所述屏蔽罩70的侧壁延伸至线路层30的侧面，且连接每一所述导电连筋33；设置于线路层30正面和背面的电镀层20；设置于所述空腔内、且与所述功能引脚31b电性连接的芯片50；以及填充所述空腔及所述线路层30之间空隙的塑封料60，所述塑封料60隔离所述屏蔽罩70和所述功能引脚31a接触。
结合图10所示，本发明另一实施方式中，所述屏蔽罩70的侧壁延伸至所述电镀层20；所述塑封料60还用于填充电镀层20之间的空隙。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的电磁屏蔽封装结构的具体结构，及各零部件的替换方式，均可以参考前述方法实施方式中的对应描述，在此不再赘述。
综上所述，本发明的电磁屏蔽封装结构及其封装方法，在铜原材质的基础板材直接形成过渡层，对过渡层进行第一次包封完成，采用蚀刻工艺去除 与功能引脚连接的导电连筋，再二次包封补平导电连筋的凹槽，使功能引脚包裹在塑封料里面，接地引脚通过导电连筋电性连接塑封体外壁面上的屏蔽罩，进而使塑封体内部的接地引脚与屏蔽金属相连接，实现屏蔽；提升封装体的性能、节约制造成本及使用成本。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种电磁屏蔽封装结构的封装方法，其特征在于，所述方法包括：
    S1、提供铜原材质的基础板材；
    S2、在基础板材的电镀区域进行电镀，以在基础板材上形成电镀层；
    S3、在形成有电镀层的基础板材上进行蚀刻使其整体形成过渡层，所述过渡层包括：引脚，一端连接引脚、另一端延伸至单体切割线的导电连筋，以及蚀刻后的电镀层，所述引脚包括：功能引脚和接地引脚；
    S4、在过渡层背面粘贴耐高温保护膜；
    S5、在过渡层正面贴装芯片，并使芯片电性连接功能引脚；
    S6、在过渡层的正面进行第一次包封；
    S7、剥离过渡层背面覆盖的耐高温保护膜；
    S8、自过渡层背面蚀刻掉与功能引脚连接的导电连筋，以在对应蚀刻掉导电连筋的位置形成若干凹槽，使得排除电镀层的过渡层形成线路层；所述线路层包括：功能引脚、接地引脚，以及分别连接每一接地引脚的导电连筋；
    S9、自线路层背面进行二次包封，所述包封区域至少包括步骤S8形成的凹槽；
    S10、自单体切割线对步骤S9形成的半成型封装体进行切割，形成若干单体封装体；
    S11、在单体封装体的塑封面上均匀溅射金属保护层形成屏蔽罩，并使得导电连筋与屏蔽罩导通，形成电磁屏蔽封装结构。
  2. 根据权利要求1所述的电磁屏蔽封装结构的封装方法，其特征在于，步骤S1具体包括：
    S1-1、提供卷铜原材料；
    S1-2、在铜表面进行酸洗或碱洗预处理，以清洁铜表面获得基础板材。
  3. 根据权利要求1所述的电磁屏蔽封装结构的封装方法，其特征在于， 步骤S2具体包括：
    S21、在基础板材上粘贴光阻膜；
    S22、通过曝光机台和显影机台去除部分光阻膜以在基础板材上曝露电镀区域；
    S23、在基础板材的电镀区域内电镀镍钯金或镀银；
    S24、剥离基础板材上剩余的光阻膜。
  4. 根据权利要求1所述的电磁屏蔽封装结构的封装方法，其特征在于，步骤S3具体包括：
    S31、在形成有电镀层的基础板材上粘贴光阻膜；
    S32、通过曝光机台和显影机台去除部分光阻膜曝露蚀刻区域；
    S33、蚀刻掉蚀刻区域的基础板材，以保留粘贴有光阻膜的过渡层；
    S34、剥离剩余的光阻膜形成过渡层。
  5. 根据权利要求1所述的电磁屏蔽封装结构的封装方法，其特征在于，步骤S3和步骤S4之间，所述方法还包括：使用punch模具或者router方式将步骤S3形成的过渡层分割为条状。
  6. 根据权利要求1所述的电磁屏蔽封装结构的封装方法，其特征在于，步骤S7还包括：采用化学药剂去除线路背面因去除保护膜而残留的黏胶层。
  7. 根据权利要求1所述的电磁屏蔽封装结构的封装方法，其特征在于，所述方法还包括：二次包封的区域还包括：线路层背面电镀层之间未塑封的区域。
  8. 根据权利要求1所述的电磁屏蔽封装结构的封装方法，其特征在于，在单体封装体的塑封面上溅射的金属保护层自内向外依次为：内层不锈钢层、铜层以及外层不锈钢层。
  9. 一种电磁屏蔽封装结构，其特征在于，所述电磁屏蔽封装结构包括：
    铜材质的线路层，所述线路层包括功能引脚、接地引脚，以及分别连接每一接地引脚，并朝向电磁屏蔽封装结构侧面延伸的导电连筋；
    设置于线路层正面且与所述线路层之间形成空腔的屏蔽罩，所述屏蔽罩的侧壁延伸至线路层的侧面，且连接每一所述导电连筋；
    设置于线路层正面和背面的电镀层；
    设置于所述空腔内、且与所述功能引脚电性连接的芯片；
    以及填充所述空腔及所述线路层之间空隙的塑封料，所述塑封料隔离所述屏蔽罩和所述功能引脚接触。
  10. 根据权利要求9所述的电磁屏蔽封装结构，其特征在于，所述屏蔽罩的侧壁延伸至所述电镀层；
    所述塑封料还用于填充电镀层之间的空隙。
PCT/CN2019/113021 2019-07-26 2019-10-24 电磁屏蔽封装结构及其封装方法 WO2021017206A1 (zh)

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