WO2020010837A1 - 单体双金属板封装结构及封装方法 - Google Patents

单体双金属板封装结构及封装方法 Download PDF

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Publication number
WO2020010837A1
WO2020010837A1 PCT/CN2019/072853 CN2019072853W WO2020010837A1 WO 2020010837 A1 WO2020010837 A1 WO 2020010837A1 CN 2019072853 W CN2019072853 W CN 2019072853W WO 2020010837 A1 WO2020010837 A1 WO 2020010837A1
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Prior art keywords
layer
plate
cavity
emi
circuit layer
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PCT/CN2019/072853
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English (en)
French (fr)
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刘恺
梁志忠
王亚琴
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江苏长电科技股份有限公司
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Publication of WO2020010837A1 publication Critical patent/WO2020010837A1/zh

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Definitions

  • the invention belongs to the field of semiconductor manufacturing, and particularly relates to a single bimetal plate packaging structure and a packaging method.
  • the prior art often sticks a metal cover or a metal layer on the outer surface of the package to shield the transmission and reception of electromagnetic waves.
  • the electromagnetic shielding is achieved by attaching a metal cover.
  • the combination of the metal cover and the package often has problems. Because the size of the metal cover and the size of the package are difficult to completely match, air often exists between the metal cover and the outer surface of the package. Residuals, which often cause reliability problems when the electronic components are heated up.
  • the grounding of the metal layer can generally only be achieved by auxiliary conductors and components. The process is more complicated. ,higher cost.
  • An object of the present invention is to provide a single bimetal plate packaging structure and a packaging method that solve the above technical problems.
  • an embodiment of the present invention provides a packaging method of a single bimetal plate packaging structure.
  • the method includes: S1, providing an upper metal plate and a lower metal plate;
  • a window is opened on the solder resist layer to expose the circuit layer, and a solder ball is implanted in the window opening area to form a package;
  • step S6 further includes:
  • the upper metal plate After opening a window on the solder resist layer to expose the circuit layer, and after implanting solder balls in the window opening area, the upper metal plate is peeled to form a package.
  • step S2 further includes:
  • An injection hole is opened on a side wall of the groove; at least one first EMI layer is plated on a position where the injection hole is removed from the inner wall of each groove to form a top plate;
  • the step S4 specifically includes: injecting injection molding material into the cavity through the injection hole for injection molding encapsulation.
  • the step S2 further includes:
  • the opening size of the injection hole remains unchanged or decreases in order.
  • step S2 further includes:
  • a lower end of the groove sidewall forms a plug-in portion
  • the circuit layer has a notch matching the plug-in portion.
  • an embodiment of the present invention provides a single bimetal plate packaging structure, the single bimetal plate packaging structure includes: a circuit layer;
  • At least one first EMI layer electrically connected above the circuit layer and forming at least one cavity with the circuit layer;
  • the solder resist layer is disposed outside the cavity and is superposed on the circuit layer, and the solder resist layer is provided with a plurality of window opening areas;
  • the single bimetal plate packaging structure further includes:
  • the injection hole communicates with the inside of the cavity and the outside of the upper metal plate.
  • the single bimetal plate packaging structure and the packaging method of the present invention realize EMI shielding by using bimetal plates for packaging, and it does not need to use a traditional cavity mold for plastic packaging and packaging, thereby saving manufacturing. Cost, the yield and stability of the package structure obtained by this method are greatly improved, and the process is simple.
  • FIG. 1A is a schematic flowchart of a packaging method for a single bimetal plate packaging structure in a first embodiment of the present invention
  • FIG. 1B is a schematic diagram of steps of the packaging method shown in FIG. 1A according to the present invention.
  • FIG. 2A and 2B are schematic structural diagrams of a single bimetal plate packaging structure encapsulated by the packaging method described in FIG. 1A, respectively;
  • FIG. 3 is a schematic diagram of a three-dimensional structure after an upper metal plate is etched to form a groove in an embodiment of the present invention
  • FIG. 4A is a schematic flowchart of a packaging method of a single bimetal plate packaging structure in a second embodiment of the present invention
  • FIG. 4B is a schematic diagram of steps of the packaging method shown in FIG. 4A according to the present invention.
  • 5A is a schematic flowchart of a packaging method of a single bimetal plate packaging structure according to a third embodiment of the present invention.
  • FIG. 5B corresponds to the steps of the packaging method shown in FIG. 5A of the present invention.
  • 6A, 6B, 6C, 6D, 6E, and 6F are schematic structural diagrams of a single bimetal plate packaging structure encapsulated by the packaging method described in FIG. 5A, respectively;
  • 7A, 7B, 7C, 7D, 7E, and 7F are schematic structural diagrams of a single bimetal plate packaging structure encapsulated by the packaging method described in FIG. 4A, respectively;
  • FIG. 8A is a schematic flowchart of a packaging method of a single bimetal plate packaging structure in a fourth embodiment of the present invention.
  • FIG. 8B is a schematic diagram of steps of the packaging method shown in FIG. 8A according to the present invention.
  • 9A, 9B, and 9C are structural schematic diagrams of a single bimetal plate packaging structure encapsulated by the packaging method described in FIG. 8A, respectively.
  • first, second, etc. may be used herein to describe various elements or structures, these described objects should not be limited by the above terms. The above terms are only used to distinguish these description objects from each other.
  • the first EMI layer may be referred to as a second EMI layer.
  • the second EMI layer may also be referred to as a first EMI layer, which does not depart from the protection scope of the application.
  • the packaging method shown in the present invention can be applied to the packaging of a single chip or the packaging method of a wafer-level chip.
  • the packaging method of a single chip is taken as an example for specific introduction.
  • the packaging method of the single bimetal plate packaging structure provided by the first embodiment of the present invention shown in FIGS. 1A and 1B includes:
  • An upper metal plate 10 and a lower metal plate 20 are provided.
  • Injection molding 60 is injected into the cavity for injection molding and encapsulation.
  • the upper metal plate 10 and the lower metal plate 20 are peeled off to form a plurality of single bimetal plate packaging structures (100a, 100b).
  • the upper metal plate 10 and the lower metal plate 20 may both be metal packaging plates, and the material is, for example, copper or iron; the upper metal plate 10 and the lower metal plate 20 may be selected the same. You can also choose a different material.
  • each single bimetal plate packaging structure corresponds to one groove.
  • each single bimetal plate packaging structure can also be made to correspond to two or more than two as required. In this way, when cutting, cutting can be performed in units of grooves, which will not be described in detail here.
  • the number of the first EMI layers 30 may be one layer or multiple layers; when the number of the first EMI layers is two or more layers, each of the first EMI layers 30 is sequentially superimposed in the formed groove.
  • Layer is the first EMI layer; the EMI layer is the English name Electromagnetic Interference, which is the abbreviation of electromagnetic interference.
  • the first EMI layer is used to shield the external signals from the influence on its internal chip. Select the material of the EMI layer for the frequency, for example: copper, silver, aluminum, etc.
  • the method of superimposing the chip 50 on the circuit layer 40 may be a flip-chip and / or a wire bonding method, and the method of combining the top plate and the bottom plate may also be a gluing or soldering method; correspondingly, in A solder paste is printed on a side of the circuit layer 40 away from the lower metal plate 20 so that the chip 50 is superimposed on the circuit layer 40 so that the upper metal plate 10 can be soldered to the lower metal plate by solder paste. 20 on.
  • the forming of the top plate includes the following steps: M11.
  • the first EMI layer 30 is plated to form a top plate.
  • the formation of the base plate includes the following steps: N11, overlaying or printing a photoresist material on the upper surface of the lower metal plate 20; used for exposure development, defining a pattern area to be etched; N12, removing part of the photoresist material through the exposure development process To form an etched area, and plate the circuit layer 40 in the etched area; N13, remove the remaining photoresist material of the lower metal 20 plate; N4, stack on the side of the circuit layer 40 away from the lower metal plate 20
  • the chip 50 is mounted to form a base plate.
  • the method further includes: opening an injection hole 13 communicating with the inside of the cavity on the periphery of the finally formed single bimetal plate packaging structure; for example, the injection hole is opened on the top plate or / Or it is opened on the bottom plate for injection molding, and injection molding 60 is injected into the cavity through the injection hole 13 to perform injection molding.
  • an injection hole 13 is opened in a side wall of the groove 11; the size, shape, and number of the injection hole 13 can be specifically set according to needs; preferably, In the extending direction of the injection hole 13 toward the inside of the groove 11, the opening size of the injection hole 13 remains unchanged or decreases in order.
  • the step S12 specifically includes: when the first EMI layer 30 is plated on the inside of the groove, the position where the injection hole 13 is removed from the inner wall of each groove 11 Electroplating at least one layer of the first EMI layer 30 to form a top plate; the step S15 specifically includes: peeling off the upper metal plate 10 and the lower metal plate 20, removing the injection molding material outside the first EMI layer 30 to form several Single bimetal plate package structure. It should be noted that, when the number of the cavities is greater than 1, the injection molding material 60 is also used to also fill a part of the gap between adjacent cavities.
  • the step S12 further includes: a plug portion 15 is formed at the lower end of the side wall of the groove 11, and the circuit layer 40 has a notch 401 matching the plug portion.
  • a first EMI layer can be selectively plated on the plug portion 15; in a preferred embodiment of the present invention, at least one first EMI layer 30 is plated on a position where the plug portion 15 is removed from the inner wall of each of the grooves 11 to A top plate is formed; when the plug portion 15 is inserted into the notch 401, the first EMI layer 30 and the circuit layer 40 are electrically connected to each other above the circuit layer 40.
  • the upper metal plate 10 and the lower metal plate 20 there are various ways to peel the upper metal plate 10 and the lower metal plate 20, for example: peel the upper metal plate 10 by etching; peel the lower metal plate 20 by etching or mechanical peeling; after the upper and lower metal plates are peeled off It is possible that the injection molding 60 in the injection hole 13 may remain on the structure of the finally formed single bimetal plate. At this time, after peeling the upper and lower metal plates, the injection molding 60 needs to be removed to form several monomers. Bimetal plate packaging structure; the method for removing the injection molding material 60 can be cutting or other methods, which will not be described in detail here.
  • the single bimetal plate packaging structure 100a includes: a circuit layer 40, at least one first EMI layer electrically connected above the circuit layer 40 and forming a cavity with the circuit layer 40. 30; an injection hole (not shown) opened at the periphery of the single bimetal plate packaging structure and communicating with the inside of the cavity; a chip 50 located in the cavity; and filling the cavity and the injection hole 13 Of injection plastic 60.
  • the number of the first EMI layer 30 is set to one layer; the injection hole extends from an outer wall surface of the first EMI layer 30 into the cavity.
  • the single bimetal plate packaging structure 100b is based on 2A, and the number of first EMI layers is set to two.
  • the outer first EMI layer 31 can pass through the inner first EMI layer 30 and the circuit layer 40. It is electrically connected to be further grounded through the wiring layer 40.
  • the number of the first EMI layers may be specifically increased as needed, and is not further described here; the injection hole is from the outer wall surface of the first EMI layer 31, The first EMI layer 30 extends into the cavity.
  • the manufacturing method of a single bimetal plate packaging structure provided by the first embodiment of the present invention realizes EMI shielding by using bimetal plates for packaging, and it does not need to use a traditional cavity mold for plastic packaging, thereby saving manufacturing costs.
  • the yield and stability of the packaging structure obtained by this method are greatly improved, and the process is simple.
  • FIG. 4A, 4B shows the first embodiment of the present invention.
  • the packaging method of the single bimetal plate packaging structure provided by the second embodiment includes:
  • An upper metal plate 10 and a lower metal plate 20 are provided.
  • Injection molding 60 is injected into the cavity for injection molding and encapsulation.
  • the lower metal plate 20 is peeled.
  • a window is opened on the solder resist layer 70 to expose the circuit layer 40, and a solder ball 80 is implanted in the window opening area 701 to form a package.
  • the combination manner of the top plate is the same as the first manner, and will not be repeated here.
  • the formation of the bottom plate includes the following steps: N21, overlaying or printing a solder resist layer 70 on the upper surface of the lower metal plate; N22, overlaying or printing a photoresist material on the solder resist layer 70; N23: Remove a part of the photoresist material through the exposure and development process to form an etched area, and plate the circuit layer 40 in the etched area; N24, remove the remaining photoresist material from the first solder resist 70 layer; N25, on the line
  • the chip 40 is stacked on a side of the layer 40 remote from the lower metal plate 20 to form a bottom plate.
  • the method further includes: opening an injection hole 13 communicating with the inside of the cavity at the periphery of the final formed single bimetal plate packaging structure; for example, the injection hole is opened on the top plate or / Or it is opened on the bottom plate for injection molding, and injection molding 60 is injected into the cavity through the injection hole 13 to perform injection molding.
  • an injection hole 13 is opened in a side wall of the groove 11; the size, shape, and number of the injection hole 13 can be specifically set according to needs; preferably, In the extending direction of the injection hole 13 toward the inside of the groove 11, the opening size of the injection hole 13 remains unchanged or decreases in order.
  • the step S22 specifically includes: when the first EMI layer 30 is plated on the inside of the groove, the position where the injection hole 13 is removed from the inner wall of each groove 11 At least one layer of the first EMI layer 30 is electroplated to form a top plate. It should be noted that, when the number of the cavities is greater than 1, the injection molding material 60 is used to also fill a part of the gap between adjacent cavities.
  • the step S22 further includes: forming a plug-in portion 15 at the lower end of the side wall of the groove 11, and the circuit layer 40 has a notch 401 matching the plug-in portion.
  • the portion is inserted into the notch 401, the first EMI layer 30 and the wiring layer 40 are electrically connected to each other.
  • a first EMI layer can be selectively plated on the plug portion 15; in a preferred embodiment of the present invention, at least one first EMI layer 30 is plated on a position where the plug portion 15 is removed from the inner wall of each of the grooves 11 to A top plate is formed; when the plug portion 15 is inserted into the notch 401, the first EMI layer 30 and the circuit layer 40 are electrically connected to each other above the circuit layer 40.
  • the lower metal plate 20 is peeled by etching or mechanical peeling.
  • FIGS. 5A and 5B a method for packaging a single bimetal plate packaging structure according to a third embodiment of the present invention, and a method for packaging a single bimetal plate packaging structure provided by the third embodiment in the second embodiment.
  • the step S26 is modified to S26 '.
  • the step S26' includes: opening a window in a region of the solder resist layer 70 corresponding to the groove 11, and implanting a solder ball in the window opening region 701.
  • the upper metal plate 10 is peeled to form a package (100i, 100j, 100k, 100l, 100m, 100n).
  • the lower metal plate 20 can be peeled off by etching.
  • the final molded single bimetal plate structure may still have injection molding.
  • the illustrated single bimetal plate packaging structure 100c includes: a circuit layer 40; at least one first EMI layer 30 electrically connected above the circuit layer 40 and forming at least one cavity with the circuit layer 40; Outside the cavity, a solder resist layer 70 disposed under the circuit layer 40 is superposed, and the solder resist layer 70 is provided with a plurality of window opening areas 701.
  • the solder resist layer 70 is provided on the periphery of the single bimetal plate packaging structure and communicates with the An injection hole (not shown) inside the cavity; a chip 50 located in the cavity; an window region 701 implanted in the solder resist layer 70 to communicate with the solder ball 80 of the circuit layer 40, and filling Injection cavity 60 for the cavity and the injection hole.
  • the injection hole extends from an outer wall surface of the first EMI layer 30 into the cavity.
  • the single bimetal plate packaging structure 100d of FIG. 6B is based on FIG. 6A.
  • the chip 50a is stacked by flip chip, and the chip 50b is soldered. Lines are superimposed.
  • the single bimetal plate packaging structure 100e of FIG. 6C is based on FIG. 6B, and the number of cavities is set to 2.
  • the injection molding 60 is also used for Fill part of the gap between adjacent cavities.
  • the way of setting the chip 50 in different cavities may be the same or different. In this embodiment, the way of setting the chip 50 in the two cavities is different, and the bonding wire and the flip chip are used for stacking, and no further steps are performed here. Repeat.
  • the single bimetal plate packaging structure 100f of FIG. 6D sets the number of the first EMI layers 30 to two layers based on FIG. 6A; the first EMI layer 31 on the outside can pass through the first EMI layer 30 on the inside and The circuit layer 40 is electrically connected to be further grounded through the circuit layer 40.
  • the number of the first EMI layers may be specifically increased according to needs, and no further details are provided herein.
  • the single bimetal plate package structure 100g of FIG. 6E is based on FIG. 6D.
  • the chip 50a is stacked by flip chip, and the chip 50b is bonded by wire. Way to superimpose.
  • the single bimetal plate packaging structure 100h of FIG. 6F is based on FIG. 6E, and the number of cavities is set to two.
  • the injection molding 60 is also used for filling. Part of the gap between adjacent cavities.
  • the way of setting the chip 50 in different cavities may be the same or different. In this embodiment, the way of setting the chip 50 in the two cavities is different, and the bonding wire and the flip chip are used for stacking, and no further steps are performed here. Repeat.
  • the illustrated single bimetal plate packaging structure 100i is added with an upper metal plate 10 disposed above the solder resist layer 70.
  • the upper metal plate 10 is connected to the solder resist layer 70 and fits the solder mask layer 70.
  • the outer wall surface of the first EMI layer 30 is provided; in a specific embodiment of the present invention, the injection hole extends from the outer wall surface of the upper metal plate 10 into the cavity through the first EMI layer 30.
  • the single bimetal plate packaging structure 100j of FIG. 7B is based on FIG. 7A.
  • the chip 50a is stacked by flipping, and the chip 50b is bonded Way to superimpose.
  • the single bimetal plate packaging structure 100k of FIG. 7C is based on FIG. 7B, and the number of cavities is set to 2.
  • the injection molding 60 is also used for filling. Part of the gap between adjacent cavities.
  • the way of setting the chip 50 in different cavities may be the same or different. In this embodiment, the way of setting the chip 50 in the two cavities is different, and the bonding wire and the flip chip are used for stacking, and no further steps are performed here. Repeat.
  • the single bimetal plate packaging structure 100l of FIG. 7D is based on FIG. 7A, and the number of the first EMI layers 30 is set to two layers; the outer first EMI layer 31 can pass through the inner first EMI layer 30 and The circuit layer 40 is electrically connected to be further grounded through the circuit layer 40.
  • the single-metal bimetal plate package structure 100m of FIG. 7E is based on FIG. 7D.
  • the chip 50a is stacked by flip chip, and the chip 50b is bonded by wire. Way to superimpose.
  • the single bimetal plate packaging structure 100n of FIG. 7F is based on FIG. 7E, and the number of cavities is set to 2.
  • the injection molding 60 is also used for filling. Part of the gap between adjacent cavities.
  • the way of setting the chip 50 in different cavities may be the same or different. In this embodiment, the way of setting the chip 50 in the two cavities is different, and the bonding wire and the flip chip are used for stacking, and no further steps are performed here. Repeat.
  • the manufacturing method of the single bimetal plate packaging structure provided by the second and third embodiments of the present invention realizes EMI shielding and line fan-out by using bimetal plates for packaging, and it does not need to use a traditional cavity mold for plastic packaging. , Saving manufacturing costs, the yield and stability of the packaging structure obtained by this method are greatly improved, and the process is simple.
  • a packaging method for a single bimetal plate packaging structure provided by a fourth embodiment of the present invention includes:
  • An upper metal plate 10 and a lower metal plate 20 are provided.
  • Injection molding 60 is injected into the cavity for injection molding and encapsulation.
  • the cutting package does not include a portion of the lower metal plate 20 to form a plurality of non-connected semi-molded monomers above the lower metal plate 20.
  • a second EMI layer 31 is superposed on the outer side of the upper metal plate 10 corresponding to each semi-molded monomer.
  • the second EMI layer 31 and the first EMI layer 30 are not connected, and
  • the EMI layer 31 is stacked on the same side away from the lower metal plate 20 and a connection metal plate 90 is stacked to form a double-layer shielding structure;
  • the second EMI layer 31 is electrically connected to the first EMI layer 30 through the upper metal plate 10 And further indirectly grounded through the first EMI layer 30; after the second EMI layer 31 is superimposed, a connection metal plate 90 is added thereon to perform the solder ball implantation operation on the package as a whole, of course, in other embodiments of the present invention, If the complexity of the process is not considered, after the second EMI layer 31 is superimposed, the solder ball implantation operation can be performed directly on each cell.
  • the lower metal plate 20 is peeled.
  • a window is opened on the solder resist layer 70 to expose the circuit layer 40.
  • a solder ball 80 is implanted in the window opening area 701, and the connection metal plate 90 is removed to directly form a plurality of single-body bimetal plate packaging structures (100p, 100q). , 100r).
  • the formed package is a combination of a plurality of single bimetal plate packaging structures. After the connection metal plate 90 is removed, a plurality of single bimetal plate packaging structures are directly formed without cutting.
  • the method further includes: opening an injection hole 13 connected to the inside of the cavity at the periphery of the finally formed single bimetal plate packaging structure; for example, the injection hole is opened on the top plate or / Or it is opened on the bottom plate for injection molding, and injection molding 60 is injected into the cavity through the injection hole 13 to perform injection molding.
  • an injection hole 13 is opened in a side wall of the groove 11; the size, shape, and number of the injection hole 13 can be specifically set according to needs; preferably, In the extending direction of the injection hole 13 toward the inside of the groove 11, the opening size of the injection hole 13 remains unchanged or decreases in order.
  • the step S42 specifically includes: when the first EMI layer 30 is plated on the inside of the groove, the position where the injection hole 13 is removed from the inner wall of each groove 11 At least one first EMI layer 30 is plated to form a top plate. It should be noted that, when the number of the cavities is greater than 1, the injection molding material 60 is used to also fill a part of the gap between adjacent cavities.
  • the step S42 further includes: a plug portion 15 is formed at the lower end of the side wall of the groove 11, and the circuit layer 40 has a notch 401 matching the plug portion.
  • a first EMI layer can be selectively plated on the plug portion 15; in a preferred embodiment of the present invention, at least one first EMI layer 30 is plated on a position where the plug portion 15 is removed from the inner wall of each of the grooves 11 to A top plate is formed; when the plug portion 15 is inserted into the notch 401, the first EMI layer 30 and the circuit layer 40 are electrically connected to each other above the circuit layer 40.
  • peel the upper metal plate 10, the lower metal plate 20, and the connecting metal plate 90 for example: peeling the upper metal plate 10 by etching; peeling the lower metal plate 20 and connecting metal plate 90 by etching or mechanical peeling .
  • the metal plate packaging structure 100p includes: a circuit layer 40; a first EMI layer 30 electrically connected above the circuit layer 40 and forming at least one cavity with the circuit layer 40; and a first EMI layer 30 disposed above the solder resist layer 70
  • An upper metal plate 10 which is connected to the solder resist layer 70 and fits on the outer wall surface of the first EMI layer 30;
  • Two EMI layers 31, and the second EMI layer 31 is electrically connected to the first EMI layer 31 through the upper metal plate 10; the EMI layer 31 is disposed outside the cavity, and a resistor disposed under the circuit layer 40 is superimposed;
  • a solder layer 70, the solder resist layer 70 is provided with a plurality of window opening areas 701; an injection hole 13 opened on the periphery of a single bimetal plate packaging structure and communicating with the interior of the cavity; and a
  • the single bimetal plate packaging structure 100q of FIG. 9B is based on FIG. 9A.
  • the chip 50a is stacked using flip chip, and the chip 50b is bonded with wire. Way to superimpose.
  • the single bimetal plate packaging structure 100r of FIG. 9C sets the number of cavities to two based on FIG. 9B.
  • the injection molding 60 is also used for filling. Part of the gap between adjacent cavities.
  • the way of setting the chip 50 in different cavities may be the same or different. In this embodiment, the way of setting the chip 50 in the two cavities is different, and the bonding wire and the flip chip are used for stacking, and no further steps are performed here. Repeat.
  • the manufacturing method of the single bimetal plate packaging structure provided by the fourth embodiment of the present invention implements EMI shielding and line fan-out by using bimetal plates for packaging, and it does not need to use a traditional cavity mold for plastic packaging, which saves The manufacturing cost, the package structure obtained by this method, its yield and stability are greatly improved, and the process is simple.
  • any two or more of the above-mentioned single bimetal plate packaging structures may be stacked and assembled by using a PoP packaging method to form a new single structure, which is not described in detail here. To repeat.

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Abstract

一种单体双金属板封装结构及封装方法，其结构包括：线路层（40）；电性连接于线路层上方且与线路层形成至少一个空腔的至少一层第一EMI层（30）；设置于空腔外，且叠加设置于线路层下方的阻焊层（70），阻焊层设置有若干个开窗区域（701）；开设于单体双金属板封装结构外围并连通空腔内部的注塑孔（13）；位于空腔内的芯片（50）；植入阻焊层的开窗区域以连通线路层的焊球（80），以及填充空腔和注塑孔的注塑料（60）。采用双金属板进行封装来实现EMI屏蔽，无需使用传统的具有型腔模具进行塑封封装，节约制造成本。

Description

单体双金属板封装结构及封装方法
本申请要求了申请日为2018年7月13日，申请号为201810769902.X，发明名称为“单体双金属板封装结构及封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于半导体制造领域，尤其涉及一种单体双金属板封装结构及封装方法。
背景技术
随着电子产品多功能化和小型化的潮流，高密度微电子组装技术在新一代电子产品上逐渐成为主流。为了配合新一代电子产品的发展，尤其是智能手机、掌上电脑、超级本等产品的发展，使得集成电路封装也向微小化、高密度、高功率、高速度的方向发展。而随着电子部件变得更小、并且在工作频率更高，由于高频芯片在运输和传输是会产生很强的电磁波，往往会对封装内的其他芯片或者封装外的电子部件的造成不期望的干扰或噪声。加上电子部件的密度过高，电子部件之间的信号传输线路的距离越来越近，使得来自集成电路封装外部或内部的芯片之间的电磁干扰(Electro-MagneticInterference,EMI)情形也日益严重。同时也会降低集成电路封的电性品质和散热效能。
为解决电磁干扰问题，现有技术往往会在封装体外表面粘贴金属盖或是镀上金属层来屏蔽电磁波的发射和接收。然而通过粘贴金属盖来实现电磁屏蔽，其金属盖和封装体的结合性往往存在问题，由于金属盖的尺寸和封装体的尺寸很难完全匹配，金属盖与封装体外表面之间往往会存在空气残留，在电子部件工作升温时往往会造成其可靠性的问题；而通过镀金属层的方式来 实现电磁屏蔽，其金属层的接地一般只能辅助导体和元器件来实现接地，其工艺比较复杂，成本较高。
所以，如何克服现有技术的种种问题，更方便的提供一种可避免电磁干扰的封装结构和封装工艺，成为业界迫切解决的课题。
发明内容
本发明的目的在于提供一种解决上述技术问题的单体双金属板封装结构及封装方法。
为了实现上述发明目的之一，本发明一实施方式提供一种单体双金属板封装结构的封装方法，所述方法包括：S1、提供上金属板和下金属板；
S2、在上金属板的下表面上蚀刻形成至少一个凹槽，并在每一所述凹槽内壁上电镀至少一层第一EMI层以形成顶板；
在下金属板的上表面依次电镀阻焊层和线路层，并在所述线路层远离所述下金属板的一侧叠装芯片以形成底板；
S3、结合顶板和底板以在所述阻焊层和第一EMI层之间形成空腔，使所述第一EMI层与所述线路层导通，使所述芯片设置于所述空腔内；
S4、向所述空腔内注入注塑料以进行注塑包封；
S5、剥离所述下金属板；
S6、在阻焊层上开窗以曝露线路层，并在其开窗区域植入焊球以形成封装体；
S7、切割所述封装体以形成若干个单体双金属板封装结构。
作为本发明一实施方式的进一步改进，所述步骤S6还包括：
在阻焊层上开窗以曝露线路层，并在其开窗区域植入焊球后，剥离所述上金属板形成封装体。
作为本发明一实施方式的进一步改进，所述步骤S2还包括：
在所述凹槽的侧壁上开设注塑孔；在每一所述凹槽内壁去除注塑孔的位 置上电镀至少一层第一EMI层以形成顶板；
所述步骤S4具体包括：通过所述注塑孔向所述空腔内注入注塑料以进行注塑包封。作为本发明一实施方式的进一步改进，所述步骤S2还包括：
M1、在上金属板的下表面贴覆或印刷光阻材料；
M2、通过曝光显影过程去除部分光阻材料以形成蚀刻区域，蚀刻所述蚀刻区域以形成凹槽；
M3、去除所述上金属板剩余的光阻材料，并在所述凹槽内壁上电镀第一EMI层以形成顶板。
作为本发明一实施方式的进一步改进，沿注塑孔朝向凹槽内部的延伸方向上，所述注塑孔的开口尺寸保持不变或依次递减。
作为本发明一实施方式的进一步改进，所述步骤S2还包括：
N1、在下金属板的上表面贴覆或印刷阻焊层；
N2、在阻焊层上贴覆或印刷光阻材料；
N3、通过曝光显影过程去除部分光阻材料以形成蚀刻区域，并在所述蚀刻区域电镀线路层；
N4、去除所述阻焊层剩余的光阻材料；
N5、在所述线路层远离所述下金属板的一侧叠装芯片以形成底板。
作为本发明一实施方式的进一步改进，所述凹槽侧壁的下端形成插接部，所述线路层上具有与插接部匹配的凹口，当插接部插入凹口时，第一EMI层与线路层相互导通。
为了实现上述发明目的另一，本发明一实施方式提供一种单体双金属板封装结构，所述单体双金属板封装结构包括：线路层；
电性连接于所述线路层上方且与所述线路层形成至少一个空腔的至少一层第一EMI层；
设置于所述空腔外，且叠加设置于所述线路层下方的阻焊层，所述阻焊层设置有若干个开窗区域；
开设于单体双金属板封装结构外围并连通所述空腔内部的注塑孔；
位于所述空腔内的芯片；
植入所述阻焊层的开窗区域以连通所述线路层的焊球，
以及填充所述空腔和所述注塑孔的注塑料。
作为本发明一实施方式的进一步改进，所述单体双金属板封装结构还包括：
设置于所述阻焊层上方的上金属板，所述上金属板连接于所述阻焊层并契合所述第一EMI层外壁面设置；
所述注塑孔连通所述空腔内部与上金属板外部。
与现有技术相比，本发明的单体双金属板封装结构及其封装方法，通过采用双金属板进行封装来实现EMI屏蔽，而且其无需使用传统的具有型腔模具进行塑封封装，节约制造成本，通过该方法获得的封装结构，其良率及稳定度均得到大幅提升，且工艺简单。
附图说明
图1A为本发明第一实施方式中单体双金属板封装结构的封装方法的流程示意图；
图1B对应本发明图1A所示封装方法的步骤示意图；
图2A、图2B分别是采用图1A所述封装方法封装出的单体双金属板封装结构的结构示意图；
图3是本发明一实施方式中上金属板蚀刻完成以形成凹槽后的立体结构示意图；
图4A为本发明第二实施方式中单体双金属板封装结构的封装方法的流程示意图；
图4B对应本发明图4A所示封装方法的步骤示意图；
图5A为本发明第三实施方式中单体双金属板封装结构的封装方法的流 程示意图；
图5B对应本发明图5A所示封装方法的步骤示意图；
图6A、6B、6C、6D、6E、6F分别是采用图5A所述封装方法封装出的单体双金属板封装结构的结构示意图；
图7A、7B、7C、7D、7E、7F分别是采用图4A所述封装方法封装出的单体双金属板封装结构的结构示意图；
图8A为本发明第四实施方式中单体双金属板封装结构的封装方法的流程示意图；
图8B对应本发明图8A所示封装方法的步骤示意图；
图9A、9B、9C分别是采用图8A所述封装方法封装出的单体双金属板封装结构的结构示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
需要说明的是，本文使用的例如“上”、“下”等表示空间相对位置的术语是出于便于说明的目的来描述如附图中所示的一个单元或特征相对于另一个单元或特征的关系。空间相对位置的术语可以旨在包括封装结构在使用或工作中除了图中所示方位以外的不同方位。例如，如果将图中的设备翻转，则被描述为位于其他单元或特征“下表面的单元将位于其他单元或特征“上表面”。因此，示例性术语“下表面”可以囊括上表面和下表面这两种方位。封装结构可以以其他方式被定向(旋转90度或其他朝向)，并相应地解释本文使用的与空间相关的描述语。
再者，应当理解的是尽管术语第一、第二等在本文中可以被用于描述各种元件或结构，但是这些被描述对象不应受到上述术语的限制。上述术语仅 用于将这些描述对象彼此区分开。例如，第一EMI层可以被称作第二EMI层，同样，第二EMI层也可以被称作第一EMI层，这并不背离该申请的保护范围。
本发明所示的封装方法可用于单颗芯片的封装，也可用于晶圆级芯片的封装方法，下面以单颗芯片的封装方法为例做具体介绍。
结合图1A、图1B、图2A、图2B、图3所示；具体的，图1A、1B所示本发明第一实施方式提供的单体双金属板封装结构的封装方法包括：
S11、提供上金属板10和下金属板20。
S12、在上金属板10的下表面上蚀刻形成至少一个凹槽11，并在每一所述凹槽11内壁上电镀至少一层第一EMI层30以形成顶板；在下金属板20的上表面电镀线路层40，并在所述线路层40远离所述下金属板的一侧叠装芯片50以形成底板。
S13、结合顶板和底板，以在所述线路层40和第一EMI层30之间形成空腔，并使所述第一EMI层30与所述线路层40导通，使所述芯片50设置于所述空腔内；所述第一EMI层30与所述线路层40导通后，所述第一EMI层30可通过线路层40接地。
S14、向所述空腔内注入注塑料60以进行注塑包封。
S15、剥离所述上金属板10和所述下金属板20，形成若干个单体双金属板封装结构(100a，100b)。
本发明具体实施方式中，所述上金属板10、下金属板20均可为金属制成的封装板，其材质例如：铜、铁；所述上金属板10和下金属板20可以选取相同的材质也可以选取不同的材质。
优选的，每个单体双金属板封装结构对应一个凹槽，当然，在本发明的其他实施方式中，也可以根据需要，使每个单体双金属板封装结构对应2个或2个以上的凹槽，如此，在切割时，可以以凹槽为单位进行切割，在此不做详细赘述。
优选的，所述第一EMI层30的数量可为1层，也可以为多层；当所述第一EMI层的数量大于等于2层时，在形成的所述凹槽内依次叠加每一层第一EMI层；所述EMI层为英文全称为Electromagnetic Interference，是电磁干扰的简称，该第一EMI层用于屏蔽其外部的信号对其内部芯片的影响，相应的，可根据需屏蔽信号的频率选择EMI层的材质，例如：铜，银，铝等。
优选的，将所述芯片50叠加于所述线路层40的方式，可以采用倒装和/或焊线的方式，结合顶板和底板的方式同样可以采用胶粘、焊锡的方式；相应的，在所述线路层40远离所述下金属板20的一侧印刷锡膏，以使所述芯片50叠加在线路层40上，使所述上金属板10可通过锡膏焊接在所述下金属板20上。本发明优选实施方式中，所述顶板的形成包括以下步骤：M11、在上金属板10的下表面贴覆或印刷光阻材料，以用于曝光显影，定义需要蚀刻的图形区域；M12、通过曝光显影过程去除部分光阻材料以形成蚀刻区域，蚀刻所述蚀刻区域以形成凹槽11；M13、去除所述上金属板10上剩余的光阻材料，在每一所述凹槽11内壁上电镀第一EMI层30以形成顶板。
所述底板的形成包括以下步骤：N11、在下金属板20的上表面贴覆或印刷光阻材料；以用于曝光显影，定义需要蚀刻的图形区域；N12、通过曝光显影过程去除部分光阻材料以形成蚀刻区域，并在所述蚀刻区域电镀线路层40；N13、去除所述下金属20板剩余的光阻材料；N4、在所述线路层40远离所述下金属板20的一侧叠装芯片50以形成底板。
优选的，所述步骤S13之前，所述方法还包括：在最终形成的单体双金属板封装结构外围开设连通所述空腔内部的注塑孔13；例如：该注塑孔开设于顶板或和/或开设于底板，以用于注塑包封时，通过所述注塑孔13向所述空腔内注入注塑料60以进行注塑包封。本发明一具体实施方式中，结合图3所示，在所述凹槽11的侧壁上开设注塑孔13；所述注塑孔13的大小、形状、数量均可以根据需要具体设置；优选的，沿注塑孔13朝向凹槽11内部的延伸方向上，所述注塑孔13的开口尺寸保持不变或依次递减。相应的，当注塑 孔13开设于凹槽11上时，所述步骤S12具体包括：在凹槽内侧电镀第一EMI层30时，在每一所述凹槽11内壁去除注塑孔13的位置上电镀至少一层第一EMI层30以形成顶板；所述步骤S15具体包括：剥离所述上金属板10和所述下金属板20，去除第一EMI层30外部的注塑料，以形成若干个单体双金属板封装结构。需要说明的是，当所述空腔数量大于1时，所述注塑料60还用于还填充相邻空腔之间的部分空隙。
本发明一优选实施方式中，所述步骤S12还包括：所述凹槽11侧壁的下端形成插接部15，所述线路层40上具有与插接部匹配的凹口401，当插接部插入凹口401时，第一EMI层30与线路层40相互导通。所述插接部15上可选择性电镀第一EMI层；本发明优选实施方式中，在每一所述凹槽11内壁去除插接部15的位置上电镀至少一层第一EMI层30以形成顶板；当插接部15插入凹口401时，第一EMI层30在所述线路层40的上方与所述线路层40相互导通。
剥离上金属板10和下金属板20的方式有多种，例如：通过蚀刻的方式剥离上金属板10；通过蚀刻或机械剥离的方式剥离下金属板20；当上、下金属板被剥离后，最终成型的单体双金属板结构上还有可能残留注塑孔13中的注塑料60，此时，在剥离上、下金属板后，还需要将该注塑料60去除以形成若干个单体双金属板封装结构；其去除注塑料60的方式可以为切割，或是采用其他方式去除，在此不做详细赘述。
如图2A所示，所述单体双金属板封装结构100a包括：线路层40，电性连接于所述线路层40上方且与所述线路层40形成空腔的至少一层第一EMI层30；开设于单体双金属板封装结构外围并连通所述空腔内部的注塑孔(未图示)；位于所述空腔内的芯片50；以及填充所述空腔和所述注塑孔13的注塑料60。需要说明的是，在该实施方式中，所述第一EMI层30的数量设置为一层；所述注塑孔自所述第一EMI层30的外壁面延伸至所述空腔内。
结合图2B所示，该单体双金属板封装结构100b在2A基础上，设置第 一EMI层的数量为2层，外侧第一EMI层31可通过内侧的第一EMI层30与线路层40电性连接，以进一步通过线路层40接地。当然，在本发明的其他实施方式中，所述第一EMI层的数量还可以根据需要具体增加，在此不做进一步的赘述；所述注塑孔自所述第一EMI层31的外壁面，通过所述第一EMI层30延伸至所述空腔内。
本发明第一实施方式提供的单体双金属板封装结构的制造方法，通过采用双金属板进行封装来实现EMI屏蔽，而且其无需使用传统的具有型腔模具进行塑封封装，节约制造成本，通过该方法获得的封装结构，其良率及稳定度均得到大幅提升，且工艺简单。
结合图3、4A、4B、5A、5B、6A、6B、6C、6D、6E、6F、7A、7B、7C、7D、7E、7F所示，具体的，图4A、4B所示本发明第二实施方式提供的单体双金属板封装结构的封装方法包括：
S21、提供上金属板10和下金属板20。
S22、在上金属板10的下表面上蚀刻形成至少一个凹槽11，并在每一所述凹槽11内壁上电镀至少一层第一EMI层30以形成顶板；在下金属板20的上表面依次电镀阻焊层70和线路层40，并在所述线路层40远离所述下金属板20的一侧叠装芯片以形成底板。
S23、结合顶板和底板以在所述阻焊层70和第一EMI层30之间形成空腔，使所述第一EMI层30与所述线路层40导通，使所述芯片50设置于所述空腔内；所述第一EMI层30与所述线路层40导通后，所述第一EMI层30可通过线路层40接地。
S24、向所述空腔内注入注塑料60以进行注塑包封。
S25、剥离所述下金属板20。
S26、在阻焊层70上开窗以曝露线路层40，并在其开窗区域701植入焊球80以形成封装体。
S27、切割所述封装体以形成若干个单体双金属板封装结构(100c，100d， 100e，100f，100g，100h)；其形成的封装体为多个单体双金属板封装结构的结合，进一步的，对封装体进行切割形成若干个单体双金属板封装结构。
本发明第二实施方式中，上、下金属板的材质，凹槽11的开设位置及数量，第一EMI层30的数量，所述芯片50的叠加方式，所述顶板的形成方式以及底板与顶板的结合方式，均与所述第一方式相同，在此不再继续赘述。
本发明第二实施方式中，所述底板的形成包括以下步骤：N21、在下金属板的上表面贴覆或印刷阻焊层70；N22、在阻焊层70上贴覆或印刷光阻材料；N23、通过曝光显影过程去除部分光阻材料以形成蚀刻区域，并在所述蚀刻区域电镀线路层40；N24、去除所述第一阻焊70层剩余的光阻材料；N25、在所述线路层40远离所述下金属板20的一侧叠装芯片50以形成底板。
优选的，所述步骤S23之前，所述方法还包括：在最终形成的单体双金属板封装结构外围开设连通所述空腔内部的注塑孔13；例如：该注塑孔开设于顶板或和/或开设于底板，以用于注塑包封时，通过所述注塑孔13向所述空腔内注入注塑料60以进行注塑包封。本发明一具体实施方式中，结合图3所示，在所述凹槽11的侧壁上开设注塑孔13；所述注塑孔13的大小、形状、数量均可以根据需要具体设置；优选的，沿注塑孔13朝向凹槽11内部的延伸方向上，所述注塑孔13的开口尺寸保持不变或依次递减。相应的，当注塑孔13开设于凹槽11上时，所述步骤S22具体包括：在凹槽内侧电镀第一EMI层30时，在每一所述凹槽11内壁去除注塑孔13的位置上电镀至少一层第一EMI层30以形成顶板；需要说明的是，当所述空腔数量大于1时，所述注塑料60用于还填充相邻空腔之间的部分空隙。
本发明一优选实施方式中，所述步骤S22还包括：所述凹槽11侧壁的下端形成插接部15，所述线路层40上具有与插接部匹配的凹口401，当插接部插入凹口401时，第一EMI层30与线路层40相互导通。所述插接部15上可选择性电镀第一EMI层；本发明优选实施方式中，在每一所述凹槽11内壁去除插接部15的位置上电镀至少一层第一EMI层30以形成顶板；当插接 部15插入凹口401时，第一EMI层30在所述线路层40的上方与所述线路层40相互导通。
剥离下金属板20的方式有多种，例如：通过蚀刻或机械剥离的方式剥离下金属板20。如图5A、5B所示，为本发明第三实施方式提供的单体双金属板封装结构的封装方法，该第三实施方式在第二实施方式提供的单体双金属板封装结构的封装方法基础上加以改进，具体的，修改其步骤S26为S26＇，所述步骤S26＇包括：在阻焊层70对应所述凹槽11的区域开窗，并在其开窗区域701植入焊球80后，剥离所述上金属板10形成封装体(100i，100j，100k，100l，100m，100n)。剥离上金属板10的方式有多种，例如：可通过蚀刻的方式剥离下金属板20，当上、下金属板均被剥离后，最终成型的单体双金属板结构上还有可能残留注塑孔13中的注塑料60，此时，在剥离上、下金属板后，还需要将该注塑料60去除以形成若干个单体双金属板封装结构；其去除注塑料60的方式可以为切割，或是采用其他方式去除，在此不做详细赘述。
结合图6A、6B、6C、6D、6E、6F所示，为通过图5A所示单体双金属板封装结构的封装方法所加工制成的6种单体双金属板封装结构；图6A所示的单体双金属板封装结构100c包括：线路层40；电性连接于所述线路层40上方且与所述线路层40形成至少一个空腔的至少一层第一EMI层30；设置于所述空腔外，且叠加设置于所述线路层40下方的阻焊层70，所述阻焊层70设置有若干个开窗区域701；开设于单体双金属板封装结构外围并连通所述空腔内部的注塑孔(未图示)；位于所述空腔内的芯片50；植入所述阻焊层70的开窗区域701以连通所述线路层40的焊球80，以及填充所述空腔和所述注塑孔的注塑料60。本发明一具体实施方式中，所述注塑孔自所述第一EMI层30的外壁面延伸至所述空腔内。
结合6B所示，图6B的单体双金属板封装结构100d在图6A基础上，所述空腔内设置芯片50的方式具有两种，芯片50a采用倒装的方式进行叠加， 芯片50b采用焊线的方式进行叠加。
结合6C所示，图6C的单体双金属板封装结构100e在图6B基础上，将空腔的数量设置为2个，当所述空腔数量大于1时，所述注塑料60还用于填充相邻空腔之间的部分空隙。不同空腔中芯片50的设置方式可以相同也可以不同，该实施方式中，2个空腔中设置芯片50的方式不同，分别采用焊线和倒装的方式进行叠装，在此不做进一步的赘述。
结合6D所示，图6D单体双金属板封装结构100f在图6A基础上，将第一EMI层30的数量设置为2层；外侧第一EMI层31可通过内侧的第一EMI层30与线路层40电性连接，以进一步通过线路层40接地。当然，在本发明的其他实施方式中，所述第一EMI层的数量还可以根据需要具体增加，在此不做进一步的赘述。
结合6E所示，图6E单体双金属板封装结构100g在图6D基础上，所述空腔内设置芯片50的方式具有两种，芯片50a采用倒装的方式进行叠加，芯片50b采用焊线的方式进行叠加。
结合6F所示，图6F单体双金属板封装结构100h在图6E基础上，将空腔的数量设置为2个，当所述空腔数量大于1时，所述注塑料60还用于填充相邻空腔之间的部分空隙。不同空腔中芯片50的设置方式可以相同也可以不同，该实施方式中，2个空腔中设置芯片50的方式不同，分别采用焊线和倒装的方式进行叠装，在此不做进一步的赘述。
结合图7A、7B、7C、7D、7E、7F所示，为通过图4A所示单体双金属板封装结构的封装方法所加工制成的6种单体双金属板封装结构；图7A所示的单体双金属板封装结构100i在图6A基础上，增加设置于所述阻焊层70上方的上金属板10，所述上金属板10连接于所述阻焊层70并契合所述第一EMI层30外壁面设置；本发明一具体实施方式中，所述注塑孔自所述上金属板10的外壁面，通过所述第一EMI层30延伸至所述空腔内。
结合7B所示，图7B单体双金属板封装结构100j在图7A基础上，所述 空腔内设置芯片50的方式具有两种，芯片50a采用倒装的方式进行叠加，芯片50b采用焊线的方式进行叠加。
结合7C所示，图7C单体双金属板封装结构100k在图7B基础上，将空腔的数量设置为2个，当所述空腔数量大于1时，所述注塑料60还用于填充相邻空腔之间的部分空隙。不同空腔中芯片50的设置方式可以相同也可以不同，该实施方式中，2个空腔中设置芯片50的方式不同，分别采用焊线和倒装的方式进行叠装，在此不做进一步的赘述。
结合7D所示，图7D单体双金属板封装结构100l在图7A基础上，将第一EMI层30的数量设置为2层；外侧第一EMI层31可通过内侧的第一EMI层30与线路层40电性连接，以进一步通过线路层40接地。
结合7E所示，图7E单体双金属板封装结构100m在图7D基础上，所述空腔内设置芯片50的方式具有两种，芯片50a采用倒装的方式进行叠加，芯片50b采用焊线的方式进行叠加。
结合7F所示，图7F单体双金属板封装结构100n在图7E基础上，将空腔的数量设置为2个，当所述空腔数量大于1时，所述注塑料60还用于填充相邻空腔之间的部分空隙。不同空腔中芯片50的设置方式可以相同也可以不同，该实施方式中，2个空腔中设置芯片50的方式不同，分别采用焊线和倒装的方式进行叠装，在此不做进一步的赘述。
本发明第二、三实施方式提供的单体双金属板封装结构的制造方法，通过采用双金属板进行封装来实现EMI屏蔽和线路扇出，而且其无需使用传统的具有型腔模具进行塑封封装，节约制造成本，通过该方法获得的封装结构，其良率及稳定度均得到大幅提升，且工艺简单。
如图3、8A、8B、9A、9B、9C所示，本发明第四实施方式提供的单体双金属板封装结构的封装方法，所述方法包括：
S41、提供上金属板10和下金属板20。
S42、在上金属板10的下表面上蚀刻形成至少一个凹槽11，并在每一所 述凹槽11内壁上电镀至少一层第一EMI层30以形成顶板；在下金属板20的上表面依次电镀阻焊层70和线路层40，并在所述线路层40远离所述下金属板的一侧叠装芯片50以形成底板。
S43、结合顶板和底板以在所述阻焊层70和第一EMI层30之间形成空腔，使所述第一EMI层30与所述线路层40导通，使所述芯片50设置于所述空腔内。
S44、向所述空腔内注入注塑料60以进行注塑包封。
S45、切割封装体未包含下金属板20部分，以在下金属板20上方形成若干个不相接的半成型单体。
S46、分别在每一个半成型单体所对应的上金属板10外侧叠加第二EMI层31，所述第二EMI层31和所述第一EMI层30不相接，并在每个第二EMI层31远离所述下金属板20的同侧叠同时叠加一块连接金属板90，以形成双层屏蔽结构；所述第二EMI层31通过上金属板10与第一EMI层30电性连接，进而通过第一EMI层30间接接地；叠加第二EMI层31后，在其上增加连接金属板90，以对封装体整体进行植入焊球操作，当然，在本发明其他实施方式中，若不考虑到工艺的复杂性，也可以在叠加完第二EMI层31后，直接在每个单体上进行植入焊球操作。
S47、剥离所述下金属板20。
S48、在阻焊层70上开窗以曝露线路层40，在其开窗区域701植入焊球80，去除连接金属板90，以直接形成若干个单体双金属板封装结构(100p，100q，100r)。该示例中，其形成的封装体为多个单体双金属板封装结构的结合，当连接金属板90去除后，无需对其进行切割即直接形成若干个单体双金属板封装结构。
本发明第三实施方式中，上、下金属板的材质，凹槽11的开设位置及数量，第一EMI层30的数量，所述芯片50的叠加方式，所述顶板、底板的形成方式以及底板与顶板的结合方式，均与所述第二方式相同，在此不再继续 赘述。
优选的，所述步骤S43之前，所述方法还包括：在最终形成的单体双金属板封装结构外围开设连通所述空腔内部的注塑孔13；例如：该注塑孔开设于顶板或和/或开设于底板，以用于注塑包封时，通过所述注塑孔13向所述空腔内注入注塑料60以进行注塑包封。本发明一具体实施方式中，结合图3所示，在所述凹槽11的侧壁上开设注塑孔13；所述注塑孔13的大小、形状、数量均可以根据需要具体设置；优选的，沿注塑孔13朝向凹槽11内部的延伸方向上，所述注塑孔13的开口尺寸保持不变或依次递减。相应的，当注塑孔13开设于凹槽11上时，所述步骤S42具体包括：在凹槽内侧电镀第一EMI层30时，在每一所述凹槽11内壁去除注塑孔13的位置上电镀至少一层第一EMI层30以形成顶板。需要说明的是，当所述空腔数量大于1时，所述注塑料60用于还填充相邻空腔之间的部分空隙。
本发明一优选实施方式中，所述步骤S42还包括：所述凹槽11侧壁的下端形成插接部15，所述线路层40上具有与插接部匹配的凹口401，当插接部插入凹口401时，第一EMI层30与线路层40相互导通。所述插接部15上可选择性电镀第一EMI层；本发明优选实施方式中，在每一所述凹槽11内壁去除插接部15的位置上电镀至少一层第一EMI层30以形成顶板；当插接部15插入凹口401时，第一EMI层30在所述线路层40的上方与所述线路层40相互导通。
剥离上金属板10、下金属板20以及连接金属板90的方式有多种，例如：通过蚀刻的方式剥离上金属板10；通过蚀刻或机械剥离的方式剥离下金属板20和连接金属板90。
结合图9A、9B、9C所示，分别为通过图8A所示单体双金属板封装结构的封装方法所加工制成的3种单体双金属板封装结构；图9A所示的单体双金属板封装结构100p包括：线路层40；电性连接于所述线路层40上方且与所述线路层40形成至少一个空腔的第一EMI层30；设置于所述阻焊层70 上方的上金属板10，所述上金属板10连接于所述阻焊层70并契合所述第一EMI层30外壁面设置；契合所述上金属板10外壁面设置且处于阻焊层上方的第二EMI层31，所述第二EMI层31通过所述上金属板10与所述第一EMI层31导通；设置于所述空腔外，且叠加设置于所述线路层40下方的阻焊层70，所述阻焊层70设置有若干个开窗区域701；开设于单体双金属板封装结构外围并连通所述空腔内部的注塑孔13；位于所述空腔内的芯片50；植入所述阻焊层70的开窗区域701以连通所述线路层40的焊球80，以及填充所述空腔和所述注塑孔11的注塑料60。本发明一具体实施方式中，所述注塑孔自所述第二EMI层31的外壁面，通过所述上金属板10以及所述第一EMI层30延伸至所述空腔内。
结合9B所示，图9B单体双金属板封装结构100q在图9A基础上，所述空腔内设置芯片50的方式具有两种，芯片50a采用倒装的方式进行叠加，芯片50b采用焊线的方式进行叠加。
结合9C所示，图9C单体双金属板封装结构100r在图9B基础上，将空腔的数量设置为2个，当所述空腔数量大于1时，所述注塑料60还用于填充相邻空腔之间的部分空隙。不同空腔中芯片50的设置方式可以相同也可以不同，该实施方式中，2个空腔中设置芯片50的方式不同，分别采用焊线和倒装的方式进行叠装，在此不做进一步的赘述。
本发明第四实施方式提供的单体双金属板封装结构的制造方法，通过采用双金属板进行封装来实现EMI屏蔽和线路扇出，而且其无需使用传统的具有型腔模具进行塑封封装，节约制造成本，通过该方法获得的封装结构，其良率及稳定度均得到大幅提升，且工艺简单。
需要说明的是，在本发明的其他实施方式中，还可以采用PoP封装方式将任两个以上的上述单体双金属板封装结构进行堆叠装配以形成新的单体结构，在此不做详细赘述。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式 仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种单体双金属板封装结构的封装方法，其特征在于，所述方法包括：
    S1、提供上金属板和下金属板；
    S2、在上金属板的下表面上蚀刻形成至少一个凹槽，并在每一所述凹槽内壁上电镀至少一层第一EMI层以形成顶板；
    在下金属板的上表面依次电镀阻焊层和线路层，并在所述线路层远离所述下金属板的一侧叠装芯片以形成底板；
    S3、结合顶板和底板以在所述阻焊层和第一EMI层之间形成空腔，使所述第一EMI层与所述线路层导通，使所述芯片设置于所述空腔内；
    S4、向所述空腔内注入注塑料以进行注塑包封；
    S5、剥离所述下金属板；
    S6、在阻焊层上开窗以曝露线路层，并在其开窗区域植入焊球以形成封装体；
    S7、切割所述封装体以形成若干个单体双金属板封装结构。
  2. 根据权要求1所述的单体双金属板封装结构的封装方法，其特征在于，
    所述步骤S6还包括：
    在阻焊层上开窗以曝露线路层，并在其开窗区域植入焊球后，剥离所述上金属板形成封装体。
  3. 根据权要求1所述的单体双金属板封装结构的封装方法，其特征在于，
    所述步骤S2还包括：
    在所述凹槽的侧壁上开设注塑孔；在每一所述凹槽内壁去除注塑孔的位置上电镀至少一层第一EMI层以形成顶板；
    所述步骤S4具体包括：通过所述注塑孔向所述空腔内注入注塑料以进行注塑包封。
  4. 根据权要求3所述的单体双金属板封装结构的封装方法，其特征在于，
    所述步骤S2还包括：
    M1、在上金属板的下表面贴覆或印刷光阻材料；
    M2、通过曝光显影过程去除部分光阻材料以形成蚀刻区域，蚀刻所述蚀刻区域以形成凹槽；
    M3、去除所述上金属板剩余的光阻材料，并在所述凹槽内壁上电镀第一EMI层以形成顶板。
  5. 根据权要求3所述的单体双金属板封装结构的封装方法，其特征在于，
    沿注塑孔朝向凹槽内部的延伸方向上，所述注塑孔的开口尺寸保持不变或依次递减。
  6. 根据权要求1所述的单体双金属板封装结构的封装方法，其特征在于，
    所述步骤S2还包括：
    N1、在下金属板的上表面贴覆或印刷阻焊层；
    N2、在阻焊层上贴覆或印刷光阻材料；
    N3、通过曝光显影过程去除部分光阻材料以形成蚀刻区域，并在所述蚀刻区域电镀线路层；
    N4、去除所述阻焊层剩余的光阻材料；
    N5、在所述线路层远离所述下金属板的一侧叠装芯片以形成底板。
  7. 根据权要求1所述的单体双金属板封装结构的封装方法，其特征在于，
    所述凹槽侧壁的下端形成插接部，所述线路层上具有与插接部匹配的凹口，当插接部插入凹口时，第一EMI层与线路层相互导通。
  8. 根据权要求7所述的单体双金属板封装结构的封装方法，其特征在于，
    所述步骤S2具体包括：在每一所述凹槽内壁去除插接部的位置上电镀至少一层第一EMI层以形成顶板；
    当插接部插入凹口时，第一EMI层在所述线路层的上方与所述线路层相互导通。
  9. 一种单体双金属板封装结构，其特征在于，所述单体双金属板封装结 构包括：
    线路层；
    电性连接于所述线路层上方且与所述线路层形成至少一个空腔的至少一层第一EMI层；
    设置于所述空腔外，且叠加设置于所述线路层下方的阻焊层，所述阻焊层设置有若干个开窗区域；
    开设于单体双金属板封装结构外围并连通所述空腔内部的注塑孔；
    位于所述空腔内的芯片；
    植入所述阻焊层的开窗区域以连通所述线路层的焊球，
    以及填充所述空腔和所述注塑孔的注塑料。
  10. 根据权利要求9所述的单体双金属板封装结构，其特征在于，所述单体双金属板封装结构还包括：
    设置于所述阻焊层上方的上金属板，所述上金属板连接于所述阻焊层并契合所述第一EMI层外壁面设置；
    所述注塑孔连通所述空腔内部与上金属板外部。
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