CN104520978A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- CN104520978A CN104520978A CN201380041840.6A CN201380041840A CN104520978A CN 104520978 A CN104520978 A CN 104520978A CN 201380041840 A CN201380041840 A CN 201380041840A CN 104520978 A CN104520978 A CN 104520978A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000008393 encapsulating agent Substances 0.000 claims description 66
- 239000000463 material Substances 0.000 claims description 33
- 230000006835 compression Effects 0.000 claims description 17
- 238000007906 compression Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 6
- 238000000748 compression moulding Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 37
- 239000002184 metal Substances 0.000 abstract description 37
- 239000003566 sealing material Substances 0.000 abstract 5
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000007711 solidification Methods 0.000 description 5
- 230000008023 solidification Effects 0.000 description 5
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 229920000840 ethylene tetrafluoroethylene copolymer Polymers 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 235000011837 pasties Nutrition 0.000 description 2
- 229920005644 polyethylene terephthalate glycol copolymer Polymers 0.000 description 2
- -1 polypropylene Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 229920000800 acrylic rubber Polymers 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000013034 phenoxy resin Substances 0.000 description 1
- 229920006287 phenoxy resin Polymers 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Abstract
本发明提供可谋求生产效率的提高的半导体装置的制造方法。半导体装置(1)的制造方法包含使密封材料(7)固化的工序,在该工序中,施予将半导体元件(3)密封的密封材料(7),在与半导体元件(3)对置的模具上设置离型膜(F),并利用上模具(22)和下模具(24)使密封材料(7)固化;在离型膜(F)的与密封材料(7)接触的一侧,预先设置用于将电磁波屏蔽的金属层(9),在使密封材料(7)固化的工序中,将金属层(9)转印到密封材料(7)上。
Description
技术领域
本发明涉及半导体装置的制造方法。
背景技术
近年来,随着电子设备小型化的要求,半导体元件的表面高密度搭载需要进一步改善。因此,近年来采用多段地层叠有多个半导体元件的所谓堆叠封装型的半导体装置。对于这种堆叠封装型的半导体装置而言,由于将半导体元件集聚地进行配置,因此会发生因外界噪音所导致的问题(电磁波障碍)。这种噪音问题越是在电子设备的数字化、高速化、高频率化时,变得越显著。因此,为了抑制因噪音所导致的影响,将屏蔽电磁波的电磁波屏蔽片材形成在将半导体元件密封的密封材料上(例如参照专利文献1)。
关于上述电磁波屏蔽片材的形成,例如已知专利文献2所记载的半导体装置的制造方法。专利文献2所记载的半导体装置的制造方法在通过使用了上模具和下模具的传递模塑成型、用密封材料将半导体元件密封的工序中,在配置于上模具的离型膜(载体膜)上涂布电磁波屏蔽树脂、形成密封材料时,将电磁波屏蔽树脂转印至密封材料上并使其固化。
现有技术文献
专利文献
专利文献1:日本专利第4133637号公报
专利文献2:日本特开2007-287937号公报
发明内容
发明欲解决的技术问题
但是,上述专利文献2所记载的方法在形成密封材料时,由于每次都需要在载体膜上涂布电磁波屏蔽树脂的作业,因此存在费功夫的问题。半导体装置的制造工序中,对于生产效率期待进一步改善。
本发明是为了解决上述课题而完成的,其目的在于提供能够实现提高生产效率的半导体装置的制造方法。
用于解决技术问题的手段
为了解决上述课题,本发明的半导体装置的制造方法的特征在于,其通过使用了具有上模具和下模具的压塑模具的压塑成型方式来制造半导体装置,所述制造方法包含使密封材料固化的工序,在该工序中,施予将半导体元件密封的密封材料,在与半导体元件对置的模具上设置离型膜,并利用上模具和下模具使密封材料固化;在离型膜的与密封材料接触的一侧预先设置用于将电磁波屏蔽的屏蔽材料,在使密封材料固化的工序中将屏蔽材料转印到密封材料上。
该半导体装置的制造方法在离型膜上预先设置屏蔽材料。离型膜是按照密封材料不与模具直接接触的方式设置的构件,在将密封材料固化时,被保持在与半导体元件对置的模具中。通过在该离型膜上预先设置屏蔽材料,能够在利用压塑模具使密封材料固化的工序中,将电磁波屏蔽用的屏蔽材料转印到密封材料上。因此,能够在省略了如以往那样逐一涂布屏蔽材料的作业的同时,进行密封材料的固化和屏蔽材料的形成。另外,可通过压塑成型方式连续地进行密封材料的形成和屏蔽材料的转印。因此,可以实现提高生产效率。
一个实施方式可以是屏蔽材料在离型膜上设置在与半导体元件的搭载位置相对应的位置上的方式。另外,一个实施方式可以是将多个半导体元件搭载在基板上、屏蔽材料在离型膜上被设置在不包含在将多个半导体元件分割成单个时的切断线的位置上的方式。由此,由于不需要将屏蔽材料形成在密封材料的整个面上,因此可以实现制造成本的降低。另外,在切断密封材料时,由于金属部分不会接触到用于切断的刀刃上,因此可以抑制切削时所产生的金属碎屑的发生、可以抑制制造装置的损伤。
发明效果
通过本发明,可以实现生产效率的提高。
附图说明
图1是表示通过一个实施方式的半导体装置的制造方法所制造得到的半导体装置的截面构成的截面图。
图2是说明半导体装置的制造方法的图。
图3是说明半导体装置的制造方法的图。
图4是说明半导体装置的制造方法的图。
图5是形成有金属层的离型膜的截面图。
图6是另一方式的形成有屏蔽材料的离型膜的截面图。
图7是另一方式的形成有屏蔽材料的离型膜的截面图。
图8是表示图7所示的转印有屏蔽材料的半导体装置的平面图。
图9是说明另一方式的半导体装置的制造方法的图。
具体实施方式
以下参照附图对本发明的优选实施方式详细地进行说明。其中,附图的说明中对相同或相当要素使用相同符号并省略重复的说明。
图1是表示通过一个实施方式的半导体装置的制造方法所制造得到的半导体装置的截面构成的截面图。图1所示的半导体装置1是多段地层叠有多个半导体芯片3的堆叠封装型的半导体装置。其中,图1所示的半导体装置1是被切断成各个半导体装置(封装单元)之前的状态。
半导体装置1在基板5上搭载有多个半导体芯片(半导体元件)3。另外,半导体芯片3多段地层叠。半导体芯片3与基板5电连接,层叠的半导体芯片3、3彼此相互间可以电连接、也可不电连接。作为将半导体芯片3与基板5以及半导体芯片3、3彼此电连接的方式,例如可以使用引线接合方式、凸块接合方式等。
多个半导体芯片3在基板5上被密封材料7密封。密封材料7是具有热固化性的树脂,例如可以使用固态、液状的环氧基系密封材料。例如,固态密封材料中有日立化成工业株式会社制CEL-9740等CEL系列、液状密封材料中有日立化成工业株式会社制CEL-C-2902等CEL-C系列。密封材料7按照将半导体芯片3整体覆盖的方式设置。
在密封材料7的表面上设置有金属层(金属膜、屏蔽材料)9。本实施方式在半导体装置1中在密封材料7的表面整体形成有金属层9。金属层9作为用于将电磁波屏蔽的电磁波屏蔽层发挥功能。其中,这里所说的屏蔽不仅是指完全地将电磁波隔绝,还包括抑制因电磁波所导致的噪音的影响的情况。金属层9例如可使用金、铝、镍、铟、铁、铜等。另外,从防止小丘或迁移的观点出发,上述材料优选使用经合金化的材料。金属层9的厚度例如从膜切断的容易性的观点出发,优选为3μm以下。另外,金属层9的厚度从电磁波的屏蔽性的观点出发,优选为0.05μm以上。
接着,一边参照图2~图4一边说明上述半导体装置1的制造方法。图2~图4是说明半导体装置的制造方法的图。半导体装置1利用压塑模具方式(压塑成型方式)制造。
首先,对压塑模具方式中使用的压塑模具20进行说明。压塑模具20是对密封材料7进行压缩、加热、使其固化的模具。压塑模具20由上模具22和下模具24构成。下模具24是载置(配置)基板5的部分、具有平坦面。上模具22是与半导体元件3对置的模具,在上模具22上设有截面大致成梯形形状的凹部26。在上模具22和下模具24中内置有用于对密封材料7进行加热固化的加热器(未图示)。
上模具22的凹部26中在将密封材料7固化时、沿着其内表面设有离型膜F。上模具22中设有未图示的吸引机构、离型膜F在上模具22中被吸附保持。
离型膜F是按照密封材料7不与上模具22直接接触的方式存在于上模具22与密封材料7之间的构件。在离型膜F保持于上模具22的状态下,离型膜F的密封材料7一侧的表面具有剥离性。其中,这里所说的剥离性还包括具有将金属层9粘接保持的程度的粘接性的情况。另外,离型膜F具有可耐受因压塑模具20的加热器产生的加热的耐热性。离型膜F可以使用挂在送出轨与卷取轨之间的长条状膜、被截断成将基板5覆盖程度的大小的膜状膜或者将两者组合而成的膜。
作为离型膜F,例如可优选地使用四氟乙烯·六氟丙烯聚合物(FEP)膜、氟含浸玻璃布、聚对苯二甲酸乙二醇酯(PET)膜、乙烯·四氟乙烯共聚物(ETFE)膜、聚丙烯膜、聚偏氯乙烯等。
如图5所示,在离型膜F的表面上预先设置金属层9。金属层9在离型膜F保持于上模具22的状态下设置在离型膜F的与密封材料7接触的一侧的表面上。金属层9通过真空蒸镀法等蒸镀法、DC溅射、RF溅射等溅射法、离子镀、非电解镀覆等形成在离型膜F上。蒸镀法和溅射法从制膜成本、制造容易性的观点出发特别优选。
接着,对半导体装置1的制造顺序进行说明。如图2所示,首先在下模具24上配置搭载有半导体芯片3的基板5。随后,在基板5上通过例如灌封施予固化前的糊状密封材料7。此时,离型膜F被吸附保持于上模具22上。
接着,如图3所示,将下模具24与上模具22对合,在将密封材料7压缩的同时对其加热。由此,密封材料7固化成沿着上模具22的凹部26的形状。进而,在密封材料7的固化后,如图4所示,上模具22自下模具24离开。此时,由于离型膜F具有剥离性,与离型膜F相比密封材料7的粘合力更高,因此金属层9自离型膜F剥离、附着并转印至密封材料7。由此,在对密封材料7进行固化的固化工序中,可以在密封材料7的表面上形成金属层9。如上所述,将搭载于基板5上的半导体芯片3密封。
如上所述,本实施方式在离型膜F上预先设置金属层9。离型膜F是按照密封材料7不直接接触上模具22的方式设置的构件,在对密封材料7进行固化时保持在压塑模具20的上模具22上。通过在该离型膜F上预先设置金属层9,能够在利用压塑模具20使密封材料7固化的工序中,将电磁波屏蔽用的金属层9转印至密封材料7。因此,可以同时进行密封材料7的固化和金属层9的形成。其结果,可以实现生产效率的提高。
另外,本实施方式还可利用压塑模具方式连续地进行密封材料7的形成和金属层9的形成。因此,可以进一步实现半导体装置1的生产效率的提高。
本发明并不限于上述实施方式。例如,上述实施方式以在离型膜F上设置金属层9的构成为一个例子进行了说明,但屏蔽材料也可以是除金属层9以外的材料。图6是另一方式的形成有屏蔽材料的离型膜的截面图。
如图6(a)所示,作为屏蔽材料,可以使用有机膜11。有机膜11含有电磁波屏蔽材料。作为有机膜11,例如可以使用聚酰亚胺、聚酰胺酰亚胺、丙烯酸橡胶、苯氧树脂、环氧树脂等。另外,作为电磁波屏蔽材料,还可以使用铁素体等。有机膜11的厚度优选例如为1μm~300μm左右。
另外,如图6(b)所示,作为屏蔽材料,还可以使用层叠有金属层9和有机膜11的材料。当为这种构成时,通过在离型膜F上形成金属层9之后层压有机膜11,可以获得层叠有金属层9和有机膜11的构成。
此外,设置在离型膜F上的金属层9(有机膜11)也可以仅形成于与半导体芯片3的搭载位置相对应的位置上。如图7所示,将金属层9仅设置在与半导体芯片3的搭载位置相对应的部分上。利用这种设置有金属层9的离型膜F,如图8所示,在半导体装置1A中仅在与半导体芯片3相对应的位置上形成金属层9。即,金属层9也可以形成在密封材料7的表面整体上,也可对应半导体芯片3的平面尺寸地形成。
另外,金属层9也可按照不包含在将半导体装置1A切断成封装单元时的切割线(切断线)内的方式形成。如此,通过在特定位置形成金属层9的构成,与在密封材料7的整个面上形成金属层9的情况相比,可以谋求制造成本的降低。
此外,作为压塑模具,例如可以使用图9所示的压塑模具20A。如图9所示,压塑模具20A由上模具24A和下模具22A构成。下模具22A是与半导体元件3对置的模具,在下模具22A上设置截面大致呈梯形形状的凹部26A。上模具24A是保持基板5的部分,具有平坦面。上模具24A和下模具22A中内置有用于对密封材料7进行加热固化的加热器(未图示)。
下模具22A的凹部26A中在对密封材料7进行固化时沿着其内表面设有离型膜F。对使用了具有这种构成的压塑模具20A的半导体装置1的制造顺序进行说明。
如图9所示,首先在上模具24A上保持搭载有半导体芯片3的基板5。接着,例如通过灌封,向吸附保持于下模具22A的离型膜F上施予固化前的糊状密封材料7。
接着,将上模具24A和下模具22A对合,在将密封材料7压缩的同时对其加热。由此,密封材料7固化成沿着下模具22A的凹部26A的形状。此时,金属层9自离型膜F剥离、附着并转印至密封材料7上。由此,在对密封材料7进行固化的固化工序中,可以在密封材料7的表面上形成金属层9。如上所述,利用密封材料7将半导体芯片3密封。
符号说明
1、1A 半导体装置
3 半导体芯片(半导体元件)
5 基板
7 密封材料
9 金属层(屏蔽材料)
11 有机膜(屏蔽材料)
20、20A 压塑模具
22、24A 上模具
24、22A 下模具
F 离型膜
Claims (3)
1.一种半导体装置的制造方法,其特征在于,其通过使用了具有上模具和下模具的压塑模具的压塑成型方式来制造半导体装置,
所述制造方法包含使密封材料固化的工序,在该工序中,施予将半导体元件密封的密封材料,在与所述半导体元件对置的模具上设置离型膜,并利用所述上模具和所述下模具使所述密封材料固化,
在所述离型膜的与所述密封材料接触的一侧,预先设置用于将电磁波屏蔽的屏蔽材料,
在使所述密封材料固化的工序中,将所述屏蔽材料转印到所述密封材料上。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,在所述离型膜上,所述屏蔽材料被设置在与所述半导体元件的搭载位置对应的位置上。
3.根据权利要求2所述的半导体装置的制造方法,其特征在于,基板上搭载有多个所述半导体元件,
在所述离型膜上,所述屏蔽材料被设置在不包含在将多个所述半导体元件分割成单个时的切断线的位置上。
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CN112602159A (zh) * | 2018-08-28 | 2021-04-02 | 松下知识产权经营株式会社 | 电容器及其制造方法 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10629457B2 (en) * | 2012-06-08 | 2020-04-21 | Hitachi Chemical Company, Ltd. | Method for manufacturing semiconductor device |
JP6237732B2 (ja) * | 2015-08-28 | 2017-11-29 | 東洋インキScホールディングス株式会社 | 電子部品モジュールの製造方法 |
KR102497577B1 (ko) | 2015-12-18 | 2023-02-10 | 삼성전자주식회사 | 반도체 패키지의 제조방법 |
JP6623747B2 (ja) * | 2015-12-25 | 2019-12-25 | 日立化成株式会社 | 配線基板の製造方法 |
US9953929B2 (en) | 2016-03-18 | 2018-04-24 | Intel Corporation | Systems and methods for electromagnetic interference shielding |
US9685413B1 (en) * | 2016-04-01 | 2017-06-20 | Intel Corporation | Semiconductor package having an EMI shielding layer |
JP6711423B2 (ja) * | 2017-08-31 | 2020-06-17 | 住友ベークライト株式会社 | 電磁波シールド用フィルム |
CN111183010A (zh) * | 2017-10-06 | 2020-05-19 | 东丽薄膜先端加工股份有限公司 | 模塑成型用脱模膜及模塑成型法 |
KR20190076250A (ko) | 2017-12-22 | 2019-07-02 | 삼성전자주식회사 | 반도체 패키지 및 반도체 모듈 |
KR102187350B1 (ko) * | 2018-11-20 | 2020-12-07 | 주식회사 에스모머티리얼즈 | 반도체 패키지 제조용 몰딩 장치 및 이를 통하여 제조된 반도체 패키지 |
KR102108974B1 (ko) * | 2018-11-27 | 2020-05-28 | 제너셈(주) | 전자파 차폐면 제거 방법 |
TWI744572B (zh) | 2018-11-28 | 2021-11-01 | 蔡憲聰 | 具有封裝內隔室屏蔽的半導體封裝及其製作方法 |
US10896880B2 (en) | 2018-11-28 | 2021-01-19 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and fabrication method thereof |
US11211340B2 (en) | 2018-11-28 | 2021-12-28 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding |
US11239179B2 (en) | 2018-11-28 | 2022-02-01 | Shiann-Tsong Tsai | Semiconductor package and fabrication method thereof |
US10923435B2 (en) | 2018-11-28 | 2021-02-16 | Shiann-Tsong Tsai | Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance |
JP6802314B2 (ja) * | 2018-11-28 | 2020-12-16 | 宗哲 蔡 | 半導体パッケージ及びその製造方法 |
KR102662146B1 (ko) * | 2018-12-17 | 2024-05-03 | 삼성전자주식회사 | 반도체 패키지 |
CN113658878A (zh) * | 2021-08-13 | 2021-11-16 | 青岛歌尔智能传感器有限公司 | 电磁屏蔽结构的制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007287937A (ja) * | 2006-04-17 | 2007-11-01 | Kyocera Chemical Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2010123839A (ja) * | 2008-11-21 | 2010-06-03 | Sharp Corp | 半導体モジュール |
CN102082103A (zh) * | 2009-12-01 | 2011-06-01 | 三星电机株式会社 | 制造电子组件的装置及制造电子组件的方法 |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4326238A (en) * | 1977-12-28 | 1982-04-20 | Fujitsu Limited | Electronic circuit packages |
JPS5635494A (en) * | 1979-08-30 | 1981-04-08 | Showa Denko Kk | High heat transfer electric insulating substrate |
US5057903A (en) * | 1989-07-17 | 1991-10-15 | Microelectronics And Computer Technology Corporation | Thermal heat sink encapsulated integrated circuit |
US4994903A (en) * | 1989-12-18 | 1991-02-19 | Texas Instruments Incorporated | Circuit substrate and circuit using the substrate |
JP3207286B2 (ja) | 1993-03-22 | 2001-09-10 | 株式会社東芝 | 樹脂封止型半導体装置 |
JPH08250533A (ja) | 1995-03-10 | 1996-09-27 | Nitto Denko Corp | 半導体パッケージの製造方法 |
US6541310B1 (en) * | 2000-07-24 | 2003-04-01 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a thin and fine ball-grid array package with embedded heat spreader |
DE10129388B4 (de) * | 2001-06-20 | 2008-01-10 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauteils |
JP3575478B2 (ja) * | 2002-07-03 | 2004-10-13 | ソニー株式会社 | モジュール基板装置の製造方法、高周波モジュール及びその製造方法 |
JP4133637B2 (ja) | 2003-07-11 | 2008-08-13 | 三井化学株式会社 | 半導体素子接着用電磁波遮断シートおよび半導体装置 |
US7109520B2 (en) * | 2003-10-10 | 2006-09-19 | E. I. Du Pont De Nemours And Company | Heat sinks |
US20050127484A1 (en) * | 2003-12-16 | 2005-06-16 | Texas Instruments Incorporated | Die extender for protecting an integrated circuit die on a flip chip package |
JP5101788B2 (ja) | 2003-12-22 | 2012-12-19 | 東レ・ダウコーニング株式会社 | 半導体装置の製造方法および半導体装置 |
JP4903987B2 (ja) | 2004-03-19 | 2012-03-28 | 東レ・ダウコーニング株式会社 | 半導体装置の製造方法 |
US7633170B2 (en) * | 2005-01-05 | 2009-12-15 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and manufacturing method thereof |
US20060208365A1 (en) * | 2005-03-17 | 2006-09-21 | Chipmos Technologies Inc. | Flip-chip-on-film package structure |
US8062930B1 (en) * | 2005-08-08 | 2011-11-22 | Rf Micro Devices, Inc. | Sub-module conformal electromagnetic interference shield |
TW200721408A (en) * | 2005-11-30 | 2007-06-01 | Chun-Liang Lin | Light-emitting device and process for manufacturing the same |
US7701040B2 (en) * | 2007-09-24 | 2010-04-20 | Stats Chippac, Ltd. | Semiconductor package and method of reducing electromagnetic interference between devices |
US7906371B2 (en) * | 2008-05-28 | 2011-03-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield |
JP2010114256A (ja) * | 2008-11-06 | 2010-05-20 | Panasonic Corp | 半導体装置、および半導体装置の製造方法 |
KR101056748B1 (ko) * | 2009-09-15 | 2011-08-16 | 앰코 테크놀로지 코리아 주식회사 | 전자파 차폐수단을 갖는 반도체 패키지 |
KR101099577B1 (ko) * | 2009-09-18 | 2011-12-28 | 앰코 테크놀로지 코리아 주식회사 | 전자파 차폐 및 열방출 수단을 갖는 반도체 패키지 |
US8378466B2 (en) * | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8569869B2 (en) * | 2010-03-23 | 2013-10-29 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulation and method of manufacture thereof |
US8012799B1 (en) | 2010-06-08 | 2011-09-06 | Freescale Semiconductor, Inc. | Method of assembling semiconductor device with heat spreader |
CN102339763B (zh) * | 2010-07-21 | 2016-01-27 | 飞思卡尔半导体公司 | 装配集成电路器件的方法 |
TWI491010B (zh) * | 2011-03-23 | 2015-07-01 | Universal Scient Ind Shanghai | 微小化電磁干擾防護結構及其製作方法 |
TWI460843B (zh) * | 2011-03-23 | 2014-11-11 | Universal Scient Ind Shanghai | 電磁屏蔽結構及其製作方法 |
US20140346686A1 (en) * | 2011-09-02 | 2014-11-27 | Fu Peng | Methods for forming color images on memory devices and memory devices formed thereby |
WO2013086741A1 (en) * | 2011-12-16 | 2013-06-20 | Sandisk Semiconductor (Shanghai) Co., Ltd. | Emi shielding and thermal dissipation for semiconductor device |
US9947606B2 (en) * | 2012-04-26 | 2018-04-17 | Sandisk Information Technology (Shanghai) Co., Ltd. | Semiconductor device including electromagnetic absorption and shielding |
US10629457B2 (en) * | 2012-06-08 | 2020-04-21 | Hitachi Chemical Company, Ltd. | Method for manufacturing semiconductor device |
US9159716B2 (en) * | 2013-08-30 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked chip layout having overlapped active circuit blocks |
JP6254509B2 (ja) * | 2014-11-07 | 2017-12-27 | 信越化学工業株式会社 | 電磁波シールド性支持基材付封止材及び封止後半導体素子搭載基板、封止後半導体素子形成ウエハ並びに半導体装置 |
US9953929B2 (en) * | 2016-03-18 | 2018-04-24 | Intel Corporation | Systems and methods for electromagnetic interference shielding |
-
2013
- 2013-06-05 US US14/405,961 patent/US10629457B2/en active Active
- 2013-06-05 KR KR1020177002742A patent/KR101944200B1/ko active IP Right Grant
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- 2013-06-07 TW TW102120422A patent/TWI594391B/zh active
-
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- 2016-08-24 JP JP2016163992A patent/JP6361709B2/ja active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007287937A (ja) * | 2006-04-17 | 2007-11-01 | Kyocera Chemical Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2010123839A (ja) * | 2008-11-21 | 2010-06-03 | Sharp Corp | 半導体モジュール |
CN102082103A (zh) * | 2009-12-01 | 2011-06-01 | 三星电机株式会社 | 制造电子组件的装置及制造电子组件的方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106935522A (zh) * | 2015-12-29 | 2017-07-07 | 意法半导体有限公司 | 用于制造具有导电屏蔽层的集成电路(ic)封装体的方法 |
CN109153239A (zh) * | 2016-05-20 | 2019-01-04 | 日立化成株式会社 | 脱模膜 |
CN109153155A (zh) * | 2016-05-20 | 2019-01-04 | 日立化成株式会社 | 脱模膜 |
CN109153155B (zh) * | 2016-05-20 | 2020-11-10 | 昭和电工材料株式会社 | 脱模膜 |
CN108010902A (zh) * | 2016-10-31 | 2018-05-08 | 东和株式会社 | 电路部件、电路部件的制造方法以及电路部件的制造装置 |
CN108010902B (zh) * | 2016-10-31 | 2021-01-01 | 东和株式会社 | 电路部件、电路部件的制造方法以及电路部件的制造装置 |
CN108695171A (zh) * | 2018-07-13 | 2018-10-23 | 江苏长电科技股份有限公司 | 单体双金属板封装结构及其封装方法 |
CN108695170A (zh) * | 2018-07-13 | 2018-10-23 | 江苏长电科技股份有限公司 | 单体双金属板封装结构及其封装方法 |
WO2020010837A1 (zh) * | 2018-07-13 | 2020-01-16 | 江苏长电科技股份有限公司 | 单体双金属板封装结构及封装方法 |
CN112602159A (zh) * | 2018-08-28 | 2021-04-02 | 松下知识产权经营株式会社 | 电容器及其制造方法 |
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Publication number | Publication date |
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US10629457B2 (en) | 2020-04-21 |
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US20150118792A1 (en) | 2015-04-30 |
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JP6361709B2 (ja) | 2018-07-25 |
CN110620052A (zh) | 2019-12-27 |
KR101944200B1 (ko) | 2019-01-30 |
JPWO2013183671A1 (ja) | 2016-02-01 |
JP2016201573A (ja) | 2016-12-01 |
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KR20170016026A (ko) | 2017-02-10 |
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