WO2021017038A1 - 化合物半导体单晶薄膜层的转移方法及单晶GaAs-OI复合晶圆的制备方法 - Google Patents
化合物半导体单晶薄膜层的转移方法及单晶GaAs-OI复合晶圆的制备方法 Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 150000001875 compounds Chemical class 0.000 title claims abstract description 37
- 239000002131 composite material Substances 0.000 title claims abstract description 27
- 238000012546 transfer Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 100
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910002804 graphite Inorganic materials 0.000 claims abstract description 48
- 239000010439 graphite Substances 0.000 claims abstract description 48
- 230000007704 transition Effects 0.000 claims abstract description 39
- 238000002360 preparation method Methods 0.000 claims abstract description 23
- 239000013078 crystal Substances 0.000 claims description 120
- 235000012431 wafers Nutrition 0.000 claims description 62
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 61
- 239000010408 film Substances 0.000 claims description 25
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 238000003486 chemical etching Methods 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 10
- 230000006872 improvement Effects 0.000 description 10
- 230000010354 integration Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 229910008045 Si-Si Inorganic materials 0.000 description 2
- 229910006411 Si—Si Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- 239000012535 impurity Substances 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000007306 functionalization reaction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
- H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds
Definitions
- the invention relates to the technical field of semiconductor device integration, in particular to a method for transferring a compound semiconductor single crystal thin film layer and a method for preparing a single crystal GaAs-OI composite wafer.
- channel materials with high mobility In order to increase the on-state current of MOS transistors, channel materials with high mobility must be used, such as germanium (Ge) and group III-V semiconductors. Group III-V compound semiconductor materials also have the ability to form high-quality MOS interfaces. As a result, the performance of MOS devices of the same size is significantly better than that of silicon-based MOS devices. Especially when the 7nm technology node is reached, for FinFET technology, the gate may lose its ability to control the channel, and III-V group materials may be used for the channel. On the other hand, people hope that chips will integrate more functions.
- SOI as a highly efficient integrated material, is considered to have unique structure in many fields. SOI devices can effectively suppress the shortcomings of bulk silicon devices, and give full play to the potential of silicon integration technology to ensure that the integrated circuit industry develops rapidly in accordance with Moore’s Law. A great tool for development.
- the existing method of epitaxial growth of single crystal GaAs on Si substrate is generally used.
- the disadvantage of this method is that the lattice structure of Si substrate is different from that of single crystal GaAs, which may be caused by dislocations during the epitaxial growth process. The reason causes the lattice mismatch, which makes the epitaxially grown GaAs crystals not of high quality, which cannot meet the requirements of high-quality devices in the later stage.
- the present invention provides a method for transferring a compound semiconductor single crystal thin film layer and a method for preparing a single crystal GaAs-OI composite wafer.
- the present invention provides a method for transferring a compound semiconductor single crystal thin film layer, including:
- a lateral external pressure is applied to laterally split the compound semiconductor single crystal film layer and the first substrate at the graphite transition layer, and transfer the compound semiconductor single crystal film layer to the second substrate.
- the first substrate is a single crystal GaAs substrate or a single crystal Ge substrate.
- the compound semiconductor single crystal thin film layer is a GaAs single crystal thin film layer.
- the second substrate is a Si substrate.
- the first dielectric layer or the second dielectric layer is a Si 3 N 4 layer, a SiO 2 layer, an Al 2 O 3 layer or an AlN layer, and the second dielectric layer serves as the second lining The bottom buried oxygen layer.
- both the first dielectric layer and the second dielectric layer are Si 3 N 4 layers.
- the present invention also provides a method for preparing a single crystal GaAs-OI composite wafer based on the above transfer method, including:
- a lateral external pressure is applied to the A wafer to split the composite wafer laterally at the graphite transition layer to remove the single crystal GaAs substrate or single crystal Ge substrate and the graphite transition layer to obtain a single crystal GaAs-OI
- the composite wafer has a Si substrate, Si 3 N 4 dielectric layer, and GaAs single crystal film layer in order.
- the thickness of the graphite transition layer is 50-100 nm
- the thickness of the GaAs single crystal thin film layer is 10-2000 nm
- the thickness of the Si 3 N 4 layer is 100-400 nm.
- An SiO 2 layer is also prepared between the Si substrate and the Si 3 N 4 dielectric layer;
- the thickness of the Si 3 N 4 layer is 100-400 nm.
- the residual graphite transition layer of the GaAs single crystal thin film layer is ground away by chemical etching and mechanical grinding and polishing methods to obtain a high-quality GaAs single crystal thin film surface.
- the method for transferring a compound semiconductor single crystal thin film layer and the method for preparing a GaAs-OI composite wafer provided by the present invention can transfer the epitaxially grown high quality compound semiconductor single crystal thin film layer to the Si-based substrate by means of dielectric layer bonding
- the above can realize the preparation of high-quality, large-area, low-cost compound semiconductor single crystal thin film layers on SOI substrates, thereby promoting the industrial application of semiconductor devices on GaAs-OI.
- FIG. 1 is a flowchart of a method for transferring a compound semiconductor single crystal thin film layer disclosed in an embodiment of the present invention
- FIG. 2 is a structure and preparation flow chart of A wafer disclosed in an embodiment of the present invention.
- FIG. 3 is a structure and preparation flow chart of the first B wafer disclosed in an embodiment of the present invention.
- FIG. 4 is a structure and preparation flow chart of a second type B wafer disclosed in an embodiment of the present invention.
- FIG. 5 is a structure and preparation flow chart of the first single crystal GaAs-OI composite wafer disclosed in an embodiment of the present invention
- FIG. 6 is a structure and preparation flow chart of a second single crystal GaAs-OI composite wafer disclosed in an embodiment of the present invention.
- a wafer 11. Single crystal GaAs substrate; 12. Graphite transition layer; 13. GaAs single crystal thin film layer; 14. Si 3 N 4 dielectric layer;
- the present invention provides a method for transferring a compound semiconductor single crystal thin film layer, which includes:
- a graphite transition layer is prepared on the first substrate; wherein,
- a layer of graphite transition layer is deposited on the first substrate by magnetron sputtering; the first substrate is preferably a single crystal GaAs substrate or a single crystal Ge substrate;
- the compound semiconductor single crystal film layer is epitaxially grown on the graphite transition layer, and the compound semiconductor single crystal film layer has the same lattice structure as the first substrate; wherein,
- the second substrate is a Si substrate, and the second dielectric layer is a Si 3 N 4 layer, an SiO 2 layer, an Al 2 O 3 layer or an AlN layer, preferably a Si 3 N 4 layer;
- the A wafer 10 of the present invention includes: a single crystal GaAs substrate 11, a graphite transition layer 12, a GaAs single crystal thin film layer 13, and a Si 3 N 4 dielectric layer 14; its preparation method is as follows:
- a layer of graphite transition layer 12 is deposited on a single crystal GaAs substrate 11 or a single crystal Ge substrate by magnetron sputtering; the specific preparation method is as follows:
- the Si 3 N 4 dielectric layer is prepared in the range of 300-500° C. by using the PECVD method.
- the B wafer 20 of the present invention includes: a Si substrate 21 and a Si 3 N 4 layer 23; its preparation method is as follows:
- a Si 3 N 4 dielectric layer 23 is prepared on the surface of the Si substrate 12 as a buried oxide layer; the specific preparation method is:
- a SiO 2 layer 22 is prepared on the surface of the Si substrate 12, and a Si 3 N 4 dielectric layer 23 is prepared on the surface of the SiO 2 layer 22; further, the thickness of the Si 3 N 4 layer is 100-400 nm.
- the single crystal GaAs-OI composite wafer 30 of the present invention includes: a Si substrate 31, a Si 3 N 4 dielectric layer 33 and a GaAs single crystal thin film layer 34; the preparation method is:
- the Si 3 N 4 layer and the Si 3 N 4 layer on the top layer of the A wafer 10 and the B wafer 20 shown in FIG. 3 are bonded by means of interatomic force bonding to make the A wafer and the B crystal Circle closely combined
- a lateral external pressure is applied to the A wafer to split the composite wafer horizontally at the graphite transition layer to remove the single crystal GaAs substrate or single crystal Ge substrate and graphite transition layer to obtain a single crystal GaAs-OI composite wafer.
- Its structure is sequentially Si substrate, Si 3 N 4 dielectric layer and GaAs single crystal thin film layer;
- the single crystal GaAs-OI composite wafer 30 of the present invention includes: a Si substrate 31, an SiO 2 layer 32, a Si 3 N 4 dielectric layer 33 and a GaAs single crystal thin film layer 34; the preparation method is:
- a lateral external pressure is applied to the A wafer to split the composite wafer horizontally at the graphite transition layer to remove the single crystal GaAs substrate or single crystal Ge substrate and graphite transition layer to obtain a single crystal GaAs-OI composite wafer.
- Its structure is sequentially Si substrate, Si 3 N 4 dielectric layer and GaAs single crystal thin film layer;
- the residual graphite transition layer of the GaAs single crystal film layer is polished by chemical etching and mechanical grinding and polishing methods to obtain a high-quality GaAs single crystal film layer surface.
- the method for transferring GaAs single crystal film layer and the method for preparing GaAs-OI composite wafer provided by the present invention can transfer the grown high-quality GaAs single crystal film layer to the Si-based substrate by means of dielectric layer bonding. Realize the preparation of high-quality, large-area, and low-cost GaAs single crystal thin film layers on SOI substrates, thereby promoting the industrial application of semiconductor devices on GaAs-OI.
- the epitaxial structure provided by the present invention takes into account the actual requirements of epitaxial growth and device performance, and the thickness of each layer and the manufacturing process can be adjusted within a certain range according to specific materials and device indicators; under the premise that epitaxial growth can be achieved, Realize GaAs single crystal film layer transfer and composite wafer preparation.
- the Si 3 N 4 dielectric layer is used as the buried oxide layer on the Si substrate and the dielectric layer on the single crystal GaAs film at the same time, not only because of the properties of Si 3 N 4 that can replace SiO 2 as the buried oxide layer, but The reason is that the Si 3 N 4 dielectric and single crystal Si can be bonded by means of interatomic force at the heterogeneous surface.
- the Si 3 N 4 dielectric and GaAs single crystal film layer are As-N bonds at the heterogeneous surface. It can be bonded by means of interatomic force, and this combination of Si-Si bond and As-N bond can make the prepared composite wafer withstand high temperatures in the subsequent epitaxy process.
- other existing technical methods have no interatomic bonding force between Si-Si bonds and As-N bonds, and breakage occurs because they cannot withstand high temperatures of thousands of degrees Celsius during the subsequent epitaxial growth process.
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Abstract
本发明公开了一种化合物半导体单晶薄膜层的转移方法及单晶GaAs-OI复合晶圆的制备方法,包括:在第一衬底上制备石墨过渡层;在石墨过渡层上生长化合物半导体单晶薄膜层;在化合物半导体单晶薄膜层上制备第一介质层;在第二衬底上制备第二介质层;通过第一介质层和第二介质层的键合,使第一衬底和第二衬底相结合;施加一个横向的外部压力,使化合物半导体单晶薄膜层与第一衬底在石墨过渡层处横向分裂,将化合物半导体单晶薄膜层转移到第二衬底上。本发明可将外延生长的高质量化合物半导体单晶薄膜层通过介质层键合的方式转移到Si基衬底上,可以实现高质量、大面积、低成本化合物半导体单晶薄膜层在SOI衬底上的制备。
Description
本发明涉及半导体器件集成技术领域,具体涉及一种化合物半导体单晶薄膜层的转移方法及单晶GaAs-OI复合晶圆的制备方法。
自上世纪七十年代开始,微电子产业按摩尔定律发展了近半个世纪。目前,器件的特征尺寸已经接近10nm。基于硅材料的CMOS技术在速度、功耗、集成度和制造成本等多方面受到了材料的基本物理特性、制造成本乃至经济运行规律等多方面的严峻挑战。国际学术界和工业界普遍认为处在“后摩尔时代”的微纳电子工业表现的三大发展趋势为:延续摩尔定律,即半导体器件尺寸继续缩小;扩展摩尔定律,即追求系统集成的功能多样化;超越COMS。这就给Si基材料带来了相当大的挑战,由于MOS晶体管的短沟道带来的二级效应,对传统平面器件而言,通过不断缩小器件的尺寸来提高性能的方法遇到了越来越大的困难,严重制约了集成度的进一步提升。
为了提高MOS晶体管的开态电流,需采用具有高迁移率的沟道材料,如:锗(Ge)和Ⅲ-Ⅴ族半导体,Ⅲ-Ⅴ族化合物半导体材料还具备形成高质量MOS界面的能力,从而使同尺寸的MOS器件性能明显优于硅基MOS器件。尤其是到了7nm技术节点时,对FinFET技术而言,栅极或许丧失对沟道的控制能力,Ⅲ-Ⅴ族材料可能被用于沟道。另一方面,人们希望芯片集成更多的功能,随着微处理器工作速度的不断攀升,集成电路中电互连技术遇到瓶颈,面临的带宽、延时、功耗等问题,为充分利用光通信的优点,需要微处理器多核间的高速光互连的实现。因此SOI作为一种高效集成材料,在很多领域被认为具有独特结构的SOI器件能够有效的抑制体硅器件的不足,充分的发挥硅集成技术的潜力,是保证集成电路产业按照摩尔定律走势进行快速发展一大利器。
传统的基于硅材料为衬底的体硅集成电路由于其存在寄生可控硅闩锁效应、在射线辐照环境下软失效、寄生电容、热载流子效应等方面的局限,使 其应用发展受到了限制。SOI技术具有高性能ULSI、耐高温高压、抗福照、低压低功耗高集成度等领域具有极其广阔的发展前景,被国际上公认为21世纪的硅集成电路技术,近年来,SOI技术已经发展成为制造ULSL集成电路的主流技术之一。SOI材料和GaAs材料的结合集成技术的发展,为实现GaAs半导体光探测器的多功能化打开一扇窗户。将GaAs材料集成到SOI衬底上为大规模的异质集成提供了可能。
现有一般采用在Si衬底上外延生长单晶GaAs的方式,这种方式的弊端是Si衬底的晶格结构和单晶GaAs的晶格结构不同,在外延生长过程中会由于位错等原因导致晶格失配,使得外延生长GaAs晶体质量不高,无法满足后期制造高质量器件的要求。
发明内容
针对上述问题中存在的不足之处,本发明提供一种化合物半导体单晶薄膜层的转移方法及单晶GaAs-OI复合晶圆的制备方法。
本发明提供一种化合物半导体单晶薄膜层的转移方法,包括:
在第一衬底上制备石墨过渡层;
在所述石墨过渡层上生长化合物半导体单晶薄膜层,所述化合物半导体单晶薄膜层与第一衬底具有相同晶格结构;
在所述化合物半导体单晶薄膜层上制备第一介质层;
在第二衬底上制备第二介质层;
通过所述第一介质层和第二介质层的键合,使所述第一衬底和第二衬底相结合;
施加一个横向的外部压力,使所述化合物半导体单晶薄膜层与第一衬底在所述石墨过渡层处横向分裂,将所述化合物半导体单晶薄膜层转移到所述第二衬底上。
作为本发明的进一步改进,所述第一衬底为单晶GaAs衬底或单晶Ge衬底。
作为本发明的进一步改进,所述化合物半导体单晶薄膜层为GaAs单晶薄膜层。
作为本发明的进一步改进,所述第二衬底为Si衬底。
作为本发明的进一步改进,所述第一介质层或第二介质层为Si
3N
4层、SiO
2层、Al
2O
3层或AlN层,所述第二介质层作为所述第二衬底的埋氧层。
作为本发明的进一步改进,所述第一介质层和第二介质层均选用Si
3N
4层。
本发明还提供一种基于上述转移方法的单晶GaAs-OI复合晶圆的制备方法,包括:
制备A晶圆:
在单晶GaAs衬底或单晶Ge衬底上制备石墨过渡层;
在所述石墨过渡层上外延生长GaAs单晶薄膜层;
在所述GaAs单晶薄膜层上制备Si
3N
4介质层;
制备B晶圆:
在Si衬底表面制备Si
3N
4介质层作为埋氧层;
制备单晶GaAs-OI复合晶圆;
将A晶圆、B晶圆上顶层的Si
3N
4层与Si
3N
4层之间进行键合,使A晶圆、B晶圆紧密结合;
在A晶圆上施加一个横向的外部压力,使复合晶圆在石墨过渡层处横向分裂去除所述单晶GaAs衬底或单晶Ge衬底、所述石墨过渡层,得到单晶GaAs-OI复合晶圆,其结构依次为Si衬底、Si
3N
4介质层和GaAs单晶薄膜层。
作为本发明的进一步改进,在所述A晶圆中:
所述石墨过渡层的厚度为50-100nm,所述GaAs单晶薄膜层的厚度为10-2000nm,所述Si
3N
4层的厚度为100-400nm。
作为本发明的进一步改进,在所述B晶圆中:
所述Si衬底与所述Si
3N
4介质层之间还制备有SiO
2层;
所述Si
3N
4层的厚度为100-400nm。
作为本发明的进一步改进,在外部压力横向分离去除所述单晶GaAs衬底或单晶Ge衬底、所述石墨过渡层后,
通过化学腐蚀和机械磨抛法将所述GaAs单晶薄膜层残留的石墨过渡层研磨掉,得到高质量的GaAs单晶薄膜层表面。
与现有技术相比,本发明的有益效果为:
本发明提供的化合物半导体单晶薄膜层的转移方法以及GaAs-OI复合晶圆的制备方法,可将外延生长的高质量化合物半导体单晶薄膜层通过介质层 键合的方式转移到Si基衬底上,可以实现高质量、大面积、低成本化合物半导体单晶薄膜层在SOI衬底上的制备,从而促进GaAs-OI上半导体器件的工业应用。
图1为本发明一种实施例公开的化合物半导体单晶薄膜层的转移方法的流程图;
图2为本发明一种实施例公开的A晶圆的结构及制备流程图;
图3为本发明一种实施例公开的第一种B晶圆的结构及制备流程图;
图4为本发明一种实施例公开的第二种B晶圆的结构及制备流程图;
图5为本发明一种实施例公开的第一种单晶GaAs-OI复合晶圆的结构及制备流程图;
图6为本发明一种实施例公开的第二种单晶GaAs-OI复合晶圆的结构及制备流程图。
图中:
10、A晶圆;11、单晶GaAs衬底;12、石墨过渡层;13、GaAs单晶薄膜层;14、Si
3N
4介质层;
20、B晶圆;21、Si衬底;22、SiO
2层;23、Si
3N
4层;
30、单晶GaAs-OI复合晶圆;31、Si衬底;32、SiO
2层;33、Si
3N
4层;34、GaAs单晶薄膜层。
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
在本发明的描述中,需要说明的是,术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指 的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”、“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性。
在本发明的描述中,还需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本发明中的具体含义。
下面结合附图对本发明做进一步的详细描述:
如图1所示,本发明提供一种化合物半导体单晶薄膜层的转移方法,包括:
S1、在第一衬底上制备石墨过渡层;其中,
在第一衬底上采用磁控溅射的方法沉积一层石墨过渡层;第一衬底优选为单晶GaAs衬底或单晶Ge衬底;
S2、在石墨过渡层上外延生长化合物半导体单晶薄膜层,化合物半导体单晶薄膜层与第一衬底具有相同晶格结构;其中,
当第一衬底为单晶GaAs衬底或单晶Ge衬底时,化合物半导体单晶薄膜层为GaAs单晶薄膜层;同时,还可根据实际需要选择其他的化合物半导体单晶薄膜层及对应的衬底。
S3、在化合物半导体单晶薄膜层上制备第一介质层;其中,
第一介质层为Si
3N
4层、SiO
2层、Al
2O
3层或AlN层,优选为Si
3N
4层;
S4、在第二衬底上制备第二介质层;其中,
第二衬底为Si衬底,第二介质层为Si
3N
4层、SiO
2层、Al
2O
3层或AlN层,优选为Si
3N
4层;
S5、通过第一介质层和第二介质层的键合,使第一衬底和第二衬底相结合;
S6、施加一个横向的外部压力,使化合物半导体单晶薄膜层与第一衬底在石墨过渡层处横向分裂,将化合物半导体单晶薄膜层转移到第二衬底上。
本发明提供一种基于上述转移方法的单晶GaAs-OI复合晶圆的制备方法, 包括:制备带有GaAs单晶薄膜层的A晶圆10,制备以Si
3N
4层作为埋氧层SOI衬底的B晶圆20和制备单晶GaAs-OI复合晶圆,即C晶圆;其中:
如图2所示,本发明的A晶圆10包括:单晶GaAs衬底11、石墨过渡层12、GaAs单晶薄膜层13和Si
3N
4介质层14;其制备方法为:
在单晶GaAs衬底11或单晶Ge衬底上采用磁控溅射的方法沉积一层石墨过渡层12;具体的制备方法为:
采用磁控溅射法在单晶GaAs衬底或Ge衬底上进行石墨过渡层的制备。首先将石墨片进行切割、打磨、抛光等工艺,然后用氮气将石墨片表面的粉末吹扫干净,然后将其放入1000℃左右的真空环境下高温烘烤60min,这样能够使石墨片中所包含各种杂质挥发,进一步去除去除石墨片表面和内部的杂质。经过上述处理后,石墨的纯度可以达到99.99%,采用上述高纯度石墨靶材以1.2nm/min的速率直流溅射一层厚度为50-100nm的石墨过渡层12。
在石墨过渡层12上外延生长GaAs单晶薄膜层13;进一步,GaAs单晶薄膜层的厚度为10-2000nm;优选为100-500nm;
在GaAs单晶薄膜层13上制备Si
3N
4介质层14;具体的制备方法为:
采用N
2、SiH
4、NH
3、HCl
4、H
2Cl
2中的几种气体作为反应气体,采用PECVD法在300-500℃范围内制备出Si
3N
4介质层。
如图3所示,本发明的B晶圆20包括:Si衬底21和Si
3N
4层23;其制备方法为:
在Si衬底12表面制备Si
3N
4介质层23作为埋氧层;具体的制备方法为:
采用N
2、SiH
4、NH
3、HCl
4、H
2Cl
2中的几种气体作为反应气体,采用PECVD法在300-500℃范围内制备出Si
3N
4介质层。
如图4所示,本发明的B晶圆20包括:Si衬底21、SiO
2层22和Si
3N
4层23;其制备方法为:
在Si衬底12表面制备SiO
2层22,在SiO
2层22表面制备Si
3N
4介质层23;进一步,Si
3N
4层的厚度为100-400nm。
如图5所示,本发明的单晶GaAs-OI复合晶圆30包括:Si衬底31、Si
3N
4介质层33和GaAs单晶薄膜层34;其制备方法为:
将A晶圆10、图3所示的B晶圆20上顶层的Si
3N
4层与Si
3N
4层之间通过原子间力键合的方式进行键合,使A晶圆、B晶圆紧密结合;
在A晶圆上施加一个横向的外部压力,使复合晶圆在石墨过渡层处横向分裂去除单晶GaAs衬底或单晶Ge衬底、石墨过渡层,得到单晶GaAs-OI复合晶圆,其结构依次为Si衬底、Si
3N
4介质层和GaAs单晶薄膜层;
通过化学腐蚀和机械磨抛法将GaAs单晶薄膜层残留的石墨过渡层研磨掉,得到高质量的GaAs单晶薄膜层表面。
如图6所示,本发明的单晶GaAs-OI复合晶圆30包括:Si衬底31、SiO
2层32、Si
3N
4介质层33和GaAs单晶薄膜层34;其制备方法为:
将A晶圆10、图4所示的B晶圆20上顶层的Si
3N
4层与Si
3N
4层之间通过原子间力键合的方式进行键合,使A晶圆、B晶圆紧密结合;
在A晶圆上施加一个横向的外部压力,使复合晶圆在石墨过渡层处横向分裂去除单晶GaAs衬底或单晶Ge衬底、石墨过渡层,得到单晶GaAs-OI复合晶圆,其结构依次为Si衬底、Si
3N
4介质层和GaAs单晶薄膜层;
通过化学腐蚀和机械磨抛法将GaAs单晶薄膜层残留的石墨过渡层研磨掉,得到高质量的GaAs单晶薄膜层表面。
本发明的优点为:
本发明提供的GaAs单晶薄膜层的转移方法以及GaAs-OI复合晶圆的制备方法,可将生长的高质量GaAs单晶薄膜层通过介质层键合的方式转移到Si基衬底上,可以实现高质量、大面积、低成本GaAs单晶薄膜层在SOI衬底上的制备,从而促进GaAs-OI上半导体器件的工业应用。本发明提供的外延结构考虑到外延生长和器件性能两方面的实际要求,各层厚度、制造工艺可在一定范围内,根据具体材料和器件指标进行调整;在满足外延生长可实现的前提下,实现GaAs单晶薄膜层转移及复合晶圆制备。
本发明的单晶GaAs薄膜外延生长在单晶GaAs衬底或单晶Ge衬底上,单晶Ge与单晶GaAs有着相同的晶格结构,石墨为六方形碳环相互连接并叠加形成的多层网状叠合体,分子层间以范德华力相互连接,在外延过程中石墨单分子层间可以发生滑移运动,薄膜内部受到的压应力得到了释放,因此可以消除晶格失配。
本发明中采用Si
3N
4介质层同时作为Si衬底上的埋氧层和单晶GaAs薄膜上的介质层,不仅是由于为了Si
3N
4的性质可以替代SiO
2作为埋氧层,而是因为Si
3N
4介质与单晶Si在异质面处Si-Si键可以以原子间力的方式键合,Si
3N
4 介质与GaAs单晶薄膜层在异质面处As-N键可以以原子间力的方式键合,这种Si-Si键和As-N键的结合方式可以使得所制备的复合晶圆在后续外延工艺过程中的承受高温。而现有的其他的技术手段由于没有Si-Si键和As-N键的原子间键合力,在后续的外延生长过程中由于难以承受上千摄氏度的高温而发生断裂。
以上仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
- 一种化合物半导体单晶薄膜层的转移方法,其特征在于,包括:在第一衬底上制备石墨过渡层;在所述石墨过渡层上生长化合物半导体单晶薄膜层,所述化合物半导体单晶薄膜层与第一衬底具有相同晶格结构;在所述化合物半导体单晶薄膜层上制备第一介质层;在第二衬底上制备第二介质层;通过所述第一介质层和第二介质层的键合,使所述第一衬底和第二衬底相结合;施加一个横向的外部压力,使所述化合物半导体单晶薄膜层与第一衬底在所述石墨过渡层处横向分裂,将所述化合物半导体单晶薄膜层转移到所述第二衬底上。
- 如权利要求1所述的转移方法,其特征在于,所述第一衬底为单晶GaAs衬底或单晶Ge衬底。
- 如权利要求2所述的转移方法,其特征在于,所述化合物半导体单晶薄膜层为GaAs单晶薄膜层。
- 如权利要求1所述的转移方法,其特征在于,所述第二衬底为Si衬底。
- 如权利要求1所述的转移方法,其特征在于,所述第一介质层或第二介质层为Si 3N 4层、SiO 2层、Al 2O 3层或AlN层,所述第二介质层作为所述第二衬底的埋氧层。
- 如权利要求5所述的转移方法,其特征在于,所述第一介质层和第二介质层均选用Si 3N 4层。
- 一种基于如权利要求1-6中任一项所述的转移方法的单晶GaAs-OI复合晶圆的制备方法,其特征在于,包括:制备A晶圆:在单晶GaAs衬底或单晶Ge衬底上制备石墨过渡层;在所述石墨过渡层上外延生长GaAs单晶薄膜层;在所述GaAs单晶薄膜层上制备Si 3N 4介质层;制备B晶圆:在Si衬底表面制备Si 3N 4介质层作为埋氧层;制备单晶GaAs-OI复合晶圆;将A晶圆、B晶圆上顶层的Si 3N 4层与Si 3N 4层之间进行键合,使A晶圆、B晶圆紧密结合;在A晶圆上施加一个横向的外部压力,使复合晶圆在石墨过渡层处横向分裂去除所述单晶GaAs衬底或单晶Ge衬底、所述石墨过渡层,得到单晶GaAs-OI复合晶圆,其结构依次为Si衬底、Si 3N 4介质层和GaAs单晶薄膜层。
- 如权利要求7所述的制备方法,其特征在于,在所述A晶圆中:所述石墨过渡层的厚度为50-100nm,所述GaAs单晶薄膜层的厚度为10-2000nm,所述Si 3N 4层的厚度为100-400nm。
- 如权利要求7所述的制备方法,其特征在于,在所述B晶圆中:所述Si衬底与所述Si 3N 4介质层之间还制备有SiO 2层;所述Si 3N 4层的厚度为100-400nm。
- 如权利要求7所述的制备方法,其特征在于,在外部压力横向分离去除所述单晶GaAs衬底或单晶Ge衬底、所述石墨过渡层后,通过化学腐蚀和机械磨抛法将所述GaAs单晶薄膜层残留的石墨过渡层研磨掉,得到高质量的GaAs单晶薄膜层表面。
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US20210035852A1 (en) | 2021-02-04 |
US11574839B2 (en) | 2023-02-07 |
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