WO2015103976A1 - 半导体衬底、半导体器件及半导体衬底制造方法 - Google Patents

半导体衬底、半导体器件及半导体衬底制造方法 Download PDF

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WO2015103976A1
WO2015103976A1 PCT/CN2015/070251 CN2015070251W WO2015103976A1 WO 2015103976 A1 WO2015103976 A1 WO 2015103976A1 CN 2015070251 W CN2015070251 W CN 2015070251W WO 2015103976 A1 WO2015103976 A1 WO 2015103976A1
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semiconductor layer
semiconductor
layer
substrate
semiconductor substrate
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PCT/CN2015/070251
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to KR1020167021367A priority Critical patent/KR20160104723A/ko
Priority to SG11201605542RA priority patent/SG11201605542RA/en
Priority to DK15735020.8T priority patent/DK3093891T3/da
Priority to EP15735020.8A priority patent/EP3093891B1/en
Priority to JP2016544829A priority patent/JP2017507478A/ja
Publication of WO2015103976A1 publication Critical patent/WO2015103976A1/zh
Priority to US15/201,533 priority patent/US10249788B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region

Definitions

  • the present invention relates to the field of microelectronics, and in particular to a semiconductor substrate, a semiconductor device, and a method of fabricating a semiconductor substrate.
  • Group III nitrides which are represented by gallium nitride, are receiving more and more attention because III-nitrides can be widely used as light-emitting diodes (LEDs) and high-power electronic devices for semiconductor illumination. Due to the lack of intrinsic substrates, gallium nitride devices are commonly fabricated on heterogeneous substrates such as sapphire, silicon carbide, and silicon. Due to its wide applicability, silicon substrates are the best in size and quality among the above several substrate materials. At present, the mainstream technology of complementary metal oxide semiconductor (CMOS) is based on a 12-inch silicon substrate, and the price of silicon is unmatched by several other materials. Therefore, the preparation of gallium nitride material on a large-sized silicon substrate is the best way to reduce the cost of the gallium nitride-based device.
  • CMOS complementary metal oxide semiconductor
  • the present invention proposes a concept of a composite substrate structure.
  • the gallium nitride epitaxial wafer is preferably prepared on a Si (111) substrate, so that the prepared epitaxial film has better crystal quality, electrical properties and optical properties.
  • the lattice structure of gallium nitride has a hexagonal symmetry and follows the same relationship when stress is released.
  • the dissociation surface of Si(111) is also characterized by triangular symmetry, and the silicon substrate is triangular symmetrical when it is damaged by stress.
  • the gallium nitride crystal prepared on Si(111) Due to the symmetrical matching relationship, the gallium nitride crystal prepared on Si(111) has the best quality, but correspondingly, it is also the most easily broken when subjected to stress.
  • the present invention proposes to fabricate a gallium nitride epitaxial layer using a silicon asymmetric composite substrate.
  • the stress in the silicon semiconductor is continuously accumulated as the thickness of the silicon in the same crystal orientation increases, and when the surface of the silicon of the same crystal orientation comes into contact with the silicon of the other crystal orientation, the stress is reduced without accumulating.
  • the invention introduces two or more layers of Si(111) in different crystal orientations, so that the dissociation surfaces of the Si(111) semiconductor layers which are in contact with each other do not overlap, thereby reducing the damage of the stress through the silicon substrate and preventing the silicon substrate from being damaged.
  • the cracking of the gallium nitride semiconductor layer caused by the cracking achieves the purpose of improving the robustness and reliability of the gallium nitride semiconductor layer.
  • the above composite substrate can also be formed by combining two different crystal orientation silicon semiconductor layers, such as a Si (111) semiconductor layer and a Si (100) semiconductor layer to form a composite substrate structure.
  • a Si (111) semiconductor layer By controlling the angle at which the silicon wafer is bonded, the dissociation surfaces of the Si (111) semiconductor layer and the Si (100) semiconductor layer are not overlapped, so that defects generated by the gallium nitride epitaxial layer are transferred to one of the silicon semiconductor layers. It will be greatly reduced, thereby avoiding the continuation of another silicon semiconductor layer, reducing the probability of substrate fracture caused by the stress of the gallium nitride epitaxial layer, and enhancing the robustness and reliability of the substrate.
  • the fabrication of the above composite substrate can be accomplished by wafer bonding.
  • two thinner substrates can be bonded at different angles in different crystal orientations to form a composite substrate.
  • a semiconductor substrate including a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are in a vertical direction Having a different dissociation surface, the semiconductor layer obtained by rotating the first semiconductor layer after the lattice symmetry of the first semiconductor layer has a different dissociation surface in the vertical direction from the second semiconductor layer.
  • the semiconductor layer obtained by rotating the first semiconductor layer and the second semiconductor layer in accordance with the lattice symmetry of the second semiconductor layer has a different dissociation surface in the vertical direction, or the first half a semiconductor layer obtained by rotating a conductor layer in a lattice symmetry of the first semiconductor layer and a lattice layer obtained by rotating the second semiconductor layer in a lattice symmetry of the second semiconductor layer has a vertical direction Different dissociation surfaces.
  • the materials of the first semiconductor layer and the second semiconductor layer are the same or different.
  • the first semiconductor layer and the second semiconductor layer have the same lattice structure, and the first semiconductor layer and the second semiconductor layer have the same crystal orientation in a vertical direction, The crystal directions in the horizontal direction do not coincide.
  • the crystal structures of the first semiconductor layer and the second semiconductor layer are different, and the crystal directions of the first semiconductor layer and the second semiconductor layer in the horizontal direction do not coincide.
  • the material form of the first semiconductor layer includes a combination of one or more of a crystalline state, an amorphous state, and an amorphous state.
  • the material of the first semiconductor layer is an amorphous material
  • the amorphous material includes a non-semiconductor material including aluminum nitride, polycrystalline silicon carbide, ceramic, and quartz. .
  • the first semiconductor layer is an amorphous material, and the bonding direction of the first semiconductor layer and the second semiconductor layer is not limited.
  • the second semiconductor layer is a crystal layer.
  • the first semiconductor layer and the second semiconductor layer are alternately formed in a stacked structure of three or more layers in this order.
  • the laminated structure includes a dielectric layer between the first semiconductor layer and the second semiconductor layer.
  • the dielectric layer has the same crystal orientation in the vertical direction and the crystal orientation in the horizontal direction does not coincide with the adjacent first semiconductor layer;
  • the dielectric layer and the adjacent second semiconductor layer have the same crystal orientation in the vertical direction and do not coincide in the crystal orientation in the horizontal direction.
  • the dielectric layer and the crystal of the adjacent first semiconductor layer The structure is different, and the crystal orientation does not coincide in the horizontal direction;
  • the dielectric layer is different from the crystal structure of the adjacent second semiconductor layer, and the crystal orientation does not coincide in the horizontal direction.
  • a semiconductor device includes a semiconductor substrate and a semiconductor epitaxial layer on the semiconductor substrate, the semiconductor substrate being the semiconductor substrate of any of the above embodiments.
  • the semiconductor epitaxial layer comprises a combination of one or more of silicon, gallium arsenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum gallium indium nitride.
  • the semiconductor device includes a light emitting diode, a laser diode, a high electron mobility transistor, a field effect transistor, a Schottky diode, a PIN diode, and a solar cell.
  • a method of manufacturing a semiconductor substrate comprising:
  • the semiconductor layer obtained by the lattice symmetry rotation of the first semiconductor layer has a different dissociation surface in the vertical direction from the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are as described above.
  • the semiconductor layer obtained after the lattice symmetry rotation of the second semiconductor layer has a different dissociation surface in the vertical direction, or the semiconductor obtained by rotating the first semiconductor layer in accordance with the lattice symmetry of the first semiconductor layer
  • the semiconductor layer obtained after the layer and the second semiconductor layer are rotated by the lattice symmetry of the second semiconductor layer has different dissociation faces in the vertical direction.
  • the method further includes:
  • a semiconductor epitaxial layer is formed on the second semiconductor layer.
  • the method of preparing the first semiconductor layer and the second semiconductor layer includes a combination of one or more of a Czochralski method, a zone melting method, a physical vapor deposition, and a chemical vapor deposition.
  • the first semiconductor layer is prepared in the step S2.
  • the method of the two semiconductor layers includes wafer bonding.
  • the method of preparing the semiconductor epitaxial layer includes a combination of one or more of metal organic chemical vapor deposition, molecular beam epitaxy, and hydride vapor phase epitaxy.
  • the method further includes:
  • the first semiconductor layer and the second semiconductor layer are alternately prepared on the second semiconductor layer in order to form a stacked structure of three or more layers.
  • the method further comprises:
  • a dielectric layer is grown between the first semiconductor layer and the second semiconductor layer.
  • the dielectric layer is formed by a method of deposition, thermal oxidation or nitridation, the method of deposition including one or a combination of CVD, PECVD, LPCVD, RTCVD, MOCVD, MBE, ALD .
  • the semiconductor substrate, the semiconductor device and the semiconductor substrate manufacturing method provided by the invention enable the semiconductor substrate to have a special lattice structure and a mechanical structure, and the semiconductor substrate is a composite substrate structure, and under the same substrate thickness condition,
  • the damage caused by the stress applied by the epitaxial layer of the semiconductor on the silicon substrate can be reduced, thereby reducing the probability of breakage of the silicon substrate; at the same time, the process difficulty can be reduced and the reliability of the semiconductor device can be enhanced.
  • FIG. 1 is a schematic view showing respective crystal orientations of silicon involved in the present invention
  • FIG. 2 is a structural view of a semiconductor substrate in which the ⁇ -211> direction of the upper layer Si (111) and the ⁇ 1-10> direction of the lower layer Si (111) are parallel in the first embodiment of the present invention;
  • FIG. 3 is a ⁇ -211> direction of the upper layer Si (111) and a lower layer Si (111) in the second embodiment of the present invention. a semiconductor substrate structure diagram parallel to the ⁇ -101> direction;
  • FIG. 4(a) is a structural view of a semiconductor substrate having an off angle of a ⁇ -211> direction of an upper Si (111) and a ⁇ -211> direction of an underlying Si (111) in a third embodiment of the present invention
  • FIG. 4 (b) and FIG. 4(c) are plan views of the upper layer Si (111) and the lower layer Si (111), respectively;
  • FIG. 5(a) is a structural view of a semiconductor substrate having an off angle of the ⁇ -211> direction of the upper layer Si (111) and the ⁇ -110> direction of the lower layer Si (100) in the fourth embodiment of the present invention
  • FIG. 5 (b) and FIG. 5(c) are plan views of the upper layer Si (111) and the lower layer Si (100), respectively;
  • FIG. 6 is a structural diagram of a semiconductor substrate having an alternate composite substrate structure of Si (111) layer and Si (100) layer in a fifth embodiment of the present invention
  • FIG. 7 is a structural diagram of a semiconductor substrate having an alternate composite substrate structure of Si (110) layer and Si (100) layer in a sixth embodiment of the present invention.
  • Figure 8 is a structural view of a semiconductor substrate having an alternate composite substrate structure of Si (111) layer and Si (110) layer in a seventh embodiment of the present invention.
  • FIG. 1 is a schematic view showing the respective crystal orientations of silicon involved in the present invention, and the present invention will be further described below with reference to FIG. 1 for different embodiments.
  • the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, and a second semiconductor layer 12 may be used to prepare the semiconductor epitaxial layer 2.
  • the first semiconductor layer 11 and the second semiconductor layer 12 have different dissociation faces in the vertical direction.
  • the first semiconductor layer 11 may be one of a semiconductor material, an amorphous material, and a crystal.
  • the semiconductor material selected by the first semiconductor layer 11 includes one or more of Si, GaN, AlN, SiC, GaAs, InP, and diamond, and the amorphous material includes aluminum nitride, ceramic, quartz, and the like.
  • the bonding direction of the first semiconductor layer 11 and the second semiconductor layer 12 is not limited.
  • the first semiconductor layer 12 may be a crystal layer, and the semiconductor material selected for the first semiconductor layer 12 includes one or more of Si, GaN, AlN, SiC, GaAs, InP, diamond, the first semiconductor layer 11 and the second semiconductor.
  • the materials of layer 12 may be the same or different, but with different crystal orientations. If the first semiconductor layer and the second semiconductor layer have the same lattice structure, the first semiconductor layer and the second semiconductor layer have the same crystal orientation in the vertical direction, the crystal orientations in the horizontal direction do not coincide; or the first semiconductor The crystal structure of the layer and the second semiconductor layer are different, and the crystal directions of the first semiconductor layer and the second semiconductor layer in the horizontal direction do not coincide.
  • the first semiconductor layer 11 and the second semiconductor layer 12 may have the same lattice structure Si (111), have the same crystal orientation in the vertical direction, but have different crystal symmetry in the horizontal direction.
  • the semiconductor epitaxial layer 2 may include a combination of one or more of silicon, gallium arsenide, gallium nitride, aluminum gallium nitride, indium gallium nitride, and aluminum gallium indium nitride.
  • LEDs light-emitting diodes
  • HEMTs high electron mobility transistors
  • FETs field effect transistors
  • Schottky diodes Schottky diodes
  • PIN diodes etc.
  • a method of manufacturing the above semiconductor substrate 1 including the following steps:
  • step S2 the method further comprises: preparing a semiconductor epitaxial layer 2 on the second semiconductor layer 12.
  • the method may further include:
  • a first semiconductor layer 13 may also be formed on the second semiconductor layer 12 to form a stacked structure of a three-layer structure. It should be noted that, in the embodiment of the present invention, the first semiconductor layer 13 and the first semiconductor layer 11 have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystals in the horizontal direction. The directions can be coincident or not coincident.
  • the method may further include:
  • the first semiconductor layer 13 and the second semiconductor layer may be alternately formed on the second semiconductor layer 12 in order to form a stacked structure of three or more layers.
  • both the first semiconductor layer 11 and the second semiconductor layer 12 include a Si (111) semiconductor layer, wherein the second semiconductor layer 12 is the ⁇ -211> direction of the upper Si (111) semiconductor layer and the first semiconductor layer 11 is that the ⁇ 1-10> directions of the underlying Si (111) semiconductor layers are parallel to each other.
  • an angle may be set between the ⁇ -211> direction of the second semiconductor layer 12 and the ⁇ 1-10> direction of the first semiconductor layer 11, such as an angle of 10°, 20°, or 30.
  • the first semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a composite structure such that the dissociation faces of the upper Si (111) semiconductor layer and the underlying Si (111) semiconductor layer are shifted from each other, and a single silicon semiconductor layer
  • this method can reduce the accumulation of stress at the interface between the upper Si (111) semiconductor layer and the lower Si (111) semiconductor layer, and can avoid the local stress accumulation of the silicon semiconductor layer to the entire silicon semiconductor layer, resulting in the entire silicon.
  • the substrate is cracked.
  • the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, and a second semiconductor layer 12 may be used to prepare the semiconductor epitaxial layer 2.
  • the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
  • the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and the ⁇ -211> direction of the upper Si (111) semiconductor layer and the lower Si (111) layer
  • the ⁇ -101> directions are parallel to each other.
  • the first semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a composite structure. This can ensure that the upper Si (111) semiconductor layer and the lower Si (111) semiconductor layer have different dissociation surfaces in the same direction, thereby avoiding the crack of the silicon substrate caused by the accumulation of stress, and the silicon substrate can be greatly improved. Reliability.
  • FIGS. 4(b) and 4(c) are schematic diagrams showing the structure of a semiconductor substrate in a third embodiment of the present invention, that is, the ⁇ -211> direction of the upper Si (111) and the lower Si (111).
  • 4(a) is a schematic cross-sectional view of the structure
  • FIGS. 4(b) and 4(c) are plan views of the upper layer Si (111) and the lower layer Si (111), respectively.
  • the semiconductor substrate 1 includes: a first semiconductor layer 11; a second semiconductor layer 12 on the first semiconductor layer 11, and a second semiconductor layer 12 may be used to prepare the semiconductor epitaxial layer 2.
  • the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
  • the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and the ⁇ -211> direction of the upper Si (111) semiconductor layer and the lower Si (111) layer
  • the first semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a composite structure. This can ensure that the upper Si (111) semiconductor layer and the lower Si (111) semiconductor layer have different dissociation surfaces in the same direction, thereby avoiding the crack of the silicon substrate caused by the accumulation of stress, and the silicon substrate can be greatly improved. Reliability.
  • 5(a), 5(b) and 5(c) are schematic views showing the structure of a semiconductor substrate in a fourth embodiment of the present invention, that is, the ⁇ -211> direction of the upper Si (111) and the lower Si (100).
  • 5(a) is a schematic cross-sectional view of the structure
  • FIGS. 5(b) and 5(c) are plan views of the upper layer Si (111) and the lower layer Si (100), respectively.
  • the semiconductor substrate 1 includes a first semiconductor layer 11 and a second semiconductor layer 12 on the first semiconductor layer 11, which may be used to prepare the semiconductor epitaxial layer 2.
  • the crystal structures of the first semiconductor layer 11 and the second semiconductor layer 12 are different, and the crystal directions of the first semiconductor layer 11 and the second semiconductor layer 12 in the horizontal direction do not overlap.
  • the first semiconductor layer 11 includes a lower Si (100) semiconductor layer
  • the second semiconductor layer 12 includes an upper Si (111) semiconductor layer, and the ⁇ -211> direction of the upper Si (111) semiconductor layer and the lower Si (100) layer There is a declination in the ⁇ -110> direction, and the magnitude of the declination is not equal to an integer multiple of 90° or 90°.
  • the first semiconductor layer and the second semiconductor layer may be alternately laminated to form a composite structure. This can ensure that the upper Si (111) semiconductor layer and the lower Si (100) semiconductor layer have different dissociation surfaces in the same direction, thereby avoiding the crack of the silicon substrate caused by the accumulation of stress, and the silicon substrate can be greatly improved. Reliability.
  • the semiconductor substrate 1 may be formed by laminating three or more semiconductor layers, and the semiconductor epitaxial layer 2 is formed on the semiconductor substrate 1.
  • the semiconductor layer includes the first semiconductor layer 11 and the second semiconductor layer 12. It should be noted that when the semiconductor substrate includes two or more first semiconductor layers, the plurality of first semiconductor layers each have the same lattice structure, and the plurality of first semiconductor layers have the same in the vertical direction. In the crystal orientation, the crystal orientations in the horizontal direction may or may not coincide.
  • the semiconductor substrate includes two or more second semiconductor layers
  • the plurality of second semiconductor layers each have the same lattice structure, and the plurality of second semiconductor layers are in a vertical direction
  • the crystal grains have the same crystal orientation upward, and the crystal orientations in the horizontal direction may or may not coincide.
  • Fig. 6 is a schematic structural view of a semiconductor substrate in a fifth embodiment of the present invention.
  • the composite substrate shown in FIG. 6 includes three semiconductor layers, which are the first semiconductor layer 11, the second semiconductor layer 12, and the first semiconductor layer 13, respectively, from the bottom to the top.
  • the first semiconductor layer 11 and the second semiconductor layer have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystal orientations in the horizontal direction may or may not coincide.
  • the first semiconductor layer and the second semiconductor layer alternately form a stacked structure composed of three semiconductor layers in this order.
  • the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
  • the second semiconductor layer 12 includes an upper Si (100) semiconductor layer.
  • the semiconductor substrate formed by alternately laminating the first semiconductor layer 11 and the second semiconductor layer 12 in this order is not limited to the three-layer structure shown in FIG. 6.
  • the first The semiconductor layer 11 and the second semiconductor layer 12 may be alternately laminated to form a laminated structure of three or more layers.
  • Si may be formed by alternately laminating the first semiconductor layer 11 and the second semiconductor layer 12 in this order.
  • the stacked structure in which the first semiconductor layer 11 and the second semiconductor layer 12 are alternately formed in three or more layers may further include a dielectric layer between the first semiconductor layer 11 and the second semiconductor layer 12 (FIG. 6).
  • the dielectric layer material includes SiO 2 , SiN, AlN, or the like.
  • the dielectric layer has the same crystal orientation in the vertical direction as the first semiconductor layer 11 adjacent thereto, and does not coincide in the horizontal direction in the horizontal direction; and/or the second layer adjacent to the dielectric layer
  • the semiconductor layers 12 have the same crystal orientation in the vertical direction and do not overlap in the crystal direction in the horizontal direction.
  • the material of the dielectric layer may also be amorphous, as a buffer layer of the substrate material, reducing the accumulation of stress; on the other hand, the material of the dielectric layer has a higher dielectric constant (such as the dielectric constant of SiO 2 ) 3.9, SiN has a dielectric constant of 7.0, AlN has a dielectric constant of 8.5) and a critical breakdown electric field. Under the premise of ensuring sufficient breakdown voltage of the substrate, it can have a sufficient thickness of dielectric material to ensure the quality of the dielectric material. Increase the robustness and reliability of the substrate material.
  • Fig. 7 is a schematic view showing the structure of a semiconductor substrate in a sixth embodiment of the present invention, which is a composite substrate formed by alternately laminating Si (110) layers and Si (100) layers.
  • the semiconductor substrate 1 may be formed by alternately laminating three or more semiconductor layers, and the semiconductor epitaxial layer 2 is formed on the semiconductor substrate 1.
  • the semiconductor layer includes the first semiconductor layer 11 and the second semiconductor layer 12.
  • the composite substrate shown in FIG. 7 includes three semiconductor layers, which are the first semiconductor layer 11, the second semiconductor layer 12, and the first semiconductor layer 13, respectively, from the bottom to the top.
  • the first semiconductor layer 11 and the second semiconductor layer have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystal orientations in the horizontal direction may or may not coincide.
  • the first semiconductor layer 11 comprises a lower Si (110) semiconductor layer
  • the second semiconductor layer 12 comprises an upper Si (100) semiconductor layer.
  • a composite substrate structure of Si (110), Si (100), Si (110), and Si (100) can be formed when the first semiconductor layer 11 and the second semiconductor layer 12 are alternately stacked in this order.
  • the composite substrate structure may include a laminated structure of three or more layers. This method also ensures that the dissociation surfaces of the respective silicon semiconductor layers are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress, and the reliability of the silicon substrate can be greatly improved.
  • the laminated structure further includes a dielectric layer (not shown in FIG. 7) between the first semiconductor layer 11 and the second semiconductor layer 12, and the dielectric layer material includes SiO 2 , SiN, AlN, or the like.
  • the dielectric layer has the same crystal orientation in the vertical direction as the adjacent first semiconductor layer 11 and/or the second semiconductor layer 12, and does not overlap in the horizontal direction in the horizontal direction; or the dielectric layer and the adjacent first semiconductor layer 11 And/or the crystal structure of the second semiconductor layer 12 is different, and the crystal orientation does not coincide in the horizontal direction.
  • the dielectric layer can act as a buffer layer for the substrate material, reducing stress accumulation; on the other hand, the dielectric layer has a higher dielectric constant (eg, SiO 2 dielectric constant is 3.9, SiN dielectric constant is 7.0, AlN) The dielectric constant is 8.5). Under the premise of ensuring sufficient breakdown voltage of the substrate, the dielectric material can be of sufficient thickness to ensure the quality of the dielectric layer and increase the robustness and reliability of the substrate.
  • FIG 8 is a schematic view showing the structure of a semiconductor substrate in a seventh embodiment of the present invention, which is a composite substrate in which Si (111) layers and Si (110) layers are alternately formed.
  • the semiconductor substrate 1 may be formed by alternately laminating three or more semiconductor layers, and the semiconductor epitaxial layer 2 is formed on the semiconductor substrate 1.
  • the semiconductor layer includes the first semiconductor layer 11 and the second semiconductor layer 12.
  • the composite substrate shown in FIG. 8 includes three semiconductor layers, which are respectively the first semiconductor from bottom to top.
  • the first semiconductor layer 11 and the second semiconductor layer have the same lattice structure, and both have the same crystal orientation in the vertical direction, and the crystal orientations in the horizontal direction may or may not coincide.
  • the first semiconductor layer and the second semiconductor layer are alternately formed in a stacked structure of three or more layers in this order.
  • the first semiconductor layer 11 includes a lower Si (111) semiconductor layer
  • the second semiconductor layer 12 includes an upper Si (110) semiconductor layer.
  • the two semiconductor layers are laminated to form a composite substrate structure of Si (111), Si (110), Si (111), and Si (110). This method also ensures that the dissociation surfaces of the respective silicon semiconductor layers are not in the same direction, thereby avoiding the cracking of the silicon substrate caused by the accumulation of stress, and the reliability of the silicon substrate can be greatly improved.
  • the stacked structure further includes a dielectric layer between the first semiconductor layer and the second semiconductor layer, the dielectric layer material including SiO 2 , SiN, AlN, or the like.
  • the dielectric layer has the same crystal orientation in the vertical direction as the adjacent first semiconductor layer and/or the second semiconductor layer, and does not coincide in the horizontal direction in the horizontal direction; or the dielectric layer and the adjacent first semiconductor layer and/or The crystal structure of the second semiconductor layer is different, and the crystal orientation does not coincide in the horizontal direction.
  • the material of the dielectric layer may also be amorphous, as a buffer layer of the substrate, reducing the accumulation of stress; on the other hand, the dielectric layer material has a high dielectric constant (such as a dielectric constant of 3.9 for SiO 2 , SiN has a dielectric constant of 7.0, AlN has a dielectric constant of 8.5) and a critical breakdown electric field. Under the premise of ensuring sufficient breakdown voltage of the substrate, it can have a dielectric layer of sufficient thickness to ensure the quality of the dielectric layer. The robustness and reliability of large substrates.
  • the first semiconductor layer and the second semiconductor layer in the substrate may be The accumulation of stress at the interface of the semiconductor layer can be prevented, and the entire substrate can be prevented from being cracked due to local stress accumulation of the second semiconductor layer to the entire semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer have different dissociation faces in a vertical direction
  • the first semiconductor layer is rotated after lattice symmetry of the first semiconductor layer
  • the obtained semiconductor layer and the second semiconductor layer have different dissociation surfaces in a vertical direction
  • the first semiconductor layer and the second semiconductor layer are rotated by lattice symmetry of the second semiconductor layer to obtain a semiconductor layer having a different dissociation surface in a vertical direction, or a semiconductor layer obtained by rotating the first semiconductor layer in a lattice symmetry of the first semiconductor layer and the second semiconductor layer according to the first
  • the semiconductor layers obtained after the lattice symmetry rotation of the two semiconductor layers have different dissociation faces in the vertical direction.
  • the present invention provides a semiconductor substrate, a semiconductor device and a semiconductor
  • the bulk substrate manufacturing method makes the semiconductor substrate have a special lattice structure and mechanical structure, and the semiconductor substrate is set as a composite substrate structure, and under the condition of the substrate thickness, the stress applied to the semiconductor epitaxial layer can be reduced to the silicon lining. Damage caused by the bottom, thereby reducing the probability of silicon substrate fracture; at the same time, it can reduce the process difficulty and enhance the reliability of the semiconductor device.

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Abstract

一种半导体衬底、半导体器件及半导体衬底的制造方法，其中半导体衬底（1）包括第一半导体层（11）以及位于第一半导体层上的第二半导体层（12），第一半导体层和第二半导体层以及各自按其晶格对称性旋转后在垂直方向上均具有不同的解离面。将半导体衬底设为复合型衬底结构，在同样衬底厚度的条件下，可以减少半导体外延层施加的应力对半导体衬底产生的损害，从而减小半导体衬底破碎的几率，同时可以减小工艺难度，增强半导体器件的可靠性。

Description

半导体衬底、半导体器件及半导体衬底制造方法
本申请要求于2014年01月07日提交中国专利局、申请号为201410006568.4、发明名称为“半导体衬底、半导体器件及半导体衬底制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及微电子技术领域，特别是涉及一种半导体衬底、半导体器件及半导体衬底制造方法。
背景技术
以氮化镓为代表的Ⅲ族氮化物越来越受到人们的重视，因为Ⅲ族氮化物可以广泛用作半导体照明的发光二极管(LED)和高功率电子器件。由于本征衬底的缺乏，氮化镓器件普遍制备在异质衬底上，比如蓝宝石、碳化硅和硅。硅衬底由于其广泛的应用性，它的尺寸和质量都是在上述几种衬底材料当中最好的。目前互补金属氧化物半导体(CMOS)的主流技术就是基于12寸的硅基板，而且硅的价格也是其他几种材料不能比拟的。所以，在大尺寸硅衬底上制备氮化镓材料，是降低氮化镓基器件成本的最佳办法。
但是，由于氮化镓和硅之间存在巨大的晶格失配和热失配，在制备和冷却的过程中会引入大量的应力。这个应力会造成外延片的翘曲和外延膜的龟裂，另外对硅衬底本身也有很大的伤害。由于硅衬底中残余的应力，在工艺过程中硅上的氮化镓外延片会发生破碎，造成巨大的损失。为了避免这种情况，通常的办法是采用厚的硅基板，但是工艺线对衬底的厚度都存在一个上限。当硅衬底的厚度超过一定临界值之后，工艺设备无法处理，比如光刻机无法聚焦对准，工艺无法实现。
因此，针对上述技术问题及改进方法，有必要提供一种半导体衬底、半导体器件及半导体衬底制造方法。
发明内容
为了解决上述问题，本发明提出了一个复合衬底结构的概念。通常来说，由于对称性的原因，氮化镓外延片最好都是在Si(111)衬底上制备，使得制备的外延膜具有较好的晶体质量、电学性质和光学性质。氮化镓的晶格结构具有六角对称的特点，在应力释放的时候也遵循同样的关系。而Si(111)的解离面也有三角对称的特点，硅衬底在因受到应力而损伤的时候则是三角对称。由于对称的匹配关系，在Si(111)上制备的氮化镓晶体质量最好，但是相应的，在受到应力的时候也是最容易破碎的。为了避免这种情况，本发明提出了利用硅非对称复合衬底来制备氮化镓外延层。
硅半导体内的应力是随着同一晶向的硅的厚度增加而不断累积的，而当同一晶向的硅的表面处与另一晶向的硅相接触时，应力会减少而不会累积。本发明通过引入两层或多层不同晶向的Si(111)，使相互接触的Si(111)半导体层的解离面不重合，从而降低应力通过硅衬底的损伤，防止硅衬底龟裂引起的氮化镓半导体层的破裂，达到提高氮化镓半导体层坚固性和可靠性的目的。
上述复合衬底也可以通过将两种不同晶向的硅半导体层结合形成，如将Si(111)半导体层和Si(100)半导体层结合形成复合衬底结构。通过控制硅片键合时的角度，可以使得Si(111)半导体层和Si(100)半导体层的解离面不重合，所以氮化镓外延层产生的缺陷传递到其中一个硅半导体层上时将会大大减少，从而避免延续到另一种硅半导体层，减少了氮化镓外延层的应力导致的衬底破碎的几率，增强了衬底的坚固性和可靠性。
上述复合型衬底的制造可以用晶片键合的方法完成，例如可以把两片较薄衬底按照不同的晶向错开一定角度进行键合生成复合衬底。
为了实现上述目的，本发明实施例提供的技术方案如下：
一种半导体衬底，所述半导体衬底包括第一半导体层以及位于所述第一半导体层上的第二半导体层，其中，所述第一半导体层和所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面，或者所述第一半 导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面。
作为本发明的进一步改进，所述第一半导体层和所述第二半导体层的材料相同或不同。
作为本发明的进一步改进，所述第一半导体层和所述第二半导体层具有相同的晶格结构，所述第一半导体层和所述第二半导体层在垂直方向上具有相同的晶向、在水平方向上的晶向不重合。
作为本发明的进一步改进，所述第一半导体层和所述第二半导体层的晶体结构不同，所述第一半导体层和所述第二半导体层在水平方向的晶向不重合。
作为本发明的进一步改进，所述第一半导体层的材料形态包括晶态、非晶态和无定形态的一种或多种的组合。
作为本发明的进一步改进，所述第一半导体层的材料为无定形态材料，所述无定形态材料包括非半导体材料，所述非半导体材料包括氮化铝、多晶碳化硅、陶瓷和石英。
作为本发明的进一步改进，所述第一半导体层为无定形态材料，第一半导体层和第二半导体层的键合方向不受限制。
作为本发明的进一步改进，所述第二半导体层为晶体层。
作为本发明的进一步改进，所述第一半导体层和第二半导体层依次交替形成三层或三层以上的层叠结构。
作为本发明的进一步改进，所述层叠结构包括位于第一半导体层和所述第二半导体层之间的介质层。
作为本发明的进一步改进，所述介质层与其相邻的所述第一半导体层在垂直方向上具有相同的晶向、在水平方向上晶向不重合；
和/或，
所述介质层与其相邻的所述第二半导体层在垂直方向上具有相同的晶向、在水平方向上晶向不重合。
作为本发明的进一步改进，所述介质层与相邻的所述第一半导体层的晶体 结构不同，且在水平方向上晶向不重合；
和/或，
所述介质层与相邻的所述第二半导体层的晶体结构不同，且在水平方向上晶向不重合。
相应地，一种半导体器件，所述半导体器件包括半导体衬底以及位于所述半导体衬底上的半导体外延层，所述半导体衬底为上述任一实施方式所述的半导体衬底。
作为本发明的进一步改进，所述半导体外延层包括硅、砷化镓、氮化镓、铝镓氮、铟镓氮、铝镓铟氮中的一种或多种的组合。
作为本发明的进一步改进，所述半导体器件包括发光二极管、激光二极管、高电子迁移率晶体管、场效应晶体管、肖特基二极管、PIN二极管和太阳能电池。
相应地，一种半导体衬底的制造方法，所述方法包括：
S1、提供第一半导体层；
S2、在所述第一半导体层上制备第二半导体层；其中，所述第一半导体层和所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面，或者所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面。
作为本发明的进一步改进，所述步骤S2后还包括：
在所述第二半导体层上制备半导体外延层。
作为本发明的进一步改进，所述第一半导体层和所述第二半导体层的制备方法包括直拉法、区熔法、物理气相沉积和化学气相沉积中的一种或多种的组合。
作为本发明的进一步改进，所述步骤S2中在所述第一半导体层上制备第 二半导体层的方法包括晶片键合。
作为本发明的进一步改进，所述半导体外延层的制备方法包括金属有机物化学气相沉积、分子束外延和氢化物气相外延中的一种或多种的组合。
作为本发明的进一步改进，所述步骤S2后还包括：
在所述第二半导体层上制备所述第一半导体层，以形成三层结构的层叠结构；
或者，在所述第二半导体层上依次交替制备所述第一半导体层和所述第二半导体层，以形成三层以上结构的层叠结构。
作为本发明的进一步改进，所述方法还包括：
在所述第一半导体层和所述第二半导体层之间生长介质层。
作为本发明的进一步改进，介质层通过沉积、热氧化或者氮化的方法制成，所述沉积的方法包括CVD、PECVD、LPCVD、RTCVD、MOCVD、MBE、ALD中的一种或多种的组合。
本发明提供的半导体衬底、半导体器件及半导体衬底制造方法使得半导体衬底具有特殊的晶格结构和力学结构，将半导体衬底设为复合型衬底结构，同样衬底厚度的条件下，可以减少半导体外延层施加的应力对硅衬底产生的损害，从而减少硅衬底破碎的几率；同时可以减小工艺难度，增强半导体器件的可靠性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明中涉及到的硅各个晶向的示意图；
图2为本发明第一实施方式中上层Si(111)的<-211>方向和下层Si(111)的<1-10>方向平行的半导体衬底结构图；
图3为本发明第二实施方式中上层的Si(111)的<-211>方向和下层Si(111) 的<-101>方向平行的半导体衬底结构图；
图4(a)为本发明第三实施方式中上层的Si(111)的<-211>方向和下层Si(111)的<-211>方向存在一个偏角的半导体衬底结构图，图4(b)和图4(c)分别为上层Si(111)和下层Si(111)的俯视图；
图5(a)为本发明第四实施方式中上层的Si(111)的<-211>方向和下层Si(100)的<-110>方向存在一个偏角的半导体衬底结构图，图5(b)和图5(c)分别为上层Si(111)和下层Si(100)的俯视图；
图6为本发明第五实施方式中具有Si(111)层和Si(100)层交替复合衬底结构的半导体衬底结构图；
图7为本发明第六实施方式中具有Si(110)层和Si(100)层交替复合衬底结构的半导体衬底结构图；
图8为本发明第七实施方式中具有Si(111)层和Si(110)层交替复合衬底结构的半导体衬底结构图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关联性。
图1所示为本发明中涉及到的硅各个晶向的示意图，以下结合图1针对不同的实施方式对本发明作进一步说明。
图2为本发明第一实施方式中半导体衬底的结构示意图，即上层Si(111)的<-211>方向和下层Si(111)的<1-10>方向平行的半导体衬底结构图。本实施方式中，半导体衬底1包括：第一半导体层11；位于第一半导体层11上的第二半导体层12，第二半导体层12可以用来制备半导体外延层2。其中，第一半导体层11和第二半导体层12在垂直方向上具有不同的解离面。
优选地，第一半导体层11可以是半导体材料、无定形材料和晶体中的一 种或多种的组合，第一半导体层11选用的半导体材料包括Si、GaN、AlN、SiC、GaAs、InP、金刚石中的一种或多种，无定形材料包括氮化铝、陶瓷和石英等，当第一半导体层11为无定形材料时，第一半导体层11和第二半导体层12的键合方向不受限制。
第一半导体层12可以是晶体层，第一半导体层12选用的半导体材料包括Si、GaN、AlN、SiC、GaAs、InP、金刚石中的一种或多种，第一半导体层11和第二半导体层12的材料可以相同或不同，但是采用不同的晶向。如第一半导体层和第二半导体层具有相同的晶格结构，第一半导体层和第二半导体层在垂直方向上具有相同的晶向、在水平方向上的晶向不重合；或者第一半导体层和第二半导体层的晶体结构不同，第一半导体层和第二半导体层在水平方向的晶向不重合。
本实施方式中，第一半导体层11和第二半导体层12可以具有相同的晶格结构Si(111)，在垂直方向上具有相同的晶向，但是在水平方向上的晶体对称性不同。
上述半导体外延层2可以包括硅、砷化镓、氮化镓、铝镓氮、铟镓氮、铝镓铟氮中的一种或多种的组合。半导体外延层为氮化物时，可以用于制作多种器件结构，包括发光二极管(LED)、激光二极管、高电子迁移率晶体管(HEMT)、场效应晶体管(FET)、肖特基二极管、PIN二极管和太阳能电池等。
本实施方式中，同时提供了上述半导体衬底1的制造方法，包括以下步骤：
S1、提供第一半导体层11；
S2、在所述第一半导体层11上制备第二半导体层12，第一半导体层11和第二半导体层12在垂直方向上具有不同的解离面。
进一步地，步骤S2后还包括：在第二半导体层12上制备半导体外延层2。
作为本发明的一个实施例，为了使得制造出的半导体衬底包括三层半导体层组成的层叠结构，在上述所述的步骤S12之后，还可以包括：
在所述第二半导体层12上还可以制备第一半导体层13以形成三层结构的层叠结构。需要说明的是，在本发明实施例中，形成的第一半导体层13与第一半导体层11具有相同的晶格结构，两者在垂直方向上具有相同的晶向，在水平方向上的晶向可以重合也可以不重合。
进一步地，作为本发明的另一实施例，为了使得制造出的半导体衬底包括三层以上半导体层组成的层叠结构，在上述所述的步骤S12之后，还可以包括：
在所述第二半导体层12上还可以依次交替制备第一半导体层13和第二半导体层，以形成三层以上结构的层叠结构。
本实施方式中第一半导体层11和第二半导体层12都包括Si(111)半导体层，其中，第二半导体层12即上层Si(111)半导体层的<-211>方向和第一半导体层11即下层Si(111)半导体层的<1-10>方向相互平行。当然在其他实施方式中第二半导体层12的<-211>方向和第一半导体层11的<1-10>方向之间可以设有夹角，如夹角可以是10°、20°或30°等；第一半导体层11和第二半导体层12可以交替层叠形成复合结构，这样使得上层Si(111)半导体层和下层Si(111)半导体层的解离面相互错开，与单一硅半导体层相比，这种方法可以在上层Si(111)半导体层和下层Si(111)半导体层界面处减小应力的累积，可以避免由于硅半导体层局部的应力累积到整个硅半导体层，导致整个硅衬底发生龟裂。
图3为本发明第二实施方式中半导体衬底的结构示意图，即上层的Si(111)的<-211>方向和下层Si(111)的<-101>方向平行的半导体衬底结构图。本实施方式中，半导体衬底1包括：第一半导体层11；位于第一半导体层11上的第二半导体层12，第二半导体层12可以用来制备半导体外延层2。
第一半导体层11包括下层Si(111)半导体层，第二半导体层12包括上层的Si(111)半导体层，且上层Si(111)半导体层的<-211>方向和下层Si(111)层的<-101>方向相互平行。优选地，第一半导体层11和第二半导体层12可以交替层叠形成复合结构。这样可以保证上层Si(111)半导体层和下层Si(111)半导体层具有的解离面不在同一个方向上，从而避免了应力的累积导致的硅衬底的龟裂，可以大大提高硅衬底的可靠性。
图4(a)、图4(b)和图4(c)为本发明第三实施方式中半导体衬底的结构示意图，即上层的Si(111)的<-211>方向和下层Si(111)的<-211>方向存在一个偏角的半导体衬底结构图。其中，图4(a)为该结构的剖面示意图，图4(b)和图4(c)分别为上层Si(111)和下层Si(111)的俯视图。本实施方式中，半导体衬底1包括：第一半导体层11；位于第一半导体层11上的第二半导体层12，第二半导体层12可以用来制备半导体外延层2。
第一半导体层11包括下层Si(111)半导体层，第二半导体层12包括上层的Si(111)半导体层，且上层Si(111)半导体层的<-211>方向和下层Si(111)层的<-211>方向存在一个偏角，该偏角的大小不等于60°或者60°的整数倍。优选地，第一半导体层11和第二半导体层12可以交替层叠形成复合结构。这样可以保证上层Si(111)半导体层和下层Si(111)半导体层具有的解离面不在同一个方向上，从而避免了应力的累积导致的硅衬底的龟裂，可以大大提高硅衬底的可靠性。
图5(a)、图5(b)和图5(c)为本发明第四实施方式中半导体衬底的结构示意图，即上层的Si(111)的<-211>方向和下层Si(100)的<-110>方向存在一个偏角的半导体衬底结构图。其中，图5(a)为该结构的剖面示意图，图5(b)和图5(c)分别为上层Si(111)和下层Si(100)的俯视图。半导体衬底1包括：第一半导体层11；位于第一半导体层11上的第二半导体层12，第二半导体层12可以用来制备半导体外延层2。本实施方式中，第一半导体层11和第二半导体层12的晶体结构不同，第一半导体层11和第二半导体层12在水平方向的晶向不重合。
第一半导体层11包括下层Si(100)半导体层，第二半导体层12包括上层的Si(111)半导体层，且上层Si(111)半导体层的<-211>方向和下层Si(100)层的<-110>方向存在一个偏角，该偏角的大小不等于90°或者90°的整数倍。优选地，第一半导体层和第二半导体层可以交替层叠形成复合结构。这样可以保证上层Si(111)半导体层和下层Si(100)半导体层具有的解离面不在同一个方向上，从而避免了应力的累积导致的硅衬底的龟裂，可以大大提高硅衬底的可靠性。
需要说明的是，本实施方式中，半导体衬底1可以由三层或三层以上的半导体层层叠形成，半导体衬底1上制备有半导体外延层2。其中，半导体层包括第一半导体层11和第二半导体层12。需要说明的是，当半导体衬底包括两层以上的第一半导体层时，该多个第一半导体层均具有相同的晶格结构，并且该多个第一半导体层在垂直方向上具有相同的晶向，在水平方向上的晶向可以重合也可以不重合。同样，当半导体衬底包括两层以上的第二半导体层时，该多个第二半导体层均具有相同的晶格结构，并且该多个第二半导体层在垂直方 向上具有相同的晶向，在水平方向上的晶向可以重合也可以不重合。
图6为本发明第五实施方式中半导体衬底的结构示意图。作为示例，图6所示的复合衬底包括三层半导体层，从下向上依次分别为第一半导体层11、第二半导体层12以及第一半导体层13。其中，第一半导体层11和第二半导体层具有相同的晶格结构，并且两者在垂直方向上具有相同的晶向，在水平方向上的晶向可以重合也可以不重合。
第一半导体层和第二半导体层依次交替形成三层半导体层组成的层叠结构。在本发明实施例中，第一半导体层11包括下层Si(111)半导体层，第二半导体层12包括上层的Si(100)半导体层。
需要说明的是，由第一半导体层11和第二半导体层12依次交替层叠形成的半导体衬底不限于图6所示的三层结构，实际上，作为本发明实施例的扩展，由第一半导体层11和第二半导体层12交替层叠还可以形成三层以上的层叠结构。
当第一半导体层11为Si(111)，第二半导体层12为Si(100)时，在本发明实施例中，由第一半导体层11和第二半导体层12依次交替层叠就可以形成Si(111)、Si(100)、Si(111)和Si(100)的复合衬底结构。这种方法同样可以保证各个硅半导体层具有的解离面不在同一个方向上，从而避免了应力的累积导致的硅衬底的龟裂，可以大大提高硅衬底的可靠性。
进一步地，由第一半导体层11和第二半导体层12依次交替形成三层或三层以上的层叠结构还可以包括位于第一半导体层11和第二半导体层12之间的介质层(图6中未示出)，介质层材料包括SiO2、SiN、AlN等。
所述介质层与其相邻的所述第一半导体层11在垂直方向上具有相同的晶向、在水平方向上晶向不重合；和/或，所述介质层与其相邻的所述第二半导体层12在垂直方向上具有相同的晶向、在水平方向上晶向不重合。
一方面，介质层的材料也可以是无定形态，作为衬底材料的缓冲层，减少应力的累积；另一方面，介质层的材料具有较高的介电常数(如SiO2介电常数为3.9，SiN介电常数为7.0，AlN介电常数为8.5)和临界击穿电场，在保证衬底承受足够的击穿电压的前提下，可以拥有足够厚度的介质材料，可以保证介质材料的质量，增大衬底材料的坚固性和可靠性。
图7为本发明第六实施方式中半导体衬底的结构示意图，该半导体衬底为由Si(110)层和Si(100)层交替层叠形成的复合衬底。本实施方式中，半导体衬底1也可以由三层或三层以上的半导体层交替层叠形成，半导体衬底1上制备有半导体外延层2。其中，半导体层包括第一半导体层11和第二半导体层12。
作为示例，图7所示的复合衬底包括三层半导体层，从下向上依次分别为第一半导体层11、第二半导体层12以及第一半导体层13。第一半导体层11和第二半导体层具有相同的晶格结构，并且两者在垂直方向上具有相同的晶向，在水平方向上的晶向可以重合也可以不重合。在本发明实施例中，其中，第一半导体层11包括下层Si(110)半导体层，第二半导体层12包括上层的Si(100)半导体层。
在本发明实施例中，当第一半导体层11和第二半导体层12依次交替层叠就可以形成Si(110)、Si(100)、Si(110)和Si(100)的复合衬底结构。该复合衬底结构可以包括三层或三层以上的层叠结构。这种方法同样可以保证各个硅半导体层具有的解离面不在同一个方向上，从而避免了应力的累积导致的硅衬底的龟裂，可以大大提高硅衬底的可靠性。
进一步地，层叠结构还包括位于第一半导体层11和第二半导体层12之间的介质层(图7中未示出)，介质层材料包括SiO2、SiN、AlN等。介质层与相邻的第一半导体层11和/或第二半导体层12在垂直方向上具有相同的晶向、在水平方向上晶向不重合；或者介质层与相邻的第一半导体层11和/或第二半导体层12的晶体结构不同，且在水平方向上晶向不重合。一方面，介质层可以作为衬底材料的缓冲层，减少应力的累积；另一方面，介质层具有较高的介电常数(如SiO2介电常数为3.9，SiN介电常数为7.0，AlN介电常数为8.5)，在保证衬底承受足够的击穿电压的前提下，可以拥有足够厚度的介质材料，可以保证介质层的质量，增大衬底的坚固性和可靠性。
图8为本发明第七实施方式中半导体衬底的结构示意图，该半导体衬底为由有Si(111)层和Si(110)层交替形成的复合衬底。本实施方式中，半导体衬底1可以由三层或三层以上的半导体层交替层叠形成，半导体衬底1上制备有半导体外延层2。其中，半导体层包括第一半导体层11和第二半导体层12。
图8所示的复合衬底包括三层半导体层，从下向上依次分别为第一半导体 层11、第二半导体层12以及第一半导体层13。第一半导体层11和第二半导体层具有相同的晶格结构，并且两者在垂直方向上具有相同的晶向，在水平方向上的晶向可以重合也可以不重合。其中，第一半导体层和第二半导体层依次交替形成三层或三层以上的层叠结构。在本发明实施例中，第一半导体层11包括下层Si(111)半导体层，第二半导体层12包括上层的Si(110)半导体层。两种半导体层层叠形成Si(111)、Si(110)、Si(111)和Si(110)的复合衬底结构。这种方法同样可以保证各个硅半导体层具有的解离面不在同一个方向上，从而避免了应力的累积导致的硅衬底的龟裂，可以大大提高硅衬底的可靠性。
进一步地，层叠结构还包括位于第一半导体层和第二半导体层之间的介质层，介质层材料包括SiO2、SiN、AlN等。介质层与相邻的第一半导体层和/或第二半导体层在垂直方向上具有相同的晶向、在水平方向上晶向不重合；或者介质层与相邻的第一半导体层和/或第二半导体层的晶体结构不同，且在水平方向上晶向不重合。一方面，介质层的材料也可以是无定形态，作为衬底的缓冲层，减少应力的累积；另一方面，介质层材料具有较高的介电常数(如SiO2介电常数为3.9，SiN介电常数为7.0，AlN介电常数为8.5)和临界击穿电场，在保证衬底承受足够的击穿电压的前提下，可以拥有足够厚度的介质层，可以保证介质层的质量，增大衬底的坚固性和可靠性。
综上所述，只要衬底中的第一半导体层和第二半导体层或者各自按其晶格对称性旋转后在垂直方向上具有不同的解离面，均可以在第一半导体层和第二半导体层界面处减小应力的累积，可以避免由于第二半导体层局部的应力累积到整个半导体层，导致整个衬底发生龟裂。具体地说，其中，所述第一半导体层和所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面，或者所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面。
由以上技术方案可以看出，本发明提供的半导体衬底、半导体器件及半导 体衬底制造方法使得半导体衬底具有特殊的晶格结构和力学结构，将半导体衬底设为复合型衬底结构，同样衬底厚度的条件下，可以减少半导体外延层施加的应力对硅衬底产生的损害，从而减少硅衬底破碎的几率；同时可以减小工艺难度，增强半导体器件的可靠性。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (23)

  1. 一种半导体衬底，其特征在于，所述半导体衬底包括第一半导体层以及位于所述第一半导体层上的第二半导体层；其中，所述第一半导体层和所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面，或者所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面。
  2. 根据权利要求1所述的半导体衬底，其特征在于，所述第一半导体层和所述第二半导体层的材料相同或不同。
  3. 根据权利要求2所述的半导体衬底，其特征在于，所述第一半导体层和所述第二半导体层具有相同的晶格结构，所述第一半导体层和所述第二半导体层在垂直方向上具有相同的晶向、在水平方向上的晶向不重合。
  4. 根据权利要求2所述的半导体衬底，其特征在于，所述第一半导体层和所述第二半导体层的晶体结构不同，所述第一半导体层和所述第二半导体层在水平方向的晶向不重合。
  5. 根据权利要求1所述的半导体衬底，其特征在于，所述第一半导体层的材料形态包括晶态、非晶态和无定形态的一种或多种的组合。
  6. 根据权利要求5所述的半导体衬底，其特征在于，所述第一半导体层的材料为无定形态材料，所述无定形态材料包括非半导体材料，所述非半导体材料包括氮化铝、多晶碳化硅、陶瓷和石英。
  7. 根据权利要求5所述的半导体衬底，其特征在于，所述第一半导体层为无定形态材料，第一半导体层和第二半导体层的键合方向不受限制。
  8. 根据权利要求1所述的半导体衬底，其特征在于，所述第二半导体层为晶体层。
  9. 根据权利要求1所述的半导体衬底，其特征在于，所述第一半导体层和所述第二半导体层依次交替形成三层或三层以上的层叠结构。
  10. 根据权利要求9所述的半导体衬底，其特征在于，所述层叠结构包括位于所述第一半导体层和所述第二半导体层之间的介质层。
  11. 根据权利要求10所述的半导体衬底，其特征在于，所述介质层与其相邻的所述第一半导体层在垂直方向上具有相同的晶向、在水平方向上晶向不重合；
    和/或，
    所述介质层与其相邻的所述第二半导体层在垂直方向上具有相同的晶向、在水平方向上晶向不重合。
  12. 根据权利要求10所述的半导体衬底，其特征在于，所述介质层与相邻的所述第一半导体层的晶体结构不同，且在水平方向上晶向不重合；
    和/或，
    所述介质层与相邻的所述第二半导体层的晶体结构不同，且在水平方向上晶向不重合。
  13. 一种半导体器件，其特征在于，包括半导体衬底以及位于所述半导体衬底之上的半导体外延层，所述半导体衬底为权利要求1～12任一项所述的半导体衬底。
  14. 根据权利要求13所述的半导体器件，其特征在于，所述半导体外延层包括硅、砷化镓、氮化镓、铝镓氮、铟镓氮、铝镓铟氮中的一种或多种的组合。
  15. 根据权利要求13所述的半导体器件，其特征在于，所述半导体器件包括发光二极管、激光二极管、高电子迁移率晶体管、场效应晶体管、肖特基二极管、PIN二极管或太阳能电池。
  16. 一种半导体衬底的制造方法，其特征在于，所述方法包括：
    S1、提供第一半导体层；
    S2、在所述第一半导体层上制备第二半导体层，其中，所述第一半导体层和所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层在垂直方向上具有不同的解离面，所述第一半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面，或者所述第一半导体层按所述第一半导体层的晶格对称性旋转后得到的半导体层与所述第二半导体层按所述第二半导体层的晶格对称性旋转后得到的半导体层在垂直方向上具有不同的解离面。
  17. 根据权利要求16所述的制造方法，其特征在于，所述步骤S2后还包括：
    在所述第二半导体层上制备半导体外延层。
  18. 根据权利要求16所述的制造方法，其特征在于，所述第一半导体层和所述第二半导体层的制备方法包括直拉法、区熔法、物理气相沉积和化学气相沉积中的一种或多种的组合。
  19. 根据权利要求16所述的制造方法，其特征在于，所述步骤S2中在所述第一半导体层上制备第二半导体层的方法包括晶片键合。
  20. 根据权利要求16所述的制造方法，其特征在于，所述半导体外延层的制备方法包括金属有机物化学气相沉积、分子束外延和氢化物气相外延中的一种或多种的组合。
  21. 根据权利要求16所述的制造方法，其特征在于，所述步骤S2后还包括：
    在所述第二半导体层上制备所述第一半导体层，以形成三层结构的层叠结构；
    或者，在所述第二半导体层上依次交替制备所述第一半导体层和所述第二半导体层，以形成三层以上结构的层叠结构。
  22. 根据权利要求21所述的制造方法，其特征在于，所述方法还包括：
    在所述第一半导体层和所述第二半导体层之间生长介质层。
  23. 根据权利要求22所述的制造方法，其特征在于，所述介质层通过沉积、热氧化或者氮化的方法制成，所述沉积的方法包括CVD、PECVD、LPCVD、RTCVD、MOCVD、MBE、ALD中的一种或多种的组合。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017222513A1 (en) * 2016-06-22 2017-12-28 Intel Corporation Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681992A (zh) * 2014-01-07 2014-03-26 苏州晶湛半导体有限公司 半导体衬底、半导体器件及半导体衬底制造方法
DE102016013540A1 (de) * 2016-11-14 2018-05-17 3 - 5 Power Electronics GmbH lll-V-Halbleiterdiode
JP6863423B2 (ja) * 2019-08-06 2021-04-21 信越半導体株式会社 電子デバイス用基板およびその製造方法
WO2023100577A1 (ja) * 2021-12-01 2023-06-08 信越半導体株式会社 電子デバイス用基板及びその製造方法
CN114759126B (zh) * 2022-06-13 2022-09-20 江苏第三代半导体研究院有限公司 基于氮化物单晶衬底的半导体器件结构及其制备方法
CN116779688A (zh) * 2023-07-28 2023-09-19 合肥安芯睿创半导体有限公司 一种具有结型p+保护的沟槽结构的碳化硅肖特基二极管及制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101017864A (zh) * 2006-02-08 2007-08-15 中国科学院半导体研究所 具有超薄碳化硅中间层的硅基可协变衬底及制备方法
CN102208337A (zh) * 2010-03-30 2011-10-05 杭州海鲸光电科技有限公司 一种硅基复合衬底及其制造方法
US20120119223A1 (en) * 2000-12-14 2012-05-17 International Rectifier Corporation Gallium Nitride Semiconductor Structures with Compositionally-Graded Transition Layer
CN103035496A (zh) * 2012-12-11 2013-04-10 广州市众拓光电科技有限公司 一种生长在Si衬底上的GaN薄膜及其制备方法和应用
CN103681992A (zh) * 2014-01-07 2014-03-26 苏州晶湛半导体有限公司 半导体衬底、半导体器件及半导体衬底制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63193517A (ja) * 1987-02-06 1988-08-10 Nec Corp 複合単結晶基板
JPH07335511A (ja) * 1994-06-13 1995-12-22 Nippon Telegr & Teleph Corp <Ntt> 張り合わせウエハ
US5981400A (en) * 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
US6333208B1 (en) * 1999-07-13 2001-12-25 Li Chiung-Tung Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding
US6984571B1 (en) * 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US7348610B2 (en) * 2005-02-24 2008-03-25 International Business Machines Corporation Multiple layer and crystal plane orientation semiconductor substrate
JP5009124B2 (ja) * 2007-01-04 2012-08-22 コバレントマテリアル株式会社 半導体基板の製造方法
JP4888276B2 (ja) * 2007-08-09 2012-02-29 三菱電機株式会社 半導体ウエハ装置
EP2357679B1 (en) * 2008-11-14 2018-08-29 Samsung Electronics Co., Ltd. Vertical/horizontal light-emitting diode for semiconductor
US8298923B2 (en) * 2010-10-27 2012-10-30 International Business Machinces Corporation Germanium-containing release layer for transfer of a silicon layer to a substrate
JP2013247362A (ja) * 2012-05-29 2013-12-09 Samsung Corning Precision Materials Co Ltd 半導体素子用薄膜貼り合わせ基板の製造方法
CN102978695A (zh) * 2012-12-12 2013-03-20 东莞市中镓半导体科技有限公司 半导体器件外延生长的隐形结构衬底
CN103296066B (zh) * 2013-05-31 2015-09-16 华南理工大学 生长在铝酸锶钽镧衬底上的GaN薄膜及其制备方法、应用

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120119223A1 (en) * 2000-12-14 2012-05-17 International Rectifier Corporation Gallium Nitride Semiconductor Structures with Compositionally-Graded Transition Layer
CN101017864A (zh) * 2006-02-08 2007-08-15 中国科学院半导体研究所 具有超薄碳化硅中间层的硅基可协变衬底及制备方法
CN102208337A (zh) * 2010-03-30 2011-10-05 杭州海鲸光电科技有限公司 一种硅基复合衬底及其制造方法
CN103035496A (zh) * 2012-12-11 2013-04-10 广州市众拓光电科技有限公司 一种生长在Si衬底上的GaN薄膜及其制备方法和应用
CN103681992A (zh) * 2014-01-07 2014-03-26 苏州晶湛半导体有限公司 半导体衬底、半导体器件及半导体衬底制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3093891A4 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017222513A1 (en) * 2016-06-22 2017-12-28 Intel Corporation Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors
US20190279908A1 (en) * 2016-06-22 2019-09-12 Intel Corporation Techniques for monolithic co-integration of silicon and iii-n semiconductor transistors
US10879134B2 (en) 2016-06-22 2020-12-29 Intel Corporation Techniques for monolithic co-integration of silicon and III-N semiconductor transistors

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