WO2021015010A1 - 基板処理装置及び処理条件調整方法 - Google Patents

基板処理装置及び処理条件調整方法 Download PDF

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Publication number
WO2021015010A1
WO2021015010A1 PCT/JP2020/027054 JP2020027054W WO2021015010A1 WO 2021015010 A1 WO2021015010 A1 WO 2021015010A1 JP 2020027054 W JP2020027054 W JP 2020027054W WO 2021015010 A1 WO2021015010 A1 WO 2021015010A1
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Prior art keywords
substrate
processing
adjustment
imaging
exposure
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Ceased
Application number
PCT/JP2020/027054
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English (en)
French (fr)
Japanese (ja)
Inventor
真任 田所
正志 榎本
健太郎 山村
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2021533945A priority Critical patent/JP7154416B2/ja
Priority to US17/625,370 priority patent/US11809091B2/en
Priority to CN202080050730.6A priority patent/CN114127903A/zh
Priority to KR1020227005086A priority patent/KR20220034879A/ko
Publication of WO2021015010A1 publication Critical patent/WO2021015010A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0602—Temperature monitoring
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/70858—Environment aspects, e.g. pressure of beam-path gas, temperature
    • G03F7/70866—Environment aspects, e.g. pressure of beam-path gas, temperature of mask or workpiece
    • G03F7/70875—Temperature, e.g. temperature control of masks or workpieces via control of stage temperature
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0604—Process monitoring, e.g. flow or thickness monitoring
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/38—Treatment before imagewise removal, e.g. prebaking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0432—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0431—Apparatus for thermal treatment
    • H10P72/0436—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0448—Apparatus for applying a liquid, a resin, an ink or the like
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H10P72/0474—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one lithography chamber
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/235—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising optical enhancement of defects or not-directly-visible states
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Definitions

  • This disclosure relates to a substrate processing apparatus and a processing condition adjusting method.
  • Patent Document 1 discloses a substrate processing method for uniformly forming a resist pattern having a desired line width on a wafer.
  • the film thickness distribution of the resist film formed on the wafer before the exposure by the exposure apparatus is acquired.
  • pattern exposure is performed on the wafer on which the resist film is formed.
  • the resist film after the pattern exposure is heat-treated.
  • the film thickness distribution of the resist film after the heat treatment is acquired, and the film thickness difference data is calculated from the film thickness distribution before the exposure and the film thickness distribution after the heat treatment.
  • the line width (estimated line width) corresponding to the film thickness difference data is calculated in the plane of the wafer by referring to the line width correlation data table.
  • the resist film is heat-treated again.
  • the conditions for this heat treatment are set so that the heating temperature in the region where the estimated line width is large is higher than the heating temperature in the other region. Then, the resist film that has been heat-treated again is developed.
  • the heat treatment after exposure is performed so that the treatment results are uniform within the substrate surface, and the line width is a surface.
  • a uniform resist pattern is formed on the substrate.
  • One aspect of the present disclosure is a substrate processing apparatus for processing a substrate, which includes a heat treatment unit that heat-treats the substrate, an imaging unit that images the substrate, and a control unit, and the control unit is the substrate.
  • the adjustment process is configured to execute an adjustment process for adjusting the processing conditions for the above, and the adjustment process is a pre-exposure imaging step of controlling the imaging unit so that an unexposed adjustment substrate on which a resist film is formed is imaged.
  • the heat treatment unit is controlled so that the heat treatment is performed on the adjustment substrate that has been subjected to a uniform exposure process that exposes each region of the substrate surface with a constant exposure amount.
  • the heat treatment condition determination step for determining the above is included.
  • At least the heat treatment after exposure can be performed so that the treatment results are uniform in the substrate surface, and the line width Can form a uniform resist pattern on the substrate in the plane.
  • a series of processes are performed in order to form a predetermined resist pattern on a semiconductor wafer (hereinafter referred to as "wafer").
  • the series of processes includes, for example, a resist coating process of supplying a resist solution onto a wafer to form a resist film, and an exposure process of exposing the resist film to a predetermined pattern.
  • the series of treatments include a heat treatment (PEB (Post Exposure Bake) treatment) for promoting a chemical reaction in the resist film after exposure, a development treatment for developing the exposed resist film, and the like.
  • PEB Post Exposure Bake
  • the temperature of the wafer in the PEB treatment has a great influence on the line width of the resist pattern finally formed on the wafer. Further, the resist pattern is required to have its line width uniformly formed in the plane. Therefore, the heat treatment apparatus that performs the PEB treatment is provided with a plurality of heating regions, and different temperatures can be set for each heating region. Conventionally, in setting the temperature of each heating region, a series of resist pattern forming treatments are actually performed on the test wafer, the line width of the resist pattern is measured for each region, and the temperature of each heating region is measured based on the measurement result. Was set.
  • the technique according to the present disclosure among the treatments performed on the substrate for forming the resist pattern, at least the heat treatment after exposure is performed so that the treatment results are uniform in the substrate surface, and the line width is obtained. Allows the formation of a uniform resist pattern in the plane.
  • FIG. 1 is an explanatory diagram showing an outline of the internal configuration of the substrate processing apparatus 1 according to the first embodiment.
  • 2 and 3 are a front view and a rear view showing an outline of the internal configuration of the substrate processing device 1, respectively.
  • the substrate processing apparatus 1 includes, for example, a cassette station 2 in which a cassette C is carried in and out of the outside, and a plurality of various processing units for performing a predetermined process such as resist coating process and PEB. It has a station 3 and.
  • the substrate processing device 1 has a configuration in which the cassette station 2, the processing station 3, and the interface station 5 that transfers the wafer W between the exposure device 4 adjacent to the processing station 3 are integrally connected. ing. Further, the substrate processing device 1 has a control unit 6 that controls the substrate processing device 1.
  • the cassette station 2 is divided into, for example, a cassette loading / unloading section 10 and a wafer transport section 11.
  • the cassette loading / unloading section 10 is provided at the end of the substrate processing device 1 on the negative direction in the Y direction (left direction in FIG. 1).
  • the cassette loading / unloading section 10 is provided with a cassette mounting table 12.
  • a plurality of, for example, four mounting plates 13 are provided on the cassette mounting table 12.
  • the mounting plates 13 are provided side by side in a row in the horizontal X direction (vertical direction in FIG. 1).
  • the cassette C can be mounted on these mounting plates 13 when the cassette C is carried in and out of the substrate processing device 1.
  • the wafer transfer unit 11 is provided with a wafer transfer unit 21 that is movable on a transfer path 20 extending in the X direction.
  • the wafer transfer unit 21 is also movable in the vertical direction and around the vertical axis ( ⁇ direction), and the cassette C on each mounting plate 13 and the transfer unit of the third block G3 of the processing station 3 described later. Wafer W can be conveyed between them.
  • the processing station 3 is provided with a plurality of blocks G1, G2, G3, and G4 having various units, for example, the first to fourth blocks.
  • a first block G1 is provided on the front side of the processing station 3 (negative direction side in the X direction in FIG. 1), and a second block G1 is provided on the back side (positive direction side in the X direction in FIG. 1) of the processing station 3.
  • Block G2 is provided.
  • a third block G3 is provided on the cassette station 2 side of the processing station 3 (negative direction side in the Y direction in FIG. 1), and the interface station 5 side of the processing station 3 (positive direction side in the Y direction in FIG. 1). Is provided with a fourth block G4.
  • a plurality of liquid treatment units for example, a development processing unit 30 as a development processing unit for developing the wafer W, and a resist liquid are applied to the wafer W to form a resist film.
  • the resist coating units 31 to be processed are arranged in this order from the bottom.
  • the development processing unit 30 and the resist coating unit 31 are arranged side by side in the horizontal direction.
  • the number and arrangement of the developing processing unit 30 and the resist coating unit 31 can be arbitrarily selected.
  • spin coating is performed, for example, by applying a predetermined processing liquid on the wafer W.
  • the processing liquid is discharged onto the wafer W from the coating nozzle, and the wafer W is rotated to diffuse the processing liquid on the surface of the wafer W.
  • the configuration of the developing processing unit 30 will be described later.
  • a heat treatment unit 40 as a heat treatment unit that performs heat treatment such as heating and cooling of the wafer W and a peripheral exposure unit 41 that exposes the outer peripheral portion of the wafer W are arranged in the vertical direction. They are arranged side by side in the horizontal direction. The number and arrangement of the heat treatment unit 40 and the peripheral exposure unit 41 can also be arbitrarily selected. The configuration of the heat treatment unit 40 will be described later.
  • a plurality of delivery units 50 are provided in the third block G3. Further, the fourth block G4 is provided with a plurality of delivery units 60, and a defect inspection unit 61 is provided on the plurality of delivery units 60. The configuration of the defect inspection unit 61 will be described later.
  • a wafer transfer region D is formed in a region surrounded by the first block G1 to the fourth block G4.
  • a wafer transfer unit 70 is arranged in the wafer transfer area D.
  • the wafer transfer unit 70 has, for example, a transfer arm 70a that can move in the Y direction, the front-rear direction, the ⁇ direction, and the vertical direction.
  • the wafer transfer unit 70 moves in the wafer transfer area D and transfers the wafer W to predetermined units in the surrounding first block G1, second block G2, third block G3, and fourth block G4. it can.
  • a plurality of wafer transfer units 70 are arranged one above the other as shown in FIG. 3, for example, and the wafer W can be transferred to predetermined units having the same height of the blocks G1 to G4, for example.
  • a shuttle transfer unit 71 that linearly conveys the wafer W between the third block G3 and the fourth block G4 is provided.
  • the shuttle transport unit 71 is linearly movable in the Y direction of FIG. 3, for example.
  • the shuttle transfer unit 71 moves in the Y direction while supporting the wafer W, and the wafer W is located between the transfer unit 50 of the third block G3 and the transfer unit 60 of the fourth block G4 having the same height. Can be transported.
  • a wafer transfer unit 72 is provided on the X-direction positive side of the third block G3.
  • the wafer transfer unit 72 has, for example, a transfer arm 72a that can move in the front-rear direction, the ⁇ direction, and the up-down direction.
  • the wafer transfer unit 72 can move up and down while supporting the wafer W to transfer the wafer W to each transfer unit 50 in the third block G3.
  • the interface station 5 is provided with a wafer transfer unit 73 and a transfer unit 74.
  • the wafer transfer unit 73 has, for example, a transfer arm 73a that can move in the Y direction, the ⁇ direction, and the vertical direction.
  • the wafer transfer unit 73 can, for example, support the wafer W on the transfer arm 73a and transfer the wafer W between each transfer unit 60, the transfer unit 74, and the exposure apparatus 4 in the fourth block G4.
  • the control unit 6 described above is, for example, a computer and has a program storage unit (not shown).
  • the program storage unit stores a program that controls the operation of drive systems such as the various processing units and transfer units described above, and controls the processing of the wafer W, including the processing condition adjustment processing in the substrate processing apparatus 1. ..
  • the program may be recorded on a computer-readable storage medium H and may be installed on the control unit 6 from the storage medium H.
  • the developing processing unit 30 has a processing container 100 whose inside can be sealed.
  • a wafer W carry-in outlet (not shown) is formed on the side surface of the processing container 100 on the wafer transfer unit 70 side, and an open / close shutter (not shown) is provided at the carry-in outlet.
  • a spin chuck 110 for holding and rotating the wafer W is provided in the central portion of the processing container 100.
  • the spin chuck 110 has a horizontal upper surface, and for example, a suction port (not shown) for sucking the wafer W is provided on the upper surface. By suction from this suction port, the wafer W can be sucked and held on the spin chuck 110.
  • a chuck drive unit 111 equipped with a motor or the like is provided below the spin chuck 110.
  • the spin chuck 110 can be rotated to a predetermined speed by the chuck drive unit 111.
  • the chuck drive unit 111 is provided with a lifting drive source such as a cylinder, and the spin chuck 110 can be raised and lowered.
  • a cup 112 that receives and collects the liquid scattered or dropped from the wafer W is provided.
  • An exhaust pipe 113 for discharging the recovered liquid and an exhaust pipe 114 for evacuating the atmosphere inside the cup 112 and exhausting the collected liquid are connected to the lower surface of the cup 112.
  • a rail 120 extending along the Y direction is formed on the X-direction negative direction (downward direction in FIG. 5) side of the cup 112.
  • the rail 120 is formed, for example, from the outside of the cup 112 on the negative direction in the Y direction (left direction in FIG. 5) to the outside on the positive direction in the Y direction (right direction in FIG. 5).
  • An arm 121 is attached to the rail 120.
  • the arm 121 supports a coating nozzle 122 that supplies a developing solution onto the wafer W.
  • the arm 121 is movable on the rail 120 by the nozzle drive unit 123 shown in FIG.
  • the coating nozzle 122 can move from the standby portion 124 installed on the outside of the cup 112 on the positive side in the Y direction to the upper part of the center of the wafer W in the cup 112, and further on the wafer W of the wafer W. Can move in the radial direction.
  • the arm 121 can be raised and lowered by the nozzle driving unit 123, and the height of the coating nozzle 122 can be adjusted.
  • a supply pipe 125 for supplying a developing solution to the coating nozzle 122 is connected to the coating nozzle 122.
  • the supply pipe 125 communicates with the developer supply source 126 that stores the developer inside. Further, the supply pipe 125 is provided with a supply equipment group 127 including a valve for controlling the flow of the developing solution, a flow rate adjusting unit, and the like.
  • the structure of the resist coating unit 31 is the same as the structure of the development processing unit 30 described above. However, the processing liquid supplied from the coating nozzle differs between the developing processing unit 30 and the resist coating unit 31.
  • 6 and 7 are a vertical sectional view and a horizontal sectional view showing an outline of the configuration of the heat treatment unit 40, respectively.
  • the heat treatment unit 40 includes a heating unit 131 for heat-treating the wafer W and a cooling unit 132 for cooling the wafer W in the housing 130.
  • a heating unit 131 for heat-treating the wafer W and a cooling unit 132 for cooling the wafer W in the housing 130.
  • a cooling unit 132 for cooling the wafer W in the housing 130.
  • carry-in / out outlets 133 for carrying in / out the wafer W are formed on both side surfaces in the vicinity of the cooling portion 132 of the housing 130.
  • the heating unit 131 is a hot plate accommodating unit that is located on the upper side and is movable up and down, and is located on the lower side and is integrated with the lid body 140 to form a processing chamber S. It is equipped with 141.
  • the lid 140 has a substantially tubular shape with an open lower surface, and covers the upper surface, which is the surface to be processed, of the wafer W placed on the hot plate 142 described later.
  • An exhaust portion 140a is provided at the center of the upper surface of the lid 140.
  • the atmosphere in the processing chamber S is exhausted from the exhaust unit 140a.
  • the lid body 140 is provided with a temperature sensor 143 which is a temperature measuring unit for measuring the temperature of the lid body 140.
  • the temperature sensor 143 is provided at the end of the lid 140, but it may be provided at the center of the lid 140 or the like.
  • a wafer W is placed in the center of the hot plate accommodating portion 141, and a hot plate 142 for heating the placed wafer W is provided.
  • the hot plate 142 has a thick substantially disk shape, and a heater 150 for heating the upper surface of the hot plate 142, that is, the mounting surface of the wafer W is provided inside the hot plate 142.
  • the heater 150 for example, an electric heater is used. The configuration of the hot plate 142 will be described later.
  • the hot plate accommodating portion 141 is provided with an elevating pin 151 that penetrates the hot plate 142 in the thickness direction.
  • the elevating pin 151 can be elevated and lowered by an elevating drive unit 152 such as a cylinder, and can project to the upper surface of the hot plate 142 to transfer the wafer W to and from the cooling plate 170 described later.
  • the hot plate accommodating portion 141 includes, for example, an annular holding member 160 that accommodates the hot plate 142 and holds the outer peripheral portion of the hot plate 142, and a substantially tubular support that surrounds the outer peripheral portion of the holding member 160. It has a ring 161.
  • the cooling unit 132 adjacent to the heating unit 131 is provided with, for example, a cooling plate 170 on which the wafer W is placed and cooled.
  • the cooling plate 170 has a substantially rectangular flat plate shape, and the end face on the heating portion 131 side is curved in an arc shape.
  • a cooling member such as a Peltier element is built in the cooling plate 170, and the cooling plate 170 can be adjusted to a predetermined set temperature.
  • the cooling plate 170 is supported by a support arm 171 as shown in FIG. 6, for example, and the support arm 171 is attached to a rail 172 extending in the X direction on the heating unit 131 side.
  • the cooling plate 170 can be moved on the rail 172 by a drive mechanism 173 attached to the support arm 171. As a result, the cooling plate 170 can move to the upper part of the hot plate 142 on the heating unit 131 side.
  • the cooling plate 170 is formed with two slits 174 along the X direction in FIG.
  • the slit 174 is formed from the end surface of the cooling plate 170 on the heating portion 131 side to the vicinity of the central portion of the cooling plate 170.
  • the slit 174 prevents interference between the cooling plate 170 that has moved to the heating unit 131 side and the elevating pin 151 on the hot plate 142.
  • an elevating pin 175 is provided below the cooling plate 170 located in the cooling unit 132.
  • the elevating pin 175 can be elevated by the elevating drive unit 176.
  • the elevating pin 175 rises from below the cooling plate 170, passes through the slit 174, projects above the cooling plate 170, and is between, for example, a wafer transfer unit 70 that enters the inside of the housing 130 from the carry-in outlet 133. Wafer W can be delivered.
  • FIG. 8 is a plan view showing an outline of the configuration of the hot plate 142.
  • the hot plate 142 is divided into a plurality of, for example, five hot plate regions (hereinafter, may be referred to as “channels”) R1 to R5.
  • the hot plate 142 is divided into, for example, a circular channel R1 located at the center when viewed from a plane, and channels R2 to R5 obtained by dividing the circumference of the channel R1 into four equal parts in an arc shape.
  • a heater 180 is individually built in each channel R1 to R5 of the hot plate 142, and each channel R1 to R5 can be individually heated.
  • the calorific value of the heaters 180 of each channel R1 to R5 is adjusted by, for example, the temperature control unit 181.
  • the temperature control unit 181 can adjust the calorific value of each heater 180 to control the temperature of each channel R1 to R5 to a predetermined set temperature.
  • the temperature setting in the temperature control unit 181 is performed by the control unit 6.
  • the defect inspection unit 61 has a casing 190 as shown in FIGS. 9 and 10.
  • a mounting table 200 on which the wafer W is mounted is provided in the casing 190.
  • the mounting table 200 can be freely rotated and stopped by a rotation driving unit 201 such as a motor.
  • a guide rail 202 extending from one end side (negative direction side in the X direction in FIG. 10) to the other end side (positive direction side in the X direction in FIG. 10) in the casing 190 is provided. ..
  • the mounting table 200 and the rotary drive unit 201 are provided on the guide rail 202, and can be moved along the guide rail 202 by the drive unit 203.
  • An imaging unit 210 is provided on the side surface of the casing 190 on the other end side (the positive direction side in the X direction in FIG. 10).
  • a wide-angle CCD camera is used as the image pickup unit 210.
  • a half mirror 211 is provided near the center of the upper part of the casing 190.
  • the half mirror 211 is provided at a position facing the image pickup unit 210 in a state in which the mirror surface is inclined 45 degrees upward from the state in which the mirror surface faces vertically downward toward the image pickup section 210.
  • An illumination unit 212 is provided above the half mirror 211.
  • the half mirror 211 and the illumination unit 212 are fixed to the upper surface inside the casing 190.
  • the illumination from the illumination unit 212 passes through the half mirror 211 and is illuminated downward. Therefore, the light reflected by the object below the illumination unit 212 is further reflected by the half mirror 211 and taken into the image pickup unit 210. That is, the imaging unit 210 can image an object in the irradiation region of the illumination unit 212.
  • the wafer transfer unit 21 takes out the wafer W from the cassette C on the cassette mounting table 12 and transfers it to the transfer unit 50 of the processing station 3.
  • the wafer W is transferred by the wafer transfer unit 70 to the heat treatment unit 40 of the second block G2 and subjected to temperature control processing. After that, the wafer W is conveyed to the resist coating unit 31 of the first block G1 to form a resist film on the wafer W. After that, the wafer W is transferred to the heat treatment unit 40 and pre-baked (PAB: Pre-Applied Bake). In the pre-baking treatment, the subsequent PEB treatment, and the post-baking treatment, the same heat treatment is performed. However, the heat treatment units 40 used for each heat treatment are different from each other.
  • the wafer W is conveyed to the peripheral exposure unit 41 and subjected to peripheral exposure processing.
  • the wafer W is conveyed to the exposure apparatus 4 and exposed in a predetermined pattern.
  • the wafer W is transferred to the heat treatment unit 40 and subjected to PEB treatment. After that, the wafer W is transferred to, for example, the development processing unit 30 for development processing. After the development process is completed, the wafer W is transferred to the heat treatment unit 40 and post-baked. Then, the wafer W is conveyed to the defect inspection unit 61, and the wafer W is inspected for defects. In the defect inspection, inspections such as whether there are scratches or foreign matter adhered are performed. After that, the wafer W is conveyed to the cassette C on the cassette mounting table 12, and a series of photolithography steps is completed.
  • FIG. 11 is a flowchart for explaining the adjustment process of the processing conditions of the PEB process.
  • FIG. 12 is a conceptual diagram of the temperature distribution estimation method.
  • the set temperature of each channel R1 to R5 of the hot plate 142 during the PEB process is adjusted.
  • the adjustment process is performed, for example, when the substrate processing device 1 is introduced, when the substrate processing device 1 is maintained, and the like.
  • step S1 the adjustment wafer W (hereinafter, referred to as “adjustment wafer W”) is carried in (step S1). Specifically, in the adjustment process, the operator places the cassette C containing the adjustment wafer W on the cassette mounting table 12, so that the adjustment wafer W is taken out from the cassette C and the next step is performed. Is transported to the resist coating unit.
  • the adjusting wafer W is a bare wafer.
  • a resist film is formed on the adjusting wafer W (step S2). Specifically, in the resist coating unit 31, a resist film is formed on the adjusting wafer W under predetermined coating treatment conditions.
  • PAB processing process After that, PAB processing is performed on the adjustment wafer W (step S3). Specifically, the adjusting wafer W on which the resist film is formed is conveyed to the heat treatment unit 40 for PAB processing, and PAB processing is performed under predetermined PAB processing conditions.
  • the resist film is formed and the adjusting wafer W is imaged before the uniform exposure process described later (step S4).
  • the adjustment wafer W subjected to the PAB treatment is conveyed to the defect inspection unit 61, and the surface thereof is imaged by the imaging unit 210.
  • the wafer W in the imaging result F1 is divided into, for example, 437 regions, and in each region, the average value of the brightness values of R (red), G (green), and B (blue) is average. Is calculated.
  • a table is created in which the coordinates of the area and the average value of the brightness values of each of R, G, and B are associated with each other.
  • captured images hereinafter, referred to as “pre-exposure captured images” I1 are acquired for each of R, G, and B.
  • the adjustment wafer W is subjected to a uniform exposure process (step S5). Specifically, the adjustment wafer W imaged in the pre-exposure imaging step of step S4 is conveyed to the exposure apparatus 4, and a uniform exposure process is performed in which each region of the wafer surface is exposed with a constant exposure amount. In the exposure apparatus 4, during the uniform exposure process, for example, exposure is performed for each exposure region with the same exposure intensity and the same exposure time without using a reticle.
  • the exposure amount of each region of the wafer surface in the uniform exposure process is less than the exposure amount at the time of actual processing, that is, at the time of mass production of the resist pattern, and specifically, it is set to 1/2 of the exposure amount at the time of actual processing. ..
  • PEB processing process After the uniform exposure step, the adjustment wafer W is subjected to PEB processing (step S6). Specifically, the adjusting wafer W that has undergone uniform exposure processing is conveyed to the heat treatment unit 40 for PEB processing, which is the object for adjusting the processing conditions, and the PEB processing is performed under the currently set PEB processing conditions. It is said.
  • the image of the adjusting wafer W is taken again (step S7). Specifically, the PEB-processed and undeveloped adjustment wafer W is conveyed to the defect inspection unit 61, and the surface thereof is imaged by the imaging unit 210. At this time, since it is undeveloped, what is imaged by the imaging unit 210 is not the resist pattern but the latent image formed on the resist film on the wafer W. Then, based on the imaging result F2, captured images (hereinafter, referred to as “post-PEB captured images”) I2 are acquired for each of R, G, and B.
  • post-PEB captured images captured images
  • the control unit 6 estimates the in-plane temperature distribution of the adjustment wafer W during the PEB process based on the imaging result in the pre-exposure imaging step and the imaging result in the PEB post-exposure imaging step (step S8). ). Specifically, the control unit 6 determines the adjustment wafer W at the time of PEB processing based on the color information of the pre-exposure image I1 acquired in the pre-exposure image capture step and the color information of the post-PEB image I2. Estimate the in-plane temperature distribution.
  • the color information is luminance information of a specific wavelength (color).
  • control unit 6 first receives the pre-exposure image I1 of R, G and B acquired in the pre-exposure imaging step and the post-PEB image of R, G and B acquired in the post-PEB imaging step. Shading correction Sh is performed on each of the captured image I2.
  • the shading correction Sh can remove luminance unevenness caused by imaging conditions (sensitivity of the image sensor, optical system, moving speed of the mounting table 200, etc.).
  • the control unit 6 determines the difference ⁇ of the brightness values between the pre-exposure image I1 ′ and the post-PEB image I2 ′ that have been shade-corrected for each R, G, and B, and for each pixel in the captured image. calculate.
  • the control unit 6 is in-plane of the adjustment wafer W during PEB processing from the calibration curve Lr showing the relationship between the difference ⁇ r for R and the temperature and the difference ⁇ r for R calculated for each pixel. Obtain the temperature distribution Pr. Further, the control unit 6 is in-plane of the adjustment wafer W during PEB processing from the calibration curve Lg showing the relationship between the difference ⁇ g for G and the temperature and the difference ⁇ g for G calculated for each pixel. Obtain the temperature distribution Pg. Further, the control unit 6 uses the calibration curve Lb showing the relationship between the difference ⁇ b for B and the temperature and the difference ⁇ b for B calculated for each pixel to determine the in-plane temperature of the adjustment wafer W during PEB processing. Obtain the distribution Pb.
  • the calibration curves Lr, Lg, and Lb have been obtained in advance.
  • the acquisition method will be described later.
  • the control unit 6 selects one of the three acquired in-plane temperature distributions Pr, Pg, and Pb of the adjustment wafer W during PEB processing.
  • the in-plane temperature distribution of the adjustment wafer W during the PEB treatment which is acquired based on the captured image of the wavelength, that is, the color corresponding to the film thickness of the resist film, is selected. More specifically, when the resist film is thick, the in-plane temperature distribution Pr acquired based on the captured image of R having a long wavelength is selected, and when the resist film is thin, it is based on the captured image of B having a short wavelength.
  • the acquired in-plane temperature distribution Pb is selected.
  • control unit 6 estimates the in-plane temperature distribution of the adjustment wafer W during the PEB process based on the captured image of the wavelength corresponding to the film thickness of the resist film.
  • the in-plane temperature distribution based on the captured image of other wavelengths is selected. Acquisition may be omitted.
  • the control unit 6 determines the processing conditions for the PEB processing based on the estimation result of the in-plane temperature distribution of the adjustment wafer W during the PEB processing (step S9). Specifically, the control unit 6 determines the processing conditions for the PEB processing based on the in-plane temperature distribution of the adjusting wafer W during the PEB processing selected in the temperature distribution estimation step. For example, the control unit 6 determines the set temperature of each of the channels R1 to R5 of the hot plate 142 based on the following equation (1), and more specifically, from the reference temperature determined for each resist film type. The amount of deviation (offset amount) is determined for each channel of the hot plate 142.
  • O is a matrix showing the offset amount of each channel of the hot plate 142
  • T is a matrix showing the in-plane temperature distribution of the adjustment wafer W during PEB processing
  • A is a transformation matrix. ..
  • the resist film formed on the adjusting wafer W is removed (step S10).
  • the adjusting wafer W imaged in the post-PEB imaging step is conveyed to the resist coating unit 31 as a removing unit, and the thinner liquid is adjusted from a discharge nozzle (not shown) that discharges the thinner liquid. It is supplied to W, and the resist film on the adjusting wafer W is peeled off.
  • a unit for removal treatment may be provided separately from the resist coating unit 31 and the like.
  • step S11 the image of the adjusting wafer W is taken again (step S11). Specifically, the adjustment wafer W from which the resist film has been removed is conveyed to the defect inspection unit 61, the surface of which is imaged by the imaging unit 210, and a substrate image showing the state of the wafer surface is acquired.
  • control unit 6 determines whether or not the adjustment wafer W can be reused based on the substrate image acquired in the imaging step after removal (step S12). Specifically, the control unit 6 compares the substrate image of the adjustment wafer W acquired in the removal imaging step with the substrate image of the unprocessed bare wafer acquired in advance, and adjusts based on the comparison result. It is determined whether or not the wafer W for use is reusable.
  • step S13 If it is not reusable (in the case of step S12 and NO), the control unit 6 notifies that it cannot be reused (step S13). Specifically, the control unit 6 causes, for example, display a warning to the effect that the adjustment wafer W cannot be reused on the display unit (not shown).
  • the control unit 6 carries out the adjustment wafer W (step S14). Specifically, the adjusting wafer W is returned to the original cassette C on the cassette mounting table 12 by the wafer transfer unit 21. If it is not reusable, the adjusting wafer may be transported to the disposal cassette C separately placed on the cassette mounting table 12. As a result, the adjustment process of the processing conditions of the PEB process is completed. In the actual processing after the adjustment processing of the processing conditions of the PEB processing described above is completed, the PEB processing is performed under the processing conditions determined by the adjustment processing.
  • FIG. 13 is a flowchart for explaining a method of acquiring the calibration curves Lr, Lg, and Lb.
  • the one used for acquiring the calibration curve is determined according to user input or the like (step). S21).
  • the calibration curve acquisition wafer W (hereinafter, referred to as “calibration curve acquisition wafer W”) is carried in in the same manner as in step S1.
  • the calibration curve acquisition wafer W is a bare wafer.
  • PAB processing process After that, the PAB process is performed on the calibration curve acquisition wafer W in the same manner as in step S3.
  • step S5 (Uniform exposure process) Next, in the same manner as in step S5, a uniform exposure process is performed on the calibration curve acquisition wafer W.
  • PEB processing process After the uniform exposure step, PEB processing is performed on the calibration curve acquisition wafer W in the same manner as in step S6.
  • the PEB treatment is performed in the heat treatment unit 40 determined in step S21.
  • step S7 the image of the calibration curve acquisition wafer W is performed.
  • step S14 the calibration curve acquisition wafer W is carried out.
  • Each step from the carry-in step of step S1 to the carry-out step of step S14 is performed on each of a plurality of (N) calibration curve acquisition wafers W.
  • the temperature of the hot plate 142 in the PEB processing step is different for each wafer W for obtaining a calibration curve.
  • the temperatures of the channels R1 to R5 of the hot plate 142 are the same.
  • the calibration curves Lr, Lg, and Lb are calculated based on the captured images acquired in the pre-exposure imaging step and the captured images acquired in the post-PEB imaging step for the plurality of calibration curve acquisition wafers W. Will be done. Specifically, in the case of the calibration line Lr, first, the average R brightness in the wafer surface in the image captured in the pre-exposure imaging step is set to the gray value Ir1 and the gray value Ir1 and the in-wafer surface in the image captured in the post-PEB imaging step.
  • the calibration curves Lg and Lb are also obtained in the same manner as the calibration curve Lr.
  • the adjustment processing of the PEB processing conditions includes the pre-exposure imaging step of imaging the adjustment wafer W before the uniform exposure processing on which the resist film is formed, and the pre-exposure imaging step.
  • the PEB processing step of performing PEB processing on the adjusting wafer W subjected to the uniform exposure processing the post-PEB imaging step of imaging the PEB-treated adjusting wafer W, and the imaging result in the pre-exposure imaging step.
  • the PEB processing condition determination step of determining the processing condition of the PEB processing is included. Therefore, in the present embodiment, the PEB treatment is actually performed under the currently set processing conditions instead of the in-plane temperature distribution of the line width of the resist pattern, and the adjustment wafer W estimated from the imaging result after the processing.
  • the processing conditions for the PEB treatment are determined based on the in-plane temperature distribution. Therefore, according to the present embodiment, the PEB treatment can be performed so that the treatment result (that is, the temperature of the wafer W) becomes uniform in the wafer surface. Therefore, it is possible to form a resist pattern having higher in-plane uniformity of line width.
  • the temperature of the wafer W in the wafer surface can be made uniform at the reference temperature set for each resist film type. Therefore, it is possible to suppress variations in the temperature of the wafer W between the heat treatment units 40 for PEB processing.
  • the control unit 6 obtains wavelengths corresponding to the film thickness of the resist film from the in-plane temperature distributions Pr, Pg, and Pb of the three acquired adjustment wafers W during PEB processing.
  • the in-plane temperature distribution of the adjustment wafer W at the time of PEB processing acquired based on the captured image of the above is selected. That is, the control unit 6 estimates the in-plane temperature distribution of the adjustment wafer W during the PEB process based on the captured image for one wavelength according to the film thickness of the resist film. Therefore, the in-plane temperature distribution during the PEB treatment can be estimated more accurately, and the PEB treatment result can be made more uniform in the wafer plane.
  • control unit 6 selects one of the three in-plane temperature distributions Pr, Pg, and Pb of the adjustment wafer W during PEB processing, the following may be performed.
  • a temperature sensor is provided for the hot plate 142, and an in-plane temperature distribution in which the measurement result of the temperature sensor and the estimated temperature of the pixels corresponding to the arrangement position of the temperature sensor are closest to each other is selected. You may do so.
  • control unit 6 estimates the in-plane temperature distribution of the adjustment wafer W during one PEB process based on all the captured images of R, G, and B by using the following equation (2). It may be.
  • control unit 6 may use the following equation (3) to estimate the in-plane temperature distribution of the adjustment wafer W during PEB processing.
  • the exposure amount of each region of the wafer surface in the uniform exposure process is less than the exposure amount in the actual process, for example, halved. Therefore, when the PEB treatment is performed during the adjustment processing of the processing conditions of the PEB treatment, the amount of change in the film thickness of the resist film before and after the PEB treatment becomes large due to the difference in the PEB treatment result. As a result, the amount of change in brightness in the captured image before and after the PEB processing becomes large due to the difference in the PEB processing result. That is, even if the difference in the PEB processing result is slight, the difference in brightness between the pre-exposure image and the post-PEB image is large.
  • the in-plane temperature distribution of the adjustment wafer W during the PEB process can be estimated with high accuracy based on the pre-exposure image and the post-PEB image. It should be noted that 1/2 of the exposure amount during the actual processing corresponds to the exposure amount applied to the edge portion of the resist pattern.
  • the adjustment wafer W from which the resist film has been removed can be reused based on the substrate image acquired in the imaging step after removal. Therefore, the consumption of the adjustment wafer W can be suppressed without impairing the adjustment accuracy of the processing conditions.
  • a bare wafer is used as the adjustment wafer W. Therefore, the processing conditions for the PEB processing can be appropriately determined.
  • FIG. 14 is a flowchart for explaining the processing for adjusting the processing conditions according to the second embodiment.
  • the processing conditions for the PEB treatment are adjusted, whereas in the present embodiment, the processing conditions for the development processing are adjusted.
  • the processing conditions for the development process are adjusted, for example, after the adjustment of the processing conditions for the PEB process. Since the adjustment of the processing conditions for the PEB processing is performed when the substrate processing apparatus 1 is introduced as described above, the processing conditions for the development processing are also adjusted at the same timing. However, it is possible to adjust the processing conditions of the developing process without adjusting the processing conditions of the PEB processing.
  • step S1 In the process of adjusting the processing conditions of the developing process, first, the adjusting wafer W is carried in as in step S1 described above.
  • PAB processing process After that, the PAB process is performed on the adjustment wafer W in the same manner as in step S3 described above (step S3).
  • step S5 (Uniform exposure process)
  • the adjustment wafer W is subjected to a uniform exposure process. Even in the adjustment process of the processing conditions of the development process, the exposure amount of each region of the wafer surface in the uniform exposure process is less than the exposure amount in the actual process, for example, halved.
  • PEB processing process After the uniform exposure step, PEB processing is performed on the adjusting wafer W in the same manner as in step S6 described above. However, if the processing conditions for the PEB treatment have been adjusted, the PEB treatment is performed under the adjusted PEB processing conditions.
  • the adjustment wafer W is subjected to a developing process (step S31). Specifically, the adjustment wafer W subjected to the PEB treatment is conveyed to the development processing unit 30 whose processing conditions are to be adjusted, and the development processing is performed under the currently set development processing conditions.
  • step S32 the image of the adjusting wafer W is taken again (step S32). Specifically, the adjustment wafer W that has undergone development processing is conveyed to the defect inspection unit 61, and the surface thereof is imaged by the image pickup unit 210, and the image image (hereinafter referred to as “development image image”) I3. Is obtained.
  • the control unit 6 has a film thickness of the resist film after the development process on the adjusting wafer W based on the imaging result in the post-development imaging step (hereinafter, referred to as “resist film residual film thickness”).
  • the in-plane distribution of is estimated (step S33). Specifically, the control unit 6 calculates or estimates the in-plane distribution of the residual film thickness of the resist film of the adjusting wafer W based on the color information of the developed image I3 for B (blue). More specifically, the control unit 6 calculates the residual film thickness of the resist film based on the brightness and the calibration curve Ldev acquired in advance for each pixel in the developed image I3 after development for B.
  • the in-plane distribution of the residual film thickness is acquired.
  • the calibration curve Ldev shows the relationship between the brightness of the developed image I3 for B and the residual film thickness of the resist film. The method of acquiring the calibration curve Ldev will be described later.
  • the in-plane distribution of the remaining film thickness amount was calculated based on the captured image of B, but the in-plane distribution of the remaining film thickness amount was calculated based on the captured image of G and the captured image of R.
  • the distribution may be calculated.
  • the estimation may be performed based on the captured image of the wavelength corresponding to the film thickness of the resist film.
  • the control unit 6 determines the processing conditions for the development process based on the estimation result of the in-plane distribution of the residual film thickness of the resist film (step S34). Specifically, the control unit 6 determines and corrects the supply time of the developer as a processing condition for the developing process, for example, based on the in-plane distribution of the residual film thickness of the resist film on the adjusting wafer W. .. More specifically, in the adjustment wafer W, when the residual film thickness of the resist film is close to the target amount at the center of the wafer and is appropriate and larger than the target amount at the outer periphery of the wafer, the control unit 6 moves to the outer periphery of the wafer.
  • the processing conditions of the developing process are determined so that the supply of the developing solution is added.
  • the length ⁇ t of the additional supply time of the developer to the outer peripheral portion of the wafer is calculated from, for example, the correction curve Lamd showing the relationship between the supply time of the developer and the amount of the remaining film thickness.
  • the correction curve Lamd has been acquired in advance. The acquisition method will be described later.
  • the calculated length ⁇ t of the additional supply time of the developer to the outer peripheral portion of the wafer that is, the determined processing conditions for the developing process are stored in the storage unit (not shown), and during the subsequent actual processing, etc. It is used in the development process in.
  • steps S10 to S14 described above are performed, whereby the adjustment process of the processing conditions of the development process is completed.
  • FIG. 15 is a flowchart for explaining a method of acquiring the calibration curve Ldev and the correction curve Lamd.
  • step S41 When acquiring the calibration curve Ldev, first, among the plurality of development processing units 30, the one used for acquiring the calibration curve and the correction curve is determined according to user input or the like (step S41).
  • the wafer W for acquiring the calibration curve and the correction curve (hereinafter, referred to as “the wafer W for acquiring the calibration curve”) is carried in in the same manner as in step S1.
  • the calibration curve acquisition wafer W is also a bare wafer.
  • PAB processing process After that, the PAB process is performed on the calibration curve acquisition wafer W in the same manner as in step S3.
  • step S5 (Uniform exposure process) Next, in the same manner as in step S5, a uniform exposure process is performed on the calibration curve acquisition wafer W.
  • PEB processing process After the uniform exposure step, PEB processing is performed on the calibration curve acquisition wafer W in the same manner as in step S6.
  • step S31 the development process is performed on the calibration curve acquisition wafer W in the same manner as in step S31.
  • the developing process is performed in the developing process unit 30 determined in step S41, and the developing solution is supplied only to the central portion of the wafer from the coating nozzle 122 during spin coating of the developing solution.
  • step S32 the image of the calibration curve acquisition wafer W is performed. As a result, the captured image for at least B is acquired.
  • step S14 the calibration curve acquisition wafer W is carried out.
  • the residual film thickness of the resist film of the calibration curve acquisition wafer W is acquired (step S42). Specifically, for example, the calibration curve acquisition wafer W that has been subjected to PEB treatment is conveyed to an external film thickness measuring device (not shown), and the amount of residual film thickness of the resist film in the center of the wafer is measured. To. The residual film thickness amount may be measured by providing a film thickness measuring device in the substrate processing device 1 and using the film thickness measuring device.
  • the calibration curve Lpeb and the correction curve Lamd are calculated based on the captured images of the calibration curve acquisition wafer W acquired in the post-development imaging step for the plurality of calibration curve acquisition wafers W (step S43). ..
  • the explanatory variable is the B brightness in the tag number in the imaging step after development
  • the objective variable is the residual film amount of the resist film acquired in the residual film amount measurement step. An approximate curve of the remaining film thickness amount with respect to the B brightness value change amount is acquired, and this is used as the calibration curve Lpeb.
  • the explanatory variable is the supply time of the developer in the developing step
  • the objective variable is the residual film amount of the resist film acquired in the residual film amount measuring step, and the resist with respect to the supply time of the developing solution is used.
  • An approximate curve of the amount of residual film thickness of the film is acquired, and this is referred to as a correction curve Lamd.
  • the development process is actually performed under the currently set processing conditions, and the development is performed based on the in-plane distribution of the film thickness of the resist film after the development process estimated from the processing result.
  • the processing conditions for processing are determined. Therefore, according to the present embodiment, the development process can be performed so that the process result is uniform on the wafer surface. Therefore, it is possible to form a resist pattern having higher in-plane uniformity of line width.
  • the exposure amount of each region of the wafer surface in the uniform exposure process is less than the exposure amount in the actual process, for example, halved. Therefore, when the development process is performed during the process of adjusting the processing conditions of the development process, the film thickness of the resist film after the development process is significantly different due to the difference in the development process results. As a result, the brightness of the captured image after the development process is significantly different due to the difference in the development process result. That is, even if the difference in the development processing results is slight, the brightness in the developed image will be significantly different. Therefore, the in-plane distribution of the film thickness of the resist film after the development process can be estimated with high accuracy based on the image taken after the development.
  • FIG. 16 is a front view showing an outline of the internal configuration of the substrate processing apparatus 1a according to the third embodiment.
  • the uniform exposure process is performed by an external exposure device 4 adjacent to the substrate processing device 1 and performing exposure during the actual process.
  • the substrate processing device 1a has an exposure unit 62 independent of the exposure device 4. Then, the exposure unit 62 performs a uniform exposure process on the adjusting wafer W. With this configuration, the processing for adjusting the processing conditions can be completed in the substrate processing device 1 without using an external exposure device.
  • the exposure unit 62 is provided on, for example, the defect inspection unit 61 in the fourth block G4.
  • FIG. 17 is a vertical cross-sectional view showing an outline of the configuration of the heat treatment unit 40a included in the substrate processing apparatus according to the fourth embodiment.
  • the lid 140 is provided with a heater 140b as a temperature control mechanism for adjusting the temperature of the lid 140.
  • the conditions of the hot plate 142 at the time of PEB processing in the actual processing such as the offset amount of each channel of the hot plate 142 are adjusted, but only adjusting the conditions of the hot plate 142 is described above.
  • the wafer temperature during the PEB treatment may be lower or higher than the desired temperature as a whole.
  • the heater 140b that adjusts the temperature of the lid 140 as in the present embodiment, the temperature of the wafer W during the PEB treatment during the actual treatment can be set to a desired temperature. This is because the wafer W is affected by the radiant heat of the lid 140.
  • the temperature of the lid 140 during the PEB treatment may differ between the adjustment treatment of the hot plate conditions during the PEB treatment and the actual treatment. is there.
  • the temperature of the lid 140 during the PEB treatment can be made the same between the adjustment treatment and the actual treatment. Since the wafer W is affected by the radiant heat of the lid 140 as described above, the temperature of the lid 140 during the PEB treatment differs between the adjustment treatment and the actual treatment in the same case after the adjustment. It is possible to improve the in-plane uniformity of the PEB processing result during the actual processing.
  • each of the hot plates 142 determined by the adjustment processing that is, based on the processing conditions determined by the adjustment processing.
  • PEB processing is performed based on the offset amount of the channel.
  • the offset amount determined by the adjustment treatment is corrected and used based on the temperature measurement result of the lid 140 of the heat treatment unit 40 by the temperature sensor 143. This is because the wafer W is affected by the radiant heat of the lid 140 as described above.
  • the adjustment processing of the processing conditions of the PEB processing is performed when the substrate processing apparatus 1 is introduced or when the substrate processing apparatus 1 is maintained.
  • the execution timing of the adjustment processing of the processing conditions of the PEB processing is not limited to the above.
  • the control unit 6 may measure the film thickness of the resist film formed during the actual treatment, and start the adjustment processing of the processing conditions of the PEB treatment based on the measurement result. Specifically, when the measured variation in the film thickness of the resist film in the wafer surface or the average value of the film thickness in the wafer surface exceeds the threshold value, the processing conditions of the PEB process are adjusted. You may want to start.
  • the film thickness of the resist film can be measured as follows.
  • the wafer W on which the resist film is formed after the PEB treatment in the actual treatment is imaged by the imaging unit 210 of the defect inspection unit 61, and the film of the resist film is based on the image captured from the imaged result. Thickness can be measured / estimated.
  • the execution timing of the adjustment processing of the processing conditions of the PEB processing and the developing processing may be as follows. That is, for example, the control unit 6 may estimate the line width of the resist pattern formed during the actual processing, and start the adjustment processing of the processing conditions of the PEB processing and the developing processing based on the estimation result. .. Specifically, the processing condition adjustment process may be started when the estimated variation in the line width in the wafer plane or the average value of the line width in the wafer plane exceeds the threshold value. ..
  • the line width of the resist pattern can be estimated as follows.
  • the wafer W on which the resist pattern is formed after the development process in the actual processing is imaged by the imaging unit 210 of the defect inspection unit 61, and the resist pattern line is based on the image captured from the imaged image.
  • the width can be estimated. Further, when adjusting the processing conditions, the adjusting wafer W was placed on the cassette mounting table 12 in a state where the operator stored it in the cassette C, but it was stored in the container in the substrate processing device 1. May be good.
  • FIG. 18 is a front view showing an outline of the internal configuration of the substrate processing apparatus 1b according to the fifth embodiment.
  • the substrate processing apparatus 1b has an inspection unit 63.
  • the defect inspection unit 61 images the entire surface of the wafer W for inspection, whereas the inspection unit 63 images only the peripheral edge of the wafer W for inspection.
  • the control unit 6 executes the adjustment processing of the processing conditions of the peripheral exposure processing by the peripheral exposure unit 41. Further, the execution timing of the adjustment processing of the processing conditions of the peripheral exposure processing is determined as follows.
  • the peripheral portion of the wafer W is imaged by the imaging unit (not shown) of the inspection unit 63, and the adjustment processing of the processing conditions of the peripheral exposure processing is started based on the imaging result.
  • the peripheral exposure width by the peripheral exposure processing is estimated based on the imaging result, and when the estimated peripheral exposure width is abnormal, the processing condition adjustment processing of the peripheral exposure processing is started.
  • the processing condition adjustment process that starts based on the imaging result of the peripheral portion of the wafer W is not limited to the processing condition adjustment process of the peripheral exposure process, but is the adjustment process of the processing conditions of other processes for the peripheral edge portion of the wafer. You may.
  • EBR treatment a treatment for removing the film on the outer peripheral edge of the wafer W
  • edge coating treatment a treatment for covering only the peripheral edge of the wafer W.
  • a substrate processing device that processes a substrate.
  • a heat treatment section that heat-treats the substrate,
  • An imaging unit that images the substrate and Has a control unit
  • the control unit is configured to execute an adjustment process for adjusting the processing conditions for the substrate.
  • the adjustment process A pre-exposure imaging step that controls the imaging unit so that an unexposed adjustment substrate on which a resist film is formed is imaged.
  • a heat treatment step of controlling the heat treatment section so that the heat treatment is performed on the adjustment substrate that has been subjected to a uniform exposure process that exposes each region of the substrate surface with a constant exposure amount.
  • a temperature distribution estimation step for estimating the in-plane temperature distribution of the adjustment substrate during the heat treatment based on the imaging result in the pre-exposure imaging step and the imaging result in the post-heating imaging step.
  • a substrate processing apparatus including a heat treatment condition determining step of determining the heat treatment processing conditions based on the estimation result of the in-plane temperature distribution of the adjusting substrate. According to the above (1), the heat treatment is actually performed, and the heat treatment treatment conditions are determined based on the in-plane temperature distribution of the adjustment substrate estimated from the imaging result after the heat treatment. Therefore, according to the present embodiment, the heat treatment can be performed so that the treatment result (that is, the temperature of the substrate) becomes uniform in the surface of the substrate. Therefore, it is possible to form a resist pattern having higher in-plane uniformity of line width.
  • the substrate processing apparatus which has an exposure unit that performs the uniform exposure process, which is different from an external exposure apparatus that performs the exposure process during the actual process. According to the above (2), the processing for adjusting the processing conditions can be completed in the substrate processing apparatus without using an external exposure apparatus.
  • the in-plane temperature distribution of the adjustment substrate during the heat treatment is estimated based on the captured image of the wavelength according to the film thickness of the resist film, the above (1) to (1).
  • the substrate processing apparatus according to any one of 4). According to the above (5), the in-plane temperature distribution during the heat treatment can be estimated more accurately, and the heat treatment result can be made more uniform in the substrate surface.
  • the adjustment process After the post-heating imaging step, a development processing step of controlling the development processing unit so that the development processing is performed on the adjustment substrate, and After the development processing step, a post-development imaging step of controlling the imaging unit so that the adjustment substrate is imaged, A film thickness distribution estimation step for estimating the in-plane distribution of the film thickness of the resist film after the development process and an estimation of the in-plane distribution of the film thickness on the adjustment substrate based on the imaging results in the heat treatment step.
  • the substrate processing apparatus according to any one of (1) to (5) above, which includes a development processing condition determining step of determining the processing conditions of the developing process based on the result. According to the above (6), the developing process can be performed so that the processing result is uniform on the substrate surface. Therefore, it is possible to form a resist pattern having higher in-plane uniformity of line width.
  • the substrate has a removing portion for removing the resist film.
  • the adjustment process A removal step of controlling the removing portion so that the resist film formed on the adjusting substrate is removed.
  • a post-removal imaging step that controls the imaging unit so that the adjustment substrate is imaged.
  • the control unit The substrate treatment according to any one of (1) to (7) above, which is configured to start the adjustment treatment based on the estimation result of the line width of the resist pattern formed on the substrate during the actual treatment. apparatus.
  • control unit Any one of (1) to (8) above, which is configured to start the adjustment processing of the processing conditions for the peripheral portion of the substrate based on the imaging result of the peripheral portion of the substrate during the actual processing.
  • the substrate processing apparatus according to.
  • the heat treatment section is The hot plate on which the board is placed and A lid covering the substrate on the hot plate and The substrate processing apparatus according to any one of (1) to (9) above, which has a temperature adjusting mechanism for adjusting the temperature of the lid.
  • a processing condition adjusting method for adjusting processing conditions for a substrate A pre-exposure imaging step of imaging an unexposed adjustment substrate on which a resist film is formed, and After the pre-exposure imaging step, a uniform exposure step of performing a uniform exposure process of exposing each region of the substrate surface with a constant exposure amount on the adjustment substrate, and a uniform exposure step. After the uniform exposure step, a heat treatment step of performing a heat treatment on the adjustment substrate and a heat treatment step After the heat treatment step, a post-heating imaging step of imaging the adjustment substrate, and A temperature distribution estimation step for estimating the in-plane temperature distribution of the adjustment substrate during the heat treatment based on the imaging result in the pre-exposure imaging step and the imaging result in the post-heating imaging step.
  • a processing condition adjusting method including a heat treatment condition determining step of determining a processing condition at the time of heat treatment based on an estimation result of an in-plane temperature distribution of the adjusting substrate.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Atmospheric Sciences (AREA)
  • Toxicology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Environmental & Geological Engineering (AREA)
  • Epidemiology (AREA)
  • Public Health (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
PCT/JP2020/027054 2019-07-19 2020-07-10 基板処理装置及び処理条件調整方法 Ceased WO2021015010A1 (ja)

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JP2021533945A JP7154416B2 (ja) 2019-07-19 2020-07-10 基板処理装置及び処理条件調整方法
US17/625,370 US11809091B2 (en) 2019-07-19 2020-07-10 Substrate processing apparatus and processing condition adjustment method
CN202080050730.6A CN114127903A (zh) 2019-07-19 2020-07-10 基片处理装置和处理条件调节方法
KR1020227005086A KR20220034879A (ko) 2019-07-19 2020-07-10 기판 처리 장치 및 처리 조건 조정 방법

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JP7431694B2 (ja) * 2020-07-28 2024-02-15 キヤノン株式会社 情報処理装置、膜形成装置、物品の製造方法、およびプログラム
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TW202107219A (zh) 2021-02-16
US11809091B2 (en) 2023-11-07
CN114127903A (zh) 2022-03-01
US20220252992A1 (en) 2022-08-11

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