WO2021012408A1 - 阵列基板、显示面板及阵列基板的制造方法 - Google Patents

阵列基板、显示面板及阵列基板的制造方法 Download PDF

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Publication number
WO2021012408A1
WO2021012408A1 PCT/CN2019/110778 CN2019110778W WO2021012408A1 WO 2021012408 A1 WO2021012408 A1 WO 2021012408A1 CN 2019110778 W CN2019110778 W CN 2019110778W WO 2021012408 A1 WO2021012408 A1 WO 2021012408A1
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Prior art keywords
layer
metal layer
array substrate
fabricating
area
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PCT/CN2019/110778
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English (en)
French (fr)
Inventor
陈诚
余赟
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武汉华星光电半导体显示技术有限公司
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Priority to US16/623,089 priority Critical patent/US11302770B2/en
Publication of WO2021012408A1 publication Critical patent/WO2021012408A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
    • H10K10/482—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors the IGFET comprising multiple separately-addressable gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H10K71/421—Thermal treatment, e.g. annealing in the presence of a solvent vapour using coherent electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • the present invention relates to the field of display technology, and in particular to a manufacturing method of an array substrate, a display panel and an array substrate.
  • OLED Organic Light Emitting Display Due to the advantages of Organic Light Emitting Display (OLED), such as light weight, self-luminescence, wide viewing angle, low driving voltage, high luminous efficiency, low power consumption, and fast response speed, the application range is becoming wider and wider, especially flexible
  • OLED display device has the characteristics of being bendable and easy to carry, and has become the main field of research and development in the field of display technology.
  • the bendable display screen has attracted much attention.
  • the service life of the display screen is seriously affected.
  • high-end terminal equipment has higher requirements for the brightness uniformity of the display screen, but the existing organic light-emitting diode display devices have poor brightness uniformity.
  • a double source and drain layer is formed by adding a source and drain layer.
  • the layer power supply voltage (ELVDD) trace reduces the resistance voltage drop (IR drop) to improve the brightness uniformity of the screen.
  • the purpose of the present invention is to provide an array substrate, a display panel, and a manufacturing method of the array substrate, so as to solve the problem of poor brightness uniformity of the existing organic light emitting diode display device and the stretching of the wiring structure after multiple bendings.
  • the present invention provides an array substrate, which includes a substrate layer, an active layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, an interlayer insulating layer, an organic A filling layer and a third metal layer;
  • the array substrate defines a display area, a bending area, and a line change area between the two, and the second metal layer located in the display area includes lines for connecting scan signals
  • the wires are electrically connected to form a double-layer power supply voltage wiring structure in the display area.
  • the traces of the second metal layer intersect each other in a rhombus, arc or square shape.
  • the traces of the second metal layer are connected to each other to form a mesh structure.
  • the resistivity of the first metal layer, the second metal layer or the third metal layer is greater than 12 ⁇ *cm.
  • the material of the first metal layer, the second metal layer or the third metal layer includes aluminum or aluminum alloy.
  • the adjacent data signal lines of the third metal layer in the display area extend to the wire change area, they respectively pass through the second via hole and the third via hole to change wires to the first Metal layer, the second metal layer; the data signal lines of the first metal layer and the second metal layer located in the swap area extend to the bending area, and pass through a fourth via hole to each other
  • the data signal wiring in the bending area is formed by electrical connection, and the data signal wiring in the bending area extends and is arranged under the organic filling layer.
  • the adjacent power supply voltage signal lines of the third metal layer located in the display area have a multi-segment structure when passing through the wire change area;
  • the wire passes through the third via hole and is changed to the second metal layer passing through the bending area to form a double-layer data signal wiring structure in the bending area.
  • the substrate layer includes a flexible substrate, a barrier layer and a buffer layer arranged in a stack.
  • the barrier layer is located on the flexible substrate; the buffer layer is located on the barrier layer, and the buffer layer is connected to the active layer on a side away from the first insulating layer.
  • the present invention also provides a manufacturing method of an array substrate.
  • the array substrate is defined with a display area, a bending area, and a wire change area between the two.
  • the manufacturing method of the array substrate includes the steps:
  • fabricating a first metal layer the material of the first metal layer includes aluminum or aluminum alloy, fabricating and patterning the first metal layer on the first insulating layer;
  • fabricating a second metal layer the material of the second metal layer includes aluminum or aluminum alloy, fabricating and patterning the second metal layer on the second insulating layer to form a second metal layer wiring;
  • the second metal layer traces are connected to each other to form a mesh structure;
  • a third metal layer is fabricated.
  • the material of the third metal layer includes aluminum or aluminum alloy.
  • the third metal layer is fabricated and patterned on the interlayer insulating layer.
  • the power supply voltage signal of the third metal layer is The wire passes through the first via hole and is electrically connected to the second metal layer wiring to form a double-layer power supply voltage wiring structure.
  • the present invention also provides a display panel including the above-mentioned array substrate.
  • the beneficial effect of the present invention is that the present invention provides a method for manufacturing an array substrate, a display panel, and an array substrate, which can connect the display area through the second metal layer and the third metal layer without adding metal wiring.
  • the double-layer power supply voltage trace design reduces the resistance voltage drop (IR drop), which improves the brightness uniformity of the screen and reduces the cost; at the same time, the data traces in the bending area of the invention are arranged under the organic filling layer in the bending area, forming a double-layer data signal wiring structure in the bending area, which reduces bending The bending stress improves the bending performance.
  • FIG. 1 is a schematic diagram of a perspective structure of an array substrate provided by the present invention in the display area;
  • Figure 2 is a cross-sectional view at A-A shown in Figure 1;
  • FIG. 3 is a schematic diagram of the overall structure of the array substrate provided by the present invention.
  • FIG. 5 is a flowchart of the steps of making a substrate layer in FIG. 4;
  • FIG. 6 is a flowchart of the steps of forming the active layer in FIG. 4.
  • the present invention provides an array substrate 100, which includes a substrate layer 1, an active layer 2, a first insulating layer 3, a first metal layer 4, a second insulating layer 5, The second metal layer 6, the interlayer insulating layer 7, the organic filling layer 8, the third metal layer 9, the flat layer 10, the anode layer 11, the pixel definition layer 12, and the support layer 13.
  • the substrate layer 1 includes a flexible substrate 110, a barrier layer 120, and the buffer layer 130 stacked in sequence.
  • the barrier layer 120 is located on the flexible substrate 110; the buffer layer 130 is located on the barrier layer 120; the active layer 2 is located on the buffer layer 130; the first insulating layer 3 is located on the active layer 2; the first metal layer 4 is located on the first insulating layer 3; the second insulating layer 5 is located on the first metal layer 4; the second metal layer 6 is located on the second insulating layer 5; the interlayer insulating layer 7 is located on the second metal layer 6; the third metal layer 9 is located on the interlayer insulating layer 7; the flat layer 10 Located on the third metal layer 9; the anode layer 11 is located on the flat layer 10; the pixel definition layer 12 is located on the anode layer 11; the support layer 13 is located on the pixel definition layer 12 .
  • the organic filling layer 8 is only disposed in the bending area 103, and the organic filling layer 8 penetrates the barrier layer 120, the buffer layer 130, the first insulating layer 3, and the second insulating layer. 5 and the interlayer insulating layer
  • the array substrate 100 is provided with a display area 101.
  • the array substrate 100 in addition to the display area 101, the array substrate 100 also includes a line change area 102 and a bending area 103, and the line change area 102 is located in the display area 101 and the bending area 103. between.
  • the second metal layer 6 located in the display area 101 includes a gate layer 61 for connecting scan signal lines and a second metal layer wiring 62 surrounding the gate layer for connecting power voltage signal lines;
  • the second metal layer wiring 62 is electrically connected to the power voltage signal line of the third metal layer 9 through the first via 31 to form a double-layer power voltage wiring structure in the display area.
  • the third metal layer 9 is a source and drain layer.
  • the second metal layer wiring 62 of the double-layer power supply voltage wiring structure in the display area is connected in parallel with the third metal layer 9, which reduces the resistance value of the circuit, and can pass through another layer when a circuit of one layer is open.
  • One layer of circuits is turned on, which improves reliability.
  • the second metal layer traces 62 intersect each other in a rhombus, arc or square shape.
  • the second metal layer traces 62 are connected to each other to form a network structure (or called a chain structure).
  • the resistivity of the first metal layer 4, the second metal layer 6 or the third metal layer 9 is greater than 12 ⁇ *cm. Since the conductivity and resistivity can be converted, I will not repeat them here.
  • the material of the first metal layer 4, the second metal layer 6 or the third metal layer 9 includes aluminum or aluminum alloy.
  • the present invention uses aluminum or aluminum alloy to make metal traces (referring to the first metal layer 4, the second metal layer 6 or the third metal layer 9), which improves the electrical conductivity and bending characteristics of the metal traces , which reduces the risk of dynamic bending and breaking.
  • FIG. 2 is a cross-sectional view at A-A shown in FIG. 1.
  • FIG. 3 is a schematic diagram of the overall structure of the array substrate 100 based on FIG. 2.
  • the adjacent data signal lines of the third metal layer 9 in the display area 101 extend to the line change area 102, they respectively pass through the second via 32 and the third via 33 to switch to the The first metal layer 4, the second metal layer 6; the data signal lines of the first metal layer 4 and the second metal layer 6 located in the wire swap area 102 respectively extend to the bending area 103 , And are electrically connected to each other through the fourth via hole 34 to form a bending area data signal wiring 63, and the bending area data signal wiring 63 extends and is disposed under the organic filling layer 8.
  • the data signal line of the second metal layer 6 located in the wire change area 102 directly extends to the bending area 103, and the data signal line located in the first metal layer 4 of the wire change area 102
  • the data signal line extends to the bending area 103, it passes through the fourth via 34 and is switched to the second metal layer 6, forming a bending area data signal wiring 63, and the bending area data signal wiring 63 extends and is arranged under the organic filling layer 8.
  • the data signal line of the display area 101 extends to the line change area 102 and is connected to the first metal layer 4 and the second metal layer 6. This two-layer wiring can save space, so that the line change The area 102 realizes a narrow frame design.
  • the adjacent power supply voltage signal lines of the third metal layer 9 located in the display area 101 are in a multi-segment structure when passing through the wire-changing area 102, and the multi-segment structure can be connected in parallel to reduce The role of resistance; when the adjacent power supply voltage signal lines of the third metal layer 9 in the wire change area 102 extend to the bending area 102, part of the power supply voltage signal lines of the third metal layer 9 Extending above the organic filling layer 8 through the bending area 102, part of the power supply voltage signal line of the third metal layer 9 passes through the third via 32 and is switched to the second metal layer 6. Through the bending area 103, a double-layer data signal wiring structure in the bending area is formed.
  • the initialization voltage signal line (VI signal line) can be designed in the third metal layer 9 or the anode layer 11 in the display area.
  • the active layer 2, the first insulating layer 3, the first metal layer 4, the second insulating layer 5, The second metal layer 6, the interlayer insulating layer 7 and the third metal layer 9 constitute a thin film transistor unit 200.
  • the gate of the thin film transistor unit 200 (referring to the gate layer 61 of the first metal layer 4 and the second metal layer 6) is connected to a scan signal (Scan) or a light emitting signal (EM),
  • the third metal layer 9 is connected to a direct current high voltage (VDD) or an input data voltage (Data), both of which are in the prior art and will not be described in detail here.
  • the double-layer power supply voltage wiring structure in the display area is arranged around the thin film transistor unit 200.
  • the second metal layer wiring 62 of the second metal layer 6 is arranged around the thin film transistor unit 200, in other words, located in the second metal layer of the display area.
  • the metal layer wiring 62 is arranged around the gate layer 61; in this embodiment, the second metal layer wiring 62 preferably has a rhombus, arc or square shape.
  • the gate of the thin film transistor unit 200 includes the first metal layer 4, the gate layer 61 of the second metal layer 6, wherein the first metal layer 4 serves as a capacitor lower electrode,
  • the gate layer 61 of the second metal layer 6 serves as the upper electrode of the capacitor.
  • the second metal layer wiring 62 is electrically connected to the third metal layer 9 through the first via 31 to form a double-layer wiring structure in the display area.
  • the power supply voltage is connected in parallel on the double-layer wiring structure in the display area, and its resistance is reduced compared with the prior art. That is, the double-layer wiring structure in the display area can reduce the resistance of the VDD signal wiring, so the voltage can be reduced. Loss reduction value, which can improve brightness uniformity.
  • the neutral plane is defined as the position where neither compressive stress nor tensile stress is exerted during bending, the bending stress at this place is 0, and the closer the trace is to the neutral plane, the less likely it is to break when bent.
  • the neutral plane is on the lower surface of the array substrate 100 (ie, the flexible substrate 110), so the closer the signal trace is to the flexible substrate 110, the better the bending characteristics.
  • the signal traces of the conventional design are located near the upper surface of the array substrate 100, which are far from the neutral plane, and therefore are easy to break.
  • the double-layer wiring structure proposed by the present invention moves downward as a whole and is closer to the neutral plane.
  • the function of providing the organic filling layer 8 in the bending area 103 is to reduce the bending stress, and the purpose of bending is to realize a narrow frame design.
  • the organic material of the organic filling layer 8 is preferably an oxidative dehydrogenation organic substance.
  • the organic material of the organic filling layer 8 may be a series of flexible organic materials such as polyimide resin or siloxane.
  • the double-layer data signal wiring structure in the bending area is arranged above and below the organic filling layer 8, and the organic filling layer 8 has flexibility to buffer stress.
  • An embodiment of the present invention provides a manufacturing method of an array substrate 100, which specifically includes the following steps:
  • an active layer 2 is fabricated, and the active layer 2 is fabricated on the substrate layer 1;
  • fabricating a first metal layer 4 includes aluminum or aluminum alloy, fabricating the first metal layer 4 on the first insulating layer 3 and patterning it;
  • the material of the second metal layer 6 includes aluminum or aluminum alloy, fabricate and pattern the second metal layer 6 on the second insulating layer 5 to form a gate layer 61 and a second metal layer wiring 62, the second metal layer wiring 62 is arranged around the gate layer 61 (upper electrode); the second metal layer wiring 62 is connected to each other to form a mesh structure; The second metal layer 6 fills the fourth via hole 34 to achieve electrical connection with the first metal layer 4 in the bending area 103;
  • a second via 32 and a third via 33 are formed on the interlayer insulating layer 7 in the bending area 103; wherein the bottoms of the first via 31 and the third via 33 are both In the second metal layer 6, the bottom of the second via hole 32 is the first metal layer 4;
  • a third metal layer 9 is made.
  • the material of the third metal layer 9 includes aluminum or aluminum alloy.
  • a third metal layer 9 is made and patterned on the interlayer insulating layer 7, and the third metal layer 9 is filled The first via 31, the second via 32, and the third via 33; the power voltage signal line of the third metal layer 9 passes through the first via 31, the third The via 33 is electrically connected to the second metal layer trace 62 to form a double-layer power supply voltage trace structure; the third metal layer 9 fills the second via 32 to achieve electrical connection with the first metal layer 4 connection;
  • the material of the first metal layer 4, the second metal layer 6 or the third metal layer 9 includes aluminum or aluminum alloy; the first metal layer 4, the second metal layer The resistivity of the layer 6 or the third metal layer 9 is greater than 12 ⁇ *cm.
  • the material of the first metal layer 4, the second metal layer 6 or the third metal layer 9 includes aluminum or aluminum alloy.
  • the use of aluminum or aluminum alloy to make metal traces improves the conductivity and bending of the metal traces. The bending characteristics reduce the risk of dynamic bending and breaking the line.
  • the step S1 of making the substrate layer 1 specifically includes the following steps:
  • the step S2 of making the active layer 2 specifically includes:
  • the present invention also provides a display panel including the above-mentioned array substrate 100.
  • the display panel in this embodiment may be any product or component with display function, such as wearable devices, mobile phones, tablet computers, televisions, displays, notebook computers, e-books, e-newspapers, digital photo frames, navigators, etc.
  • wearable devices include smart bracelets, smart watches, VR (Virtual Reality) and other devices.

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Abstract

本发明公开了一种阵列基板、显示面板及阵列基板的制造方法。阵列基板包括层叠设置的衬底层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、有机填充层和第三金属层；显示区设计网状第二金属层，通过第一过孔与第三金属层的电源电压信号线电连接，形成显示区双层电源电压走线结构。

Description

阵列基板、显示面板及阵列基板的制造方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板、显示面板及阵列基板的制造方法。
 背景技术
由于有机发光二极管显示器件(Organic Light Emitting Display，OLED)重量轻、自发光、广视角、驱动电压低、发光效率高功耗低、响应速度快等优点，应用范围越来越广泛，尤其是柔性OLED显示装置具有可弯折易携带的特点，成为显示技术领域研究和开发的主要领域。
目前可弯折的显示屏备受关注，但由于走线结构经多次弯折后出现拉伸断裂或裂纹，严重影响显示屏的使用寿命。同时高端终端设备对显示屏亮度均一性要求较高，但现有的有机发光二极管显示器件亮度均一性较差，一般通过新增一层源漏极层形成双层源漏极层的方式布局双层电源电压（ELVDD）走线降低电阻压降（IR drop），以提升屏幕亮度均一性。
因此，确有必要来开发一种新型的阵列基板、显示面板及阵列基板的制造方法，来克服现有技术中的缺陷。
 技术问题
本发明的目的在于，提供一种阵列基板、显示面板及阵列基板的制造方法，以解决现有的有机发光二极管显示器件亮度均一性较差，以及走线结构经多次弯折后出现拉伸断裂或裂纹的技术问题。
 技术解决方案
为了实现上述目的，本发明提供一种阵列基板，包括层叠设置的衬底层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、有机填充层和第三金属层；所述阵列基板定义有显示区、弯折区以及位于两者之间的换线区，位于所述显示区的所述第二金属层包括用于连接扫描信号线的栅极层和环绕所述栅极层用于连接电源电压信号线的第二金属层走线；所述第二金属层走线通过第一过孔与所述第三金属层的电源电压信号线电连接，形成显示区双层电源电压走线结构。
进一步地，所述第二金属层走线相互交错呈菱形、弧形或方形。
进一步地，所述第二金属层走线相互连接，形成网状结构。
进一步地，所述第一金属层、所述第二金属层或所述第三金属层的电阻率大于12μΩ*cm。
进一步地，所述第一金属层、所述第二金属层或所述第三金属层的材质包含铝或铝合金。
进一步地，位于所述显示区的所述第三金属层的相邻数据信号线在延伸到所述换线区时，分别穿过第二过孔、第三过孔换线到所述第一金属层、所述第二金属层；位于所述换线区的所述第一金属层、所述第二金属层的数据信号线分别延伸至所述弯折区，并通过第四过孔相互电连接形成弯折区数据信号走线，所述弯折区数据信号走线延伸并设于所述有机填充层的下方。
进一步地，位于所述显示区的所述第三金属层的相邻电源电压信号线在通过所述换线区时，呈多段式结构；位于所述换线区的所述第三金属层的数据信号线在延伸到所述弯折区时，部分所述第三金属层的数据信号线在所述有机填充层的上方延伸通过所述弯折区，部分所述第三金属层的数据号线穿过所述第三过孔换线到所述第二金属层通过所述弯折区，形成弯折区双层数据信号走线结构。
进一步的，其中所述衬底层包括层叠设置的柔性基底、阻隔层和缓冲层。具体地讲，所述阻隔层位于所述柔性基底上；所述缓冲层位于所述阻隔层上，所述缓冲层与所述有源层背离所述第一绝缘层一侧连接。
本发明还提供一种阵列基板的制作方法，所述阵列基板定义有显示区、弯折区以及位于两者之间的换线区，所述阵列基板的制作方法包括步骤：
制作衬底层；
制作有源层，在所述衬底层上制作所述有源层；
制作第一绝缘层，在所述有源层上制作所述第一绝缘层；
制作第一金属层，所述第一金属层的材质包含铝或铝合金，在所述第一绝缘层上制作所述第一金属层并图形化处理；
制作第二绝缘层，在所述第一金属层上制作所述第二绝缘层；
制作第二金属层，所述第二金属层的材质包含铝或铝合金，在所述第二绝缘层上制作所述第二金属层并图形化处理，形成第二金属层走线；所述第二金属层走线相互连接形成网状结构；
制作层间绝缘层，在所述第二金属层上制作所述层间绝缘层，并蚀刻形成第一过孔；以及
制作第三金属层，所述第三金属层的材质包含铝或铝合金，在所述层间绝缘层上制作所述第三金属层并图形化处理，所述第三金属层的电源电压信号线穿过所述第一过孔与所述第二金属层走线电连接，形成双层电源电压走线结构。
本发明还提供一种显示面板，包括上述阵列基板。
 有益效果
本发明的有益效果是：本发明提出一种阵列基板、显示面板及阵列基板的制造方法，可在不新增金属走线的前提下，通过第二金属层和第三金属层连接的显示区双层电源电压走线设计，降低了电阻压降（IR drop），提升了屏幕亮度均一性，降低了成本；同时该发明弯折区的数据走线设置在弯折区的有机填充层下方，形成弯折区双层数据信号走线结构，降低了弯折应力，提升了弯折性能。
 附图说明
图1是本发明提供的阵列基板在所述显示区的透视结构示意图；
图2是在图1所示A-A处的截面图；
图3是本发明提供的阵列基板的整体结构示意图；
图4是本发明提供的阵列基板的制作方法的流程图；
图5是图4中制作衬底层步骤的流程图；
图6是图4中制作有源层步骤的流程图。
图中部件标识如下：
1衬底层、2有源层、3第一绝缘层、4第一金属层、
5第二绝缘层、6第二金属层、7层间绝缘层、8有机填充层、
9第三金属层、10平坦层、11阳极层、12像素定义层、13支撑层，
31第一过孔、32第二过孔、33第三过孔、34第四过孔、
61栅极层、62第二金属层走线、63弯折区数据信号走线、
100阵列基板、101显示区、102换线区、103弯折区，
110柔性基底、120阻隔层、130所述缓冲层，200薄膜晶体管单元。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]、[横向]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明的说明书和权利要求书以及上述附图中的术语“第一”、“第二”、“第三”等（如果存在）是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
请参阅图1-图3所示，本发明提供一种阵列基板100，包括层叠设置的衬底层1、有源层2、第一绝缘层3、第一金属层4、第二绝缘层5、第二金属层6、层间绝缘层7、有机填充层8、第三金属层9、平坦层10、阳极层11、像素定义层12和支撑层13。其中所述衬底层1包括依次层叠设置的柔性基底110、阻隔层120和所述缓冲层130。
具体地讲，所述阻隔层120位于所述柔性基底110上；所述缓冲层130位于所述阻隔层120上；所述有源层2位于所述缓冲层130上；所述第一绝缘层3位于所述有源层2上；所述第一金属层4位于所述第一绝缘层3上；所述第二绝缘层5位于所述第一金属层4上；所述第二金属层6位于所述第二绝缘层5上；所述层间绝缘层7位于所述第二金属层6上；所述第三金属层9位于所述层间绝缘层7上；所述平坦层10位于所述第三金属层9上；所述阳极层11位于所述平坦层10上；所述像素定义层12位于所述阳极层11上；所述支撑层13位于所述像素定义层12上。所述有机填充层8仅设置在所述弯折区103内，所述有机填充层8贯穿所述阻隔层120、所述缓冲层130、所述第一绝缘层3、所述第二绝缘层5和所述层间绝缘层7。
请参阅图1、图2所示，所述阵列基板100设有显示区101。请参阅图3所示，所述阵列基板100除了包括显示区101以外，还包括换线区102和弯折区103，所述换线区102位于所述显示区101和所述弯折区103之间。位于所述显示区101的所述第二金属层6包括用于连接扫描信号线的栅极层61和环绕所述栅极层用于连接电源电压信号线的第二金属层走线62；所述第二金属层走线62通过第一过孔31与所述第三金属层9的电源电压信号线电连接，形成显示区双层电源电压走线结构。在本实施例中，所述第三金属层9为源漏极层。
所述显示区双层电源电压走线结构的所述第二金属层走线62与所述第三金属层9并联，降低了电路的电阻值，并且当某一层电路断路时，可通过另一层电路导通，提高了可靠性。
请参阅图1所示，在本实施例中，所述第二金属层走线62相互交错呈菱形、弧形或方形。所述第二金属层走线62相互连接形成网状结构（或称链状结构）。
在本实施例中，所述第一金属层4、所述第二金属层6或所述第三金属层9的电阻率大于12μΩ*cm。由于电导率和电阻率可以换算，在此不做赘述。
在本实施例中，所述第一金属层4、所述第二金属层6或所述第三金属层9的材质包括铝或铝合金。本发明使用铝或铝合金制作金属走线（指所述第一金属层4、所述第二金属层6或所述第三金属层9），提升了金属走线的电导率、弯折特性，降低了动态弯折断线风险。
请参阅图2和图3所示，图2为在图1所示A-A处的截面图。图3为在图2基础上的所述阵列基板100的整体结构示意图。位于所述显示区101的所述第三金属层9的相邻数据信号线在延伸到所述换线区102时，分别穿过第二过孔32、第三过孔33换线到所述第一金属层4、所述第二金属层6；位于所述换线区102的所述第一金属层4、所述第二金属层6的数据信号线分别延伸至所述弯折区103，并通过第四过孔34相互电连接形成弯折区数据信号走线63，所述弯折区数据信号走线63延伸并设于所述有机填充层8的下方。换句话讲，位于所述换线区102的所述第二金属层6的数据信号线直接延伸到所述弯折区103，位于所述换线区102的所述第一金属层4的数据信号线在延伸到所述弯折区103时穿过第四过孔34换线到所述第二金属层6，形成弯折区数据信号走线63，所述弯折区数据信号走线63延伸并设于所述有机填充层8的下方。
所述显示区101的数据信号线延伸到所述换线区102连接到所述第一金属层4、所述第二金属层6，这种两层走线可节省空间，使得所述换线区102实现窄边框设计。
在本实施例中，位于所述显示区101的所述第三金属层9的相邻电源电压信号线在通过所述换线区102时，呈多段式结构，多段式结构可并联实现了降低电阻的作用；位于所述换线区102的所述第三金属层9的相邻电源电压信号线在延伸到所述弯折区102时，部分所述第三金属层9的电源电压信号线在所述有机填充层8的上方延伸通过所述弯折区102，部分所述第三金属层9的电源电压信号线穿过所述第三过孔32换线到所述第二金属层6通过所述弯折区103，形成弯折区双层数据信号走线结构。
在本实施例中，初始化电压信号线（VI信号线）可设计在所述显示区第三金属层9或所述阳极层11。
请参阅图2所示，在所述显示区101内，依次层叠设置的所述有源层2、所述第一绝缘层3、所述第一金属层4、所述第二绝缘层5、所述第二金属层6、所述层间绝缘层7和所述第三金属层9构成薄膜晶体管单元200。请结合图1，所述薄膜晶体管单元200的栅极（指所述第一金属层4、所述第二金属层6的栅极层61）连接扫描信号（Scan）或发光信号（EM），所述第三金属层9连接直流高电压（VDD）或输入数据电压（Data），其均为现有技术，在此不做详细说明。
本实施例中，所述显示区双层电源电压走线结构环绕所述薄膜晶体管单元200设置。具体的，在所述显示区101内，所述第二金属层6的第二金属层走线62环绕所述薄膜晶体管单元200设置，换句话讲，位于所述显示区的所述第二金属层走线62环绕所述栅极层61设置；本实施例优选所述第二金属层走线62呈菱形、弧形或方形。请结合图1，所述薄膜晶体管单元200的栅极包括所述第一金属层4、所述第二金属层6的栅极层61，其中所述第一金属层4作为电容下电极、所述第二金属层6的栅极层61作为电容上电极。在所述显示区内，所述第二金属层走线62通过第一过孔31与所述第三金属层9电连接形成所述显示区双层走线结构。电源电压在所述显示区双层走线结构上并联接通，与现有技术相比其电阻下降，即所述显示区双层走线结构可降低VDD信号走线的电阻，故可以降低电压损耗下降值，从而可提升亮度均一性。
若定义中性面是指弯折时既不受压应力亦不受张应力的位置，该处弯折应力为0，在走线越接近中性面其弯折时越不容易断，一般产品中性面在所述阵列基板100的下表面（即所述柔性基底110），故信号走线越接近所述柔性基底110其弯折特性越好。但是，一般现有设计的信号走线均在所述阵列基板100上表面附近，其离中性面较远，因此易折断。本发明提出的双层走线结构相对于现有技术的信号走线整体下移，离中性面更近，通过设置双层走线结构能够减小走线结构的拉伸应力，从而提升弯折特性、降低断线风险，增加使用寿命。
在所述弯折区103设置所述有机填充层8的作用就是为了实现弯折应力的减小，弯折的目的是实现窄边框设计。在本实施例中，所述有机填充层8的有机材料优选氧化脱氢有机物。在其他实施例中，所述有机填充层8的有机材料可以是聚酰亚胺树脂或硅氧烷等系列的柔性有机材料。所述弯折区双层数据信号走线结构设置在所述有机填充层8的上方和下方，所述有机填充层8具有柔性起到缓冲应力的作用。
在具体实施时，请参阅图1-图4所示，本发明一实施例提供一种阵列基板100的制作方法，具体包括以下步骤：
S1、制作衬底层1；
S2、制作有源层2，在所述衬底层1上制作所述有源层2；
S3、制作第一绝缘层3，在所述有源层2上制作所述第一绝缘层3；
S4、制作第一金属层4，所述第一金属层4的材质包含铝或铝合金，在所述第一绝缘层3上制作所述第一金属层4并图形化处理；
S5、制作第二绝缘层5，在所述第一金属层4上制作所述第二绝缘层5；并在所述弯折区103的所述第二绝缘层5上制作第四过孔34；所述第四过孔34的孔底为所述第一金属层4；
S6、制作第二金属层6，所述第二金属层6的材质包含铝或铝合金，在所述第二绝缘层5上制作所述第二金属层6并图形化处理，形成栅极层61和第二金属层走线62，所述第二金属层走线62环绕所述栅极层61（上电极)设置；所述第二金属层走线62相互连接形成网状结构；所述第二金属层6填充所述第四过孔34实现在所述弯折区103与所述第一金属层4电连接；
S7、制作层间绝缘层7，在所述第二金属层6上制作所述层间绝缘层7，并在所述显示区101的所述层间绝缘层7上制作第一过孔31，在所述弯折区103的所述层间绝缘层7上制作第二过孔32、第三过孔33；其中所述第一过孔31、所述第三过孔33的孔底均为所述第二金属层6，所述第二过孔32的孔底为所述第一金属层4；
S8、制作第三金属层9，所述第三金属层9的材质包含铝或铝合金，在层间绝缘层7上制作第三金属层9并图形化处理，所述第三金属层9填充所述第一过孔31、所述第二过孔32、所述第三过孔33；所述第三金属层9的电源电压信号线穿过所述第一过孔31、所述第三过孔33与所述第二金属层走线62电连接，形成双层电源电压走线结构；所述第三金属层9填充所述第二过孔32实现与所述第一金属层4电连接；
S9、制作平坦层10，在所述第三金属层9上制作所述平坦层10；
S10、制作阳极层11，在所述平坦层10上制作所述阳极层11并图形化处理，所述阳极层11与所述第三金属层9电连接；
S11、制作像素定义层12，在所述阳极层11上制作所述像素定义层12并图形化处理，裸露所述阳极层11形成像素限定槽；以及
S12、制作支撑层13，在所述像素定义层12上制作所述支撑层13并图形化处理。
在本实施例中，所述第一金属层4、所述第二金属层6或所述第三金属层9的材质包括铝或铝合金；所述第一金属层4、所述第二金属层6或所述第三金属层9的电阻率大于12μΩ*cm。所述第一金属层4、所述第二金属层6或所述第三金属层9的材质包括铝或铝合金，使用铝或铝合金制作金属走线提升了金属走线的电导率、弯折特性，降低了动态弯折断线风险。
请参阅图5所示，在本实施例中，所述制作衬底层1步骤S1具体包括以下步骤：
S101、提供一柔性基底110；
S102、制作阻隔层120，在所述柔性基底110上制作所述阻隔层120；
S103、制作缓冲层130，在所述阻隔上制作所述缓冲层130。
请参阅图6所示，本实施例中，所述制作有源层2步骤S2具体包括：
S201、在缓冲层130上沉积一层非晶硅层；
S202、通过准分子激光退火工艺将所述非晶硅层转化结晶为多晶硅层；
S203、将所述多晶硅层进行图案化处理，并进行离子掺杂，形成包括源极区域21和漏极区域22的有源层2。
本发明还提供一种显示面板，包括以上所述阵列基板100。本实施例中的显示面板可以为：可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、电子书、电子报纸、数码相框、导航仪等任何具有显示功能的产品或部件。其中可穿戴设备包括智能手环、智能手表、VR（Virtual Reality，即虚拟现实）等设备。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，包括层叠设置的衬底层、有源层、第一绝缘层、第一金属层、第二绝缘层、第二金属层、层间绝缘层、有机填充层和第三金属层；
    其中：
    所述阵列基板定义有显示区、弯折区以及位于两者之间的换线区，位于所述显示区的所述第二金属层包括用于连接扫描信号线的栅极层和环绕所述栅极层用于连接电源电压信号线的第二金属层走线；
    所述第二金属层走线通过第一过孔与所述第三金属层的电源电压信号线电连接，形成显示区双层电源电压走线结构。
  2. 根据权利要求1所述的阵列基板，其中，所述第二金属层走线相互交错呈菱形、弧形或方形。
  3. 根据权利要求1所述的阵列基板，其中，所述第二金属层走线相互连接，形成网状结构。
  4. 根据权利要求1所述的阵列基板，其中，所述第一金属层、所述第二金属层或所述第三金属层的电阻率大于12μΩ*cm。
  5. 根据权利要求1所述的阵列基板，其中，所述第一金属层、所述第二金属层或所述第三金属层的材质包含铝或铝合金。
  6. 根据权利要求1所述的阵列基板，其中，
    位于所述显示区的所述第三金属层的相邻数据信号线在延伸到所述换线区时，分别穿过第二过孔、第三过孔换线到所述第一金属层、所述第二金属层；
    位于所述换线区的所述第一金属层、所述第二金属层的数据信号线分别延伸至所述弯折区，并通过第四过孔相互电连接形成弯折区数据信号走线，所述弯折区数据信号走线延伸并设于所述有机填充层的下方。
  7. 根据权利要求6所述的阵列基板，其中，
    位于所述显示区的所述第三金属层的相邻数据信号线在通过所述换线区时，呈多段式结构；
    位于所述换线区的所述第三金属层的数据信号线在延伸到所述弯折区时，部分所述第三金属层的数据信号线在所述有机填充层的上方延伸通过所述弯折区，部分所述第三金属层的数据号线穿过所述第三过孔换线到所述第二金属层通过所述弯折区，形成弯折区双层数据信号走线结构。
  8. 根据权利要求1所述的阵列基板，其中，所述衬底层包括：
    柔性基底；
    阻隔层，位于所述柔性基底上；以及
    缓冲层，位于所述阻隔层上，所述缓冲层与所述有源层背离所述第一绝缘层一侧连接。
  9. 一种阵列基板的制作方法，所述阵列基板定义有显示区、弯折区以及位于两者之间的换线区，其中，所述阵列基板的制作方法包括步骤：
    制作衬底层；
    制作有源层，在所述衬底层上制作所述有源层；
    制作第一绝缘层，在所述有源层上制作所述第一绝缘层；
    制作第一金属层，所述第一金属层的材质包含铝或铝合金，在所述第一绝缘层上制作所述第一金属层并图形化处理；
    制作第二绝缘层，在所述第一金属层上制作所述第二绝缘层；
    制作第二金属层，所述第二金属层的材质包含铝或铝合金，在所述第二绝缘层上制作所述第二金属层并图形化处理，形成第二金属层走线；所述第二金属层走线相互连接形成网状结构；
    制作层间绝缘层，在所述第二金属层上制作所述层间绝缘层，并蚀刻形成第一过孔；以及
    制作第三金属层，所述第三金属层的材质包含铝或铝合金，在所述层间绝缘层上制作所述第三金属层并图形化处理，所述第三金属层的电源电压信号线穿过所述第一过孔与所述第二金属层走线电连接，形成双层电源电压走线结构。
  10. 一种显示面板，其包括权利要求1所述的阵列基板。
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