WO2021072600A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2021072600A1
WO2021072600A1 PCT/CN2019/111057 CN2019111057W WO2021072600A1 WO 2021072600 A1 WO2021072600 A1 WO 2021072600A1 CN 2019111057 W CN2019111057 W CN 2019111057W WO 2021072600 A1 WO2021072600 A1 WO 2021072600A1
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WIPO (PCT)
Prior art keywords
power bus
base substrate
gate
driving
array substrate
Prior art date
Application number
PCT/CN2019/111057
Other languages
English (en)
French (fr)
Inventor
黄炜赟
龙跃
黄耀
曾超
李孟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19945474.5A priority Critical patent/EP4047653A4/en
Priority to CN201980001972.3A priority patent/CN115668499A/zh
Priority to PCT/CN2019/111057 priority patent/WO2021072600A1/zh
Priority to US17/256,186 priority patent/US11551609B2/en
Publication of WO2021072600A1 publication Critical patent/WO2021072600A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present disclosure relates to the field of display, in particular to an array substrate and a display device.
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the present disclosure provides an array substrate and a display device.
  • an array substrate including:
  • a base substrate including a display area and a peripheral area at least on one side of the display area;
  • a plurality of data lines, located in the display area, are configured to provide data signals to the plurality of sub-pixels
  • a plurality of first power lines located in the display area are configured to provide power signals to the plurality of sub-pixels
  • Multiple data line leads located in the peripheral area and electrically connected to the multiple data lines;
  • a plurality of selection switches are located in the peripheral area and arranged at intervals, the plurality of selection switches are located on the side of the plurality of data line leads away from the display area, and at least part of each of the plurality of selection switches is connected At least two data line leads in the plurality of data line leads;
  • a plurality of data signal input lines are located in the peripheral area and on a side of the plurality of selection switches away from the display area, at least part of each of the plurality of selection switches is connected to the plurality of data signal input lines
  • the first power bus is located in the peripheral area and on the side of the multiple selection switches away from the display area;
  • a plurality of connecting parts are electrically connected to the first power bus and the plurality of first power lines, and the plurality of connecting parts extend to the display area along the area between the plurality of selection switches.
  • it further includes a second power bus between the multiple selection switches and the display area;
  • the multiple connecting parts are respectively connected to the first power bus and the second power bus.
  • the first power bus and the second power bus are located on the same layer.
  • the first power bus, the second power bus, and the multiple connection parts are located on the same layer.
  • the first power bus, the second power bus, and the plurality of connecting portions define a plurality of first openings arranged in an array, and the plurality of selection switches are arranged on the base substrate
  • the orthographic projection is located in the plurality of first openings.
  • it also includes a third power bus,
  • the orthographic projection of the third power bus on the base substrate and the orthographic projection of the first power bus on the base substrate at least partially overlap, and the third power bus and the first power source Bus connection.
  • it further includes a fourth power bus,
  • the orthographic projection of the fourth power bus on the base substrate and the orthographic projection of the second power bus on the base substrate at least partially overlap, and the fourth power bus and the second power source Bus connection.
  • the third power bus and the fourth power bus are located on the same layer.
  • At least one of the plurality of sub-pixels includes a driving thin film transistor and a connection electrode;
  • the drive thin film transistor includes a drive active layer located on the base substrate, a drive gate located on the side of the drive active layer away from the base substrate, and located at the drive gate away from the substrate.
  • the first power bus and the second power bus are located on the same layer as the connection electrode.
  • At least one of the plurality of sub-pixels includes a driving thin film transistor and a connection electrode;
  • the drive thin film transistor includes a drive active layer located on the base substrate, a drive gate located on the side of the drive active layer away from the base substrate, and located at the drive gate away from the substrate.
  • the third power bus, the fourth power bus and the driving source are located on the same layer, or the third power bus, the fourth power bus and the driving drain are located on the same layer.
  • the selection switch includes:
  • a first active layer located on the base substrate
  • the first source, the first drain and the second drain located on the side of the first gate and the second gate away from the base substrate, the first source, the first drain and the The second drain is located in the same layer and does not overlap, and the first source is located between the first drain and the second drain;
  • the first source electrode is connected to one data signal input line of the plurality of data signal input lines, and the first drain electrode and the second drain electrode are connected to one data line of the plurality of data line leads Lead connection.
  • the orthographic projection of each of the first gate and the second gate on the base substrate is different from the first source, the first drain and the The orthographic projection of the second drain electrode on the base substrate does not overlap.
  • it further includes a first control line and a second control line;
  • the first control line is connected to the first gate, and the second control line is connected to the second gate;
  • the orthographic projection of the first control line and the second control line on the base substrate overlaps the orthographic projection of the plurality of first openings on the base substrate.
  • At least one of the plurality of connecting portions includes a second opening, and the orthographic projection of the second opening on the base substrate is in the same position as the first control line and the second control line.
  • the orthographic projections of the base substrate are all overlapped.
  • the plurality of data line leads and the first gate or the second gate are located on the same layer.
  • the plurality of data signal input lines include a first data signal input line and a second data signal input line, the first data signal input line and the second data signal input line are alternately arranged, and The first data signal input line and the second data signal input line are located in different layers.
  • At least one of the plurality of sub-pixels includes a driving thin film transistor, a connection electrode, and a storage capacitor;
  • the drive thin film transistor includes a drive active layer located on the base substrate, a drive gate located on the side of the drive active layer away from the base substrate, and located at the drive gate away from the substrate
  • the gate insulating layer (GI2) on the side of the substrate, the interlayer dielectric layer on the side of the gate insulating layer (GI2) away from the base substrate, and the side of the interlayer dielectric layer away from the base substrate
  • the driving source and driving drain; the connecting electrode is located on the side of the driving source and the driving drain away from the base substrate;
  • the storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the driving gate are located on the same layer, and the second capacitor electrode is located on the gate insulating layer (GI2) and the layer. Between the dielectric layers;
  • the first data signal input line and the driving gate are located on the same layer, and the second data signal input line and the second capacitor electrode are located on the same layer.
  • the first active layer and the driving active layer are in the same layer, the first gate and the driving gate are in the same layer, and the first source and the driving source are Located on the same floor.
  • At least one of the plurality of sub-pixels further includes: a light emitting diode located on a side of the connecting electrode away from the base substrate, and the driving drain, the connecting electrode, and the light emitting diode are sequentially connection.
  • a display device including any of the above-mentioned display substrates.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of section XX in FIG. 1 according to an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of the section YY in FIG. 1 provided by an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of the section ZZ in FIG. 1 provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a cross-section UU in FIG. 1 according to an embodiment of the disclosure
  • FIG. 6 is a schematic diagram of the section VV in FIG. 1 according to an embodiment of the disclosure.
  • FIG. 7-1 is a schematic diagram of the cross-section WW in FIG. 1 provided by an embodiment of the disclosure.
  • FIG. 7-2 is a schematic diagram of the cross-section TT in FIG. 1 provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • the array substrate in the related art includes: a display area and a peripheral area, wherein the peripheral area is arranged with a power bus for providing power signals for the display area (usually denoted by VDD in the art), and for providing data signals for the display area
  • the selection switch such as the data selector (Multiplexer, MUX).
  • the power bus and the selection switch overlap and generate parasitic capacitance, which affects the normal operation of the power bus and the selection switch.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure. As shown in FIG. 1, the array substrate includes:
  • the base substrate 01 includes a display area AA and a peripheral area BB located on at least one side of the display area AA.
  • the peripheral area BB is located on four sides of the display area AA as an example.
  • a plurality of sub-pixels 02 are located in the display area AA;
  • a plurality of data lines 03, located in the display area AA, are configured to provide data signals to the plurality of sub-pixels 02;
  • the plurality of first power lines 04 are located in the display area AA and are configured to provide power signals to the plurality of sub-pixels 02;
  • Multiple data line leads 05 located in the peripheral area BB and connected to multiple data lines 03;
  • Multiple selection switches 06 are located in the peripheral area BB and arranged at intervals, multiple selection switches 06 are located on the side of the multiple data line leads 05 away from the display area AA, and at least part of the multiple selection switches 06 select each of the switches 06
  • the selection switch is connected to at least two data line leads 05 among the plurality of data line leads 05; in FIG. 1, each selection switch 06 is connected to two data line leads 05 as an example.
  • the multiple data signal input lines 07 are located in the peripheral area BB and on the side of the multiple selection switches 06 away from the display area AA. At least some of the multiple selection switches 06 are connected to each selection switch 06 of multiple data.
  • the first power bus 08 is located in the peripheral area BB and on the side of the multiple selection switches 06 away from the display area AA;
  • the plurality of connecting portions 09 are connected to the first power bus 08 and the plurality of first power lines 04, and the plurality of connecting portions 09 extend to the display area AA along the area between the plurality of selection switches 06.
  • the first power bus located in the peripheral area does not overlap with the selection switch. Therefore, the degree of overlap between the first power bus and the selection switch is reduced, and the parasitic capacitance formed by the first power bus and the selection switch is reduced, so that both the first power bus and the selection switch can work normally.
  • the first power bus 08 may be connected to the sub-pixel 02 in the display area AA through the multiple connection portions 09 and the multiple first power lines 04, so as to realize the connection to the sub-pixel 02.
  • the purpose of power supply may be connected to the sub-pixel 02 in the display area AA through the multiple connection portions 09 and the multiple first power lines 04, so as to realize the connection to the sub-pixel 02. The purpose of power supply.
  • the array substrate further includes a second power bus 010 located between the plurality of selection switches 06 and the display area AA.
  • the multiple connection parts 09 are respectively connected to the first power bus 08 and the second power bus 010, that is, each connection part 09 is connected to the first power bus 08 and the second power bus 010. It can be seen from FIG. 1 that the second power bus 010 does not overlap with the selection switch 06. Therefore, there is no parasitic capacitance between the second power bus 010 and the selection switch 06, and the second power bus 010 can also normal work.
  • the first power bus 08 and the second power bus 010 are located on the same layer. It should be noted that the meaning that the two structures are located on the same layer is: the materials of the two structures are the same, and the two structures can be obtained by the same patterning process. When the first power bus 08 and the second power bus 010 are located on the same layer, the first power bus 08 and the second power bus 010 can be obtained at the same time by one patterning process, so the process complexity of preparing the array substrate can be reduced. Further, the first power bus 08, the second power bus 010 and the multiple connection parts 09 are located on the same layer.
  • the first power bus 08, the second power bus 010 and the multiple connection parts 09 can use the same patterning process
  • the preparation can further reduce the complexity of the preparation process of the array substrate.
  • the first power bus and the second power bus may not be located in the same layer, which is not limited in the embodiment of the present disclosure.
  • the first power bus 08, the second power bus 010, and the plurality of connecting portions 09 define a plurality of first openings 011 arranged in an array, and the orthographic projection of the plurality of selection switches 06 on the base substrate 01 Located in the plurality of first openings 011.
  • the multiple selection switches 06 correspond to the multiple first openings 011 one-to-one, and the orthographic projection of each selection switch 06 on the base substrate 01 may be located in the corresponding first opening 011.
  • the first power bus 08, the second power bus 010, and the connecting portion 09 configured to transmit power signals do not overlap with the selection switch 06, which can reduce the parasitic capacitance. In this way, the power supply The signal is effectively transmitted to the sub-pixel 02 in the display area AA.
  • FIG. 2 is a schematic diagram of a cross-section XX in FIG. 1 provided by an embodiment of the present disclosure.
  • the array substrate further includes a third power bus 012, and the third power bus 012 is on the substrate.
  • the orthographic projection on the substrate 01 and the orthographic projection of the first power bus 08 on the base substrate 01 at least partially overlap, and the third power bus 012 is connected to the first power bus 08.
  • the power bus configured to transmit the power signal in the related art is usually a single-layer structure, and this single-layer structure will result in a higher resistance during the transmission of the power signal, resulting in a larger voltage drop during the transmission of the power signal.
  • the first power bus 08 in the embodiment of the present disclosure may also be connected to the third power bus 012, so that the structure configured to transmit power signals is a double-layer structure, which reduces the resistance and voltage drop during power signal transmission.
  • FIG. 3 is a schematic diagram of the cross-section YY in FIG. 1 provided by an embodiment of the present disclosure.
  • the array substrate further includes a fourth power bus 013, and the fourth power bus 013 is on the substrate.
  • the orthographic projection on the substrate 01 and the orthographic projection of the second power bus 010 on the base substrate 01 at least partially overlap, and the fourth power bus 013 is connected to the second power bus 010.
  • the second power bus 010 may also be connected to a fourth power bus 013, so that the structure configured to transmit power signals is a double-layer structure, which reduces the resistance during power signal transmission And the pressure drop.
  • the third power bus 012 in FIG. 2 and the fourth power bus 013 in FIG. 3 may be located on the same layer.
  • the connecting portion 09 is of a single-layer structure as an example.
  • the connecting portion 09 can also be made into a double-layer structure, for example, it also includes a connecting sub-part 09' (not shown in the drawings of the specification).
  • the connecting sub-portion 09' is located on the same layer as the third power bus 012, and is connected to the third power bus 012 and the fourth power bus 013.
  • the connecting portion 09 and the connecting sub-portion 09' may also be connected through a via hole.
  • FIG. 4 is a schematic diagram of a cross-section ZZ in FIG. 1 provided by an embodiment of the present disclosure.
  • at least one sub-pixel 02 of the plurality of sub-pixels 02 in the display area AA includes a driving thin film transistor 021 and a connection Electrode 022.
  • the driving thin film transistor 021 includes a driving active layer 0211 located on the base substrate 01, a driving gate 0212 located on the side of the driving active layer 0211 away from the base substrate 01, and a driving gate 0212 located far away from the base substrate 01.
  • the above-mentioned connecting electrode 022 is located on the side of the driving source 0213 and the driving drain 0214 away from the base substrate 01.
  • the sub-pixel in FIG. 4 may also include a light-emitting diode 023 (including a first electrode 0231, a light-emitting layer 0232, and a second electrode 0233 arranged in a direction away from the base substrate 01).
  • the light-emitting diode 023 is located at the connecting electrode 022 away from the substrate.
  • the driving drain 0214, the connection electrode 022 and the light emitting diode 023 are connected in sequence.
  • the sub-pixel 02 in FIG. 4 may further include: a buffer layer 024, a first gate insulating layer 025, a second gate insulating layer 026, an interlayer dielectric layer 027, and a buffer layer 024 sequentially arranged in a direction away from the base substrate 01.
  • the driving active layer 0211 is located between the buffer layer 024 and the first gate insulating layer 025; the driving gate 0212 is located between the first gate insulating layer 025 and the second gate insulating layer 026; the driving source 0213 and the driving drain 0214 It is located between the interlayer dielectric layer 027 and the passivation layer 028; the connection electrode 022 is located between the first flat layer 029 and the second flat layer 030.
  • the pixel defining layer 031 is configured to define a pixel area on the base substrate 01, and the above-mentioned light emitting diode 023 is located in the pixel area.
  • the buffer layer 024, the first gate insulating layer 025, the second gate insulating layer 026, the interlayer dielectric layer 027, the passivation layer 028, the first flat layer 029, and the second flat layer 030 in the display area AA All of them can extend to the peripheral area BB, and the relative positional relationship of these film layers in the peripheral area BB is the same as the relative positional relationship in the display area AA, which is not repeated in the embodiments of the present disclosure.
  • the sub-pixel 02 in FIG. 4 may further include: a storage capacitor 034.
  • the storage capacitor 034 includes a first capacitor electrode 0341 and a second capacitor electrode 0342.
  • the first capacitor electrode 0341 and the driving gate 0212 are located on the same layer, and the second capacitor
  • the electrode 0342 is located between the second gate insulating layer 026 and the interlayer dielectric layer 027.
  • a part of the structure of the display area AA in the array substrate may be located on the same layer as a part of the structure of the peripheral area BB, and these structures will be explained below.
  • the first power bus 08 and the second power bus 010 may be located on the same layer as the connection electrode 022.
  • the first power bus 08 and the second power bus 010 of the peripheral area BB can be prepared at the same time, which simplifies the process of preparing the array substrate.
  • the first power bus 08 and the second power bus 010 may or may not be located on the same layer as the connecting electrode 022, which is not limited in the embodiment of the present disclosure.
  • the connecting portion 09 and the first power bus 08 are located on the same layer, if the first power bus 08 and the connecting electrode 022 are also located on the same layer, it indicates that the connecting portion 09 and the connecting electrode 022 are also located on the same layer.
  • the selection switch 06 is usually located on a different layer from the connecting electrode 022. In this way, the connecting portion 09, the first power bus 08, and the second power bus 010 are located on a different layer from the selection switch 06. Therefore, the connecting portion 09 can be further reduced. , The parasitic capacitance between the first power bus 08 and the second power bus 010 and the selection switch 06.
  • the third power bus 012, the fourth power bus 013, and the driving source 0213 are located on the same layer, or the third power bus 012, the fourth power bus 013, and the driving drain 0214 are located on the same layer.
  • the driving source 0213 and the driving drain 0214 are located in the same layer as an example. Therefore, the third power bus 012, the fourth power bus 013, the driving source 0213, and the driving drain 0214 are all located in the same layer.
  • the third power bus 012, the fourth power bus 013 and the driving source 0213 may not be on the same layer, and the third power bus 012, the fourth power bus 013 and the driving drain 0214 may not be on the same layer.
  • the present disclosure does not limit this.
  • FIG. 5 is a schematic diagram of the cross-section UU in FIG. 1 provided by an embodiment of the present disclosure.
  • the above-mentioned selection switch 06 may include:
  • the first source electrode 064, the first drain electrode 065 and the second drain electrode 066 located on the side of the first gate 062 and the second gate 063 away from the base substrate 01, the first source electrode 064, the first drain electrode 065 and the The second drain electrode 066 is located in the same layer and does not overlap, and the first source electrode 064 is located between the first drain electrode 065 and the second drain electrode 066;
  • the first source electrode 064 is connected to one data signal input line 07 among the plurality of data signal input lines 07, and the first drain electrode 065 and the second drain electrode 066 are connected to two data line leads 05 of the plurality of data line leads 05 .
  • the orthographic projection of each of the first gate 062 and the second gate 063 on the base substrate 01 is aligned with the first source 064, the first drain 065, and the second drain 066.
  • the orthographic projections on the base substrate 01 do not overlap.
  • some structures in the selection switch 06 may be located on the same layer as some structures in the driving transistor.
  • the first active layer 061 and the driving active layer 0211 are located in the same layer
  • the first gate 062 and the driving gate 0212 are located in the same layer
  • the first source 064 and the driving source 0213 are located in the same layer.
  • the first active layer 061 and the driving active layer 0211 may not be in the same layer
  • the first gate 062 and the driving gate 0212 may not be in the same layer
  • the first source 064 and the driving source 0213 may also be They are not located on the same layer, which is not limited in the embodiments of the present disclosure.
  • the array substrate may further include a first control line 014 and a second control line 015; the first control line 014 is connected to the first gate 062, and the second control line 015 is connected to the second gate 063;
  • the orthographic projection of the first control line 014 and the second control line 015 on the base substrate 01 overlaps the orthographic projection of the plurality of first openings 011 on the base substrate 01.
  • FIG. 6 is a schematic diagram of the cross-section VV in FIG. 1 provided by an embodiment of the disclosure
  • FIG. 7-1 is a schematic diagram of the cross-section WW in FIG. 1 provided by an embodiment of the disclosure
  • FIG. 7-2 is a schematic diagram of the cross-section WW in FIG.
  • the disclosed embodiment provides a schematic diagram of the section TT in FIG. 1.
  • at least one connecting part 09 of the plurality of connecting parts 09 includes a second opening 091, the orthographic projection of the second opening 091 on the base substrate 01 and the first The orthographic projections of a control line 014 and a second control line 015 on the base substrate 01 both overlap.
  • a second opening 091 is provided in the connecting portion 09, and under the action of the second opening 091, the overlap between the connecting portion 09 and the first control line 014 and the second control line 015 can be reduced. degree. As a result, the parasitic capacitance formed by the connecting portion 09 and the two control lines can be reduced, and the influence on the power signal transmitted on the connecting portion 09 can be further reduced.
  • the plurality of data line leads 05 and the first gate 062 or the second gate 063 are located on the same layer.
  • the first gate 062 and the second gate 063 may be located on the same layer.
  • the multiple data line leads 05, the first gate 062 and the second gate 063 are all located on the same layer.
  • the multiple data line leads 05 and the first gate 062 or the second gate 063 may not be located in the same layer, which is not limited in the embodiment of the present disclosure.
  • the multiple data signal input lines 07 include a first data signal input line 071 and a second data signal input line 072, the first data signal input line 071 and the second data signal input line 072 are alternately arranged, and the first data signal input line 072
  • the data signal input line 071 and the second data signal input line 072 are located in different layers.
  • the first data signal input line 071 and the driving gate in the sub-pixel 02 are located in the same layer
  • the second data signal input line 072 is in the same layer as the second data signal input line in the sub-pixel 02.
  • the capacitor electrode 0342 is located on the same layer.
  • first data signal input line 071 and the driving gate in the sub-pixel 02 may not be located in the same layer, and the second data signal input line 072 and the second capacitor electrode 0342 in the sub-pixel 02 may not be located in the same layer.
  • the embodiment of the present disclosure does not limit this.
  • the first power bus, the second power bus, the third power bus, the fourth power bus and the connection part in the array substrate transmit power signals.
  • the power signal is transmitted to each sub-pixel through a plurality of first power lines.
  • the signal source terminals in the array substrate can also input data signals to multiple selection switches through multiple data signal input lines.
  • the signal source terminal inputs a data signal to a selection switch through each data signal input line
  • the data signal is input to the first source of the selection switch.
  • the data signal on the first source electrode can be respectively transmitted to the two data lines.
  • the turn-on signal can be first input to the first control line to turn on the first source and the first drain. At this time, the data signal on the first source is transmitted to the first drain and a data line lead.
  • One data line after that, the second control line is input with an on signal to make the first source and the second drain turn on, at this time the data signal on the first source passes through the second drain and the other data line
  • the lead is transmitted to another data line.
  • the sub-pixels connected to each data line also receive the data signal.
  • each sub-pixel After each sub-pixel receives the power signal and the data signal, it can emit light based on the power signal and the data signal, thereby achieving the purpose of displaying images on the array substrate.
  • the array substrate provided by the embodiment of the present disclosure has a low degree of overlap between the structure configured to transmit power signals and the selection switch, the structure configured to transmit power signals and the selection switch can work normally.
  • the structure configured to transmit the power signal in the array substrate is a multilayer structure, so the impedance of the power signal transmission is small, and the power signal can be effectively transmitted to the sub-pixels.
  • the conductive structure may be made of transparent material or non-transparent material, such as indium tin oxide, copper, aluminum, silver, molybdenum, nickel, gold and other metal elements. Simple metal or alloy.
  • the present disclosure also provides a method for manufacturing any of the above-mentioned array substrates, the method including:
  • a plurality of sub-pixels, a plurality of data lines, a plurality of first power lines, a plurality of data line leads, a plurality of selection switches, a plurality of data signal input lines, a first power bus, and a plurality of connecting parts are formed on the base substrate.
  • the base substrate includes a display area and a peripheral area at least on one side of the display area;
  • a plurality of data lines located in the display area are configured to provide data signals to a plurality of sub-pixels
  • a plurality of first power lines located in the display area are configured to provide power signals to a plurality of sub-pixels
  • Multiple data line leads located in the peripheral area and connected to multiple data lines;
  • a plurality of selection switches are located in the peripheral area and arranged at intervals, the plurality of selection switches are located on the side of the plurality of data line leads away from the display area, and each of at least some of the plurality of selection switches is connected to at least two of the plurality of data line leads Data line lead;
  • a plurality of data signal input lines are located in the peripheral area and on a side of the plurality of selection switches away from the display area, and at least part of each of the plurality of selection switches is connected to one of the plurality of data signal input lines;
  • the first power bus is located in the peripheral area and on the side of the multiple selection switches away from the display area;
  • the plurality of connection parts are connected to the first power bus and the plurality of first power lines, and the plurality of connection parts extend to the display area along the area between the plurality of selection switches.
  • one or more of the second power bus, the third power bus, the fourth power bus, the first control line, and the second control line can also be prepared on the base substrate.
  • the method of the embodiment of the present disclosure can be realized by, for example, changing the pattern on the mask plate by referring to any method of manufacturing the array substrate provided in the related art that is similar to the embodiment of the present disclosure. This will not be repeated one by one.
  • the embodiments of the present disclosure also provide a display device, which includes any one of the above-mentioned array substrates.
  • the display device in the embodiment of the present disclosure may be any display panel (such as a liquid crystal display panel, an organic light emitting diode display panel, etc.), a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., which has a display function Products or parts.
  • FIG. 8 is a schematic structural diagram of a display device provided by an embodiment of the disclosure.
  • the display device includes any one of the above-mentioned display panels, and the display area AA of the display device includes sub-pixels 02 arranged in rows and columns.
  • the detailed structure of the peripheral area BB is not shown in FIG. 8.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • At least one of the following” or similar expressions refers to any combination of these items, including any combination of single items or plural items.
  • at least one of a, b, or c can mean: a, b, c, a+b, a+c, b+c, and a+b+c, where a, b, c can be A single item can also be multiple.
  • connection refers to the direct or indirect connection of the two conductors, and the two conductors can transmit electrical signals.
  • the method embodiments provided in the embodiments of the present disclosure can be cross-referenced with the corresponding embodiments of the array substrate, which is not limited in the embodiments of the present disclosure.
  • the sequence of steps in the method embodiments provided in the embodiments of the present disclosure can be adjusted appropriately, and the steps can be increased or decreased accordingly according to the situation. Any person skilled in the art can easily think of changes within the technical scope disclosed in the present disclosure. The methods should all be covered in the scope of protection of the present disclosure, so they will not be repeated here.

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Abstract

一种阵列基板及显示装置，其中，所述阵列基板包括：衬底基板（01）、多个子像素（02）、多条数据线（03）、多条第一电源线（04）和多条数据线引线（05），阵列基板还包括：多个选择开关（06），位于周边区（BB）且间隔排列，多个选择开关（06）位于多条数据线引线（05）远离显示区（AA）的一侧；多条数据信号输入线（07），位于周边区（BB）且位于多个选择开关（06）远离显示区（AA）的一侧，至少部分多个选择开关（06）中的每一个连接多条数据信号输入线（07）中的一条；第一电源总线（08），位于周边区（BB），且位于多个选择开关（06）远离显示区（AA）的一侧；多个连接部（09），与第一电源总线（08）和多条第一电源线（04）连接，多个连接部（09）沿着多个选择开关（06）之间的区域向显示区（AA）延伸。可以实现电源信号的有效传输。

Description

阵列基板及显示装置 技术领域
本公开涉及显示领域，特别涉及一种阵列基板及显示装置。
背景技术
近年来，随着智能显示技术的进步，有机发光显示器(Organic Light Emitting Diode，OLED)成为当今显示器研究领域的热点之一，越来越多的有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示面板进入市场，相对于传统的薄膜晶体管液晶显示面板(Thin Film Transistor Liquid Crystal Display，TFT-LCD)，AMOLED显示器具有更快的反应速度和更高的对比度。
发明内容
本公开提供一种阵列基板及显示装置。
第一方面，本公开提供了一种阵列基板，包括：
衬底基板，所述衬底基板包括显示区和至少位于所述显示区一侧的周边区；
多个子像素，位于所述显示区；
多条数据线，位于所述显示区，被配置为向所述多个子像素提供数据信号；
多条第一电源线，位于所述显示区，被配置为向所述多个子像素提供电源信号；
多条数据线引线，位于所述周边区且与所述多条数据线电连接；
多个选择开关，位于所述周边区且间隔排列，所述多个选择开关位于所述多条数据线引线远离所述显示区的一侧，至少部分所述多个选择开关中的每一个连接所述多条数据线引线中的至少两条数据线引线；
多条数据信号输入线，位于所述周边区且位于所述多个选择开关远离所述显示区的一侧，至少部分所述多个选择开关中的每一个连接所述多条数据信号输入线中的一条；
第一电源总线，位于所述周边区，且位于所述多个选择开关远离所述显示 区的一侧；
多个连接部，与所述第一电源总线和所述多条第一电源线电连接，所述多个连接部沿着所述多个选择开关之间的区域向所述显示区延伸。
可选地，还包括位于所述多个选择开关和所述显示区之间的第二电源总线；
其中，所述多个连接部分别与所述第一电源总线和所述第二电源总线连接。
可选地，所述第一电源总线与所述第二电源总线位于同一层。
可选地，所述第一电源总线、所述第二电源总线和所述多个连接部位于同一层。
可选地，所述第一电源总线、所述第二电源总线和所述多个连接部限定出阵列排布的多个第一开口，所述多个选择开关在所述衬底基板上的正投影位于所述多个第一开口中。
可选地，还包括第三电源总线，
所述第三电源总线在所述衬底基板上的正投影和所述第一电源总线在所述衬底基板上的正投影至少部分重叠，且所述第三电源总线与所述第一电源总线连接。
可选地，还包括第四电源总线，
所述第四电源总线在所述衬底基板上的正投影和所述第二电源总线在所述衬底基板上的正投影至少部分重叠，且所述第四电源总线与所述第二电源总线连接。
可选地，所述第三电源总线和所述第四电源总线位于同一层。
可选地，所述多个子像素中的至少一个包含驱动薄膜晶体管和连接电极；
所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的驱动源极和驱动漏极；所述连接电极位于所述驱动源极和所述驱动漏极远离所述衬底基板的一侧；
所述第一电源总线与所述第二电源总线与所述连接电极位于同一层。
可选地，所述多个子像素中的至少一个包含驱动薄膜晶体管和连接电极；
所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的驱动源极和驱动漏极；所述连接电极位于所述驱动源极和所述驱动 漏极远离所述衬底基板一侧；
所述第三电源总线、所述第四电源总线与所述驱动源极位于同一层，或所述第三电源总线、所述第四电源总线与所述驱动漏极位于同一层。
可选地，所述选择开关包括：
位于所述衬底基板上的第一有源层；
位于所述第一有源层远离所述衬底基板一侧的第一栅极和第二栅极，所述第一栅极和第二栅极位于同一层且不交叠；
位于所述第一栅极和所述第二栅极远离所述衬底基板一侧的第一源极、第一漏极和第二漏极，所述第一源极、第一漏极和第二漏极位于同一层且不交叠，所述第一源极位于所述第一漏极和所述第二漏极之间；
所述第一源极与所述多条数据信号输入线中的一条数据信号输入线连接，所述第一漏极、所述第二漏极与所述多条数据线引线中的一条数据线引线连接。
可选地，所述第一栅极、所述第二栅极中的每个栅极在所述衬底基板上的正投影，与所述第一源极、所述第一漏极和所述第二漏极在所述衬底基板上的正投影不交叠。
可选地，还包括第一控制线和第二控制线；
所述第一控制线与所述第一栅极连接，所述第二控制线与所述第二栅极连接；
所述第一控制线和所述第二控制线在所述衬底基板的正投影与所述多个第一开口在所述衬底基板上的正投影交叠。
可选地，所述多个连接部中的至少一个包括第二开口，所述第二开口在所述衬底基板的正投影与所述第一控制线和所述第二控制线在所述衬底基板的正投影均交叠。
可选地，所述多条数据线引线与所述第一栅极或所述第二栅极位于同一层。
可选地，所述多条数据信号输入线包括第一数据信号输入线和第二数据信号输入线，所述第一数据信号输入线和所述第二数据信号输入线交替排布，且所述第一数据信号输入线和所述第二数据信号输入线位于不同层。
可选地，所述多个子像素中的至少一个包含驱动薄膜晶体管、连接电极和存储电容；
所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱 动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的栅绝缘层(GI2)，位于所述栅绝缘层(GI2)远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的驱动源极和驱动漏极；所述连接电极位于所述驱动源极和所述驱动漏极远离所述衬底基板一侧；
所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述驱动栅极位于同一层，所述第二电容电极位于所述栅绝缘层(GI2)和所述层间介质层之间；
所述第一数据信号输入线与所述驱动栅极位于同一层，所述第二数据信号输入线与所述第二电容电极位于同一层。
可选地，所述第一有源层与所述驱动有源层位于同一层，所述第一栅极与所述驱动栅极位于同一层，所述第一源极与所述驱动源极位于同一层。
可选地，所述多个子像素中的至少一个还包括：位于所述连接电极远离所述衬底基板一侧的发光二极管，且所述驱动漏极、所述连接电极以及所述发光二极管依次连接。
第二方面，提供了一种显示装置，包括上述任一种显示基板。
附图说明
图1为本公开实施例提供的一种阵列基板的结构示意图；
图2为本公开实施例提供的一种图1中截面XX的示意图；
图3为本公开实施例提供的一种图1中截面YY的示意图；
图4为本公开实施例提供的一种图1中截面ZZ的示意图；
图5为本公开实施例提供的一种图1中截面UU的示意图；
图6为本公开实施例提供的一种图1中截面VV的示意图；
图7-1为本公开实施例提供的一种图1中截面WW的示意图；
图7-2为本公开实施例提供的一种图1中截面TT的示意图；
图8为本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开的原理、技术方案和优点更加清楚，下面将结合附图对本公开 实施方式作进一步地详细描述。
相关技术中的阵列基板包括：显示区和周边区，其中，周边区排布有用于为显示区提供电源信号(本领域中通常以VDD表示)的电源总线，以及用于为显示区提供数据信号的选择开关，如数据选择器(Multiplexer，MUX)。但是，电源总线与选择开关存在交叠，并产生寄生电容，影响电源总线和选择开关的正常工作。
本公开实施例提供了一种阵列基板，该阵列基板中的电源总线与MUX不交叠，因此不会产生寄生电容。示例地，图1为本公开实施例提供的一种阵列基板的结构示意图，如图1所示，该阵列基板包括：
衬底基板01，该衬底基板01包括显示区AA和至少位于显示区AA一侧的周边区BB，图1中以周边区BB位于显示区AA的四侧为例。
多个子像素02，位于显示区AA；
多条数据线03，位于显示区AA，被配置为向多个子像素02提供数据信号；
多条第一电源线04，位于显示区AA，被配置为向多个子像素02提供电源信号；
多条数据线引线05，位于周边区BB且与多条数据线03连接；
多个选择开关06，位于周边区BB且间隔排列，多个选择开关06位于多条数据线引线05远离显示区AA的一侧，多个选择开关06中的至少部分选择开关06中的每一个选择开关连接多条数据线引线05中的至少两条数据线引线05；图1中以每个选择开关06均连接两条数据线引线05为例。
多条数据信号输入线07，位于周边区BB且位于多个选择开关06远离显示区AA的一侧，多个选择开关06中的至少部分选择开关06中的每一个选择开关06连接多条数据信号输入线07中的一条；图1中以每个选择开关06连接一条数据信号输入线07为例。
第一电源总线08，位于周边区BB，且位于多个选择开关06远离显示区AA的一侧；
多个连接部09，与第一电源总线08和多条第一电源线04连接，多个连接部09沿着多个选择开关06之间的区域向显示区AA延伸。
综上所述，本公开实施例提供的阵列基板中，位于周边区的第一电源总线与选择开关并没有重叠。因此减少了第一电源总线与选择开关的交叠程度，进 而减少了第一电源总线与选择开关形成的寄生电容，使得第一电源总线和选择开关均能够正常工作。
需要说明的是，在本公开实施例中，第一电源总线08可以通过上述多个连接部09以及多条第一电源线04与显示区AA中的子像素02连接，以实现向子像素02供电的目的。
可选地，请继续参考图1，该阵列基板还包括位于多个选择开关06和显示区AA之间的第二电源总线010。多个连接部09分别与第一电源总线08和第二电源总线010连接，也即是，每个连接部09均与第一电源总线08以及第二电源总线010连接。从图1中可以看出，该第二电源总线010也并未与选择开关06交叠，因此，第二电源总线010与选择开关06之间也不存在寄生电容，第二电源总线010也能够正常工作。
示例地，第一电源总线08与第二电源总线010位于同一层。需要说明的是，两个结构位于同一层的含义是：这两个结构的材质相同，这两个结构可以采用同一次构图工艺处理得到。当第一电源总线08与第二电源总线010位于同一层时，可以采用一次构图工艺同时得到第一电源总线08与第二电源总线010，因此能够降低制备阵列基板的工艺复杂度。进一步地，第一电源总线08、第二电源总线010和多个连接部09位于同一层，此时，第一电源总线08、第二电源总线010和多个连接部09能够采用同一次构图工艺制备得到，能够进一步降低阵列基板的制备工艺复杂程度。当然，该第一电源总线与第二电源总线也可以不是位于同一层，本公开实施例对此不作限定。
请继续参考图1，第一电源总线08、第二电源总线010和多个连接部09限定出阵列排布的多个第一开口011，多个选择开关06在衬底基板01上的正投影位于多个第一开口011中。示例地，该多个选择开关06与多个第一开口011一一对应，每个选择开关06在衬底基板01上的正投影可以位于对应的第一开口011内。可以看出，被配置为传输电源信号的第一电源总线08、第二电源总线010以及连接部09均与选择开关06不存在交叠，能够减小寄生电容，这样一来，就能使电源信号有效地传输至显示区AA的子像素02中。
可选地，图2为本公开实施例提供的一种图1中截面XX的示意图，请结合图1和图2，该阵列基板还包括第三电源总线012，第三电源总线012在衬底基板01上的正投影和第一电源总线08在衬底基板01上的正投影至少部分重叠， 且第三电源总线012与第一电源总线08连接。示例地，第一电源总线08与第三电源总线012之间存在一些绝缘层，第一电源总线08和第三电源总线012可以通过这些绝缘层中的过孔VH1连接。
需要说明的是，相关技术中被配置为传输电源信号的电源总线通常是单层结构，该单层结构会导致电源信号传输时的电阻较高，使得电源信号在传输过程中的压降较大。而本公开实施例中的第一电源总线08还可以连接有第三电源总线012，使得被配置为传输电源信号的结构为双层结构，减小了电源信号传输时的电阻以及压降。
可选地，图3为本公开实施例提供的一种图1中截面YY的示意图，请结合图1和图3，该阵列基板还包括第四电源总线013，第四电源总线013在衬底基板01上的正投影和第二电源总线010在衬底基板01上的正投影至少部分重叠，且第四电源总线013与第二电源总线010连接。示例地，第二电源总线010与第四电源总线013之间存在一些绝缘层，第二电源总线010和第四电源总线013可以通过这些绝缘层中的过孔VH2连接。
在阵列基板还包括第四电源总线013时，第二电源总线010还可以连接有第四电源总线013，使得被配置为传输电源信号的结构为双层结构，减小了电源信号传输时的电阻以及压降。
示例地，图2中的第三电源总线012和图3中的第四电源总线013可以位于同一层。这样一来，在制备阵列基板时，可以同时制备第三电源总线012和第四电源总线013，从而降低了制备阵列基板的工艺复杂程度。当然，该第三电源总线012与第四电源总线013也可以不是位于同一层，本公开实施例对此不作限定。可选地，本发明实施例中以连接部09为单层结构为例，当然连接部09也可以做成双层结构，例如，还包括连接子部09’(说明书附图中并未示出和标出)，所述连接子部09’与第三电源总线012位于同一层，且与第三电源总线012以及第四电源总线013连接。可选地，所述连接部09和连接子部09’之间还可以通过过孔连接。
图4为本公开实施例提供的一种图1中截面ZZ的示意图，请结合图1和图4，显示区AA中的多个子像素02中的至少一个子像素02包含驱动薄膜晶体管021和连接电极022。其中，驱动薄膜晶体管021包含位于衬底基板01上的驱动有源层0211，位于驱动有源层0211远离衬底基板01一侧的驱动栅极0212， 位于驱动栅极0212远离衬底基板01一侧的驱动源极0213和驱动漏极0214。上述连接电极022位于驱动源极0213和驱动漏极0214远离衬底基板01的一侧。图4中的子像素还可以包括发光二极管023(包括沿远离衬底基板01的方向依次排布的第一电极0231、发光层0232和第二电极0233)，发光二极管023位于连接电极022远离衬底基板01一侧，且驱动漏极0214、连接电极022以及发光二极管023依次连接。
进一步地，图4中的子像素02还可以包括：沿远离衬底基板01的方向依次排布的缓冲层024、第一栅绝缘层025、第二栅绝缘层026、层间介质层027、钝化层028、第一平坦层029、第二平坦层030、像素界定层031、支撑层032以及封装层033。上述驱动有源层0211位于缓冲层024和第一栅绝缘层025之间；驱动栅极0212位于第一栅绝缘层025和第二栅绝缘层026之间；驱动源极0213和驱动漏极0214位于层间介质层027和钝化层028之间；连接电极022位于第一平坦层029和第二平坦层030之间。像素界定层031被配置为限定出衬底基板01上的像素区域，上述发光二极管023位于该像素区域内。
需要说明的是，显示区AA中的缓冲层024、第一栅绝缘层025、第二栅绝缘层026、层间介质层027、钝化层028、第一平坦层029、第二平坦层030均可以延伸至周边区BB，且这些膜层在周边区BB的相对位置关系与在显示区AA的相对位置关系相同，本公开实施例在此不做赘述。
另外，图4中的子像素02还可以包括：存储电容034，存储电容034包括第一电容电极0341和第二电容电极0342，第一电容电极0341与驱动栅极0212位于同一层，第二电容电极0342位于第二栅绝缘层026和层间介质层027之间。
可选地，阵列基板中显示区AA的部分结构可以与周边区BB的部分结构位于同一层，以下将对这些结构进行解释说明。
示例地，上述第一电源总线08与第二电源总线010可以与连接电极022位于同一层。这样一来，在制备显示区AA中的连接电极022时，可以同时制备得到周边区BB的第一电源总线08和第二电源总线010，简化了制备阵列基板的工艺。当然，第一电源总线08与第二电源总线010可以与连接电极022也可以不是位于同一层，本公开实施例对此不作限定。
当连接部09与第一电源总线08位于同一层时，若第一电源总线08还与连接电极022位于同一层，则表明连接部09与连接电极022也位于同一层。而选 择开关06通常与连接电极022位于不同层，这样一来，连接部09、第一电源总线08以及第二电源总线010均与选择开关06位于不同层，因此，能够进一步减小连接部09、第一电源总线08以及第二电源总线010与选择开关06之间的寄生电容。
又示例地，上述第三电源总线012、第四电源总线013与驱动源极0213位于同一层，或者，上述第三电源总线012、第四电源总线013与驱动漏极0214位于同一层。本公开实施例中以驱动源极0213和驱动漏极0214位于同一层为例，因此，第三电源总线012、第四电源总线013、驱动源极0213以及驱动漏极0214均位于同一层。当然，第三电源总线012、第四电源总线013与驱动源极0213也可以不是位于同一层，第三电源总线012、第四电源总线013与驱动漏极0214也可以不是位于同一层，本公开实施例对此不作限定。
图5为本公开实施例提供的一种图1中截面UU的示意图，请结合图1和图5，上述选择开关06可以包括：
位于衬底基板01上的第一有源层061；
位于第一有源层061远离衬底基板01一侧的第一栅极062和第二栅极063，第一栅极062和第二栅极063位于同一层且不交叠；
位于第一栅极062和第二栅极063远离衬底基板01一侧的第一源极064、第一漏极065和第二漏极066，第一源极064、第一漏极065和第二漏极066位于同一层且不交叠，第一源极064位于第一漏极065和第二漏极066之间；
第一源极064与多条数据信号输入线07中的一条数据信号输入线07连接，第一漏极065、第二漏极066与多条数据线引线05中的两条数据线引线05连接。
可选地，第一栅极062、第二栅极063中的每个栅极在衬底基板01上的正投影，与第一源极064、第一漏极065和第二漏极066在衬底基板01上的正投影不交叠。
可选地，选择开关06中的一些结构可以与驱动晶体管中的一些结构位于同层。例如：第一有源层061与驱动有源层0211位于同一层，第一栅极062与驱动栅极0212位于同一层，第一源极064与驱动源极0213位于同一层。当然，第一有源层061与驱动有源层0211也可以不是位于同一层，第一栅极062与驱动栅极0212也可以不是位于同一层，第一源极064与驱动源极0213也可以不是位于同一层，本公开实施例对此不作限定。
请继续参考图1，该阵列基板还可以包括第一控制线014和第二控制线015；第一控制线014与第一栅极062连接，第二控制线015与第二栅极063连接；第一控制线014和第二控制线015在衬底基板01的正投影与多个第一开口011在衬底基板01上的正投影交叠。
可选地，图6为本公开实施例提供的一种图1中截面VV的示意图，图7-1为本公开实施例提供的一种图1中截面WW的示意图，图7-2为本公开实施例提供的一种图1中截面TT的示意图。请结合图1、图6、图7-1和图7-2，多个连接部09中的至少一个连接部09包括第二开口091，第二开口091在衬底基板01的正投影与第一控制线014和第二控制线015在衬底基板01的正投影均交叠。需要说明的是，本公开实施例中在连接部09中设置第二开口091，在第二开口091的作用下，能够减少连接部09与第一控制线014以及第二控制线015的交叠程度。从而能够减少连接部09与这两条控制线形成的寄生电容，进一步减轻对连接部09上传输的电源信号的影响。
可选地，多条数据线引线05与第一栅极062或第二栅极063位于同一层。示例地，该第一栅极062和第二栅极063可以位于同一层，此时多条数据线引线05、第一栅极062和第二栅极063均位于同一层。当然，多条数据线引线05与第一栅极062或第二栅极063也可以不是位于同一层，本公开实施例对此不作限定。
可选地，多条数据信号输入线07包括第一数据信号输入线071和第二数据信号输入线072，第一数据信号输入线071和第二数据信号输入线072交替排布，且第一数据信号输入线071和第二数据信号输入线072位于不同层。示例地，上述第一数据信号输入线071与子像素02中的驱动栅极(如图4中的驱动栅极0212)位于同一层，第二数据信号输入线072与子像素02中的第二电容电极0342位于同一层。当然，第一数据信号输入线071与子像素02中的驱动栅极也可以不是位于同一层，第二数据信号输入线072与子像素02中的第二电容电极0342也可以不是位于同一层，本公开实施例对此不作限定。
以下将对本公开实施例提供的阵列基板的工作原理进行讲解。
在阵列基板需要显示图像时，阵列基板中的第一电源总线、第二电源总线、第三电源总线、第四电源总线和连接部上传输有电源信号。该电源信号经由多条第一电源线传输至各个子像素。
在阵列基板需要显示图像时，阵列基板中的信号源端(如图1中的多个信号输入垫C)也可以通过多条数据信号输入线分别向多个选择开关分别输入数据信号。信号源端在通过每条数据信号输入线向一个选择开关输入数据信号时，该数据信号输入该选择开关的第一源极。通过配合第一控制线和第二控制线，可以实现将第一源极上的数据信号分别传输至两条数据线。示例地，可以首先向第一控制线输入开启信号，以使第一源极和第一漏极导通，此时第一源极上的数据信号经由第一漏极和一条数据线引线传输至一条数据线；之后，再将第二控制线输入开启信号，以使第一源极与第二漏极导通，此时第一源极上的数据信号经由第二漏极和另一条数据线引线传输至另一条数据线。在向每条数据线均输入数据信号后，与每条数据线连接的子像素也接收到该数据信号。
每个子像素在接收到电源信号和数据信号后，便可以基于电源信号和数据信号发光，从而实现阵列基板显示图像的目的。由于本公开实施例提供的阵列基板中，被配置为传输电源信号的结构与选择开关的交叠程度较低，因此，被配置为传输电源信号的结构以及选择开关都能够正常工作。并且，该阵列基板中被配置为传输电源信号的结构为多层结构，因此电源信号传输的阻抗较小，电源信号能够有效传输至子像素。另外，本公开实施例提供的阵列基板中存在位于同一层的多个结构，使得制备该阵列基板的工艺流程较为简单。
可选地，本公开实施例提供的阵列基板中，导电的结构的材质可以为透明材质也可以为非透明材质，如氧化铟锡、铜、铝、银、钼、镍、金等金属元素的金属单质或合金。
本公开还提供了上述任意一种阵列基板的制造方法，该方法包括：
在衬底基板上形成多个子像素、多条数据线、多条第一电源线、多条数据线引线、多个选择开关、多条数据信号输入线、第一电源总线以及多个连接部。
其中，衬底基板包括显示区和至少位于显示区一侧的周边区；
多个子像素，位于显示区；
多条数据线，位于显示区，被配置为向多个子像素提供数据信号；
多条第一电源线，位于显示区，被配置为向多个子像素提供电源信号；
多条数据线引线，位于周边区且与多条数据线连接；
多个选择开关，位于周边区且间隔排列，多个选择开关位于多条数据线引 线远离显示区的一侧，至少部分多个选择开关中的每一个连接多条数据线引线中的至少两条数据线引线；
多条数据信号输入线，位于周边区且位于多个选择开关远离显示区的一侧，至少部分多个选择开关中的每一个连接多条数据信号输入线中的一条；
第一电源总线，位于周边区，且位于多个选择开关远离显示区的一侧；
多个连接部，与第一电源总线和多条第一电源线连接，多个连接部沿着多个选择开关之间的区域向显示区延伸。
可选地，还可以在衬底基板上制备第二电源总线、第三电源总线、第四电源总线、第一控制线和第二控制线中的一个或多个。这些结构可以参考上述阵列基板实施例，本公开实施例在此不做赘述。
应理解的是，可以参考相关技术中任意一种具有类似于本公开实施例提供的阵列基板的制造方法，来通过例如改变掩膜板上的图案的方式来实现本公开实施例的方法，在此不再一一赘述。
本公开实施例还提供一种显示装置，该显示装置包括上述任意一种的阵列基板。本公开实施例中的显示装置可以为：显示面板(如液晶显示面板、有机发光二极管显示面板等)、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
作为一种示例，图8为本公开实施例提供的一种显示装置的结构示意图。所述显示装置包括上述任意一种显示面板，该显示装置的显示区AA内包括行列设置的子像素02。图8中并未示出周边区BB的详细结构。
本公开中，“至少一个”指的是一个或多个，“多个”指的是两个或两个以上。“以下至少一项”或其类似表达，指的是这些项中的任意组合，包括单项或复数项的任意组合。例如，a，b或c中的至少一项，可以表示：a，b，c，a+b，a+c，b+c，以及a+b+c，其中，a、b、c可以是单项也可以是多项。
需要指出的是，在附图中，为了图示的清晰可能夸大了部分或全部的层的尺寸，或者部分或全部区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间惟一 的层，或还可以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
在本公开中，术语“第一”、“第二”等仅被配置为描述目的，而不能理解为指示或暗示相对重要性。两个导体“连接”所指的是这两个导体直接的或间接的连接，并且，这两个导体能够传输电信号。
需要说明的是，本公开实施例提供的方法实施例能够与相应的阵列基板实施例相互参考，本公开实施例对此不做限定。本公开实施例提供的方法实施例步骤的先后顺序能够进行适当调整，步骤也能够根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，所述衬底基板包括显示区和至少位于所述显示区一侧的周边区；
    多个子像素，位于所述显示区；
    多条数据线，位于所述显示区，被配置为向所述多个子像素提供数据信号；
    多条第一电源线，位于所述显示区，被配置为向所述多个子像素提供电源信号；
    多条数据线引线，位于所述周边区且与所述多条数据线电连接；
    多个选择开关，位于所述周边区且间隔排列，所述多个选择开关位于所述多条数据线引线远离所述显示区的一侧，至少部分所述多个选择开关中的每一个电连接所述多条数据线引线中的至少两条数据线引线；
    多条数据信号输入线，位于所述周边区且位于所述多个选择开关远离所述显示区的一侧，至少部分所述多个选择开关中的每一个电连接所述多条数据信号输入线中的一条；
    第一电源总线，位于所述周边区，且位于所述多个选择开关远离所述显示区的一侧；
    多个连接部，与所述第一电源总线电连接，且与所述多条第一电源线电连接，所述多个连接部沿着所述多个选择开关之间的区域向所述显示区延伸。
  2. 根据权利要求1所述的阵列基板，还包括位于所述多个选择开关和所述显示区之间的第二电源总线；
    其中，所述多个连接部分别与所述第一电源总线和所述第二电源总线电连接。
  3. 根据权利要求2所述的阵列基板，其中，所述第一电源总线与所述第二电源总线位于同一层。
  4. 根据权利要求2所述的阵列基板，其中，所述第一电源总线、所述第二电源总线和所述多个连接部位于同一层。
  5. 根据权利要求2至4任一所述的阵列基板，其中，所述第一电源总线、所述第二电源总线和所述多个连接部限定出阵列排布的多个第一开口，所述多个选择开关在所述衬底基板上的正投影位于所述多个第一开口中。
  6. 根据权利要求2至5任一所述的阵列基板，还包括第三电源总线，
    所述第三电源总线在所述衬底基板上的正投影和所述第一电源总线在所述衬底基板上的正投影至少部分重叠，且所述第三电源总线与所述第一电源总线电连接。
  7. 根据权利要求6所述的阵列基板，还包括第四电源总线，
    所述第四电源总线在所述衬底基板上的正投影和所述第二电源总线在所述衬底基板上的正投影至少部分重叠，且所述第四电源总线与所述第二电源总线电连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第三电源总线和所述第四电源总线位于同一层。
  9. 根据权利要求2至8任一所述的阵列基板，其中，所述多个子像素中的至少一个包含驱动薄膜晶体管和连接电极；
    所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的驱动源极和驱动漏极；
    所述连接电极位于所述驱动源极和所述驱动漏极远离所述衬底基板的一侧；
    所述第一电源总线与所述第二电源总线与所述连接电极位于同一层。
  10. 根据权利要求7至8任一所述的阵列基板，其中，所述多个子像素中的至少一个包含驱动薄膜晶体管和连接电极；
    所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱 动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的驱动源极和驱动漏极；所述连接电极位于所述驱动源极和所述驱动漏极远离所述衬底基板一侧；
    所述第三电源总线、所述第四电源总线与所述驱动源极位于同一层，或所述第三电源总线、所述第四电源总线与所述驱动漏极位于同一层。
  11. 根据权利要求1至10任一所述的阵列基板，其中，所述选择开关包括：
    位于所述衬底基板上的第一有源层；
    位于所述第一有源层远离所述衬底基板一侧的第一栅极和第二栅极，所述第一栅极和第二栅极位于同一层且不交叠；
    位于所述第一栅极和所述第二栅极远离所述衬底基板一侧的第一源极、第一漏极和第二漏极，所述第一源极、第一漏极和第二漏极位于同一层且不交叠，所述第一源极位于所述第一漏极和所述第二漏极之间；
    所述第一源极与所述多条数据信号输入线中的一条数据信号输入线电连接，所述第一漏极、所述第二漏极与所述多条数据线引线中的一条数据线引线电连接。
  12. 根据权利要求11所述的阵列基板，其中，所述第一栅极、所述第二栅极中的每个栅极在所述衬底基板上的正投影，与所述第一源极、所述第一漏极和所述第二漏极在所述衬底基板上的正投影不交叠。
  13. 根据权利要求12所述的阵列基板，还包括第一控制线和第二控制线；
    所述第一控制线与所述第一栅极电连接，所述第二控制线与所述第二栅极电连接；
    所述第一控制线和所述第二控制线在所述衬底基板的正投影与所述多个第一开口在所述衬底基板上的正投影交叠。
  14. 根据权利要求13所述的阵列基板，其中，所述多个连接部中的至少一个包括第二开口，所述第二开口在所述衬底基板的正投影与所述第一控制线和所述第二控制线在所述衬底基板的正投影均交叠。
  15. 根据权利要求11至14任一所述的阵列基板，其中，所述多条数据线引线与所述第一栅极或所述第二栅极位于同一层。
  16. 根据权利要求11至15任一所述的阵列基板，其中，所述多条数据信号输入线包括第一数据信号输入线和第二数据信号输入线，所述第一数据信号输入线和所述第二数据信号输入线交替排布，且所述第一数据信号输入线和所述第二数据信号输入线位于不同层。
  17. 根据权利要求16所述的阵列基板，其中，所述多个子像素中的至少一个包含驱动薄膜晶体管、连接电极和存储电容；
    所述驱动薄膜晶体管包含位于所述衬底基板上的驱动有源层，位于所述驱动有源层远离所述衬底基板一侧的驱动栅极，位于所述驱动栅极远离所述衬底基板一侧的栅绝缘层，位于所述栅绝缘层远离所述衬底基板一侧的层间介质层，以及位于所述层间介质层远离所述衬底基板一侧的驱动源极和驱动漏极；所述连接电极位于所述驱动源极和所述驱动漏极远离所述衬底基板一侧；
    所述存储电容包括第一电容电极和第二电容电极，所述第一电容电极与所述驱动栅极位于同一层，所述第二电容电极位于所述栅绝缘层和所述层间介质层之间；
    所述第一数据信号输入线与所述驱动栅极位于同一层，所述第二数据信号输入线与所述第二电容电极位于同一层。
  18. 根据权利要求17所述的阵列基板，其中，所述第一有源层与所述驱动有源层位于同一层，所述第一栅极与所述驱动栅极位于同一层，所述第一源极与所述驱动源极位于同一层。
  19. 根据权利要求17或18所述的阵列基板，其中，所述多个子像素中的至少一个还包括：位于所述连接电极远离所述衬底基板一侧的发光二极管，且所述驱动漏极、所述连接电极以及所述发光二极管依次连接。
  20. 一种显示装置，包括权利要求1至19任一所述的阵列基板。
PCT/CN2019/111057 2019-10-14 2019-10-14 阵列基板及显示装置 WO2021072600A1 (zh)

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