WO2021008020A1 - 驱动电路 - Google Patents

驱动电路 Download PDF

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Publication number
WO2021008020A1
WO2021008020A1 PCT/CN2019/116578 CN2019116578W WO2021008020A1 WO 2021008020 A1 WO2021008020 A1 WO 2021008020A1 CN 2019116578 W CN2019116578 W CN 2019116578W WO 2021008020 A1 WO2021008020 A1 WO 2021008020A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrode
electrically connected
pull
stage
Prior art date
Application number
PCT/CN2019/116578
Other languages
English (en)
French (fr)
Inventor
张盛东
廖聪维
韩佰祥
薛炎
张留旗
曹昆
张玮
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Publication of WO2021008020A1 publication Critical patent/WO2021008020A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present invention relates to the field of display driving technology, in particular to a driving circuit.
  • the conventional driving circuit is electrically connected to the pixel unit in the display panel through the scan line in the display panel, and the driving circuit is used to drive the pixel unit to display an image.
  • the conventional driving circuit includes multiple oxide thin film transistors. Due to the manufacturing process, the threshold voltage (Vth) of the oxide thin film transistors between different batches actually produced may have a certain deviation.
  • the traditional driving circuit is greatly affected by the threshold voltage of the oxide thin film transistor, which causes the output of the traditional driving circuit to be unstable, and even causes poor function of the driving circuit.
  • the object of the present invention is to provide a driving circuit which can make the output of the driving circuit more stable.
  • a driving circuit includes at least two gate driving unit circuits, at least two of the gate driving unit circuits are electrically connected in a cascade connection; at least two of the gate driving unit circuits are in the Nth stage Gate drive unit circuit and clock signal terminal, high potential terminal, previous stage scan output terminal, previous stage cascade output terminal, first low potential terminal, second low potential terminal, current stage cascade output terminal, and current stage scan output
  • the Nth stage gate drive unit circuit is also electrically connected to at least one of the first initialization signal terminal, the second initialization signal terminal, and at least one of the subsequent cascade output terminal and the reset signal terminal , Where N is an integer greater than or equal to 1;
  • the N-th stage gate drive unit circuit includes an input part, a pull-down control part, a pull-down part, and a driving part; the input part is used to control the N-th stage gate
  • the first node of the driving unit circuit is precharged so that the fifth transistor and the sixth transistor in the driving part are turned on in advance, and the second node of the pull
  • the input part is electrically connected to the previous-stage scan output terminal, the previous-stage cascade output terminal, the clock signal terminal, the current stage cascade output terminal, and the first node.
  • the input part includes a first transistor, a second transistor, and a third transistor; the first electrode of the first transistor is electrically connected to the output terminal of the previous stage cascade and the first electrode of the second transistor , The second electrode of the first transistor is electrically connected to the scan output terminal of the previous stage, the third electrode of the first transistor and the second electrode of the second transistor, and the second electrode of the third transistor.
  • the third electrode of the second transistor is electrically connected to the first node, and the first electrode of the third transistor is electrically connected to the clock signal terminal; the third electrode of the third transistor is electrically connected to the clock signal terminal;
  • the three poles are electrically connected to the cascade output terminal of the current stage, or the first pole of the third transistor is electrically connected to the clock signal terminal.
  • the pull-down part is connected to the first node, the third node, the first low potential terminal, the second low potential terminal, the cascaded output terminal of the current stage, the The scan output terminal of the current stage and the subsequent cascade output terminal are electrically connected;
  • the pull-down part includes a fourth transistor, a fifteenth transistor, and an eighteenth transistor; the first electrode of the fourth transistor is connected to the The three-node, the first pole of the fifteenth transistor and the first pole of the eighteenth transistor are electrically connected, the second pole of the fourth transistor is electrically connected to the first node, and the The third electrode of the four-transistor is electrically connected to the second electrode of the fifteenth transistor and the cascade output terminal of the current stage, and the third electrode of the fifteenth transistor is electrically connected to the first low potential terminal connection.
  • a driving circuit includes at least two gate driving unit circuits, at least two of the gate driving unit circuits are electrically connected in a cascade connection; at least two of the gate driving unit circuits are in the Nth stage Gate drive unit circuit and clock signal terminal, high potential terminal, previous stage scan output terminal, previous stage cascade output terminal, first low potential terminal, second low potential terminal, current stage cascade output terminal, and current stage scan output
  • the Nth stage gate drive unit circuit is also electrically connected to at least one of the first initialization signal terminal, the second initialization signal terminal, and at least one of the subsequent cascade output terminal and the reset signal terminal , Where N is an integer greater than or equal to 1;
  • the N-th stage gate drive unit circuit includes an input part, a pull-down control part, a pull-down part, and a driving part; the input part is used to control the N-th stage gate
  • the first node of the driving unit circuit is precharged so that the fifth transistor and the sixth transistor in the driving part are turned on in advance, and the second node of the pull
  • the input part is electrically connected to the previous-stage scan output terminal, the previous-stage cascade output terminal, the clock signal terminal, the current stage cascade output terminal, and the first node.
  • the input part includes a first transistor, a second transistor, and a third transistor; the first electrode of the first transistor is electrically connected to the output terminal of the previous stage cascade and the first electrode of the second transistor , The second electrode of the first transistor is electrically connected to the scan output terminal of the previous stage, the third electrode of the first transistor and the second electrode of the second transistor, and the second electrode of the third transistor.
  • the third electrode of the second transistor is electrically connected to the first node, and the first electrode of the third transistor is electrically connected to the clock signal terminal; the third electrode of the third transistor is electrically connected to the clock signal terminal;
  • the three poles are electrically connected to the cascade output terminal of the current stage, or the first pole of the third transistor is electrically connected to the clock signal terminal.
  • the pull-down control part is connected to the first initialization signal terminal, the second initialization signal terminal, the high potential terminal, the first low potential terminal, and the previous stage cascade output terminal ,
  • the current stage cascade output terminal, the subsequent stage cascade output terminal and the third node are electrically connected;
  • the pull-down control part includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, An eleventh transistor and a coupling capacitor;
  • the first electrode of the seventh transistor is electrically connected to the second initialization signal terminal, the second electrode of the seventh transistor is connected to the high potential terminal, and the eighth transistor
  • the second electrode of the seventh transistor is electrically connected to the second electrode of the ninth transistor, the third electrode of the seventh transistor is electrically connected to the second node, and the first electrode of the eighth transistor is electrically connected to The output terminal of the latter stage cascade or the reset signal terminal, the third electrode of the eighth transistor, the third electrode of the seventh transistor, the first electrode of the ninth transistor, and the tenth transistor
  • the coupling capacitor is used to make the second node bootstrap to a higher potential than the high potential end as the potential of the third node rises, so as to reduce the threshold voltage bias timing The impact of the threshold loss on the potential of the third node and the increase in the resistance of the third node to leakage when the threshold voltage is negative.
  • the pull-down control section further includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, the first pole of the twelfth transistor is connected to the cascaded output terminal of the current stage, and the The first electrode of the thirteenth transistor is electrically connected, the second electrode of the twelfth transistor is electrically connected to the third electrode of the eighth transistor, and the third electrode of the twelfth transistor is electrically connected to the third electrode of the eighth transistor.
  • the second electrode of the thirteenth transistor is electrically connected to the second electrode of the fourteenth transistor
  • the first electrode of the fourteenth transistor is electrically connected to the first initialization signal terminal
  • the thirteenth transistor The third electrode of the fourteenth transistor and the third electrode of the fourteenth transistor are electrically connected to the first low potential terminal.
  • the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor of the pull-down control part constitute two sets of STT leakage prevention A circuit structure to suppress the charge leakage of the second node
  • the seventh transistor of the pull-down control part serves as the feedback tube of the two sets of the STT anti-leakage circuit structure to cut off the possible leakage of the second node A path to prevent leakage of the second node.
  • the pull-down control part further includes the fourteenth transistor, the first electrode of the fourteenth transistor is electrically connected to the first initialization signal terminal, and the first electrode of the fourteenth transistor is electrically connected to the first initialization signal terminal.
  • the two electrodes are electrically connected to the third node, and the third electrode of the fourteenth transistor is electrically connected to the first low potential terminal.
  • the pull-down control part further includes a twelfth transistor and a thirteenth transistor, the first pole of the twelfth transistor is connected to the cascaded output terminal of the current stage and the The first electrode is electrically connected, the second electrode of the twelfth transistor is electrically connected to the third electrode of the eighth transistor, and the third electrode of the twelfth transistor is electrically connected to the third electrode of the thirteenth transistor.
  • the two poles are electrically connected, and the third pole of the thirteenth transistor is electrically connected to the first low potential terminal.
  • the reset signal at the reset signal terminal is used to change the first stage after the current stage scan signal at the current stage scan output terminal and before the clock signal at the clock signal terminal jumps to high again.
  • a node is discharged to a low level
  • the reset signal is also used to control the eighth transistor to turn on after jumping to a high level to charge the second node and turn on the ninth transistor,
  • the third node is pulled up to a high potential.
  • the pull-down part is connected to the first node, the third node, the first low potential terminal, the second low potential terminal, the cascaded output terminal of the current stage, the The scan output terminal of the current stage and the subsequent cascade output terminal are electrically connected;
  • the pull-down part includes a fourth transistor, a fifteenth transistor, and an eighteenth transistor; the first electrode of the fourth transistor is connected to the The three-node, the first pole of the fifteenth transistor and the first pole of the eighteenth transistor are electrically connected, the second pole of the fourth transistor is electrically connected to the first node, and the The third electrode of the four-transistor is electrically connected to the second electrode of the fifteenth transistor and the cascade output terminal of the current stage, and the third electrode of the fifteenth transistor is electrically connected to the first low potential terminal connection.
  • the second electrode of the eighteenth transistor is electrically connected to the scan output terminal of the current stage, and the third electrode of the eighteenth transistor is electrically connected to the second low potential terminal.
  • the pull-down part further includes a sixteenth transistor and a seventeenth transistor; the first pole of the sixteenth transistor is cascaded with the output terminal of the subsequent stage, and the first pole of the seventeenth transistor Electrically connected, the second electrode of the sixteenth transistor is electrically connected to the cascade output terminal of the current stage, and the third electrode of the sixteenth transistor is electrically connected to the first low potential terminal; The second pole of the seventeenth transistor is electrically connected to the first pole of the decoupling capacitor of the driving part and the second pole of the eighteenth transistor, and the third pole of the seventeenth transistor is electrically connected to the The second low potential terminal and the third electrode of the eighteenth transistor are electrically connected.
  • the driving part is electrically connected to the clock signal terminal, the first node, the cascade output terminal of the current stage, and the scan output terminal of the current stage;
  • the driving part includes a fifth transistor, a sixth transistor, and Decoupling capacitor;
  • the first electrode of the fifth transistor is electrically connected to the first node, the first electrode of the sixth transistor, and the second electrode of the decoupling capacitor, and the first electrode of the fifth transistor
  • the two poles are electrically connected to the clock signal terminal and the second pole of the sixth transistor, the third pole of the fifth transistor is electrically connected to the cascade output terminal of the current stage, and the sixth transistor
  • the third pole is electrically connected to the scan output terminal of the current stage.
  • the clock signal at the clock signal terminal is an M-phase clock signal, where M is an integer greater than or equal to 2; the Nth stage gate drive unit circuit and the N+1th stage gate drive unit The circuits are respectively electrically connected with clock signal terminals corresponding to different clock signals.
  • the reset signal terminal is connected to the N+k-th stage cascade output terminal, where k is an integer greater than or equal to 2.
  • the pull-down control part is further configured to utilize the first initialization signal of the first initialization signal terminal and the first initialization signal of the second initialization signal terminal in the initialization phase and the pull-down phase in the pull-down and low-level maintenance phase.
  • Two initialization signals, as well as the front-stage cascade output signal of the front-stage cascade output terminal and the rear-stage cascade output signal of the rear-stage cascade output terminal bootstrap the second node twice to ensure the The third node can achieve full swing output before and after the output of this stage.
  • the first node is located between the third pole of the second transistor of the input part and the first pole of the fifth transistor of the driving part; the second node is located in the pull-down control Part of the third electrode of the seventh transistor and the first electrode of the coupling capacitor of the pull-down control section; the third node is located between the first electrode of the eighteenth transistor of the pull-down section and the pull-down control section Between the second pole of the fourteenth transistor.
  • the pull-down control structure includes an STT anti-leakage circuit structure, so the third node in the drive circuit can be biased positively and negatively at the threshold voltage of the transistor. At any time, it can be pulled up to the potential of the high potential end, thereby ensuring that the pull-down transistor in the driving circuit is in a good turn-on state, the output is more stable, and the driving circuit can work in a larger threshold voltage range.
  • FIG. 1 is a schematic diagram of the driving circuit of the present invention
  • FIG. 2 is a circuit diagram of a first embodiment of an Nth stage gate driving unit circuit in the driving circuit shown in FIG. 1;
  • FIG. 3 is a waveform diagram of signals in the N-th stage gate driving unit circuit shown in FIG. 2;
  • FIG. 4 is a circuit diagram of a second embodiment of the Nth stage gate driving unit circuit in the driving circuit shown in FIG. 1;
  • FIG. 5 is a waveform diagram of signals in the N-th stage gate driving unit circuit shown in FIG. 4;
  • FIG. 6 is a circuit diagram of a third embodiment of the N-th stage gate driving unit circuit in the driving circuit shown in FIG. 1;
  • FIG. 7 is a circuit diagram of a fourth embodiment of the Nth stage gate driving unit circuit in the driving circuit shown in FIG. 1;
  • FIG. 8 is a circuit diagram of a fifth embodiment of the Nth stage gate driving unit circuit in the driving circuit shown in FIG. 1;
  • FIG. 9 is a waveform diagram of signals in the N-th stage gate driving unit circuit shown in FIG. 8.
  • the driving circuit of the present invention is applied to a display panel, and the display panel may be a TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display panel), OLED (Organic Light Emitting Diode, organic light emitting diode display panel), etc.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display panel
  • OLED Organic Light Emitting Diode, organic light emitting diode display panel
  • the driving circuit is electrically connected to the pixel unit in the display panel, and the driving circuit is used to send a driving signal (scanning signal) to the pixel unit to drive the pixel unit to display an image.
  • FIG. 1 is a schematic diagram of the driving circuit of the present invention
  • FIG. 2 is a circuit diagram of a first embodiment of the Nth stage gate driving unit circuit in the driving circuit shown in FIG. 3 is a waveform diagram of signals in the Nth stage gate driving unit circuit shown in FIG. 2.
  • the driving circuit of this embodiment includes P (stages) of cascaded gate driving unit circuits, and P (stages) of the gate driving unit circuits are electrically connected in a cascade manner. That is, P (stages) of the gate drive unit circuits are electrically connected in a cascade manner. As shown in Figure 1. Wherein, P is an integer greater than or equal to 2.
  • the driving circuit also includes a first initialization signal terminal STV1, a second initialization signal terminal STV2, a clock signal terminal CLK, a high potential terminal VGH, a previous scan output terminal G (N-1), and a previous cascade output terminal C ( N-1), the subsequent stage cascade output terminal C (N+1), the first low potential terminal VSSL, the second low potential terminal VSS, the current stage cascade output terminal C (N), and the current stage scan output terminal G ( N).
  • the gate driving unit circuit is used to generate a driving signal (scan signal) to control the on or off of the thin film transistor switch in the pixel unit of the display panel, thereby driving the pixel unit to display an image.
  • a driving signal scan signal
  • the term "previous stage” refers to the N-1th stage in the drive circuit, where N is greater than or equal to 1, and less than or equal to An integer of P, for example, the scan output terminal G(N-1) of the previous stage refers to the scan output terminal G(N-1) in the gate drive unit circuit of the N-1th stage; the term “this stage” refers to the The Nth stage in the driving circuit, for example, the cascade output terminal C(N) of this stage refers to the cascade output terminal of the gate drive unit circuit of the Nth stage, and the scan output terminal G(N) of this stage refers to the Nth stage The scan output terminal of the gate drive unit circuit; the term "post-stage” refers to the N+1th stage in the drive circuit, for example, the latter cascade output terminal C(N+1) refers to the N+1th stage The cascade output terminal of the gate drive unit circuit.
  • the transistors in this embodiment can be a thin film field effect transistor
  • the first electrode of the transistor can be the gate of the thin film field effect transistor
  • the second electrode of the transistor can be the drain or source of the thin film field effect transistor
  • the third electrode of the transistor It can be the source or drain of a thin film field effect transistor. Both the source and drain of the transistor in this embodiment can vary with the bias state of the transistor.
  • the Nth stage gate drive unit circuit in the P (stages) cascaded gate drive unit circuits is connected to the first initialization signal terminal STV1, the second initialization signal terminal STV2, the clock signal terminal CLK, the high potential terminal VGH, Pre-scan output terminal G (N-1), pre-stage cascade output terminal C (N-1), post-stage cascade output terminal C (N+1), first low potential terminal VSSL, second low potential terminal VSS, the cascade output terminal C(N) of this stage and the scan output terminal G(N) of this stage are electrically connected.
  • the Nth stage gate driving unit circuit includes an input part 10, a pull-down control part 20, a driving part 30, and a pull-down part 40.
  • the input portion 10 is electrically connected to the pull-down control portion 20 and the drive portion 30, the pull-down control portion 20 is electrically connected to the pull-down portion 40, and the pull-down portion 40 is electrically connected to the drive portion 30.
  • sexual connection is electrically connected to the pull-down control portion 20 and the drive portion 30.
  • the input part 10 is connected to the previous stage scan output terminal G (N-1), the previous stage cascade output terminal C (N-1), the clock signal terminal CLK, the current stage cascade output terminal C (N), and the A node Q is electrically connected.
  • the first node Q is located between the input portion 10 and the driving portion 30. Specifically, the first node Q is located between the third electrode of the second transistor T2 of the input portion 10 and the Between the first pole of the fifth transistor T5 of the driving part 30.
  • the input part 10 is used to precharge the first node Q of the current stage (the Nth gate drive unit circuit), so that the fifth transistor T5 and the sixth transistor T6 in the driving part 30 are turned on in advance , To prepare for the output of the current-level scan signal at the current-level scan output terminal G(N) and the current-level cascade output signal at the current-level cascade output terminal C(N); at the same time, the input part 10 is also used to The second node IQ of the pull-down control section 20 and the third node QB of the pull-down section 40 are pulled down to a low potential, so that the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor in the pull-down section 40 The transistor T18 is turned off in advance to prevent the transistors in the pull-down section 40 (including the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18) from leaking at the initial moment of the pull-up phase S3, thereby improving the drive circuit Drive speed and reduce power consumption.
  • the second node IQ is located inside the pull-down control section 20, specifically, the second node IQ is located at the third pole of the seventh transistor T7 of the pull-down control section 20 and the pull-down control section 20 Between the first pole of the coupling capacitor CI.
  • the third node QB is located inside the pull-down portion 40 (that is, between the pull-down portion 40 and the pull-down control portion 20). Specifically, the third node QB is located on the first side of the pull-down portion 40. Between the first pole of the eighteenth transistor T18 and the second pole of the fourteenth transistor T14 of the pull-down control section 20.
  • the input part 10 includes a first transistor T1, a second transistor T2, and a third transistor T3.
  • the first electrode of the first transistor T1 is electrically connected to the previous stage cascade output terminal C(N-1) and the first electrode of the second transistor T2, and the second electrode of the first transistor T1 is electrically connected to the previous stage scan output Terminal G (N-1), the third electrode of the first transistor T1 is electrically connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3; the third electrode of the second transistor T2 is electrically connected to The first node Q; the first pole of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the third pole of the third transistor T3 is electrically connected to the cascade output terminal C(N) of this stage.
  • the pull-down control part 20 is connected to the first initialization signal terminal STV1, the second initialization signal terminal STV2, the high potential terminal VGH, the first low potential terminal VSSL, the previous stage cascade output terminal C(N-1), the current stage The cascade output terminal C(N), the subsequent cascade output terminal C(N+1), and the third node QB are electrically connected.
  • the pull-down control part 20 is used to generate a control signal for controlling the pull-down part 40, and the control signal is at a low level during the precharge stage S2 and the pull-up stage S3, so that the transistors in the pull-down part 40 (including The fourth transistor T4, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18) are turned off; the control signal is at a high level during the pull-down and low-level maintenance phase S4 to The transistors in the pull-down section 40 (including the fourth transistor T4, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18) are turned on.
  • the pull-down control part 20 includes a coupling capacitor CI for enabling the second node IQ to be bootstrapped to a higher potential than the high potential terminal VGH as the potential of the third node QB rises to reduce The influence of the threshold loss on the potential of the third node QB when the threshold voltage is positive and the resistance of the third node QB to leakage when the threshold voltage is negative (ie, the charge leakage of the third node QB is suppressed).
  • the pull-down control section 20 is configured to use the first initialization signal of the first initialization signal terminal STV1 and the first initialization signal of the second initialization signal terminal STV2 during the pull-down phase in the initialization phase S1 and the pull-down and low-level maintenance phase S4.
  • Two initialization signals, as well as the front-stage cascade output signal of the front-stage cascade output terminal C (N-1) and the rear-stage cascade output signal of the rear-stage cascade output terminal C (N+1) carry out the second node IQ Two bootstraps, so as to ensure that the third node QB can achieve full swing output before and after the output of this stage, which helps to stabilize the output.
  • the pull-down control section 20 adopts an STT (Series connected Two-Transistor) anti-leakage circuit structure for leakage protection, that is, the ninth transistor T9 and the second transistor T9 of the pull-down control section 20
  • the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 constitute two sets of STT anti-leakage circuit structures to suppress the charge leakage of the second node IQ.
  • the seventh transistor of the pull-down control part 20 T7 serves as the feedback tube of two sets of STT anti-leakage circuit structures to cut off the possible leakage path of the second node IQ and prevent the second node IQ from leakage, thereby increasing the anti-leakage capability of the pull-down control part 20.
  • the structure of the STT anti-leakage circuit is a circuit structure including transistor A, transistor B, and transistor C.
  • Transistor A, transistor B, and transistor C are thin film field effect transistors, wherein the first electrode of transistor A is electrically connected to the first electrode of transistor B.
  • the third electrode of the transistor A is electrically connected to the second electrode of the transistor B and the second electrode of the transistor C.
  • the pull-down control section 20 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14. And the coupling capacitor CI.
  • the first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal STV2, the second electrode of the seventh transistor T7 and the high potential terminal VGH, the second electrode of the eighth transistor T8 and the second electrode of the ninth transistor T9
  • the third electrode of the seventh transistor T7 is electrically connected to the second node IQ; the first electrode of the eighth transistor T8 is electrically connected to the subsequent cascade output terminal C(N+1), and the eighth transistor T8
  • the third pole of the ninth transistor T9 is electrically connected to the second pole of the coupling capacitor CI and the third node QB; the first pole of the tenth transistor T10 is connected to the previous stage cascade output terminal C(N-1) and The first electrode of the eleventh transistor T11 is electrically connected, the third electrode of the ten
  • the third electrode of the twelve transistor T12 and the second electrode of the thirteenth transistor T13 are electrically connected, the third electrode of the eleventh transistor T11 and the first low potential terminal VSSL, the third electrode of the thirteenth transistor T13, and the The third pole of the fourteenth transistor T14 is electrically connected; the first pole of the twelfth transistor T12 is electrically connected to the cascade output terminal C(N) of the current stage and the first pole of the thirteenth transistor T13; the fourteenth transistor The first pole of T14 is electrically connected to the first initialization signal terminal STV1.
  • the pull-down part 40 is connected to the first node Q, the third node QB, the first low potential terminal VSSL, the second low potential terminal VSS, the current stage cascade output terminal C (N), and the current stage scan output terminal G (N) And the subsequent stage cascade output terminal C(N+1) is electrically connected.
  • the pull-down section 40 includes a fourth transistor T4, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18.
  • the pull-down section 40 is used to scan the output terminal G( After the current level scan signal of N) is output, pull down the potential of the first node Q, the current level cascade output terminal C (N) and the current level scan output terminal G (N) to a low level, and pull it down before the next output Keep it low.
  • the fourth transistor T4 the fifteenth transistor T15 of the pull-down part 40, and the fifth transistor T5 of the driving part 30 form an STT anti-leakage circuit structure to prevent leakage of the first node Q and ensure Pull up speed.
  • the first node Q is connected to the first low-potential terminal VSSL through the fourth transistor T4 and the fifteenth transistor T15, and is not in a floating state (that is, the first node Q is maintained at Low potential) to reduce the potential fluctuations at the first node Q caused by the clock feedthrough effect, and stabilize the output, that is, in the low-level sustaining phase in the pull-down and low-level sustaining phase S4, the pull-down portion 40
  • the fourth transistor T4 connects the first node Q with the cascade output terminal C(N) of the current stage, and stabilizes the potential of the first node Q to stabilize the output.
  • the fifteenth transistor T15 and the eighteenth transistor T18 under the control of the pull-down control section 20 respectively continuously discharge the cascade output terminal C (N) of the current stage and the scan output terminal G (N) of the current stage to stabilize the output. At low potential.
  • the first electrode of the fourth transistor T4 is electrically connected to the third node QB, the first electrode of the fifteenth transistor T15, and the first electrode of the eighteenth transistor T18, and the second electrode of the fourth transistor T4 is electrically connected to the A node Q, the third pole of the fourth transistor T4 is electrically connected to the second pole of the fifteenth transistor T15, the second pole of the sixteenth transistor T16, and the cascade output terminal C(N) of this stage; fifteenth The third pole of the transistor T15 is electrically connected to the first low potential terminal VSSL and the third pole of the sixteenth transistor T16; the first pole of the sixteenth transistor T16 and the subsequent cascade output terminal C(N+1) are connected to The first electrode of the seventeenth transistor T17 is electrically connected; the second electrode of the seventeenth transistor T17 is electrically connected to the first electrode of the decoupling capacitor CS of the driving part 30 and the second electrode of the eighteenth transistor T18 , The third electrode of the seventeenth transistor T17 is electrically connected to the
  • the driving part 30 is electrically connected to the clock signal terminal CLK, the first node Q, the cascade output terminal C(N) of the current stage, and the scan output terminal G(N) of the current stage.
  • the driving part 30 is used to transfer the clock signal of the clock signal terminal CLK to the cascade output terminal C(N) of the current stage and the scan output terminal G(N) of the current stage when the first node Q is at a high potential, and When the clock signal of the clock signal terminal CLK is at a high level, the potential of the first node Q is coupled to a higher potential, thereby increasing the driving speed.
  • the driving part 30 includes a fifth transistor T5, a sixth transistor T6 and a decoupling capacitor CS.
  • the first electrode of the fifth transistor T5 is electrically connected to the first node Q, the first electrode of the sixth transistor T6, and the second electrode of the decoupling capacitor CS.
  • the second electrode of the fifth transistor T5 is electrically connected to the clock signal terminal CLK and the second electrode of the decoupling capacitor CS.
  • the second pole of the six transistor T6 is electrically connected, the third pole of the fifth transistor T5 is electrically connected to the cascade output terminal C(N) of this stage; the third pole of the sixth transistor T6 is electrically connected to the scan output of this stage End G(N).
  • the clock signal of the clock signal terminal CLK is an M-phase clock signal (M is an integer greater than or equal to 2).
  • the clock signal of the clock signal terminal CLK is a 2-phase clock signal, that is, the clock signal terminal CKL includes a first clock signal terminal CK1 and a second clock signal terminal CK2.
  • the first clock signal terminal CK1 The first clock signal in CK2 is different from the second clock signal in the second clock signal terminal CK2.
  • Two adjacent gate drive unit circuits in the drive circuit are electrically connected to clock signal terminals corresponding to different clock signals, for example, the Nth stage gate drive unit circuit and the N+1th stage gate drive unit
  • the circuit is electrically connected to the second clock signal terminal CK2 and the first clock signal terminal CK1, or the Nth stage gate drive unit circuit and the N+1 stage gate drive unit circuit are respectively connected to the first clock signal terminal CK1 and
  • the second clock signal terminal CK2 is electrically connected.
  • the level of the signal in the first low potential terminal VSSL and the second low potential terminal VSS are different, so as to use the voltage reverse bias to reduce possible internal Leakage, the voltage difference between the low level of the signal in the first low potential terminal VSSL and the second low potential terminal VSS may vary with device performance and usage conditions.
  • the Nth stage gate drive unit circuit in this embodiment adopts a bootstrap pull-down control structure with STT leakage prevention (STT leakage prevention circuit structure). Regardless of whether the threshold voltage of the transistor is positive or negative, the Nth gate The pole drive unit circuit can output a full swing high-level signal in the pull-down and low-level maintenance phase S4, which improves the stability of the drive circuit.
  • STT leakage prevention circuit structure STT leakage prevention circuit structure
  • the Nth stage gate drive unit circuit adopts a new pull-down control structure, and the pull-down control section 20 increases the bootstrap of the gate of the pull-up transistor and the STT leakage prevention circuit structure, so that the third node QB is at the threshold voltage
  • Both positive and negative conditions can be pulled up to the potential of the high potential terminal VGH, thus ensuring that the pull-down transistors (including the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18) are in a good turn-on state and the output is more stable. It also enables the drive circuit to work in a larger threshold voltage range. When the threshold voltage is negative, the leakage current of the Nth gate drive unit circuit is smaller, and the multi-stage gate drive unit circuit can still work normally when cascaded, and the delay time is shorter and the response speed is shorter. Faster.
  • the driving circuit of this embodiment also reduces the leakage of the first node Q in the pull-up phase S3, and improves the performance of the driving circuit in the negative threshold region. Secondly, the number of clock signals required by the driving circuit is small, and the working speed is faster, which is beneficial to the realization of high resolution and narrow frame. Specifically, since the Nth stage gate drive unit circuit adopts a new pull-down structure, the fifth transistor T5 is multiplexed as the feedback tube of the STT anti-leakage circuit structure, which not only prevents the pull-down tube from leaking to the first node Q, but also And the number of transistors is reduced.
  • FIG. 4 is a circuit diagram of a second embodiment of the N-th stage gate driving unit circuit in the driving circuit shown in FIG. 1
  • FIG. 5 is the N-th stage gate driving unit shown in FIG. 4 Waveform diagram of the signal in the circuit.
  • the second embodiment of the driving circuit of the present invention is similar to or similar to the above-mentioned first embodiment, and the difference lies in:
  • the driving circuit further includes a reset signal terminal C(N+k).
  • the first pole of the eighth transistor T8 in the pull-down control part 20 is electrically connected to the reset signal terminal C(N+k), that is, in the above-mentioned first embodiment, the first pole of the eighth transistor T8 is connected to The rear-stage cascade output terminal C(N+1) is replaced with a reset signal terminal C(N+k); the first pole of the sixteenth transistor T16 and the first pole of the seventeenth transistor T17 are electrically connected to the rear Cascade output terminal C(N+1).
  • the reset signal terminal C(N+k) is connected to the N+k-th stage cascade output terminal, and k is an integer greater than or equal to 2. In order to ensure the reliability of the driving circuit, k is preferably less than M.
  • the pull-up transistors (the fifth transistor T5 and the sixth transistor T6) are used to discharge and reduce the fall time , Preferably, k is greater than or equal to 2.
  • the pull-down control part 20 is used to generate a control signal for controlling the pull-down part 40, and the control signal is at a low level during the precharge stage S2 and the pull-up stage S3, so that the pull-down part
  • the transistors in 40 including the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18) are turned off; the control signal is at a high level during the pull-down and low-level maintenance phase S4, so that the pull-down part 40
  • the transistors including the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18 are turned on.
  • the clock signal terminal CLK jumps to a low level
  • the subsequent stage cascade output terminal C(N+1) jumps to a high level.
  • the six transistors T16 and the seventeenth transistor T17 are turned on, and the sixteenth transistor T16 and the seventeenth transistor T17 respectively discharge (output signals) the cascaded output terminal C (N) of the current stage and the scan output terminal G (N) of the current stage.
  • the first node Q still maintains a high potential
  • the fifth transistor T5 and the sixth transistor T6 remain in the on state
  • the fifth transistor T5 and the sixth transistor T6 are respectively connected to the cascaded output terminal C(N) and the scan output terminal of the current stage.
  • G(N) discharge (output signal) to increase the discharge speed.
  • the potential of the first node Q is maintained at a high level to connect the current stage cascaded output terminal C (N) and the current stage scan output
  • the output signal of terminal G(N) is continuously pulled down.
  • the reset signal of the reset signal terminal C (N+k) is used to jump to the clock signal of the clock signal terminal CLK after the current level of scan signal output of the current level of scan output terminal G (N) Before the high level, the first node Q is discharged to a low level, that is, k is less than M.
  • the reset signal of the reset signal terminal C(N+k) is used to control the eighth transistor T8 to turn on after the transition to a high level to charge the second node IQ, and to turn on the ninth transistor T9 to turn on the third The node QB is pulled up to a high potential.
  • the second node IQ is bootstrapped to a higher potential, so the potential of the third node QB can be fully pulled up to the potential of the high potential terminal VGH.
  • the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18 electrically connected to the third node QB are all turned on, and the first node Q is discharged to a low potential through the fourth transistor T4 and the fifteenth transistor T15 .
  • the third node QB maintains a high potential
  • the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18 are continuously turned on.
  • the first node Q, the cascade output terminal C(N) of the current stage and the scan output terminal of the current stage G(N) outputs a stable low-level signal.
  • FIG. 6 is a circuit diagram of a third embodiment of the Nth stage gate driving unit circuit in the driving circuit shown in FIG. 1.
  • the third embodiment of the driving circuit of the present invention is similar to or similar to the above-mentioned second embodiment, except that:
  • the sixteenth transistor T16 and the seventeenth transistor T17 are removed from the pull-down part 40, that is, the pull-down part 40 only includes the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18.
  • the pull-down part 40 is electrically connected to the first node Q, the third node QB, the first low potential terminal VSSL, the second low potential terminal VSS, the cascade output terminal C(N) of the current stage, and the scan output terminal G(N) of the current stage. connection.
  • the first electrode of the fourth transistor T4 is electrically connected to the third node QB, the first electrode of the fifteenth transistor T15, and the first electrode of the eighteenth transistor T18, and the second electrode of the fourth transistor T4 is electrically connected to the A node Q, the third electrode of the fourth transistor T4 is electrically connected to the second electrode of the fifteenth transistor T15 and the cascade output terminal C(N) of this stage; the third electrode of the fifteenth transistor T15 is electrically connected to The first low potential terminal VSSL; the second pole of the eighteenth transistor T18 is electrically connected to the scan output terminal G(N) of the current stage, and the third pole of the eighteenth transistor T18 is electrically connected to the second low potential terminal VSS.
  • the waveform diagram of the signals in the N-th stage gate driving unit circuit of this embodiment is the same as that of FIG. 5 described above.
  • FIG. 7 is a circuit diagram of a fourth embodiment of the N-th stage gate driving unit circuit in the driving circuit shown in FIG. 1.
  • the fourth embodiment of the driving circuit of the present invention is similar to or similar to the above-mentioned second or third embodiment, and the difference lies in:
  • the feedback tube (the twelfth transistor T12 and the second transistor T12 and the second transistor T12) introduced from the cascade output terminal C(N) of the current stage in the pull-down control section 20
  • the thirteen transistor T13) is removed to simplify the circuit. That is, in this embodiment, the pull-down control unit 20 removes the twelfth transistor T12 and the thirteenth transistor T13.
  • the sixteenth transistor T16 and the seventeenth transistor T17 are removed from the pull-down part 40, that is, the pull-down part 40 only includes the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18.
  • the pull-down control part 20 is connected to the first initialization signal terminal STV1, the second initialization signal terminal STV2, the high potential terminal VGH, the first low potential terminal VSSL, the previous stage cascade output terminal C (N-1), and the reset signal terminal C (N+k) and the third node QB are electrically connected.
  • the pull-down control section 20 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a fourteenth transistor T14, and a coupling capacitor CI.
  • the first electrode of the eighth transistor T8 is electrically connected to the reset signal terminal C (N+k), the third electrode of the eighth transistor T8 and the third electrode of the seventh transistor T7, the first electrode and the second electrode of the ninth transistor T9
  • the second electrode of the tenth transistor T10 and the first electrode of the coupling capacitor CI are electrically connected;
  • the second electrode of the eleventh transistor T11 is electrically connected to the third electrode of the tenth transistor T10 and the second electrode of the fourteenth transistor T14 ,
  • the third electrode of the eleventh transistor T11 is electrically connected to the first low potential terminal VSSL and the third electrode of the fourteenth transistor T14;
  • the first electrode of the fourteenth transistor T14 is electrically connected to the first initialization signal terminal STV1 .
  • the waveform diagram of the signals in the N-th stage gate driving unit circuit of this embodiment is the same as that of FIG. 5 described above.
  • FIG. 8 is a circuit diagram of a fifth embodiment of the N-th stage gate driving unit circuit in the driving circuit shown in FIG. 1
  • FIG. 9 is the N-th stage gate driving unit shown in FIG. Waveform diagram of the signal in the circuit.
  • the fifth embodiment of the driving circuit of the present invention is similar to or similar to the above-mentioned third embodiment, and the difference lies in:
  • the fourteenth transistor T14 is removed from the pull-down control section 20.
  • the sixteenth transistor T16 and the seventeenth transistor T17 are removed from the pull-down part 40, that is, the pull-down part 40 only includes the fourth transistor T4, the fifteenth transistor T15, and the eighteenth transistor T18.
  • the first electrode and the third electrode of the third transistor T3 in the input part 10 are electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the third electrode of the first transistor T1 and The first node Q.

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Abstract

一种驱动电路，其中，第N级栅极驱动单元电路包括输入部分（10）、下拉控制部分（20）、下拉部分（40）和驱动部分（30）；下拉控制部分（20）用于产生控制信号，控制信号用于将下拉部分（40）中的晶体管关闭或开启；下拉部分（40）用于将第一节点、驱动电路的本级级联输出端和本级扫描输出端的电位下拉至低电位。本驱动电路能使得输出更加稳定。

Description

驱动电路 技术领域
本发明涉及显示驱动技术领域，特别涉及一种驱动电路。
 背景技术
传统的驱动电路通过显示面板中的扫描线与显示面板中的像素单元电性连接，所述驱动电路用于驱动所述像素单元显示图像。
传统的驱动电路中包括多个氧化物薄膜晶体管，由于制造工艺的原因，实际生产出的不同批次之间的氧化物薄膜晶体管的阈值电压（Vth）可能存在一定的偏差。
传统的驱动电路受氧化物薄膜晶体管的阈值电压影响较大，这导致了传统的驱动电路输出不稳定，甚至造成驱动电路功能不良。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种驱动电路，其能使得驱动电路的输出更加稳定。
 技术解决方案
为解决上述问题，本发明的技术方案如下：
一种驱动电路，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路与时钟信号端、高电位端、前级扫描输出端、前级级联输出端、第一低电位端、第二低电位端、本级级联输出端以及本级扫描输出端电性连接，第N级栅极驱动单元电路还与第一初始化信号端、第二初始化信号端中的至少一者以及后级级联输出端、复位信号端中的至少一者电性连接，其中，N为大于或等于1的整数；所述第N级栅极驱动单元电路包括输入部分、下拉控制部分、下拉部分和驱动部分；所述输入部分用于对所述第N级栅极驱动单元电路的第一节点进行预充电，以使所述驱动部分中的第五晶体管和第六晶体管提前打开，以及用于将所述下拉控制部分的第二节点及所述下拉部分的第三节点下拉至低电位，以使所述下拉部分中的第四晶体管、第十五晶体管和第十八晶体管提前关闭；所述下拉控制部分用于产生控制信号，所述控制信号在预充阶段和上拉阶段为低电平，以将所述下拉部分中的晶体管关闭，所述控制信号在下拉及低电平维持阶段为高电平，以将下拉部分中的晶体管开启；所述下拉部分用于在所述驱动电路的本级扫描输出端的本级扫描信号输出之后，将所述第一节点、所述驱动电路的本级级联输出端和所述本级扫描输出端的电位下拉至低电位，并在下次输出之前将其保持在低电位；所述驱动部分用于在所述第一节点为高电位时，将所述驱动电路的时钟信号端的时钟信号传递至所述本级级联输出端和所述本级扫描输出端，并且在所述时钟信号端的时钟信号为高电平时，将所述第一节点的电位耦合到更高的电位；所述第一节点位于所述输入部分的第二晶体管的第三极与所述驱动部分的第五晶体管的第一极之间；所述第二节点位于所述下拉控制部分的第七晶体管的第三极与所述下拉控制部分的耦合电容的第一极之间；所述第三节点位于所述下拉部分的第十八晶体管的第一极与所述下拉控制部分的第十四晶体管的第二极之间；所述时钟信号端的时钟信号为M相时钟信号，其中，M为大于或者等于2的整数；所述第N级栅极驱动单元电路和第N+1级栅极驱动单元电路分别与对应于不同时钟信号的时钟信号端电性连接。
在上述驱动电路中，所述输入部分与所述前级扫描输出端、所述前级级联输出端、所述时钟信号端、所述本级级联输出端和所述第一节点电性连接；所述输入部分包括第一晶体管、第二晶体管和第三晶体管；所述第一晶体管的第一极与所述前级级联输出端以及所述第二晶体管的第一极电性连接，所述第一晶体管的第二极电性连接于所述前级扫描输出端，所述第一晶体管的第三极与所述第二晶体管的第二极以及所述第三晶体管的第二极电性连接，所述第二晶体管的第三极电性连接于所述第一节点，所述第三晶体管的第一极电性连接于所述时钟信号端；所述第三晶体管的第三极电性连接于所述本级级联输出端，或者所述第三晶体管的第一极电性连接于所述时钟信号端。
在上述驱动电路中，所述下拉部分与所述第一节点、所述第三节点、所述第一低电位端、所述第二低电位端、所述本级级联输出端、所述本级扫描输出端以及所述后级级联输出端电性连接；所述下拉部分包括第四晶体管、第十五晶体管和第十八晶体管；所述第四晶体管的第一极与所述第三节点、所述第十五晶体管的第一极以及所述第十八晶体管的第一极电性连接，所述第四晶体管的第二极电性连接于所述第一节点，所述第四晶体管的第三极与所述第十五晶体管的第二极以及所述本级级联输出端电性连接，所述第十五晶体管的第三极与所述第一低电位端电性连接。
一种驱动电路，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路与时钟信号端、高电位端、前级扫描输出端、前级级联输出端、第一低电位端、第二低电位端、本级级联输出端以及本级扫描输出端电性连接，第N级栅极驱动单元电路还与第一初始化信号端、第二初始化信号端中的至少一者以及后级级联输出端、复位信号端中的至少一者电性连接，其中，N为大于或等于1的整数；所述第N级栅极驱动单元电路包括输入部分、下拉控制部分、下拉部分和驱动部分；所述输入部分用于对所述第N级栅极驱动单元电路的第一节点进行预充电，以使所述驱动部分中的第五晶体管和第六晶体管提前打开，以及用于将所述下拉控制部分的第二节点及所述下拉部分的第三节点下拉至低电位，以使所述下拉部分中的第四晶体管、第十五晶体管和第十八晶体管提前关闭；所述下拉控制部分用于产生控制信号，所述控制信号在预充阶段和上拉阶段为低电平，以将所述下拉部分中的晶体管关闭，所述控制信号在下拉及低电平维持阶段为高电平，以将下拉部分中的晶体管开启；所述下拉部分用于在所述驱动电路的本级扫描输出端的本级扫描信号输出之后，将所述第一节点、所述驱动电路的本级级联输出端和所述本级扫描输出端的电位下拉至低电位，并在下次输出之前将其保持在低电位；所述驱动部分用于在所述第一节点为高电位时，将所述驱动电路的时钟信号端的时钟信号传递至所述本级级联输出端和所述本级扫描输出端，并且在所述时钟信号端的时钟信号为高电平时，将所述第一节点的电位耦合到更高的电位。
在上述驱动电路中，所述输入部分与所述前级扫描输出端、所述前级级联输出端、所述时钟信号端、所述本级级联输出端和所述第一节点电性连接；所述输入部分包括第一晶体管、第二晶体管和第三晶体管；所述第一晶体管的第一极与所述前级级联输出端以及所述第二晶体管的第一极电性连接，所述第一晶体管的第二极电性连接于所述前级扫描输出端，所述第一晶体管的第三极与所述第二晶体管的第二极以及所述第三晶体管的第二极电性连接，所述第二晶体管的第三极电性连接于所述第一节点，所述第三晶体管的第一极电性连接于所述时钟信号端；所述第三晶体管的第三极电性连接于所述本级级联输出端，或者所述第三晶体管的第一极电性连接于所述时钟信号端。
在上述驱动电路中，所述下拉控制部分与所述第一初始化信号端、所述第二初始化信号端、所述高电位端、所述第一低电位端、所述前级级联输出端、所述本级级联输出端、所述后级级联输出端以及所述第三节点电性连接；所述下拉控制部分包括第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和耦合电容；所述第七晶体管的第一极电性连接于所述第二初始化信号端，所述第七晶体管的第二极与所述高电位端、所述第八晶体管的第二极和所述第九晶体管的第二极电性连接，所述第七晶体管的第三极与所述第二节点电性连接，所述第八晶体管的第一极电性连接于所述后级级联输出端或所述复位信号端，所述第八晶体管的第三极与所述第七晶体管的第三极、所述第九晶体管的第一极、所述第十晶体管的第二极以及所述耦合电容的第一极电性连接，所述第九晶体管的第三极与所述耦合电容的第二极和所述第三节点电性连接，所述第十晶体管的第一极与所述前级级联输出端和所述第十一晶体管的第一极电性连接，所述第十晶体管的第三极与所述第三节点电性连接，所述第十一晶体管的第二极与所述第十晶体管的第三极电性连接，所述第十一晶体管的第三极与所述第一低电位端电性连接。
在上述驱动电路中，所述耦合电容用于使得所述第二节点随所述第三节点电位的升高而被自举到比高电位端更高的电位，以减小阈值电压偏正时阈值损失对第三节点的电位的影响以及增加阈值电压偏负时第三节点对漏电的抵抗能力。
在上述驱动电路中，所述下拉控制部分还包括第十二晶体管、第十三晶体管、第十四晶体管，所述第十二晶体管的第一极与所述本级级联输出端以及所述第十三晶体管的第一极电性连接，所述第十二晶体管的第二极与所述第八晶体管的第三极电性连接，所述第十二晶体管的第三极与所述第十三晶体管的第二极、所述第十四晶体管的第二极电性连接，所述第十四晶体管的第一极电性连接于所述第一初始化信号端，所述第十三晶体管的第三极以及所述第十四晶体管的第三极与所述第一低电位端电性连接。
在上述驱动电路中，所述下拉控制部分的所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管和所述第十三晶体管构成两套STT防漏电电路结构，以抑制所述第二节点的电荷泄漏，所述下拉控制部分的所述第七晶体管充当两套所述STT防漏电电路结构的反馈管，以切断所述第二节点可能存在的漏电通路，防止所述第二节点漏电。
在上述驱动电路中，所述下拉控制部分还包括所述第十四晶体管，所述第十四晶体管的第一极电性连接于所述第一初始化信号端，所述第十四晶体管的第二极电性连接于所述第三节点，所述第十四晶体管的第三极电性连接于所述第一低电位端。
在上述驱动电路中，所述下拉控制部分还包括第十二晶体管、第十三晶体管，所述第十二晶体管的第一极与所述本级级联输出端以及所述第十三晶体管的第一极电性连接，所述第十二晶体管的第二极与所述第八晶体管的第三极电性连接，所述第十二晶体管的第三极与所述第十三晶体管的第二极电性连接，所述第十三晶体管的第三极与所述第一低电位端电性连接。
在上述驱动电路中，所述复位信号端的复位信号用于在所述本级扫描输出端的本级扫描信号输出之后、所述时钟信号端的时钟信号再次跳变为高电平之前，将所述第一节点放电至低电位，所述复位信号还用于在跳变为高电平后，控制所述第八晶体管开启，以对所述第二节点进行充电，以及使所述第九晶体管开启，将所述第三节点上拉至高电位。
在上述驱动电路中，所述下拉部分与所述第一节点、所述第三节点、所述第一低电位端、所述第二低电位端、所述本级级联输出端、所述本级扫描输出端以及所述后级级联输出端电性连接；所述下拉部分包括第四晶体管、第十五晶体管和第十八晶体管；所述第四晶体管的第一极与所述第三节点、所述第十五晶体管的第一极以及所述第十八晶体管的第一极电性连接，所述第四晶体管的第二极电性连接于所述第一节点，所述第四晶体管的第三极与所述第十五晶体管的第二极以及所述本级级联输出端电性连接，所述第十五晶体管的第三极与所述第一低电位端电性连接。
在上述驱动电路中，所述第十八晶体管的第二极电性连接于所述本级扫描输出端，所述第十八晶体管的第三极电性连接于所述第二低电位端。
在上述驱动电路中，所述下拉部分还包括第十六晶体管、第十七晶体管；所述第十六晶体管的第一极与所述后级级联输出端、第十七晶体管的第一极电性连接，所述第十六晶体管的第二极与所述本级级联输出端电性连接，所述第十六晶体管的第三极与所述第一低电位端电性连接；所述第十七晶体管的第二极与所述驱动部分的去耦电容的第一极和所述第十八晶体管的第二极电性连接，所述第十七晶体管的第三极与所述第二低电位端以及所述第十八晶体管的第三极电性连接。
在上述驱动电路中，所述驱动部分与所述时钟信号端、第一节点、本级级联输出端、本级扫描输出端电性连接；所述驱动部分包括第五晶体管、第六晶体管和去耦电容；所述第五晶体管的第一极与所述第一节点、所述第六晶体管的第一极以及所述去耦电容的第二极电性连接，所述第五晶体管的第二极与所述时钟信号端以及所述第六晶体管的第二极电性连接，所述第五晶体管的第三极电性连接于所述本级级联输出端，所述第六晶体管的第三极电性连接于所述本级扫描输出端。
在上述驱动电路中，所述时钟信号端的时钟信号为M相时钟信号，其中，M为大于或者等于2的整数；所述第N级栅极驱动单元电路和第N+1级栅极驱动单元电路分别与对应于不同时钟信号的时钟信号端电性连接。
在上述驱动电路中，M=2；所述复位信号端连接至第N+k级级联输出端，其中，k为大于等于2的整数。
在上述驱动电路中，所述下拉控制部分还用于在初始化阶段和下拉及低电平维持阶段中的下拉阶段利用所述第一初始化信号端的第一初始化信号和所述第二初始化信号端的第二初始化信号，以及所述前级级联输出端的前级级联输出信号和所述后级级联输出端的后级级联输出信号对所述第二节点进行两次自举，以保证所述第三节点在本级输出前后均可以实现满摆幅输出。
在上述驱动电路中，所述第一节点位于所述输入部分的第二晶体管的第三极与所述驱动部分的第五晶体管的第一极之间；所述第二节点位于所述下拉控制部分的第七晶体管的第三极与所述下拉控制部分的耦合电容的第一极之间；所述第三节点位于所述下拉部分的第十八晶体管的第一极与所述下拉控制部分的第十四晶体管的第二极之间。
 有益效果
相对现有技术，由于本发明的驱动电路采用了新型的下拉控制结构，该下拉控制结构中包括STT防漏电电路结构，因此可以使得驱动电路中的第三节点在晶体管的阈值电压偏正和偏负时均可以上拉至高电位端的电位，从而保证了驱动电路中的下拉晶体管处于良好的开启状态，输出更加稳定，也使得驱动电路可以在更大的阈值电压范围内工作。
 附图说明
图1为本发明的驱动电路的示意图；
图2为图1所示的驱动电路中的第N级栅极驱动单元电路的第一实施例的电路图；
图3为图2所示的第N级栅极驱动单元电路中的信号的波形图；
图4为图1所示的驱动电路中的第N级栅极驱动单元电路的第二实施例的电路图；
图5为图4所示的第N级栅极驱动单元电路中的信号的波形图；
图6为图1所示的驱动电路中的第N级栅极驱动单元电路的第三实施例的电路图；
图7为图1所示的驱动电路中的第N级栅极驱动单元电路的第四实施例的电路图；
图8为图1所示的驱动电路中的第N级栅极驱动单元电路的第五实施例的电路图；
图9为图8所示的第N级栅极驱动单元电路中的信号的波形图。
 本发明的实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的驱动电路应用于显示面板中，所述显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）、OLED（Organic Light Emitting Diode，有机发光二极管显示面板）等。
所述驱动电路与所述显示面板中的像素单元电性连接，所述驱动电路用于向所述像素单元发送驱动信号（扫描信号），以驱动所述像素单元显示图像。
参考图1、图2和图3，图1为本发明的驱动电路的示意图，图2为图1所示的驱动电路中的第N级栅极驱动单元电路的第一实施例的电路图，图3为图2所示的第N级栅极驱动单元电路中的信号的波形图。
本实施例的驱动电路包括P个（级）级联的栅极驱动单元电路，P个（级）所述栅极驱动单元电路以级联的方式电性连接。即，P个（级）所述栅极驱动单元电路以级联的方式电性连接。如图1所示。其中，P为大于或等于2的整数。
所述驱动电路还包括第一初始化信号端STV1、第二初始化信号端STV2、时钟信号端CLK、高电位端VGH、前级扫描输出端G(N-1)、前级级联输出端C(N-1)、后级级联输出端C(N+1)、第一低电位端VSSL、第二低电位端VSS、本级级联输出端C(N)以及本级扫描输出端G(N)。
所述栅极驱动单元电路用于生成驱动信号（扫描信号），以控制显示面板的像素单元中的薄膜晶体管开关开启或关闭，从而驱动所述像素单元显示图像。
在本实施例中，对于第N级栅极驱动单元电路而言，术语“前级”是指所述驱动电路中的第N-1级，其中，N为大于或等于1，且小于或等于P的整数，例如，前级扫描输出端G(N-1)是指第N-1级栅极驱动单元电路中的扫描输出端G(N-1)；术语“本级”是指所述驱动电路中的第N级，例如，本级级联输出端C(N)是指第N级栅极驱动单元电路的级联输出端，本级扫描输出端G(N) 是指第N级栅极驱动单元电路的扫描输出端；术语“后级”是指所述驱动电路中的第N+1级，例如，后级级联输出端C(N+1)是指第N+1级栅极驱动单元电路的级联输出端。
本实施例中的晶体管（例如：第一晶体管T1、第二晶体管T2和第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17和第十八晶体管T18）可以为薄膜场效应晶体管，晶体管的第一极为薄膜场效应晶体管的栅极，晶体管的第二极可以为薄膜场效应晶体管的漏极或者源级，晶体管的第三极可以为薄膜场效应晶体管的源极或者漏极。本实施例中的晶体管的源极和漏极均可以随晶体管偏置状态的不同而变化。
P个（级）级联的所述栅极驱动单元电路中的第N级栅极驱动单元电路与第一初始化信号端STV1、第二初始化信号端STV2、时钟信号端CLK、高电位端VGH、前级扫描输出端G(N-1)、前级级联输出端C(N-1)、后级级联输出端C(N+1)、第一低电位端VSSL、第二低电位端VSS、本级级联输出端C(N)以及本级扫描输出端G(N)电性连接。
所述第N级栅极驱动单元电路包括输入部分10、下拉控制部分20、驱动部分30、下拉部分40。所述输入部分10与所述下拉控制部分20和所述驱动部分30电性连接，所述下拉控制部分20与所述下拉部分40电性连接，所述下拉部分40与所述驱动部分30电性连接。
所述输入部分10与所述前级扫描输出端G(N-1)、前级级联输出端C(N-1)、时钟信号端CLK、本级级联输出端C(N)和第一节点Q电性连接。其中，所述第一节点Q位于所述输入部分10与所述驱动部分30之间，具体地，所述第一节点Q位于所述输入部分10的第二晶体管T2的第三极与所述驱动部分30的第五晶体管T5的第一极之间。所述输入部分10用于对本级（所述第N级栅极驱动单元电路）的第一节点Q进行预充电，以使所述驱动部分30中的第五晶体管T5和第六晶体管T6提前打开，为本级扫描输出端G(N)的本级扫描信号和本级级联输出端C(N)的本级级联输出信号的输出做准备；同时，所述输入部分10还用于将所述下拉控制部分20的第二节点IQ及所述下拉部分40的第三节点QB下拉至低电位，以使所述下拉部分40中的第四晶体管T4、第十五晶体管T15和第十八晶体管T18提前关闭，避免所述下拉部分40中的晶体管（包括第四晶体管T4、第十五晶体管T15和第十八晶体管T18）在上拉阶段S3的初始时刻产生漏电，从而提高所述驱动电路的驱动速度和减小功耗。
其中，所述第二节点IQ位于所述下拉控制部分20的内部，具体地，所述第二节点IQ位于所述下拉控制部分20的第七晶体管T7的第三极与所述下拉控制部分20的耦合电容CI的第一极之间。所述第三节点QB位于所述下拉部分40的内部（即，所述下拉部分40与所述下拉控制部分20之间），具体地，所述第三节点QB位于所述下拉部分40的第十八晶体管T18的第一极与所述下拉控制部分20的第十四晶体管T14的第二极之间。
所述输入部分10包括第一晶体管T1、第二晶体管T2和第三晶体管T3。第一晶体管T1的第一极与前级级联输出端C(N-1)以及第二晶体管T2的第一极电性连接，第一晶体管T1的第二极电性连接于前级扫描输出端G(N-1)，第一晶体管T1的第三极与第二晶体管T2的第二极以及第三晶体管T3的第二极电性连接；第二晶体管T2的第三极电性连接于第一节点Q；第三晶体管T3的第一极电性连接于时钟信号端CLK，第三晶体管T3的第三极电性连接于本级级联输出端C(N)。
所述下拉控制部分20与所述第一初始化信号端STV1、第二初始化信号端STV2、高电位端VGH、第一低电位端VSSL、前级级联输出端C(N-1)、本级级联输出端C(N)、后级级联输出端C(N+1)以及第三节点QB电性连接。所述下拉控制部分20用于产生控制所述下拉部分40的控制信号，所述控制信号在预充阶段S2和上拉阶段S3为低电平，以将所述下拉部分40中的晶体管（包括第四晶体管T4、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17和第十八晶体管T18）关闭；所述控制信号在下拉及低电平维持阶段S4为高电平，以将下拉部分40中的晶体管（包括第四晶体管T4、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17和第十八晶体管T18）开启。所述下拉控制部分20包括耦合电容CI，所述耦合电容CI用于使得第二节点IQ随第三节点QB电位的升高而被自举到比高电位端VGH更高的电位，以减小阈值电压偏正时阈值损失对第三节点QB的电位的影响以及增加阈值电压偏负时第三节点QB对漏电的抵抗能力（即，抑制第三节点QB的电荷泄漏）。所述下拉控制部分20用于在初始化阶段S1和下拉及低电平维持阶段S4中的下拉阶段利用所述第一初始化信号端STV1的第一初始化信号和所述第二初始化信号端STV2的第二初始化信号，以及前级级联输出端C(N-1)的前级级联输出信号和后级级联输出端C(N+1)的后级级联输出信号对第二节点IQ进行两次自举，从而保证第三节点QB在本级输出前后均可以实现满摆幅输出，有助于输出的稳定。此外，对于所述第二节点IQ，所述下拉控制部分20采用了STT（Series connected Two-Transistor）防漏电电路结构进行防漏电保护，即，所述下拉控制部分20的第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12和第十三晶体管T13构成两套STT防漏电电路结构，以抑制第二节点IQ的电荷泄漏，所述下拉控制部分20的第七晶体管T7充当两套STT防漏电电路结构的反馈管，以切断第二节点IQ可能存在的漏电通路，防止第二节点IQ漏电，从而增加了所述下拉控制部分20的防漏电能力。STT防漏电电路结构为包括晶体管A、晶体管B和晶体管C的电路的结构，晶体管A、晶体管B和晶体管C为薄膜场效应晶体管，其中，晶体管A的第一极与晶体管B的第一极电性连接，晶体管A的第三极与晶体管B的第二极以及晶体管C的第二极电性连接。
所述下拉控制部分20包括第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14和耦合电容CI。第七晶体管T7的第一极电性连接于第二初始化信号端STV2，第七晶体管T7的第二极与高电位端VGH、第八晶体管T8的第二极和第九晶体管T9的第二极电性连接，第七晶体管T7的第三极与第二节点IQ电性连接；第八晶体管T8的第一极电性连接于后级级联输出端C(N+1)，第八晶体管T8的第三极与第七晶体管T7的第三极、第九晶体管T9的第一极、第十晶体管T10的第二极、第十二晶体管T12的第二极以及耦合电容CI的第一极电性连接；第九晶体管T9的第三极与耦合电容CI的第二极和第三节点QB电性连接；第十晶体管T10的第一极与前级级联输出端C(N-1)和第十一晶体管T11的第一极电性连接，第十晶体管T10的第三极与第三节点QB电性连接；第十一晶体管T11的第二极与第十晶体管T10的第三极、第十二晶体管T12的第三极以及第十三晶体管T13的第二极电性连接，第十一晶体管T11的第三极与第一低电位端VSSL、第十三晶体管T13的第三极以及第十四晶体管T14的第三极电性连接；第十二晶体管T12的第一极与本级级联输出端C(N)以及第十三晶体管T13的第一极电性连接；第十四晶体管T14的第一极电性连接于第一初始化信号端STV1。
所述下拉部分40与第一节点Q、第三节点QB、第一低电位端VSSL、第二低电位端VSS、本级级联输出端C(N)、本级扫描输出端G(N)以及后级级联输出端C(N+1)电性连接。所述下拉部分40包括第四晶体管T4、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17和第十八晶体管T18，所述下拉部分40用于在本级扫描输出端G(N)的本级扫描信号输出之后，将第一节点Q、本级级联输出端C(N)和本级扫描输出端G(N)的电位下拉至低电位，并在下次输出之前将其保持在低电位。在上拉阶段S3，所述下拉部分40的第四晶体管T4、第十五晶体管T15和所述驱动部分30的第五晶体管T5构成STT防漏电电路结构，以防止第一节点Q的漏电，保证上拉速度。在下拉及低电平维持阶段S4，第一节点Q通过第四晶体管T4和第十五晶体管T15与第一低电位端VSSL相连，不处于悬浮状态（即，使得所述第一节点Q保持在低电位），以减小时钟馈通效应在第一节点Q造成的电位波动，稳定了输出，即，在下拉及低电平维持阶段S4中的低电平维持阶段，所述下拉部分40的第四晶体管T4将第一节点Q和本级级联输出端C(N)连接，稳定第一节点Q的电位从而稳定输出。同时，第十五晶体管T15和第十八晶体管T18在所述下拉控制部分20的控制下分别对本级级联输出端C(N)和本级扫描输出端G(N)持续放电，将输出稳定在低电位。
第四晶体管T4的第一极与第三节点QB、第十五晶体管T15的第一极以及第十八晶体管T18的第一极电性连接，第四晶体管T4的第二极电性连接于第一节点Q，第四晶体管T4的第三极与第十五晶体管T15的第二极、第十六晶体管T16的第二极以及本级级联输出端C(N)电性连接；第十五晶体管T15的第三极与第一低电位端VSSL以及第十六晶体管T16的第三极电性连接；第十六晶体管T16的第一极与后级级联输出端C(N+1)与第十七晶体管T17的第一极电性连接；第十七晶体管T17的第二极与所述驱动部分30的去耦电容CS的第一极和第十八晶体管T18的第二极电性连接，第十七晶体管T17的第三极与第二低电位端VSS以及第十八晶体管T18的第三极电性连接。
所述驱动部分30与所述时钟信号端CLK、第一节点Q、本级级联输出端C(N)、本级扫描输出端G(N)电性连接。所述驱动部分30用于在第一节点Q为高电位时，将时钟信号端CLK的时钟信号传递至本级级联输出端C(N)和本级扫描输出端G(N)，并且在时钟信号端CLK的时钟信号为高电平时，将第一节点Q的电位耦合到更高的电位，从而提高驱动速度。
所述驱动部分30包括第五晶体管T5、第六晶体管T6和去耦电容CS。第五晶体管T5的第一极与第一节点Q、第六晶体管T6的第一极以及去耦电容CS的第二极电性连接，第五晶体管T5的第二极与时钟信号端CLK以及第六晶体管T6的第二极电性连接，第五晶体管T5的第三极电性连接于本级级联输出端C(N)；第六晶体管T6的第三极电性连接于本级扫描输出端G(N)。
所述时钟信号端CLK的时钟信号为M相时钟信号（M为大于或者等于2的整数）。在本实施例中，所述时钟信号端CLK的时钟信号为2相时钟信号，即，所述时钟信号端CKL包括第一时钟信号端CK1和第二时钟信号端CK2，第一时钟信号端CK1中的第一时钟信号与第二时钟信号端CK2中的第二时钟信号不同。所述驱动电路中相邻的两个栅极驱动单元电路分别与对应于不同时钟信号的时钟信号端电性连接，例如，第N级栅极驱动单元电路和第N+1级栅极驱动单元电路分别与第二时钟信号端CK2和第一时钟信号端CK1电性连接，或者，第N级栅极驱动单元电路和第N+1级栅极驱动单元电路分别与第一时钟信号端CK1和第二时钟信号端CK2电性连接。
当所使用的晶体管展现负阈值特性时，优选地，所述第一低电位端VSSL和所述第二低电位端VSS中的信号的电平值不相同，以利用电压反偏减少可能产生的内部漏电，所述第一低电位端VSSL和所述第二低电位端VSS中的信号的低电平的电压差可以随器件性能和使用情况不同而改变。
本实施例中的第N级栅极驱动单元电路采用了具有STT防漏电的可自举的下拉控制结构（STT防漏电电路结构），无论晶体管的阈值电压偏正或者偏负，第N级栅极驱动单元电路均可在下拉及低电平维持阶段S4输出满摆幅高电平信号，提高了驱动电路的稳定性。具体地，所述第N级栅极驱动单元电路采用新型下拉控制结构，所述下拉控制部分20通过增加上拉晶体管栅极的自举以及STT防漏电电路结构，使得第三节点QB在阈值电压偏正和偏负时均可以上拉至高电位端VGH 的电位，从而保证了下拉晶体管（包括第四晶体管T4、第十五晶体管T15、第十八晶体管T18）处于良好的开启状态，输出更加稳定，也使得驱动电路可以在更大的阈值电压范围内工作。当阈值电压为负时，所述第N级栅极驱动单元电路所泄漏的电流更小，多级的所述栅极驱动单元电路级联时仍然可以正常工作，并且延迟时间更短、响应速度更快。
本实施例的驱动电路还减小了上拉阶段S3第一节点Q的漏电，提高了驱动电路在负阈值区的性能。其次，所述驱动电路所需的时钟信号的数量较少，工作速度较快，有利于高分辨率和窄边框的实现。具体地，由于所述第N级栅极驱动单元电路采用新型的下拉结构，将第五晶体管T5复用为STT防漏电电路结构的反馈管，不仅可以防止下拉管对第一节点Q的漏电，而且减小了晶体管的数量。
所述第N级栅极驱动单元电路的时钟信号更加灵活，根据不同的使用情况，可以采用M相时钟信号控制（M为大于或者等于2的整数）。当M=2时，更加有利于窄边框的实现。当M较大时，有利于减少驱动电路的功耗。
参考图4和图5，图4为图1所示的驱动电路中的第N级栅极驱动单元电路的第二实施例的电路图，图5为图4所示的第N级栅极驱动单元电路中的信号的波形图。
本发明的驱动电路的第二实施例与上述第一实施例相近或相似，不同之处在于：
在本实施例中，所述驱动电路还包括复位信号端C(N+k)。
所述下拉控制部分20中的第八晶体管T8的第一极电性连接于复位信号端C(N+k)，即，在上述第一实施例中，第八晶体管T8的第一极所连接的后级级联输出端C(N+1)替换为复位信号端C(N+k)；第十六晶体管T16的第一极以及第十七晶体管T17的第一极均电性连接于后级级联输出端C(N+1)。
时钟信号端CLK的时钟信号为M相不交叠的时钟信号（M为大于或者等于2的整数），具体地，在本实施例中，M=2。复位信号端C(N+k)连接至第N+k级级联输出端，k为大于等于2的整数。为了保证驱动电路的可靠性，优选地，k小于M。为了使得第一节点Q的放电晚于（延迟于）本级级联输出端C(N)的放电，从而利用上拉晶体管（第五晶体管T5和第六晶体管T6）进行放电、减小下降时间，优选地，k大于或者等于2。
在本实施例中，所述下拉控制部分20用于产生控制所述下拉部分40的控制信号，所述控制信号在预充阶段S2和上拉阶段S3为低电平，以将所述下拉部分40中的晶体管（包括第四晶体管T4、第十五晶体管T15和第十八晶体管T18）关闭；所述控制信号在下拉及低电平维持阶段S4为高电平，以将下拉部分40中的晶体管（包括第四晶体管T4、第十五晶体管T15和第十八晶体管T18）开启。
所述第N级栅极驱动单元电路在下拉及低电平维持阶段S4，时钟信号端CLK跳变为低电位，后级级联输出端C(N+1)跳变为高电位，第十六晶体管T16和第十七晶体管T17开启，第十六晶体管T16和第十七晶体管T17分别对本级级联输出端C(N)和本级扫描输出端G(N)放电（输出信号）。此时第一节点Q仍保持高电位，第五晶体管T5和第六晶体管T6保持开启状态，第五晶体管T5和第六晶体管T6分别对本级级联输出端C(N)和本级扫描输出端G(N)放电（输出信号），提高放电速度。从此直至复位信号端C(N+k)的复位信号跳变为高电平之前，第一节点Q的电位保持在高电位，以将本级级联输出端C(N)和本级扫描输出端G(N)的输出信号持续下拉。为了确保电路的功能正常，复位信号端C(N+k)的复位信号用于在本级扫描输出端G(N)的本级扫描信号输出之后、时钟信号端CLK的时钟信号再次跳变为高电平之前，将第一节点Q放电至低电位，即k小于M。复位信号端C(N+k)的复位信号用于在跳变为高电平后，控制第八晶体管T8开启，以对第二节点IQ进行充电，以及使第九晶体管T9开启，将第三节点QB上拉至高电位。随着第三节点QB的电位的升高，第二节点IQ被自举到更高的电位，因而第三节点QB的电位可以被充分上拉至高电位端VGH 的电位。此时，与第三节点QB电性连接的第四晶体管T4、第十五晶体管T15和第十八晶体管T18均开启，第一节点Q通过第四晶体管T4和第十五晶体管T15放电至低电位。此后，第三节点QB保持高电位，第四晶体管T4、第十五晶体管T15和第十八晶体管T18持续开启，第一节点Q、本级级联输出端C(N)以及本级扫描输出端G(N)输出稳定的低电平信号。
参考图6，图6为图1所示的驱动电路中的第N级栅极驱动单元电路的第三实施例的电路图。
本发明的驱动电路的第三实施例与上述第二实施例相近或相似，不同之处在于：
在本实施例中，下拉部分40中去掉了第十六晶体管T16和第十七晶体管T17，即，所述下拉部分40仅包括第四晶体管T4、第十五晶体管T15和第十八晶体管T18。
下拉部分40与第一节点Q、第三节点QB、第一低电位端VSSL、第二低电位端VSS、本级级联输出端C(N)、本级扫描输出端G(N)电性连接。
第四晶体管T4的第一极与第三节点QB、第十五晶体管T15的第一极以及第十八晶体管T18的第一极电性连接，第四晶体管T4的第二极电性连接于第一节点Q，第四晶体管T4的第三极与第十五晶体管T15的第二极以及本级级联输出端C(N)电性连接；第十五晶体管T15的第三极电性连接于第一低电位端VSSL；第十八晶体管T18的第二极电性连接于本级扫描输出端G(N)，第十八晶体管T18的第三极电性连接于第二低电位端VSS。
本实施例的第N级栅极驱动单元电路中的信号的波形图与上述图5相同。
参考图7，图7为图1所示的驱动电路中的第N级栅极驱动单元电路的第四实施例的电路图。
本发明的驱动电路的第四实施例与上述第二实施例或第三实施例相近或相似，不同之处在于：
在本实施例中，当仅适用于阈值电压偏正的场合时，可以将所述下拉控制部20中由本级级联输出端C(N)引入的反馈管（第十二晶体管T12和第十三晶体管T13）去掉，从而简化电路。即，在本实施例中，所述下拉控制部20去掉了第十二晶体管T12和第十三晶体管T13。
下拉部分40中去掉了第十六晶体管T16和第十七晶体管T17，即，所述下拉部分40仅包括第四晶体管T4、第十五晶体管T15和第十八晶体管T18。
下拉控制部分20与所述第一初始化信号端STV1、第二初始化信号端STV2、高电位端VGH、第一低电位端VSSL、前级级联输出端C(N-1)、复位信号端C(N+k)以及第三节点QB电性连接。所述下拉控制部分20包括第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十四晶体管T14和耦合电容CI。第八晶体管T8的第一极电性连接于复位信号端C(N+k)，第八晶体管T8的第三极与第七晶体管T7的第三极、第九晶体管T9的第一极、第十晶体管T10的第二极以及耦合电容CI的第一极电性连接；第十一晶体管T11的第二极与第十晶体管T10的第三极以及第十四晶体管T14的第二极电性连接，第十一晶体管T11的第三极与第一低电位端VSSL以及第十四晶体管T14的第三极电性连接；第十四晶体管T14的第一极电性连接于第一初始化信号端STV1。
本实施例的第N级栅极驱动单元电路中的信号的波形图与上述图5相同。
参考图8和图9，图8为图1所示的驱动电路中的第N级栅极驱动单元电路的第五实施例的电路图，图9为图8所示的第N级栅极驱动单元电路中的信号的波形图。
本发明的驱动电路的第五实施例与上述第三实施例相近或相似，不同之处在于：
在本实施例中，所述下拉控制部分20中去掉了第十四晶体管T14。
下拉部分40中去掉了第十六晶体管T16和第十七晶体管T17，即，所述下拉部分40仅包括第四晶体管T4、第十五晶体管T15和第十八晶体管T18。
所述输入部分10中的第三晶体管T3的第一极、第三极均电性连接于时钟信号端CLK，第三晶体管T3的第二极电性连接于第一晶体管T1的第三极和第一节点Q。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种驱动电路，其中，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；
    至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路与时钟信号端、高电位端、前级扫描输出端、前级级联输出端、第一低电位端、第二低电位端、本级级联输出端以及本级扫描输出端电性连接，第N级栅极驱动单元电路还与第一初始化信号端、第二初始化信号端中的至少一者以及后级级联输出端、复位信号端中的至少一者电性连接，其中，N为大于或等于1的整数；
    所述第N级栅极驱动单元电路包括输入部分、下拉控制部分、下拉部分和驱动部分；
    所述输入部分用于对所述第N级栅极驱动单元电路的第一节点进行预充电，以使所述驱动部分中的第五晶体管和第六晶体管提前打开，以及用于将所述下拉控制部分的第二节点及所述下拉部分的第三节点下拉至低电位，以使所述下拉部分中的第四晶体管、第十五晶体管和第十八晶体管提前关闭；
    所述下拉控制部分用于产生控制信号，所述控制信号在预充阶段和上拉阶段为低电平，以将所述下拉部分中的晶体管关闭，所述控制信号在下拉及低电平维持阶段为高电平，以将下拉部分中的晶体管开启；
    所述下拉部分用于在所述驱动电路的本级扫描输出端的本级扫描信号输出之后，将所述第一节点、所述驱动电路的本级级联输出端和所述本级扫描输出端的电位下拉至低电位，并在下次输出之前将其保持在低电位；
    所述驱动部分用于在所述第一节点为高电位时，将所述驱动电路的时钟信号端的时钟信号传递至所述本级级联输出端和所述本级扫描输出端，并且在所述时钟信号端的时钟信号为高电平时，将所述第一节点的电位耦合到更高的电位；
    所述第一节点位于所述输入部分的第二晶体管的第三极与所述驱动部分的第五晶体管的第一极之间；
    所述第二节点位于所述下拉控制部分的第七晶体管的第三极与所述下拉控制部分的耦合电容的第一极之间；
    所述第三节点位于所述下拉部分的第十八晶体管的第一极与所述下拉控制部分的第十四晶体管的第二极之间；
    所述时钟信号端的时钟信号为M相时钟信号，其中，M为大于或者等于2的整数；
    所述第N级栅极驱动单元电路和第N+1级栅极驱动单元电路分别与对应于不同时钟信号的时钟信号端电性连接。
  2. 根据权利要求1所述的驱动电路，其中，所述输入部分与所述前级扫描输出端、所述前级级联输出端、所述时钟信号端、所述本级级联输出端和所述第一节点电性连接；
    所述输入部分包括第一晶体管、第二晶体管和第三晶体管；
    所述第一晶体管的第一极与所述前级级联输出端以及所述第二晶体管的第一极电性连接，所述第一晶体管的第二极电性连接于所述前级扫描输出端，所述第一晶体管的第三极与所述第二晶体管的第二极以及所述第三晶体管的第二极电性连接，所述第二晶体管的第三极电性连接于所述第一节点，所述第三晶体管的第一极电性连接于所述时钟信号端；
    所述第三晶体管的第三极电性连接于所述本级级联输出端，或者所述第三晶体管的第一极电性连接于所述时钟信号端。
  3. 根据权利要求1所述的驱动电路，其中，所述下拉部分与所述第一节点、所述第三节点、所述第一低电位端、所述第二低电位端、所述本级级联输出端、所述本级扫描输出端以及所述后级级联输出端电性连接；
    所述下拉部分包括第四晶体管、第十五晶体管和第十八晶体管；
    所述第四晶体管的第一极与所述第三节点、所述第十五晶体管的第一极以及所述第十八晶体管的第一极电性连接，所述第四晶体管的第二极电性连接于所述第一节点，所述第四晶体管的第三极与所述第十五晶体管的第二极以及所述本级级联输出端电性连接，所述第十五晶体管的第三极与所述第一低电位端电性连接。
  4. 一种驱动电路，其中，所述驱动电路包括至少两栅极驱动单元电路，至少两所述栅极驱动单元电路以级联的方式电性连接；
    至少两所述栅极驱动单元电路中的第N级栅极驱动单元电路与时钟信号端、高电位端、前级扫描输出端、前级级联输出端、第一低电位端、第二低电位端、本级级联输出端以及本级扫描输出端电性连接，第N级栅极驱动单元电路还与第一初始化信号端、第二初始化信号端中的至少一者以及后级级联输出端、复位信号端中的至少一者电性连接，其中，N为大于或等于1的整数；
    所述第N级栅极驱动单元电路包括输入部分、下拉控制部分、下拉部分和驱动部分；
    所述输入部分用于对所述第N级栅极驱动单元电路的第一节点进行预充电，以使所述驱动部分中的第五晶体管和第六晶体管提前打开，以及用于将所述下拉控制部分的第二节点及所述下拉部分的第三节点下拉至低电位，以使所述下拉部分中的第四晶体管、第十五晶体管和第十八晶体管提前关闭；
    所述下拉控制部分用于产生控制信号，所述控制信号在预充阶段和上拉阶段为低电平，以将所述下拉部分中的晶体管关闭，所述控制信号在下拉及低电平维持阶段为高电平，以将下拉部分中的晶体管开启；
    所述下拉部分用于在所述驱动电路的本级扫描输出端的本级扫描信号输出之后，将所述第一节点、所述驱动电路的本级级联输出端和所述本级扫描输出端的电位下拉至低电位，并在下次输出之前将其保持在低电位；
    所述驱动部分用于在所述第一节点为高电位时，将所述驱动电路的时钟信号端的时钟信号传递至所述本级级联输出端和所述本级扫描输出端，并且在所述时钟信号端的时钟信号为高电平时，将所述第一节点的电位耦合到更高的电位。
  5. 根据权利要求4所述的驱动电路，其中，所述输入部分与所述前级扫描输出端、所述前级级联输出端、所述时钟信号端、所述本级级联输出端和所述第一节点电性连接；
    所述输入部分包括第一晶体管、第二晶体管和第三晶体管；
    所述第一晶体管的第一极与所述前级级联输出端以及所述第二晶体管的第一极电性连接，所述第一晶体管的第二极电性连接于所述前级扫描输出端，所述第一晶体管的第三极与所述第二晶体管的第二极以及所述第三晶体管的第二极电性连接，所述第二晶体管的第三极电性连接于所述第一节点，所述第三晶体管的第一极电性连接于所述时钟信号端；
    所述第三晶体管的第三极电性连接于所述本级级联输出端，或者所述第三晶体管的第一极电性连接于所述时钟信号端。
  6. 根据权利要求4所述的驱动电路，其中，所述下拉控制部分与所述第一初始化信号端、所述第二初始化信号端、所述高电位端、所述第一低电位端、所述前级级联输出端、所述本级级联输出端、所述后级级联输出端以及所述第三节点电性连接；
    所述下拉控制部分包括第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和耦合电容；
    所述第七晶体管的第一极电性连接于所述第二初始化信号端，所述第七晶体管的第二极与所述高电位端、所述第八晶体管的第二极和所述第九晶体管的第二极电性连接，所述第七晶体管的第三极与所述第二节点电性连接，所述第八晶体管的第一极电性连接于所述后级级联输出端或所述复位信号端，所述第八晶体管的第三极与所述第七晶体管的第三极、所述第九晶体管的第一极、所述第十晶体管的第二极以及所述耦合电容的第一极电性连接，所述第九晶体管的第三极与所述耦合电容的第二极和所述第三节点电性连接，所述第十晶体管的第一极与所述前级级联输出端和所述第十一晶体管的第一极电性连接，所述第十晶体管的第三极与所述第三节点电性连接，所述第十一晶体管的第二极与所述第十晶体管的第三极电性连接，所述第十一晶体管的第三极与所述第一低电位端电性连接。
  7. 根据权利要求6所述的驱动电路，其中，所述耦合电容用于使得所述第二节点随所述第三节点电位的升高而被自举到比高电位端更高的电位，以减小阈值电压偏正时阈值损失对第三节点的电位的影响以及增加阈值电压偏负时第三节点对漏电的抵抗能力。
  8. 根据权利要求6所述的驱动电路，其中，所述下拉控制部分还包括第十二晶体管、第十三晶体管、第十四晶体管，所述第十二晶体管的第一极与所述本级级联输出端以及所述第十三晶体管的第一极电性连接，所述第十二晶体管的第二极与所述第八晶体管的第三极电性连接，所述第十二晶体管的第三极与所述第十三晶体管的第二极、所述第十四晶体管的第二极电性连接，所述第十四晶体管的第一极电性连接于所述第一初始化信号端，所述第十三晶体管的第三极以及所述第十四晶体管的第三极与所述第一低电位端电性连接。
  9. 根据权利要求8所述的驱动电路，其中，所述下拉控制部分的所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管和所述第十三晶体管构成两套STT防漏电电路结构，以抑制所述第二节点的电荷泄漏，所述下拉控制部分的所述第七晶体管充当两套所述STT防漏电电路结构的反馈管，以切断所述第二节点可能存在的漏电通路，防止所述第二节点漏电。
  10. 根据权利要求6所述的驱动电路，其中，所述下拉控制部分还包括所述第十四晶体管，所述第十四晶体管的第一极电性连接于所述第一初始化信号端，所述第十四晶体管的第二极电性连接于所述第三节点，所述第十四晶体管的第三极电性连接于所述第一低电位端。
  11. 根据权利要求6所述的驱动电路，其中，所述下拉控制部分还包括第十二晶体管、第十三晶体管，所述第十二晶体管的第一极与所述本级级联输出端以及所述第十三晶体管的第一极电性连接，所述第十二晶体管的第二极与所述第八晶体管的第三极电性连接，所述第十二晶体管的第三极与所述第十三晶体管的第二极电性连接，所述第十三晶体管的第三极与所述第一低电位端电性连接。
  12. 根据权利要求6所述的驱动电路，其中，所述复位信号端的复位信号用于在所述本级扫描输出端的本级扫描信号输出之后、所述时钟信号端的时钟信号再次跳变为高电平之前，将所述第一节点放电至低电位，所述复位信号还用于在跳变为高电平后，控制所述第八晶体管开启，以对所述第二节点进行充电，以及使所述第九晶体管开启，将所述第三节点上拉至高电位。
  13. 根据权利要求4所述的驱动电路，其中，所述下拉部分与所述第一节点、所述第三节点、所述第一低电位端、所述第二低电位端、所述本级级联输出端、所述本级扫描输出端以及所述后级级联输出端电性连接；
    所述下拉部分包括第四晶体管、第十五晶体管和第十八晶体管；
    所述第四晶体管的第一极与所述第三节点、所述第十五晶体管的第一极以及所述第十八晶体管的第一极电性连接，所述第四晶体管的第二极电性连接于所述第一节点，所述第四晶体管的第三极与所述第十五晶体管的第二极以及所述本级级联输出端电性连接，所述第十五晶体管的第三极与所述第一低电位端电性连接。
  14. 根据权利要求13所述的驱动电路，其中，所述第十八晶体管的第二极电性连接于所述本级扫描输出端，所述第十八晶体管的第三极电性连接于所述第二低电位端。
  15. 根据权利要求13所述的驱动电路，其中，所述下拉部分还包括第十六晶体管、第十七晶体管；
    所述第十六晶体管的第一极与所述后级级联输出端、第十七晶体管的第一极电性连接，所述第十六晶体管的第二极与所述本级级联输出端电性连接，所述第十六晶体管的第三极与所述第一低电位端电性连接；
    所述第十七晶体管的第二极与所述驱动部分的去耦电容的第一极和所述第十八晶体管的第二极电性连接，所述第十七晶体管的第三极与所述第二低电位端以及所述第十八晶体管的第三极电性连接。
  16. 根据权利要求4所述的驱动电路，其中，所述驱动部分与所述时钟信号端、第一节点、本级级联输出端、本级扫描输出端电性连接；
    所述驱动部分包括第五晶体管、第六晶体管和去耦电容；
    所述第五晶体管的第一极与所述第一节点、所述第六晶体管的第一极以及所述去耦电容的第二极电性连接，所述第五晶体管的第二极与所述时钟信号端以及所述第六晶体管的第二极电性连接，所述第五晶体管的第三极电性连接于所述本级级联输出端，所述第六晶体管的第三极电性连接于所述本级扫描输出端。
  17. 根据权利要求4所述的驱动电路，其中，所述时钟信号端的时钟信号为M相时钟信号，其中，M为大于或者等于2的整数；
    所述第N级栅极驱动单元电路和第N+1级栅极驱动单元电路分别与对应于不同时钟信号的时钟信号端电性连接。
  18. 根据权利要求17所述的驱动电路，其中，M=2；
    所述复位信号端连接至第N+k级级联输出端，其中，k为大于等于2的整数。
  19. 根据权利要求4所述的驱动电路，其中，所述下拉控制部分还用于在初始化阶段和下拉及低电平维持阶段中的下拉阶段利用所述第一初始化信号端的第一初始化信号和所述第二初始化信号端的第二初始化信号，以及所述前级级联输出端的前级级联输出信号和所述后级级联输出端的后级级联输出信号对所述第二节点进行两次自举，以保证所述第三节点在本级输出前后均可以实现满摆幅输出。
  20. 根据权利要求4所述的驱动电路，其中，所述第一节点位于所述输入部分的第二晶体管的第三极与所述驱动部分的第五晶体管的第一极之间；
    所述第二节点位于所述下拉控制部分的第七晶体管的第三极与所述下拉控制部分的耦合电容的第一极之间；
    所述第三节点位于所述下拉部分的第十八晶体管的第一极与所述下拉控制部分的第十四晶体管的第二极之间。
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