WO2021007937A1 - 显示面板测试电路 - Google Patents

显示面板测试电路 Download PDF

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Publication number
WO2021007937A1
WO2021007937A1 PCT/CN2019/104614 CN2019104614W WO2021007937A1 WO 2021007937 A1 WO2021007937 A1 WO 2021007937A1 CN 2019104614 W CN2019104614 W CN 2019104614W WO 2021007937 A1 WO2021007937 A1 WO 2021007937A1
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Prior art keywords
signal line
display panel
electrically connected
mos transistors
pin
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PCT/CN2019/104614
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English (en)
French (fr)
Inventor
王朝欢
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武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/637,807 priority Critical patent/US11222561B2/en
Publication of WO2021007937A1 publication Critical patent/WO2021007937A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel test circuit.
  • AMOLED Active-matrix organic light-emitting diode, active matrix organic light-emitting diode
  • LCD Liquid crystal Display, liquid crystal display
  • FIG. 1 is a schematic diagram of a display panel of an existing AMOLED mobile phone.
  • a second fanout area 11 In the border area under the panel, there are a second fanout area 11, a bending area 12, and a first fanout area 13, from top to bottom.
  • a cell test area 14 and a bonding area 15 are provided with test pad areas on the left and right sides of the bonding area 15 (as shown at 16 in FIG. 2).
  • the test pad area 16 is used for the lighting test of the panel, and after the test is qualified, the panel will undergo a module manufacturing process, and finally an AMOLED display panel will be produced.
  • FIG. 2 is a schematic diagram of the wiring in the frame area under the display panel of the existing AMOLED mobile phone.
  • the signal is input through the test pad area 16 on the flexible printed circuit board (FPC) pressing the panel.
  • the left and right test pad areas 16 are symmetrical, each with 20
  • the remaining pins, of which there is a dummy pin on the left and right, the input signals of the remaining pins can be divided into three categories, the first category (CK, VGL, VGH, etc.) is directly connected to the GOA (Gate on array) area, Used to provide gate lines, the second type (CT_EN and CT_data) is connected to the test area 14 to provide data signals, and the third type (VDD and VSS) provides power for the panel.
  • the test area 14 provides data signals for the panel, and when the module reaches the lighting stage, the flexible printed circuit board and IC bound to the panel provide data signals for the panel.
  • the present invention provides a display panel test circuit to solve the technical problem of poor yield of AMOLED display panels.
  • the present invention provides a display panel test circuit, including: a plurality of MOS transistors; a first signal line, the first signal line is electrically connected to the gates of the plurality of MOS transistors; a second signal line, the second A signal line is electrically connected to the sources of some MOS transistors among the plurality of MOS transistors; and a third signal line is electrically connected to the sources of other MOS transistors among the plurality of MOS transistors; wherein The sources of any two adjacent MOS transistors in the plurality of MOS transistors are electrically connected to the second signal line and the third signal line, respectively.
  • the first signal line is a driving signal line
  • the second signal line and the third signal line are data signal lines.
  • the driving signal line is a green driving signal line
  • the data signal line is a green data signal line
  • the third signal line when the second signal line is at a low potential, the third signal line is at a high potential, and when the third signal line is at a low potential, the second signal The line is high.
  • the display panel is an AMOLED display panel.
  • the MOS transistor is a PMOS transistor.
  • the present invention also provides a test pad pin of a display panel test circuit, which is electrically connected to the display panel test circuit, and the test pad pin includes an odd-numbered green data signal pin, which is electrically connected to the second signal line.
  • the test pad pins further include empty pins, and the empty pins are even-numbered green data signal pins, which are electrically connected to the third signal line.
  • the test pad pin further includes: a direct current signal pin; a test pin; and even green data located between the direct current signal pin and the test pin
  • the signal pin is electrically connected to the third signal line.
  • the test pad pins further include: empty pins; and even-numbered green data signal pins on one side of the empty pins, electrically connected to the third signal line.
  • the display panel test circuit provided by the present invention can detect the short circuit of the green data signal during the lighting test stage, thereby monitoring and improving the production yield of the AMOLED display panel.
  • Figure 1 is a schematic diagram of an existing AMOLED mobile phone display panel
  • Fig. 2 is a schematic diagram of the circuit of the frame area under the display panel of the existing AMOLED mobile phone
  • FIG. 3 is a schematic diagram of the circuit design of the display panel test circuit of the present invention.
  • FIG. 4 is a schematic diagram of the green data signal driving part of the display panel test circuit of the present invention.
  • FIG. 5 is a schematic diagram of an embodiment of the test pad pins of the display panel test circuit of the present invention.
  • FIG. 6 is a schematic diagram of another embodiment of the test pad pins of the display panel test circuit of the present invention.
  • the present invention is aimed at the technical problem that the existing test circuit cannot be detected when two adjacent data signal lines are short-circuited during the lighting test stage. This embodiment can solve the defect.
  • the display panel test circuit includes a plurality of MOS (Metal-Oxide-Semiconductor, Metal-oxide-semiconductor) transistors T3, T6; a first signal line W1, the first signal line W1 is electrically connected to the gates of the plurality of MOS transistors T3, T6; a second signal line W2, the first signal line W2 Two signal lines W2 are electrically connected to the sources of some of the MOS transistors; and a third signal line W3, the third signal line W3 is electrically connected to other MOS transistors Source; wherein the sources of any two adjacent MOS transistors in the plurality of MOS transistors are electrically connected to the second signal line W2 and the third signal line W3, respectively.
  • MOS Metal-Oxide-Semiconductor, Metal-oxide-semiconductor
  • the first signal line W1 is a driving signal line
  • the second signal line W2 and the third signal line W3 are data signal lines.
  • the driving signal line is a green driving signal line
  • the data signal line is a green data signal line.
  • the MOS transistor is a PMOS transistor.
  • Figure 3 only depicts two MOS transistors T3 and T6 corresponding to the green data signal, but in fact the MOS transistor corresponding to the green data signal includes other MOS transistors located in the same row corresponding to the green data signal MOS transistor.
  • the present invention optimizes the signal lines of the green data signal, and changes the signal lines that were originally electrically connected to the sources of the MOS transistors T3 and T6 into the second signal line W2 and the third signal line W3, and the signal lines corresponding to the green data signal MOS transistors (T3, T6, etc.) are divided into odd-numbered MOS transistors (T3, etc.) and even-numbered MOS transistors (T6, etc.), and then the second signal line W2 is electrically connected to the odd-numbered sequence
  • FIG. 4 is a schematic diagram of the green data signal driving part of the display panel test circuit of the present invention.
  • the third signal line W3 is at a high level, and when the third signal line W3 When it is at a low potential, the second signal line W2 is at a high potential.
  • the signal line W1 controls whether the data signal is input or not, and is in a normally open state, the signal line W2 controls the lighting of the pixels corresponding to the odd-numbered MOS transistors, and the signal line W3 controls the lighting of the pixels corresponding to the even-numbered MOS transistors.
  • the signal line W2 inputs 3V and the signal line W3 inputs 6V.
  • the two green data signals The voltage will change to about 4.5V, and two dark lines will appear in the screen of the lighting test, so you can quickly determine whether there is a data signal short circuit.
  • the signal line W3 inputs 3V and the signal line W2 inputs 6V.
  • the two adjacent MOS transistors corresponding to the green data signal are short-circuited, the two green data signals The voltage will become approximately 4.5V, and two dark lines will appear in the screen of the lighting test to quickly determine whether there is a short-circuit of the data signal.
  • test pad pins are electrically connected to the display panel test circuit of the present invention, and include odd-numbered green data signal pins 511, which are electrically connected ⁇ The second signal line W2.
  • the test pad pins further include empty pins, and the empty pins are even-numbered green data signal pins 610, which are electrically connected to the third signal line W3.
  • the test pad pins include DC signal pins 110, 120 and 130; test pins 210 and 220; GOA signal pins 310 and 320; drive signal pins 400; data signal pins 500 and are electrically connected to the third The even-numbered green data signal pins 610 of the signal line W3, wherein the data signal pins 500 include odd-numbered green data signal pins 511, blue data signal pins 520, and red data signal pins 530 electrically connected to the second signal line W2 .
  • the original green data signal pins are changed to odd-numbered green data signal pins 511, and the empty pins are changed to even-numbered green data signal pins 610. Therefore, the manufacturing process remains unchanged. It is necessary to add lines connected to the test circuit of the display panel of the present invention to the empty pins, and then the odd and even numbers of MOS transistors can be controlled separately.
  • test pad pins are a schematic diagram of another embodiment of the test pad pins of the display panel test circuit of the present invention.
  • the test pad pins further include even numbers between the DC signal pins 120 and the test pins 210.
  • the green data signal pin 700 is electrically connected to the third signal line W3.
  • the test pad pins further include an even-numbered green data signal pin (not shown) on one side of the empty pin 600, which is electrically connected to the third signal line W3.
  • Fig. 6 is a test pad pin of another embodiment of the present invention.
  • the difference from Fig. 5 is that an even green data signal pin electrically connected to the third signal line W3 is added between the test pin 210 and the DC signal pin 120 700.
  • the increased position of the even-numbered green data signal pin electrically connected to the third signal line W3 is located on one side of the empty pin 600 (not shown), thereby achieving separate control of the odd and even number of MOS transistors .
  • the display panel test circuit provided by the present invention can detect the short circuit of the green data signal during the lighting test stage, thereby monitoring and improving the production yield of AMOLED display panels.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板测试电路，包括：多个MOS晶体管；第一信号线(W1)，第一信号线(W1)电连接于多个MOS晶体管的栅极；第二信号线(W2)，第二信号线(W2)电连接于多个MOS晶体管中部份MOS晶体管的源极；及第三信号线(W3)，第三信号线(W3)电连接于多个MOS晶体管中其他MOS晶体管的源极；其中，多个MOS晶体管中任两相邻MOS晶体管的源极分别电连接于第二信号线(W2)与第三信号线(W3)。显示面板测试电路可以在点灯测试阶段检测到绿色资料信号短路的问题，藉此监测以及提高AMOLED显示面板的生产良率。

Description

显示面板测试电路 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板测试电路。
 背景技术
AMOLED(Active-matrix organic light-emitting diode, 主动矩阵有机发光二极体)显示面板与LCD(Liquid crystal display, 液晶显示器)相比具有自发光的独特优势，且具有能耗小、对比度高、色域广以及可折叠等具有竞争力的优点，已经成为目前的主流显示面板，但是AMOLED显示面板仍然有良率不佳的问题。
图1为现有AMOLED手机显示面板的示意图，在面板下方的边框(border)区域中，由上而下有第二扇出(fanout)区11、弯折区12、第一扇出区13、测试(cell test)区14和绑定(bonding)区15，以及在绑定区15的左右两边设有测试焊垫(pad)区(如图2中的16所示)。测试焊垫区16用于面板的点灯测试，而在测试合格后，会对面板进行模组的制程，最终会产出AMOLED显示面板。
图2为现有AMOLED手机显示面板下方边框区域的线路示意图。在点灯测试阶段，通过柔性印刷电路板(FPC)压合面板上的测试焊垫区16来输入信号，以覆晶薄膜(COF)为例，左右测试焊垫区16为对称，各有二十余个引脚，其中左右各有一个空(dummy) 引脚，其余引脚的输入信号可分为三类，第一类（CK、VGL、VGH等）直接连接GOA(Gate on array)区，用于提供栅极线，第二类（CT_EN和CT_data）连接测试区14，用于提供资料信号，第三类（VDD和VSS）为面板提供电源。在点灯测试阶段由测试区14为面板提供资料信号，到达模组点灯阶段由绑定在面板上的柔性印刷电路板及IC为面板提供资料信号。
在点灯测试阶段，当相邻两条资料信号线发生短路时，以现在的测试电路并无法检测出来，因为所有的资料信号线均电连接于同一条输入线，在点灯测试的画面中会显示一致的结果，但是到了模组绑定阶段之后就会显现出一些异常，需要再次进行重工(rework)修复，过程比较复杂且影响制程良率。
 技术问题
本发明提供一种显示面板测试电路，以解决AMOLED显示面板良率不佳的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种显示面板测试电路，包括：多个MOS晶体管；第一信号线，所述第一信号线电连接于所述多个MOS晶体管的栅极；第二信号线，所述第二信号线电连接于所述多个MOS晶体管中部份MOS晶体管的源极；及第三信号线，所述第三信号线电连接于所述多个MOS晶体管中其他MOS晶体管的源极；其中，所述多个MOS晶体管中任两相邻MOS晶体管的源极分别电连接于所述第二信号线与所述第三信号线。
在本发明的至少一种实施例中，所述第一信号线为驱动信号线，所述第二信号线与所述第三信号线为资料信号线。
在本发明的至少一种实施例中，所述驱动信号线为绿色驱动信号线，所述资料信号线为绿色资料信号线。
在本发明的至少一种实施例中，当所述第二信号线为低电位时，所述第三信号线为高电位，当所述第三信号线为低电位时，所述第二信号线为高电位。
在本发明的至少一种实施例中，所述显示面板为AMOLED显示面板。
在本发明的至少一种实施例中，所述MOS晶体管为PMOS晶体管。
本发明还提供一种显示面板测试电路的测试焊垫引脚，电连接于所述显示面板测试电路，所述测试焊垫引脚包括奇数绿色资料信号引脚，电连接于所述第二信号线。
在本发明的至少一种实施例中，所述测试焊垫引脚更包括空引脚，所述空引脚为偶数绿色资料信号引脚，电连接于所述第三信号线。
在本发明的至少一种实施例中，所述测试焊垫引脚更包括: 直流信号引脚；测试引脚；及位于所述直流信号引脚与所述测试引脚之间的偶数绿色资料信号引脚，电连接于所述第三信号线。
在本发明的至少一种实施例中，所述测试焊垫引脚更包括: 空引脚；及位于所述空引脚一侧的偶数绿色资料信号引脚，电连接于所述第三信号线。
 有益效果
本发明提供的显示面板测试电路，可以在点灯测试阶段检测到绿色资料信号短路的问题，藉此监测以及提高AMOLED显示面板的生产良率。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有AMOLED手机显示面板的示意图；
图2为现有AMOLED手机显示面板下方边框区域的线路示意图；
图3为本发明显示面板测试电路的电路设计示意图；
图4为本发明显示面板测试电路中绿色资料信号驱动部分的示意图；
图5为本发明显示面板测试电路的测试焊垫引脚一实施例的示意图；
图6为本发明显示面板测试电路的测试焊垫引脚另一实施例的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明针对现有的测试电路在点灯测试阶段，当相邻两条资料信号线发生短路时无法检测出来的技术问题，本实施例能够解决该缺陷。
图3为本发明显示面板测试电路的电路设计示意图，本发明主要讨论绿色资料信号(G data)。所述显示面板测试电路包括多个MOS(Metal-Oxide-Semiconductor, 金属-氧化物-半导体)晶体管T3、T6；第一信号线W1，所述第一信号线W1电连接于所述多个MOS晶体管T3、T6的栅极；第二信号线W2，所述第二信号线W2电连接于所述多个MOS晶体管中部份MOS晶体管的源极；及第三信号线W3，所述第三信号线W3电连接于所述多个MOS晶体管中其他MOS晶体管的源极；其中，所述多个MOS晶体管中任两相邻MOS晶体管的源极分别电连接于所述第二信号线W2与所述第三信号线W3。所述第一信号线W1为驱动信号线，所述第二信号线W2与所述第三信号线W3为资料信号线。所述驱动信号线为绿色驱动信号线，所述资料信号线为绿色资料信号线。所述MOS晶体管为PMOS晶体管。
为了清楚说明本发明的测试电路，图3仅绘出两个对应于绿色资料信号的MOS晶体管T3、T6，但实际上对应于绿色资料信号的MOS晶体管还包括其他位于同一列对应于绿色资料信号的MOS晶体管。本发明对绿色资料信号的信号线进行优化，将原本电连接于MOS晶体管T3及T6源极的信号线，更改为第二信号线W2与第三信号线W3，并将对应于绿色资料信号的MOS晶体管(T3、T6等)区分为顺序是第奇数个的MOS晶体管(T3等)以及顺序是第偶数个的MOS晶体管(T6等)，然后把第二信号线W2电连接于顺序是第奇数个的MOS晶体管(T3等)的源极，第三信号线W3则是电连接于顺序是第偶数个的MOS晶体管(T6等) 的源极，形成以第二信号线W2及第三信号线W3分别对第奇数个MOS晶体管(T3等)及第偶数个MOS晶体管(T6等) 进行驱动的电路设计，即任两相邻对应于绿色资料信号的MOS晶体管的源极分别电连接于第二信号线W2与第三信号线W3。当点亮第奇数个MOS晶体管(T3等)或者点亮第偶数个MOS晶体管(T6等)时，如果对应于绿色资料信号的相邻两个MOS晶体管发生短路的问题，就会在点灯测试的画面中以两条暗线的形式体现出来，极大的避免了资料信号短路在点灯测试阶段未检测出来的可能性，提高了模组制程良率。
图4为本发明显示面板测试电路中绿色资料信号驱动部分的示意图，当所述第二信号线W2为低电位时，所述第三信号线W3为高电位，当所述第三信号线W3为低电位时，所述第二信号线W2为高电位。信号线W1控制资料信号的输入与否，处于常开状态，信号线W2控制第奇数个MOS晶体管对应像素的点亮情况，信号线W3控制第偶数个MOS晶体管对应像素的点亮情况。当控制第奇数个MOS晶体管对应的像素点亮时，信号线W2输入3V，信号线W3输入6V，如果对应于绿色资料信号的相邻两个MOS晶体管发生短路的问题，两条绿色资料信号的电压会变为大约4.5V，在点灯测试的画面中会出现两条暗线，因此可以快速判断是否存在资料信号短路的情况。当控制第偶数个MOS晶体管对应的像素点亮时，信号线W3输入3V，信号线W2输入6V，如果对应于绿色资料信号的相邻两个MOS晶体管发生短路的问题，两条绿色资料信号的电压会变为大约4.5V，在点灯测试的画面中会出现两条暗线，藉此快速判断是否存在资料信号短路的情况。
图5为本发明显示面板测试电路的测试焊垫引脚一实施例的示意图，所述测试焊垫引脚电连接于本发明的显示面板测试电路，包括奇数绿色资料信号引脚511，电连接于所述第二信号线W2。在一种实施例中，所述测试焊垫引脚更包括空引脚，所述空引脚为偶数绿色资料信号引脚610，电连接于所述第三信号线W3。
所述测试焊垫引脚包括直流信号引脚110、120和130；测试引脚210和220；GOA信号引脚310和320；驱动信号引脚400；资料信号引脚500以及电连接于第三信号线W3的偶数绿色资料信号引脚610，其中资料信号引脚500包括电连接于第二信号线W2的奇数绿色资料信号引脚511、蓝色资料信号引脚520以及红色资料信号引脚530。本实施例的测试焊垫引脚将原有的绿色资料信号引脚改为奇数绿色资料信号引脚511，并将空引脚改为偶数绿色资料信号引脚610，因此制程工艺不变，只需对空引脚增加连接本发明显示面板测试电路的线路，就可以实现奇偶数个MOS晶体管分别控制。
图6为本发明显示面板测试电路的测试焊垫引脚另一实施例的示意图，所述测试焊垫引脚更包括位于所述直流信号引脚120与所述测试引脚210之间的偶数绿色资料信号引脚700，电连接于所述第三信号线W3。在另一种实施例中，所述测试焊垫引脚更包括位于所述空引脚600一侧的偶数绿色资料信号引脚(图未示)，电连接于所述第三信号线W3。
图6本发明另一实施例的测试焊垫引脚，与图5的差异在于测试引脚210与直流信号引脚120之间增加了电连接于第三信号线W3的偶数绿色资料信号引脚700。在另一种实施例中，电连接于第三信号线W3的偶数绿色资料信号引脚增加的位置位于空引脚600的一侧(图未示)，借此实现奇偶数个MOS晶体管分别控制。
有益效果：本发明提供的显示面板测试电路，可以在点灯测试阶段检测到绿色资料信号短路的问题，藉此监测以及提高AMOLED显示面板的生产良率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种显示面板测试电路，包括：
    多个MOS晶体管；
    第一信号线，所述第一信号线电连接于所述多个MOS晶体管的栅极；
    第二信号线，所述第二信号线电连接于所述多个MOS晶体管中部份MOS晶体管的源极；及
    第三信号线，所述第三信号线电连接于所述多个MOS晶体管中其他MOS晶体管的源极；
    其中，所述多个MOS晶体管中任两相邻MOS晶体管的源极分别电连接于所述第二信号线与所述第三信号线。
  2. 根据权利要求1的显示面板测试电路，其中，所述第一信号线为驱动信号线，所述第二信号线与所述第三信号线为资料信号线。
  3. 根据权利要求2的显示面板测试电路，其中，所述驱动信号线为绿色驱动信号线，所述资料信号线为绿色资料信号线。
  4. 根据权利要求2的显示面板测试电路，其中，当所述第二信号线为低电位时，所述第三信号线为高电位，当所述第三信号线为低电位时，所述第二信号线为高电位。
  5. 根据权利要求1的显示面板测试电路，其中，所述显示面板为AMOLED显示面板。
  6. 根据权利要求1的显示面板测试电路，其中，所述MOS晶体管为PMOS晶体管。
  7. 一种显示面板测试电路的测试焊垫引脚，电连接于如权利要求1的显示面板测试电路，其中，所述测试焊垫引脚包括奇数绿色资料信号引脚，电连接于所述第二信号线。
  8. 根据权利要求7的测试焊垫引脚，其中，更包括空引脚，所述空引脚为偶数绿色资料信号引脚，电连接于所述第三信号线。
  9. 根据权利要求7的测试焊垫引脚，其中，更包括:
    直流信号引脚；
    测试引脚；及
    位于所述直流信号引脚与所述测试引脚之间的偶数绿色资料信号引脚，电连接于所述第三信号线。
  10. 根据权利要求7的测试焊垫引脚，其中，更包括:
    空引脚；及
    位于所述空引脚一侧的偶数绿色资料信号引脚，电连接于所述第三信号线。
  11. 一种显示面板测试电路，包括：
    多个MOS晶体管；
    第一信号线，所述第一信号线电连接于所述多个MOS晶体管的栅极；
    第二信号线，所述第二信号线电连接于所述多个MOS晶体管中部份MOS晶体管的源极；及
    第三信号线，所述第三信号线电连接于所述多个MOS晶体管中其他MOS晶体管的源极；
    其中，所述多个MOS晶体管中任两相邻MOS晶体管的源极分别电连接于所述第二信号线与所述第三信号线，当所述第二信号线为低电位时，所述第三信号线为高电位，当所述第三信号线为低电位时，所述第二信号线为高电位。
  12. 根据权利要求11的显示面板测试电路，其中，所述第一信号线为驱动信号线，所述第二信号线与所述第三信号线为资料信号线。
  13. 根据权利要求12的显示面板测试电路，其中，所述驱动信号线为绿色驱动信号线，所述资料信号线为绿色资料信号线。
  14. 根据权利要求11的显示面板测试电路，其中，所述显示面板为AMOLED显示面板。
  15. 根据权利要求11的显示面板测试电路，其中，所述MOS晶体管为PMOS晶体管。
  16. 一种显示面板测试电路的测试焊垫引脚，电连接于如权利要求11的显示面板测试电路，其中，所述测试焊垫引脚包括奇数绿色资料信号引脚，电连接于所述第二信号线。
  17. 根据权利要求16的测试焊垫引脚，其中，更包括空引脚，所述空引脚为偶数绿色资料信号引脚，电连接于所述第三信号线。
  18. 根据权利要求16的测试焊垫引脚，其中，更包括:
    直流信号引脚；
    测试引脚；及
    位于所述直流信号引脚与所述测试引脚之间的偶数绿色资料信号引脚，电连接于所述第三信号线。
  19. 根据权利要求16的测试焊垫引脚，其中，更包括:
    空引脚；及
    位于所述空引脚一侧的偶数绿色资料信号引脚，电连接于所述第三信号线。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210055375A (ko) * 2019-11-07 2021-05-17 엘지디스플레이 주식회사 표시 장치 및 표시 장치의 데이터 링크 라인 결함 검출 방법
CN111681609A (zh) * 2020-06-11 2020-09-18 武汉华星光电半导体显示技术有限公司 一种显示装置和驱动电路检测方法
CN111864108B (zh) * 2020-07-13 2022-01-04 武汉华星光电半导体显示技术有限公司 Oled显示面板
CN112037656B (zh) * 2020-09-11 2022-06-21 京东方科技集团股份有限公司 一种显示装置和显示装置的绑定检测方法
CN112270908B (zh) * 2020-11-27 2023-07-28 武汉天马微电子有限公司 阵列基板、阵列基板母板、显示面板及其制备方法
CN112289243A (zh) * 2020-11-30 2021-01-29 上海天马有机发光显示技术有限公司 显示面板及其制备方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057112A (zh) * 2016-08-09 2016-10-26 武汉华星光电技术有限公司 成盒测试电路以及液晶显示基板
CN106652967A (zh) * 2017-03-21 2017-05-10 厦门天马微电子有限公司 显示面板、显示装置和应用于显示面板的驱动方法
CN106773174A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 显示面板的测试方法与测试装置
CN207198278U (zh) * 2017-09-30 2018-04-06 安徽金视界光电科技有限公司 一种高路数小pitch的电测板结构
KR20180036841A (ko) * 2016-09-30 2018-04-10 엘지디스플레이 주식회사 터치 패널 및 그 검사방법과 터치 패널을 포함하는 액정 표시장치
CN108806563A (zh) * 2018-04-27 2018-11-13 南京中电熊猫平板显示科技有限公司 一种检测电路及显示面板

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2490861A1 (en) * 2004-12-01 2006-06-01 Ignis Innovation Inc. Fuzzy control for stable amoled displays
US7298165B2 (en) * 2006-01-20 2007-11-20 Chunghwa Picture Tubes, Ltd. Active device array substrate, liquid crystal display panel and examining methods thereof
CN101540134B (zh) * 2009-04-08 2010-12-08 深圳华映显示科技有限公司 一种检测显示面板的方法
CN102768815B (zh) * 2012-07-23 2015-04-08 京东方科技集团股份有限公司 Dds检测结构及检测方法
US9443469B2 (en) * 2013-11-22 2016-09-13 Global Oled Technology Llc Pixel circuit, driving method, display device, and inspection method
KR102270083B1 (ko) * 2014-10-13 2021-06-29 삼성디스플레이 주식회사 유기 발광 표시 패널 및 테스트 방법
KR102439225B1 (ko) * 2015-08-31 2022-09-01 엘지디스플레이 주식회사 유기 발광 표시장치와 그 구동 장치 및 방법
CN105261317B (zh) * 2015-09-17 2018-05-29 京东方科技集团股份有限公司 数据线短接不良的检测方法和检测装置
CN106297615B (zh) * 2016-09-09 2017-12-22 京东方科技集团股份有限公司 显示装置的检测电路及方法
CN106935167A (zh) * 2017-05-19 2017-07-07 京东方科技集团股份有限公司 用于显示面板画面测试的装置及显示面板画面的测试方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057112A (zh) * 2016-08-09 2016-10-26 武汉华星光电技术有限公司 成盒测试电路以及液晶显示基板
KR20180036841A (ko) * 2016-09-30 2018-04-10 엘지디스플레이 주식회사 터치 패널 및 그 검사방법과 터치 패널을 포함하는 액정 표시장치
CN106773174A (zh) * 2016-12-30 2017-05-31 武汉华星光电技术有限公司 显示面板的测试方法与测试装置
CN106652967A (zh) * 2017-03-21 2017-05-10 厦门天马微电子有限公司 显示面板、显示装置和应用于显示面板的驱动方法
CN207198278U (zh) * 2017-09-30 2018-04-06 安徽金视界光电科技有限公司 一种高路数小pitch的电测板结构
CN108806563A (zh) * 2018-04-27 2018-11-13 南京中电熊猫平板显示科技有限公司 一种检测电路及显示面板

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