WO2021004438A1 - 一种芯片失效定位方法 - Google Patents

一种芯片失效定位方法 Download PDF

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WO2021004438A1
WO2021004438A1 PCT/CN2020/100497 CN2020100497W WO2021004438A1 WO 2021004438 A1 WO2021004438 A1 WO 2021004438A1 CN 2020100497 W CN2020100497 W CN 2020100497W WO 2021004438 A1 WO2021004438 A1 WO 2021004438A1
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chip
emmi
effect
effect map
adapter board
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PCT/CN2020/100497
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English (en)
French (fr)
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单书珊
陈燕宁
付振
赵扬
潘成
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北京智芯微电子科技有限公司
国网信息通信产业集团有限公司
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Publication of WO2021004438A1 publication Critical patent/WO2021004438A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement

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  • This application relates to the technical field of chip failure analysis, and in particular to a method for locating failures of high-density packaged chips based on a manual wire bonding machine.
  • Emission Microscope Emission Microscope
  • OBIRCH Laser Beam Induced Resistance Change
  • EMMI Emission Microscope
  • OBIRCH Laser Beam Induced Resistance Change
  • EMMI uses an indium gallium arsenide probe to capture the photons generated during the electron-hole recombination process in the chip, and then performs background processing through computer operations to form hot spot labels. Perform the above experiment on the failed sample and the good product with the same sample, compare the difference between the good sample and the failed sample, and locate the failure point.
  • EMMI is mainly used for Junction Leakage, Contact Spiking, Gate Oxide Defects, Hot Electrons, Latch Up, etc.
  • OBIRCH uses a laser beam to induce resistance changes. It is mainly used for Ohmic Short, Metal Line Defect, ESD Defect, Low Power Leakage (Low Power Leakage), etc.
  • the chip is usually fixed in the chip package, and the function of the chip package is to place, fix, seal, protect the chip and enhance the electrothermal performance.
  • the chip is fixed in the chip package in two forms, one is the wire bonding form and the other is the flip chip form.
  • the EMMI experiment is mostly suitable for barely exposing the back of the chip, because photons easily penetrate the silicon and overflow.
  • the OBIRCH experiment is mostly suitable for front opening, which is conducive to the laser heating the sample to capture the resistance change.
  • a laser unsealing machine is generally used to pre-open the plastic part of the chip package, and after unsealing, the plastic part of the chip package is continuously etched until the chip surface or the back of the chip is corroded.
  • EMMI or OBIRCH experiments can be performed by directly connecting external pins through probes, but most flip-chip packages cannot be tested through probe connection pins.
  • the direct unpacking test method mainly applies to the package type with external pins. After the chip package is opened on the back, the external pins of the package can be directly connected, and then the back of the chip is opened, and the EMMI or OBIRCH test is performed after unpacking.
  • the main problem is this
  • the method is only applicable to package types whose external pins extend beyond the package body, such as flat package (QFP), integrated circuit package (SOP), surface mount package (PLCC), etc.
  • This method is not suitable for other pin-type packages without super-packages, such as ball grid array (BGA), surface mount (QFN), chip-scale packaging (CSP) and other high-density packages, so this method has great disadvantages .
  • the main problem of the Kaifeng welding method is that it is easily affected by the level and density of welders.
  • the pins of the chip package are led out by soldering to achieve the characteristics of, for example, QFP and SOP type packages.
  • the level of the welding personnel directly leads to the feasibility of this method, and the method has problems of adhesion and inequality during welding. Therefore, welding is largely affected by the experience of the engineer and the controllability is relatively low.
  • high-density packaging is developing rapidly, and the pitch value of the pins is very low, and manual soldering can no longer meet the needs of high-density packaging.
  • the main problem of the direct chip and die test method is the need for front-side EMMI testing.
  • Most high-density packages use 6 or more levels of metal wiring. Too many metal wiring layers will prevent the photons from the device layer from overflowing, causing photons to flow from the edges or open areas. Overflow, resulting in inaccurate location of the hot spot and inaccurate positioning.
  • the purpose of the embodiments of the present application is to provide a chip failure location method, specifically a high-density package chip failure location method based on a manual wire bonding machine, which can overcome the above-mentioned problems of the prior art.
  • an embodiment of the present application provides a method for locating a chip failure.
  • the method includes the following steps:
  • Step (S) 101 Based on the connection between the chip and the adapter board, obtain a low-light microscope analysis EMMI effect diagram of the chip in the connection mode; wherein, the chip and the adapter board are tied The connection performed by the wire machine connecting the pin to be tested of the chip with the designated pin of the adapter board;
  • the method further includes:
  • the pre-winding of the adapter plate in step S1 is specifically: slotting in the center of the adapter plate according to the window size of the chip.
  • setting the wire binding machine parameters in step S6 includes: setting the ultrasonic power to 200-230W, the ultrasonic time to 100-150S, and the ultrasonic pressure to 125Pa.
  • setting the wire binding machine parameters in step S6 further includes: setting the welding temperature to normal temperature.
  • the thickness of the transparent thin glass slide is 1 millimeter (mm).
  • hot melt wax is used for bonding in both steps S4 and S5.
  • step S7 a wire binding machine is used to connect the pins to be tested of the chip with the designated pins of the adapter board through the key alloy-copper, gold-tin, gold-nickel.
  • using EMMI to locate the failure location of the chip in step S8 is: matching the EMMI effect map of the chip with the EMMI effect map of the failed sample and the good sample respectively, when the EMMI effect map of the chip and the failed sample If the EMMI effect map of the chip matches, it is determined that the chip is invalid; the EMMI effect map of the chip is compared with the EMMI effect map of a good sample, and the EMMI effect map of the chip is different from the EMMI effect map of the good sample.
  • the position of the effect map is regarded as the failure position of the chip, and the failure position of the chip is located in this way.
  • the chip positioning method provided by the embodiment of the present application includes: based on the connection between the chip and the adapter board, obtaining the EMMI effect diagram of the chip in the connection mode; wherein, between the chip and the adapter board is Use a wire binding machine to connect the pins to be tested of the chip with the designated pins of the adapter board; determine whether the chip fails based on the EMMI effect diagram; determine the failure of the chip Next, determine the failure location of the chip.
  • the EMMI effect diagram of the chip is obtained, and the chip failure is determined based on the effect diagram. In the case of failure , To determine the failure location of the chip.
  • the method for locating the failure of a high-density packaged chip based on a manual wire binding machine also has the following advantages: the embodiment of the present application uses an adapter plate, a glass slide, and a manual wire binding machine In combination, by setting the manual binding machine parameters, it can be used with various metal materials such as nickel, tin, copper, etc., to overcome the problem that many types of packages cannot be tested in the direct unpacking test method, and it can also avoid the direct test of the chip and die. The method cannot locate the problem on the back, and has the advantages of low price and wide range of use. In the embodiment of this application, various materials such as printed circuit boards, solder bumps, nickel-plated pins, etc.
  • the binding parameters of the embodiments of this application can guarantee the formation of gold-copper, gold-tin, and gold-nickel
  • the adhesion of other materials is within the acceptable range of the test. Therefore, it overcomes the problems that the high-density package cannot be welded and the welding level is uneven and cannot be welded when the unsealing welding method encounters.
  • FIG. 1 is a flowchart of a method for locating a failure of a high-density package chip according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a COB adapter board that has undergone windowing pretreatment according to an embodiment of the application.
  • FIG. 3 is a schematic diagram of the connection of the chip, the slide glass and the adapter board in the embodiment of the present application.
  • FIG. 4 is a diagram showing the connection effect of the chip, the slide glass and the adapter board in the embodiment of the present application.
  • Fig. 5 is an effect diagram of an embodiment of the present application after binding wires.
  • Figure 6A is a good (sample) EMMI effect diagram of an embodiment of the present application.
  • Fig. 6B is an EMMI effect diagram of a failed (sample) product in an embodiment of the present application.
  • Fig. 7 is a flowchart of a failure location method according to an embodiment of the present application.
  • the embodiment of the application provides a method for locating chip failure. As shown in FIG. 7, the method includes the following steps:
  • Step (S) 101 Based on the connection between the chip and the adapter board, obtain a low-light microscope analysis EMMI effect diagram of the chip in the connection mode; wherein, the chip and the adapter board are tied The connection performed by the wire machine connecting the pin to be tested of the chip with the designated pin of the adapter board;
  • the EMMI technology is used to capture the photons generated during the electron-hole recombination process in the chip of the chip, and the EMMI effect map of the chip is obtained through calculation.
  • the EMMI effect diagram of the chip is obtained by connecting the pin under test of the chip with the designated pin of the adapter board by using a wire binding machine, and whether the chip is invalid is determined based on the effect diagram. In the case of determining the failure, determine the failure location of the chip. It overcomes the problem that many types of packages cannot be tested without extension pins in the direct unpacking test method, and it can also avoid the problem that the chip and die direct test method cannot be positioned on the back. This chip failure location solution has the advantage of a wide range of applications.
  • the chip failure location method in the embodiment of the present application may specifically be a high-density packaging chip failure location method based on a manual wire bonding machine.
  • the method for locating the failure of a high-density packaged chip based on a manual wire bonding machine includes the following steps: Step S1: Obtain a COB adapter board 1, and perform processing on the adapter board 1.
  • Step S2 Obtain the transparent thin glass slide 2;
  • Step S3 Unpack the back or the front of the chip 3 to expose the silicon base surface (note that the package connection relationship should not be damaged when opening);
  • Step S4 Turn the opening cover of the chip 3 towards the glass slide 2 and perform bonding and fixing;
  • Step S5 After the chip is bonded and fixed, the transparent thin glass slide is glued to the window opening 4 of the adapter plate so that the silicon base faces Observation surface;
  • Step S6 Set the binding machine parameters;
  • Step S7 Use the binding machine to connect the pins to be tested of the chip with the designated pins of the adapter board;
  • Step S8 Use EMMI to locate the chip failure position.
  • the pre-processing of window opening on the adapter plate in step S1 is specifically: slotting in the center of the adapter plate 1 according to the window size of the chip, as shown in FIG. 2.
  • the thickness of the transparent thin glass slide is 1 mm.
  • the two ends of the slide glass 2 are bonded to the adapter plate 1, and the chip 3 is located in the central slot of the adapter plate 1.
  • the open cover of the chip 3 faces the transparent thin glass slide 2, and hot melt wax is used for bonding. After the chip 3 is bonded and fixed, the transparent thin glass slide 2 is bonded by hot melt wax. Stick it to the window opening of the adapter board 1, and ensure that the silicon base of the chip faces the surface to be observed.
  • the effect diagram is shown in Figure 4.
  • setting the wire binding machine parameters in step S6 includes: setting the ultrasonic power to 200-230 watts (W), the ultrasonic time to 100-150 seconds (S), the ultrasonic pressure to 125 Pa (Pa), and the welding The temperature is normal temperature. Use the binding machine parameters set as above for welding.
  • step S7 a wire binding machine is used to connect the pins to be tested of the chip with the designated pins of the adapter board through the key alloy-copper, gold-tin, gold-nickel.
  • the effect diagram after binding the wire is shown in Figure 5.
  • using EMMI to locate the chip failure location in step S8 is: matching the EMMI effect map of the chip with the EMMI effect map of the failed sample and the good sample respectively, and the EMMI effect map of the chip and the failed sample If the EMMI effect map matches, it is determined that the chip is invalid.
  • Fig. 6A is a good product EMMI effect diagram of an embodiment of the present application.
  • Fig. 6B is an EMMI effect diagram of a failed product in an embodiment of the present application. If the chip has a failure position, its EMMI effect diagram should be similar to the effect diagram shown in Figure 6B; if the chip does not have a failure position, its EMMI effect diagram should be similar to the effect diagram shown in Figure 6a.
  • the EMMI effect diagram of the chip is compared with the EMMI effect diagram shown in Figure 6a, and the difference between the two EMMI effect diagrams is found.
  • the difference lies in the EMMI effect diagram of the chip
  • the middle is the failure position of the chip, as shown in the hot spot area (HOT SPOT) in Figure 6B.
  • An embodiment of the present invention also provides a computer storage medium that stores an executable program, and the executable program is used to implement the chip failure location method of the embodiment of the present application when the executable program is executed by a processor.
  • the storage medium includes volatile random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital Universal Disk (DVD) or other media being accessed.
  • a wire binding machine is used to connect the pins to be tested of the chip with the designated pins of the adapter board, and based on the connection, the EMMI effect diagram of the chip is obtained, and the chip is invalid based on the EMMI effect diagram of the chip.
  • determine the failure location of the chip determines the failure location of the chip. It overcomes the problem that many types of packages cannot be tested without extension pins in the direct unpacking test method, and it can also avoid the problem that the chip and die direct test method cannot be positioned on the back.
  • This chip failure location solution at least has the advantage of a wide range of applications.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本申请实施例公开了一种芯片失效定位方法，包括如下步骤：基于芯片与转接板之间的连接，获得在所述连接方式下所述芯片的微光显微镜分析EMMI效果图；其中，所述芯片与转接板之间为利用绑线机将所述芯片的待测针脚与所述转接板的指定管脚相连接而进行的连接；基于所述EMMI效果图，确定所述芯片是否失效；确定所述芯片失效的情况下，确定所述芯片的失效位置。

Description

一种芯片失效定位方法
相关申请的交叉引用
本申请基于申请号为201910602633.2、申请日为2019年07月05日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的内容在此以引入方式并入本申请。
技术领域
本申请涉及芯片失效分析技术领域，特别涉及一种基于手动绑线机的高密度封装芯片失效定位方法。
背景技术
芯片内部失效定位的手段通常有两种，一种是微光显微镜(Emission Microscope，简称EMMI)分析，一种是激光束电阻异常侦测(Optical Beam Induced Resistance Change，简称OBIRCH)。其中，EMMI是利用铟镓砷探头对芯片中电子空穴复合过程中产生的光子进行捕捉，而后通过电脑运算进行背景处理，形成热点标注。对失效样品及好品以同样样品进行上述实验，对比好样品及失效样品之间的差异，从而定位到失效点。EMMI主要用于结漏电(Junction Leakage)、接触毛刺(Contact spiking)、栅氧化缺陷(Gate oxide defects)、热电子(Hot electrons)、闩锁效应(Latch up)等。OBIRCH是利用激光束感生电阻变化，其主要用于欧姆短路(Ohmic Short)、金属线缺陷(Metal line Defect)、静电放电缺陷(ESD Defect)、Low power leakage(Low power leakage)等。
芯片通常固定在芯片封装内，芯片封装的作用是安放、固定、密封、保护芯片和增强电热性能的作用。通常芯片固定在芯片封装内有两种形式，一种是绑线(Wire bonding)形式，一种是倒装(Flip chip)形式。然而，在采用上述两种方法进行实验时，均需要将芯片开封，而EMMI实验多适合裸露出芯片背面，因为光子易穿透硅而溢出。OBIRCH实验多适合正面开，利于激光对样品加热，从而捕获到电阻变化。现有技术通常采用激光开封机对芯片封装的塑封部分进行预开封，开封后继续用酸液腐蚀直至腐蚀至芯片表面或芯片背部。对于可引出管脚的封装类型，通过探针直接连接外接针脚，即可进行EMMI或OBIRCH实验，但多数倒装(Flip chip)形式的封装则无法通过探针连接针脚测试。现有技术的一些测试方法存在以下问题：
直接开封测试法主要应有于存在外接部针脚的封装类型，芯片封装通过背面开封后，可以直接接上封装外部管脚，而后对芯片背面开封，开封后进行EMMI或OBIRCH测试，主要问题是该方法仅适用于外部针脚超出封装体的封装类型如：扁平式封装(QFP)、集成电路封装(SOP)、表面贴装型封装(PLCC)等。该方法不适用于其他无超封装体针脚型封装，如球栅阵列封装(BGA)、表面贴装型(QFN)、芯片级封装(CSP)等高密度封装，所以该方法存在很大的弊端。
开封焊接法主要问题是容易受焊接人员水平和密度影响。该方法是通过焊接的方法将芯片封装的针脚引出，达到例如QFP、SOP类型封装的特征。但由于焊接时焊接人员的水平直接导致了该方法是否可行，并且，该方法在焊接时存在粘连、高低不平等问题，所以，焊接很大程度上受工程师的经验影响，可控度比较低。而现今高密度封装发展迅猛，针脚的pitch值很低，人工焊接已经无法满足高密度封装的需求。
芯片取die直测法主要问题为需要正面进行EMMI测试，高密度封装多数采用6层甚至更多层次金属布线，过多金属布线层会阻挡器件层产生的光子溢出，导致光子自边缘或空旷区域溢出，致使热点位置不准确，不能准确定位。
因此，需要一种能够解决无法直接连接外接针脚的封装芯片失效定位问题(诸如QFN、BGA等)的方法。
公开于该背景技术部分的信息仅仅旨在增加对本申请的总体背景的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有技术。
发明内容
本申请实施例的目的在于提供一种芯片失效定位方法、具体是基于手动绑线机的高密度封装芯片失效定位方法，其能够克服现有技术的上述问题。
为实现上述目的，本申请实施例提供了一种芯片失效定位方法，该方法包括如下步骤：
步骤(S)101：基于芯片与转接板之间的连接，获得在所述连接方式下所述芯片的微光显微镜分析EMMI效果图；其中，所述芯片与转接板之间为利用绑线机将所述芯片的待测针脚与所述转接板的指定管脚相连接而进行的连接；
S102：基于所述EMMI效果图，确定所述芯片是否失效；
S103：确定所述芯片失效的情况下，确定所述芯片的失效位置。
在前述方案中，在S101之前，所述方法还包括：
S1：获得COB转接板，并对转接板进行开窗预处理，得到转接板的开窗 部位；
S2：获得透明薄载玻片；
S3：将芯片背面开封或者正面开封，以露出硅基面；
S4：将芯片的开封面朝向载玻片，并进行粘接固定；
S5：芯片粘接固定后将透明薄载玻片粘到转接板的开窗部位，使得硅基面朝向待观测面；
S6：设置绑线机参数；
S7：使用绑线机将芯片的待测针脚与转接板的指定管脚相连接；以及
S8：使用EMMI定位芯片失效位置。
在一实施方式中，步骤S1中对转接板进行开窗预处理具体为：根据芯片的开窗尺寸在转接板的中央开槽。
在一实施方式中，步骤S6中设置绑线机参数包括：设置超声功率为200-230W、超声时间为100-150S、超声压力为125Pa。
在一实施方式中，步骤S6中设置绑线机参数还包括：设置焊接温度为常温。
在一实施方式中，透明薄载玻片的厚度为1毫米(mm)。
在一实施方式中，步骤S4和S5中均采用热熔蜡进行粘接。
在一实施方式中，步骤S7中使用绑线机通过键合金-铜、金-锡、金-镍将芯片的待测针脚与转接板的指定管脚相连接。
在一实施方式中，步骤S8中使用EMMI定位芯片失效位置为：将所述芯片的EMMI效果图分别与失效样品和好样品的EMMI效果图进行匹配，当所述芯片的EMMI效果图与失效样品的EMMI效果图匹配的情况下，确定所述芯片失效；将所述芯片的EMMI效果图和好样品的EMMI效果图进行对比， 将所述芯片的EMMI效果图中不同于所述好样品的EMMI效果图的位置视为所述芯片的失效位置，如此定位出芯片的失效位置。
本申请实施例提供的芯片定位方法，包括：基于芯片与转接板之间的连接，获得在所述连接方式下所述芯片的EMMI效果图；其中，所述芯片与转接板之间为利用绑线机将所述芯片的待测针脚与所述转接板的指定管脚相连接而进行的连接；基于所述EMMI效果图，确定所述芯片是否失效；确定所述芯片失效的情况下，确定所述芯片的失效位置。通过利用绑线机将所述芯片的待测针脚与所述转接板的指定管脚进行连接，获得芯片的EMMI效果图，并基于效果图进行芯片是否失效的确定，在确定失效的情况下，确定芯片的失效位置。克服了直接开封测试法中由许多类型封装无外延针脚无法测试问题，也可以规避芯片取die直测法无法背面定位的问题，同时具备价格低廉、使用范围广的优点。
此外，与现有技术相比，根据本申请实施例的基于手动绑线机的高密度封装芯片失效定位方法还具有如下优点：本申请实施例通过转接板、载玻片与手动绑线机相结合，通过设置手动绑线机参数，可以与镍、锡、铜等多种金属材料，克服了直接开封测试法中由许多类型封装无外延针脚无法测试问题，也可以规避芯片取die直测法无法背面定位的问题，同时具备价格低廉、使用范围广的优点。本申请实施例通过绑线机可以绑定印制电路板、solder bump、镀镍针脚等多种材料，本申请实施例的绑线参数可以保证形成的金-铜、金-锡、金-镍等材料的粘结力在测试可接受范围内。因此，克服了开封焊接法遇到的高密度封装无法焊接及焊接水平参差不齐无法焊接的问题。
附图说明
图1是本申请实施例的高密度封装芯片失效定位方法的流程图。
图2是本申请实施例的经过开窗预处理的COB转接板示意图。
图3是本申请实施例的芯片、载玻片和转接板连接示意图。
图4是本申请实施例的芯片、载玻片和转接板连接效果图。
图5是本申请实施例的绑线后的效果图。
图6A是本申请实施例的好(样)品EMMI效果图。
图6B是本申请实施例的失效(样)品EMMI效果图；
图7是本申请实施例的失效定位方法的流程图。
具体实施方式
下面结合附图，对本申请的具体实施方式进行详细描述，但应当理解本申请的保护范围并不受具体实施方式的限制。
除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。
本申请实施例提供了一种芯片失效定位方法，如图7所示，该方法包括如下步骤：
步骤(S)101：基于芯片与转接板之间的连接，获得在所述连接方式下所述芯片的微光显微镜分析EMMI效果图；其中，所述芯片与转接板之间为利用绑线机将所述芯片的待测针脚与所述转接板的指定管脚相连接而进行的连接；
本步骤中，基于芯片与转接板之间的以上连接方式，利用EMMI技术， 对芯片的芯片中电子空穴复合过程中产生的光子进行捕捉，而通过运算得到芯片的EMMI效果图。
S102：基于所述EMMI效果图，确定所述芯片是否失效；
S103：确定所述芯片失效的情况下，确定所述芯片的失效位置。
S101～S103中，通过利用绑线机将所述芯片的待测针脚与所述转接板的指定管脚进行连接，获得芯片的EMMI效果图，并基于效果图进行芯片是否失效的确定，在确定失效的情况下，确定芯片的失效位置。克服了直接开封测试法中由许多类型封装无外延针脚无法测试问题，也可以规避芯片取die直测法无法背面定位的问题。这种芯片失效定位方案，具备使用范围广的优点。
本申请实施例中的芯片失效定位方法具体可以是一种基于手动绑线机的高密度封装芯片失效定位方法。如图1-5所示，根据本申请优选实施方式的基于手动绑线机的高密度封装芯片失效定位方法，包括如下步骤：步骤S1：获得COB转接板1，并对转接板1进行开窗预处理，得到开窗部位；步骤S2：获得透明薄载玻片2；步骤S3：将芯片3背面开封或者正面开封，露出硅基面(注意开封时不要破坏封装连接关系)；步骤S4：将芯片3的开封面朝向载玻片2，并进行粘接固定；步骤S5：芯片粘接固定后将透明薄载玻片粘到转接板的开窗部位4，使得硅基面朝向待观测面；步骤S6：设置绑线机参数；步骤S7：使用绑线机将芯片的待测针脚与转接板的指定管脚相连接；以及步骤S8：使用EMMI定位芯片失效位置。
上述方案中，步骤S1中对转接板进行开窗预处理具体为：根据芯片的开窗尺寸在转接板1的中央开槽，如图2所示。优选地，透明薄载玻片的厚度为1mm。在图2中，载玻片2的两端位置与粘接在转接板1上，芯片3位于转接板1的中央开槽内。
在一实施方式中，如图3所示，芯片3的开封面朝向透明薄载玻片2，使用热熔蜡进行粘接，芯片3粘接固定后使用热熔蜡把透明薄载玻片2粘到转接板1的开窗部位，并保证芯片硅基朝向待观测面，效果图如图4所示。
在一实施方式中，步骤S6中设置绑线机参数包括：设置超声功率为200-230瓦(W)、超声时间为100-150秒(S)、超声压力为125帕(Pa)，设置焊接温度为常温。利用如上设置的绑线机参数进行焊接。
在一实施方式中，步骤S7中使用绑线机通过键合金-铜、金-锡、金-镍将芯片的待测针脚与转接板的指定管脚相连接。绑线后的效果图如图5所示。
在一实施方式中，步骤S8中使用EMMI定位芯片失效位置为：将所述芯片的EMMI效果图分别与失效样品、好样品的EMMI效果图进行匹配，在所述芯片的EMMI效果图与失效样品的EMMI效果图匹配的情况下，确定所述芯片失效。在技术实现上，将所述芯片的EMMI效果图分别与失效样品的EMMI效果图、好样品的EMMI效果图进行相似度参数的计算，如计算出所述芯片的EMMI效果图与失效样品的EMMI效果图的相似度参数大于或高于计算出所述芯片的EMMI效果图与好样品的EMMI效果图的相似度参数，或者，计算出所述芯片的EMMI效果图与失效样品的EMMI效果图的相似度参数大于或高于预设的参数阈值如0.9，则认为所述芯片的EMMI效果图与失效样品的EMMI效果图匹配。
在确定所述芯片失效的情况下，将所述芯片的EMMI效果图和好样品的EMMI效果图进行对比，对比出两幅EMMI效果图的不同位置，将对比出的该不同位置作为芯片的失效位置，如此定位出芯片的失效位置。图6A是本申请实施例的好品EMMI效果图。图6B是本申请实施例的失效品EMMI效果图。如果芯片存在失效位置，则其EMMI效果图应该类似于图6B所示的效果 图；如果芯片不存在失效位置，则其EMMI效果图应该类似于图6a所示的效果图。
本申请实施例中假定芯片存在失效位置，则将芯片的EMMI效果图和图6a所示的EMMI效果图进行对比，查找出两个EMMI效果图的不同点，该不同点在芯片的EMMI效果图中即为芯片的失效位置，如图6B所示的热点区域(HOT SPOT)。
本发明实施例还提供一种计算机存储介质，存储有可执行程序，所述可执行程序被处理器执行时用于实现本申请实施例的芯片失效定位方法。该存储介质包括易挥发性随机存取存储器(RAM)、只读存储器(ROM)、电可擦可编程只读存储器(EEPROM)、闪存或其他存储器技术、只读光盘(CD-ROM)、数字通用盘(DVD)或其他被访问的他介质。
前述对本申请的具体示例性实施方案的描述是为了说明和例证的目的。这些描述并非想将本申请限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本申请的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本申请的各种不同的示例性实施方案以及各种不同的选择和改变。本申请的范围意在由权利要求书及其等同形式所限定。
工业实用性
本申请实施例中，利用绑线机将芯片的待测针脚与转接板的指定管脚进行连接，基于所述连接，获得芯片的EMMI效果图，并基于芯片的EMMI效果图进行芯片是否失效的确定，在确定失效的情况下，确定芯片的失效位置。克服了直接开封测试法中由许多类型封装无外延针脚无法测试问题，也可以规避芯片取die直测法无法背面定位的问题。这种芯片失效定位方案，至少具备使用范围广的优点。

Claims (10)

  1. 一种芯片失效定位方法，所述方法包括如下步骤：
    基于芯片与转接板之间的连接，获得在所述连接方式下所述芯片的微光显微镜分析EMMI效果图；其中，所述芯片与转接板之间为利用绑线机将所述芯片的待测针脚与所述转接板的指定管脚相连接而进行的连接；
    基于所述EMMI效果图，确定所述芯片是否失效；
    确定所述芯片失效的情况下，确定所述芯片的失效位置。
  2. 如权利要求1所述的方法，其中，所述基于所述EMMI效果图，确定所述芯片是否失效，包括：
    将所述芯片的EMMI效果图分别与失效样品、好样品的EMMI效果图进行匹配；
    在所述芯片的EMMI效果图与失效样品的EMMI效果图匹配的情况下，确定所述芯片失效。
  3. 根据权利要求2所述的方法，其中，所述方法还包括：
    将所述芯片的EMMI效果图分别与失效样品的EMMI效果图、好样品的EMMI效果图进行相似度参数的计算；
    计算出所述芯片的EMMI效果图与失效样品的EMMI效果图的相似度参数大于或高于计算出所述芯片的EMMI效果图与好样品的EMMI效果图的相似度参数；或者，计算出所述芯片的EMMI效果图与失效样品的EMMI效果图的相似度参数大于或高于预设的参数阈值，则所述芯片的EMMI效果图与失效样品的EMMI效果图匹配。
  4. 如权利要求1至3任一所述的方法，其中，所述确定所述芯片失效的情况下，确定所述芯片的失效位置，包括：
    在确定所述芯片失效的情况下，将所述芯片的EMMI效果图和好样品的EMMI效果图进行对比，对比出两幅EMMI效果图的不同位置，将在 EMMI图像中对比出的不同位置作为芯片的失效位置。
  5. 如权利要求1所述的方法，其中，所述方法还包括如下步骤：
    S1：获得COB转接板，并对所述转接板进行开窗预处理，得到所述转接板的开窗部位；
    S2：获得透明薄载玻片；
    S3：将芯片背面开封或者正面开封，露出硅基面；
    S4：将所述芯片的开封面朝向所述载玻片，并进行粘接固定；
    S5：芯片粘接固定后将所述透明薄载玻片粘到所述转接板的开窗部位，使得所述硅基面朝向待观测面；
    S6：设置绑线机参数；
    S7：使用绑线机将所述芯片的待测针脚与所述转接板的指定管脚相连接；以及
    S8：使用EMMI定位芯片失效位置。
  6. 如权利要求5所述的方法，其中，步骤S1中对所述转接板进行开窗预处理具体为：根据芯片的开窗尺寸在所述转接板的中央开槽。
  7. 如权利要求5所述的方法，其中，步骤S6中设置绑线机参数包括：设置超声功率为200-230瓦W、超声时间为100-150秒S、超声压力为125帕Pa。
  8. 如权利要求7所述的方法，其中，步骤S6中设置绑线机参数还包括：设置焊接温度为常温。
  9. 如权利要求5所述的方法，其中，所述透明薄载玻片的厚度为1毫米mm。
  10. 如权利要求5所述的方法，其中，步骤S4和S5中均采用热熔蜡进行粘接。
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