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  • H10D12/01—Manufacture or treatment
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
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  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
  • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
  • H10D62/157—Impurity concentrations or distributions
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  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
  • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates

Definitions

• the invention relates to a method for producing semiconductor components and a semiconductor component.
• Discrete high-blocking power semiconductor components with a nominal blocking voltage of more than 600V are generally built vertically in both silicon and SiC.
• diodes e.g. MPS (merged-pin Schottky) diodes, Schottky diodes or p-n diodes
• MPS merged-pin Schottky diodes
• Schottky diodes or p-n diodes this means that the cathode is arranged on the substrate front side and the anode on the substrate rear side.
• MOS metal-oxide-semiconductor
• the actual transistor element or the channel region can be arranged parallel to the surface (D-MOS) or perpendicular to the surface (Trench-MOS). Special constructions have become established for SiC-MOSFETs, e.g. Trench transistors.
• the width of the voltage-absorbing layer can be somewhat reduced compared to “simple” vertical MOSFETs.
• the specialty of this type of vertical components is that the drift zone is characterized by alternating vertical p- and n-doped columns.
• the additionally introduced p-doping compensates in the blocking case the increased charge in the n-doped area, which determines the resistance between the source electrode and drain electrode when switched on.
• the on-resistance can be reduced by up to a factor of 10 compared to conventional vertical MOS transistors.
• the actual transistor element or the channel area can be arranged parallel to the surface (D-MOS) or perpendicular to the surface (Trench-MOS).
• D-MOS surface
• Trench-MOS surface
• the special material properties of SiC require the provision of specific manufacturing processes and the use of specific architectures of the channel and transistor area for vertical power semiconductor components.
• the active zones of many vertical power diodes or all power transistors are in epitaxial, i.e. monocrystalline, layers. These epitaxial layers are placed on crystalline carrier wafers.
• the doping in the active zone can thus be matched to the respective reverse voltage and the highly doped carrier wafer can be optimized with regard to its doping in such a way that its contribution to the switch-on resistance is minimized.
• the above-described production of the layer structure is complex and expensive, since on the one hand the carrier wafers, which however do not assume an active function in the component, are very expensive and, on the other hand, the epitaxial layer deposition is extremely cost-intensive.
• the present invention is based on the object of specifying a method for producing semiconductor components with which high-performance, high-quality semiconductor components can be produced industrially with reduced effort and cost.
• the method according to the invention for producing semiconductor components with a vertical structure has the following steps:
• the energy filter being a microstructured membrane with a predefined structural profile for setting a dopant depth profile and / or defect depth profile caused by the implantation in the substrate, with the drift zone being generated when the drift zone is created entire drift zone is doped.
• the drift zone is generated entirely without epitaxial deposition.
• the drift zone is generated according to the above steps during the manufacture of a semiconductor component, the costs of the manufacturing process are significantly lower.
• the above-mentioned method is particularly preferred when the semiconductor material of the substrate is SiC.
• the substrate has a thickness of 4 ⁇ m to 30 ⁇ m.
• the savings compared to conventional manufacturing processes are particularly high.
• the semiconductor material of the substrate is undoped or weakly n-doped before the drift zone is produced.
• the thickness of the substrate is preferably between 4 and 25 gm, more preferably between 4 and 20 gm, more preferably between 4 and 15 gm, more preferably between 6 and 14 gm, more preferably between 7 and 13 gm. In these thickness ranges of the substrate, it is possible to achieve complete doping of the drift zone in SiC by ion implantation with accelerators that are available industrially today.
• the drift zone preferably extends over 40 to 100%, preferably 50 to 98%, more preferably 60 to 95% of the height of the substrate. As a rule, the proportion is more in a higher range of the specified spectrum.
• the drift zone is n-doped after the ion implantation.
• the doped drift zone is produced by ion implantation from one side of the substrate.
• the doped drift zone can be produced by ion implantation from two sides of the substrate. The two implantations complement each other from the two sides towards the final doping profile.
• the doped drift zone is generated with ions of nitrogen, phosphorus or hydrogen (the latter only for silicon crystals) as the dopant.
• ions of nitrogen, phosphorus or hydrogen the latter only for silicon crystals
• a doped field stop layer is produced on an edge of the substrate by means of ion implantation using an energy filter. This further simplifies the manufacturing process and reduces the overall costs. It is generally desired that the field stop layer is n-doped after the ion implantation, the doping of the field stop layer being stronger than the doping of the drift zone, preferably at least twice as strong as the doping of the drift zone.
• the thickness of the field stop layer is preferably between 0.6 ⁇ m and 150 ⁇ m, more preferably between 0.8 ⁇ m and 5 ⁇ m.
• the ion implantation for producing the field stop layer takes place from the side of the substrate on which the field stop layer is formed. This simplifies the manufacturing process and ion beams with less energy can be used.
• a superficial functional zone with areas of different doping is also generated using ion implantation with an energy filter. This further simplifies the manufacture of the semiconductor component.
• the superficial functional zone is preferably located on an edge of the substrate which is opposite the field stop layer. In this way, semiconductor components are formed with a vertical structure.
• the superficial functional zone is preferably implanted from the side of the substrate on which the superficial functional zone is formed. This further simplifies the process and it is possible to work with an ion beam of lower energy.
• the thickness of the superficial functional zone is preferably between 0.5 ⁇ m and 6 ⁇ m, more preferably between 0.8 ⁇ m and 5 ⁇ m.
• p-doped columns are additionally generated in the region of the drift zone by means of ion implantation using an energy filter.
• the p-doped pillars are used to compensate for the charge in the n-doped areas of the drift zone.
• the substrate is preferably masked in areas.
• the substrate is preferably provided by splitting a rod-shaped starting crystal made of the semiconductor material into thin slices. These thin disks then each form the thin substrate, which is further treated by ion implantation.
• Also according to the invention is a semiconductor component with a substrate made of semiconductor material which has a thickness of 4 ⁇ m to 300 ⁇ m, preferably 4 ⁇ m to 30 ⁇ m, the semiconductor component having a doping profile of the substrate in a central region of the substrate, a depression or an elevation .
• Fig. 1 is a schematic representation of the splitting of a starting crystal into thin substrate wafers, which can be used in the context of the present invention
• FIG. 2 shows a doping profile of a substrate before the ion implantation of the drift zone
• Fig. 3 is a schematic view of the principle of operation of the ion implantation in a
• FIG. 4 is a schematic representation of the mode of operation of an energy filter which can be used in the method according to the invention.
• Fig. 5 is a schematic representation of various doping profiles that can be generated by means of different structured energy filters
• FIG. 6 shows schematically the process of doping the drift zone and a resulting doping profile of the substrate
• 7 shows schematically the process of doping the drift zone and a resulting alternative doping profile of the substrate
• 8a shows schematically an alternative sequence of doping the drift zone and an alternative doping profile of the substrate resulting therefrom, the implantation taking place from two sides of the substrate;
• Fig. 8b shows a total doping profile of the substrate with an implantation of two
• FIG. 9 shows schematically an alternative sequence of doping the drift zone and an alternative doping profile of the substrate resulting therefrom, the implantation taking place from two sides of the substrate;
• FIG. 10 shows schematically the sequence of doping the drift zone using a masking of the substrate in regions and a resulting alternative doping profile of the substrate
• Fig. 1 1 shows schematically the process of an ion implantation from two sides of the
• FIG. 12 shows schematically the sequence of the ion implantation for the formation of a field stop layer and a doping profile of the substrate resulting therefrom;
• Fig. 13 shows a schematic cross section through a first example of a semicon terbauelements which was produced with the method according to the invention, including the associated doping profile;
• FIG. 14 shows a schematic cross section through a second example of a semiconductor component which was produced by the method according to the invention.
• Fig. 15 shows a schematic cross section through a third example of a semicon terbauelements that was produced with the method according to the invention, and two associated doping profiles in mutually perpendicular directions.
• the inventive method for producing semiconductor components begins with the provision of a substrate 12 made of semiconductor material.
• the material of the substrate 12 is preferably silicon carbide (SiC).
• SiC silicon carbide
• other semiconductor materials such as silicon, gallium arsenide, cadmium telluride, zinc selenide, gallium nitride etc. can also be used.
• the substrates 12 are preferably designed as wafers.
• the substrate 12 is initially undoed or extremely weakly n-doped, for example with a doping concentration of ⁇ 5 10 13 cm 3 .
• the substrates 12 have a thickness of 4 ⁇ m to 300 ⁇ m. As a rule, however, the substrates 12 according to the method according to the invention are thinner.
• the substrates 12 usually have a thickness of between 4 and 30 gm, preferably between 4 and 25 gm, more preferably between 4 and 20 gm, more preferably between 4 and 15 gm, more preferably between 6 and 14 gm, more preferably between 7 and 13 gm.
• FIG. 1 An example of the production of such substrates 12 is shown in FIG.
• An undoped or weakly n-doped starting crystal 2 e.g. a wafer rod
• the separated substrates 12 can, if necessary, temporarily, i. E. reversibly, mechanically held by carrier wafers or similar structures in order to avoid breakage of the substrate 12.
• Another alternative is thin grinding.
• the thickness of the individual substrates 12 preferably corresponds to a previously determined width of a combination of active drift zone plus a field stop layer and a superficial functional zone, as will be described in more detail later.
• the total thickness of the substrate 12 is thus determined solely by the type and above all by the voltage class of the semiconductor component to be manufactured. The higher the voltage class, the thicker the substrate 12.
• the upper limit of 300 ⁇ m is due to the sensible field of application of ion implantation (proton beam in silicon). In SiC, the maximum thickness with accelerators available industrially today is 30 gm. This is also a sensible upper limit because radioactive activation of the base material due to excessive ion beam energy should be avoided.
• a doping profile of a weakly n-doped substrate 12 is shown in FIG.
• the doping profile is shown along the section AA 'c stands for the doping concentration.
• a doped drift zone also called an active zone or stress-absorbing zone
• the corresponding basic structure is shown in FIG. 3.
• the structure shown in Fig. 3 for ion implantation in a substrate 12 shows an irradiation chamber 8, in which there is usually a high vacuum. In the irradiation chamber 8, the substrate 12 to be doped is received in a substrate holder 30.
• An ion beam 10 is generated by means of a particle accelerator (not shown) and directed into the irradiation chamber 8. There the energy of the ion beam 10 is spread out by an energy filter 20 and it strikes the substrate 12 to be irradiated.
• the energy filter 20 can be arranged in a separate vacuum chamber that can be closed with valves within the irradiation chamber 8 or directly adjacent to the irradiation chamber 8 .
• the substrate holder 30 does not have to be stationary, but can optionally be provided with a device for moving the substrate 12 in x-y (in the plane perpendicular to the plane of the sheet).
• a wafer wheel on which the substrates 12 to be implanted are fixed and which rotates during the implantation can also be used as the substrate holder 30.
• a displacement of the substrate holder 30 in the beam direction (z-direction) can also be possible.
• the substrate holder 30 can optionally be provided with heating or cooling.
• the basic principle of the energy filter 20 is shown in FIG.
• the energy of the monoenergetic ion beam 10 is modified as it passes through the energy filter 20, which is designed as a microstructured membrane, depending on the point of entry.
• the resulting energy distribution of the ions of the ion beam 10 leads to a modification of the depth profile of the implanted substance in the matrix of the substrate 12.
• E1 denotes the energy of a first ion
• E2 denotes the energy of a second ion
• c denotes the doping concentration
• d denotes the depth in the substrate 12.
• the usual Gaussian distribution is identified by the reference symbol A, which arises without the use of an energy filter 20.
• FIG. 5 show the basic possibilities of generating a large number of dopant depth profiles or defect depth profiles by means of energy filters 20 can in principle be combined with one another in order to obtain new filter structure profiles and thus new dopant depth profiles or defect depth profiles.
• Such energy filters 20 are usually made of silicon. They have a thickness of between 3 pm and 200 pm, preferably between 5 pm and 50 pm and particularly preferably between 7 pm and 20 pm. They can be held in a filter frame (not shown). The filter frame can be exchangeably received in a filter holder (not illustrated).
• n-doped drift zone 21 For the preferred formation of an n-doped drift zone 21, the implantation with ions of nitrogen, phosphorus or hydrogen (the latter only for silicon crystals) is particularly suitable.
• the ion implantation into the substrate 12 takes place from only one side, here the front side of the substrate 12.
• the short arrow filled with black indicates the ions of minimal energy transmitted through the energy filter 20 and the long arrow filled with black indicates the ions of maximum energy transmitted through the energy filter 20.
• the resulting doping profile along section A-A ' is shown on the right in the coordinate system; c again stands for the doping concentration.
• the doping profile is approximately uniform over the entire substrate 12.
• the ion implantation into the substrate 12 can likewise take place from the rear side of the substrate 12.
• the sub strate 12 as in all other exemplary embodiments, is itself formed as a drift zone 21. There is no epitaxial deposition.
• the exemplary embodiment of the method step of doping the drift zone 21 shown in FIG. 7 is similar to the exemplary embodiment from FIG. 6. The only difference is the shape of the doping profile, which has a shape that rises towards the rear side of the substrate 12.
• the exemplary embodiment of the method step of doping the drift zone 21 shown in FIG. 8a is similar to the exemplary embodiment from FIG. 6, but the substrate 12 is doped from two opposite sides, in this case the front and rear of the substrate 12.
• a doping profile is implemented from the front and back of the substrate 12 by means of a suitably designed energy filter 20, each doping profile being characterized by a concentration plateau P1, P2 and a doping flank S1, S2.
• S1, S2 can also be designed as any curve shape.
• plateaus P1 and P2 can rise or fall or be designed as any curve shape.
• a doped substrate thickness of up to 20 ⁇ m, possibly also up to 30 ⁇ m, can be achieved with available accelerators by means of two combined implantations, one of which is implanted from the front side and the other implantation takes place from the rear. This increases the dielectric strength of the semiconductor component to be manufactured.
• the implantation from two sides is usually done one after the other.
• the substrate 12 is usually rotated by 180 ° between the implantations, so that the same beam device can be used.
• FIG. 8b shows an exemplary total doping profile of the substrate during an implantation similar to that in FIG. 8a.
• the total doping profile of the drift zone 21 has a depression in a central region of the substrate 12. It could also have a survey at this point.
• the doping profile of the drift zone 21 is essentially constant from a first edge region of the substrate 12 (left) to the central region.
• the doping profile of the drift zone 21 is essentially constant from a second edge region of the substrate 12 (right), which is opposite the first edge region, towards the central region. It is also possible that the doping of the substrate 12 is used not only to produce a drift zone 21, but also to produce other regions of the semiconductor component 4.
• the doping profile can drop from a second edge region of the substrate 12, which is opposite the first edge region, towards the middle region during an implantation from two sides.
• a more highly doped field stop layer can be formed in the second edge region.
• the central area is generally within a range of between 20% and 80%, preferably between 30% and 70%, more preferably between 40% and 60%, of the thickness of the substrate 12.
• FIG. 1 Another advantageous embodiment is shown in FIG.
• the embodiment corresponds in essential parts to the embodiment according to FIGS. 8a and 8b.
• a doping profile is implemented from the front and the rear of the substrate 12 by means of a suitably designed energy filter 20, each doping profile being characterized by a concentration plateau P1, P2 and a doping flank S1, S2.
• the advantage of this embodiment is that fluctuations in the thickness of the substrate 12 have only a slight effect on fluctuations in the resulting total doping concentration and an elevation or depression in the central area of the drift zone 21 is avoided as far as possible.
• the flatter S1 and S2 are designed, the smaller the resulting doping concentration fluctuations.
• S1, S2 can, in addition to the linear rise or fall shown in FIG. 9, also be designed as any curve shape.
• the plateaus P1 and P2 can again rise or fall or be designed as any curve shape.
• the energy-filtered implantation must be masked or a masked energy-filtered implantation must be carried out several times.
• a masking 26 is arranged on the front side of the substrate 12. This ensures that the region of the substrate 12 covered by the masking 26 is not doped.
• the masking 26 does not have to be permanently connected to the substrate 12, but can also be implemented by means of screen masks (not shown) arranged at a distance from the substrate 12. As shown in FIG. 10, this means that, despite doping of the drift zone 21, undoped regions 14, for example, can remain in the substrate 12.
• Masking 26 can also be removable det on opposite sides of the substrate 12, this even at the same time.
• FIG. 11 An example of this can be seen in FIG. 11, in which a p-doped column 16 is formed in an n-doped drift zone 21, as is necessary for the manufacture of the semiconductor component 4 according to FIG.
• the ion beam 10 shown above is an ion beam for p-doping, for example with aluminum ions
• the ion beam 10 shown below is an ion beam for n-doping, for example with nitrogen ions.
• the doping of a field stop layer 18 on the back of the sub strate 12 outlined in FIG. 12 is introduced into the substrate 12 before, simultaneously or after the formation of the doping of the drift zone 21.
• the field stop layer 18 is preferably doped from the rear side of the substrate 12, but can also be implanted from the front side if the implantation process and the energy filter 20 are suitably configured.
• the field stop layer 18 is preferably n-doped. Thus, nitrogen ions or phosphorus ions are particularly suitable for forming the field stop layer 18.
• the doping of the field stop layer 18 is stronger than the doping of the drift zone 21.
• the doping of the field stop layer 18 is preferably more than twice as strong as the doping of the drift zone 21.
• the thickness of the field stop layer 18 is between 0.5 ⁇ m and 6 ⁇ m, preferably between 0.8 pm and 5 pm. No epitaxial process is required for the formation of the field stop layer 18.
• a superficial functional zone 24 is generated on the front side of the substrate 12 before, simultaneously or after the formation of the doping of the drift zone 21 in the substrate 12 and also before, simultaneously or after the formation of the doping of the field stop layer 18. This can be done by doping different areas of the front side of the substrate 12 by ion implantation using an energy filter 20; however, other techniques are also conceivable. If some or all areas of the superficial functional zone 24 are doped by implantation, these areas of the superficial functional zone 24 are preferably doped from the front side of the substrate 12, but can also be done from the rear side if the implantation process and the energy filter 20 are suitably configured .
• the thickness of the superficial functional zone 24 is between 0.5 pm and 6 pm, preferably between 0.8 pm and 5 pm.
• the superficial functional zone 24 can be designed in various ways.
• All implantations described in the context of the invention must be healed in an annealing process so that the doping atoms can be electrically activated.
• channel areas, p-n junctions, connection metallizations, etc. can be applied to the front side of the substrate 12.
• a drain connection metallization and, if necessary, an n ++ doped connection area can be arranged on the rear side of the substrate 12.
• FIG. 1 An example of a semiconductor component 4 with a vertical structure produced by the method according to the invention is shown in FIG.
• a vertical semiconductor component structure can be produced according to the invention, in particular for diodes (Schottky, MPS diode and pn diode) and MOSFETs with a superficial functional zone 24 (IGBT, MOS transistor, channel area, pn junction, Schottky diode), a drift zone 21 and a field stop layer 18, but without a carrier wafer.
• diodes Schottky, MPS diode and pn diode
• MOSFETs with a superficial functional zone 24 IGBT, MOS transistor, channel area, pn junction, Schottky diode
• This structure is characterized in that, with regard to its vertical extension, it corresponds exactly to the required width of the drift zone 21 plus the field stop layer 18 and plus the functional superficial zone 24. Particularly noteworthy is the fact that this structure reaches the minimum conceivable chip thickness or thickness of the substrate 12 when forming complete vertical high-voltage power components.
• a MOSFET is shown as an example. S stands for the source connection, G for the gate connection and D for the drain connection.
• the superficial functional zone 24 consists of a MOS channel region 31, a gate electrode 32, a p-body 33 and a source connection region 34.
• FIG. 13 Another example of a semiconductor component 4 with a vertical structure produced by the method according to the invention is shown in FIG. Identical reference numerals denote identical elements as in FIG. 13.
• Real high-voltage components consist of an active area 40 and an edge area 41. Due to the not perfectly insulating saw edge of the substrate 12, the drain potential at the edge of the substrate 12 will always also be applied to the surface.
• the task of the edge area 41 is to reduce the voltage between the source and drain on the surface laterally in a defined reliable manner. In concrete terms, this means that the equipotential lines 44 must be guided to the surface with a defined curvature. It is important here that the permissible field strength due to the curvature of the equipotential lines 44 is not exceeded. It is therefore advantageous to minimize the doping rich in the edge area.
• the edge area 41 is undoped or less doped doping profile than the active area 40, or generally the doping profile in the edge area 41 differs from the doping profile in the active area 40. There is thus at the transition between the active area 40 and Edge region 41 has a transition region 43 which is characterized by a doping gradient.
• the field stop layer 18 can only be arranged in the active region 40 and end at the transition region 43, additionally extend partially into the edge region 41 or extend completely over the edge region 41.
• the construction of the edge area 41 (field plate edge 46) shown in FIG. 14 is only an example of other conceivable and known edge constructions, such as p-rings.
• FIG. 13 Another example of a semiconductor component 4 with a vertical structure produced by the method according to the invention is shown in FIG. Identical reference numerals denote identical elements as in FIG. 13.
• the structure shown is a superjunction MOSFET, which is constructed identically to the MOSFET from FIG. 13, but additionally has p-doped columns 16 or regions which are introduced into the stress-absorbing layer to compensate for the n-doping of the drift zone 21.
• the vertical and lateral doping profile are shown on the right.
• the donor concentration is plotted upwards in the lateral doping profile, while the acceptor concentration is plotted downwards. 45 denotes a transition zone with net doping close to zero.

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• Physical Vapour Deposition (AREA)

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• 2019
  • 2019-05-16 DE DE102019112985.0A patent/DE102019112985B4/de active Active
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