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  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
  • H10D12/01—Manufacture or treatment
  • H10D12/031—Manufacture or treatment of IGBTs
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
  • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D62/149—Source or drain regions of field-effect devices
  • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
  • H10D62/156—Drain regions of DMOS transistors
  • H10D62/157—Impurity concentrations or distributions
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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  • H10D62/60—Impurity distributions or concentrations
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
  • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
  • H10D62/8325—Silicon carbide
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
  • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
  • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates

Definitions

• the invention relates to a method for manufacturing semiconductor components.
• Discrete high-blocking power semiconductor devices with a nominal reverse voltage exceeding 600 V are generally built vertically in both silicon and silicon carbide (SiC).
• diodes such as MPS (merged-pin Schottky) diodes, Schottky diodes, or p-n diodes
• MPS merged-pin Schottky
• Schottky diodes Schottky diodes
• p-n diodes this means that the cathode is located on the front of the substrate and the anode on the back.
• vertical power MOSFETs metal-oxide-semiconductor devices.
• the gate and source electrodes are located on the front of the substrate, and the drain electrode on the back.
• the actual transistor element or channel region can be arranged parallel to the surface (D-MOS) or perpendicular to the surface (trench-MOS) in conventional power MOSFETs. Special designs have become established for SiC MOSFETs, such as trench transistors.
• the width of the drift zone (active zone, voltage-receiving layer) is adjusted.
• the width of the drift zone for a 600 V silicon MOSFET will be approximately 50 ⁇ m.
• the width of the voltage-receiving layer can be somewhat reduced compared to "simple" vertical MOSFETs.
• the special feature of this type of vertical device is that the drift zone is characterized by alternating vertical p- and n-doped columns. The additional p-doping compensates for the increased charge in the n-doped region when the device is off, which determines the resistance between the source and drain electrodes when the device is on.
• the on-resistance can be reduced by up to a factor of 10 compared to conventional vertical MOSFETs.
• the actual transistor element, or channel area can be arranged parallel to the surface (D-MOS) or perpendicular to the surface (Trench-MOS).
• SiC silicon-oxide-semiconductor
• the active regions of many vertical power diodes and all power transistors are formed in epitaxial, i.e., single-crystal, layers. These epitaxial layers are deposited on crystalline support wafers. This allows the doping in the active region to be tailored to the respective reverse voltage, and the highly doped support wafer can be optimized with respect to its doping to minimize its contribution to the on-resistance.
• the above-described production of the layer structure is complex and expensive, since on the one hand the support wafers, which do not perform any active function in the component, are very expensive and on the other hand the epitaxial layer deposition is extremely cost-intensive.
• the present invention is based on the objective of providing a method for manufacturing semiconductor components with which high-performance semiconductor components of high quality can be manufactured industrially with reduced effort and lower costs.
• the inventive method for manufacturing semiconductor devices with a vertical structure comprises the steps defined in claim 1.
• drift zone is created according to the above steps during the production of a semiconductor device, the manufacturing process costs are significantly lower.
• the above-mentioned method is particularly advantageous when the substrate semiconductor material is SiC.
• the substrate has a thickness of 4 ⁇ m to 30 ⁇ m.
• the savings compared to conventional manufacturing methods are especially high.
• the semiconductor material of the substrate is undoped or weakly n-doped before the drift zone is generated.
• the substrate thickness is preferably between 4 and 25 ⁇ m, more preferably between 4 and 20 ⁇ m, more preferably between 4 and 15 ⁇ m, more preferably between 6 and 14 ⁇ m, and more preferably between 7 and 13 ⁇ m. Within these substrate thickness ranges, complete doping of the drift zone in SiC can be achieved by ion implantation using currently available industrial accelerators.
• the drift zone extends over 40 to 100%, preferably 50 to 98%, and more preferably 60 to 95% of the substrate height.
• the proportion lies in a higher range of the specified spectrum.
• the drift zone is n-doped after ion implantation.
• the doped drift zone is generated by ion implantation from one side of the substrate.
• the doped drift zone can be generated by ion implantation from both sides of the substrate. In this case, the two implantations from the two sides complement each other to form the final doping profile.
• the doped drift zone is generated using nitrogen, phosphorus, or hydrogen ions (the latter only for silicon crystals) as the dopant.
• a doped field-stop layer is generated at an edge of the substrate by ion implantation using an energy filter. This further simplifies the manufacturing process and reduces overall costs.
• the field stop layer is n-doped after ion implantation, wherein the doping of the field stop layer is stronger than the doping of the drift zone, preferably at least twice as strong as the doping of the drift zone.
• the thickness of the field stop layer is preferably between 0.6 ⁇ m and 150 ⁇ m, more preferably between 0.8 ⁇ m and 5 ⁇ m.
• ion implantation for generating the field stop layer is performed from the side of the substrate on which the field stop layer is formed. This simplifies the manufacturing process and allows the use of lower-energy ion beams.
• a surface functional zone with areas of different doping is also created using ion implantation with an energy filter. This further simplifies the fabrication of the semiconductor device.
• the surface functional zone is located at an edge of the substrate opposite the field-stop layer. This allows the formation of semiconductor devices with a vertical structure.
• the surface functional zone is preferably implanted from the side of the substrate on which it is formed. This further simplifies the process and allows the use of a lower-energy ion beam.
• the thickness of the surface functional zone is preferably between 0.5 ⁇ m and 6 ⁇ m, more preferably between 0.8 ⁇ m and 5 ⁇ m.
• p-doped columns in the drift zone region by ion implantation using an energy filter.
• the p-doped columns serve to compensate the charge of the n-doped regions of the drift zone.
• the substrate is preferably masked in certain areas.
• the substrate is provided by splitting a rod-shaped starting crystal made of the semiconductor material into thin slices. These thin slices then each form the thin substrate, which is further processed by ion implantation.
• a semiconductor device with a substrate made of semiconductor material having a thickness of 4 ⁇ m to 300 ⁇ m, preferably 4 ⁇ m to 30 ⁇ m, wherein the semiconductor device has a doping profile of the substrate in a central region of the substrate having a depression or a protrusion.
• the inventive process for manufacturing semiconductor devices begins with the provision of a substrate 12 made of semiconductor material.
• the substrate 12 is preferably silicon carbide (SiC).
• SiC silicon carbide
• other semiconductor materials such as silicon, gallium arsenide, cadmium telluride, zinc selenide, gallium nitride, etc., are also suitable.
• the substrates 12 are preferably formed as wafers.
• the substrate 12 is initially undoped or extremely weakly n-doped, e.g., with a doping concentration of ⁇ 5 ⁇ 1018 cm ⁇ 3 .
• the substrates 12 have a thickness of 4 ⁇ m to 300 ⁇ m. However, according to the inventive method, the substrates 12 are generally thinner. Most often, the substrates 12 have a thickness of between 4 and 30 ⁇ m, preferably between 4 and 25 ⁇ m, more preferably between 4 and 20 ⁇ m, more preferably between 4 and 15 ⁇ m, more preferably between 6 and 14 ⁇ m, and more preferably between 7 and 13 ⁇ m.
• an undoped or weakly n-doped starting crystal 2 e.g., a wafer bar
• the cleaved substrates 12 can, if necessary, be temporarily, i.e., reversibly, mechanically held by support wafers or similar structures during the fabrication process to prevent substrate breakage.
• Another alternative is thin-looping.
• a doping profile of a weakly n-doped substrate 12 is presented in Fig. 2 The doping profile is shown along section AA'. c represents the doping concentration.
• a doped drift zone (also called active zone or voltage-absorbing zone) is generated in the substrate 12 by means of ion implantation.
• the corresponding basic structure is described in Fig. 3 depicted.
• the one in Fig. 3 The setup shown for ion implantation into a substrate 12 includes an irradiation chamber 8, which is typically under high vacuum.
• the substrate 12 to be doped is held in a substrate holder 30 within the irradiation chamber 8.
• An ion beam 10 is generated by a particle accelerator (not shown) and directed into the irradiation chamber 8. There, the energy of the ion beam 10 is spread out by an energy filter 20 and it strikes the substrate 12 to be irradiated.
• the energy filter 20 can be arranged in a separate vacuum chamber, which can be closed with valves, either within the irradiation chamber 8 or directly adjacent to the irradiation chamber 8.
• the substrate holder 30 need not be stationary, but can optionally be equipped with a device for moving the substrate 12 in the x-y plane (in the plane perpendicular to the plane of the sheet).
• a wafer wheel, on which the substrates 12 to be implanted are fixed and which rotates during implantation, can also serve as the substrate holder 30. Movement of the substrate holder 30 in the beam direction (z-direction) is also possible.
• the substrate holder 30 can optionally be equipped with heating or cooling.
• the basic principle of the Energy Filter 20 is in Fig. 4
• the monoenergetic ion beam 10 is shown.
• the energy filter 20 which is designed as a microstructured membrane, its energy is modified depending on the point of entry.
• the resulting energy distribution of the ions in the ion beam 10 leads to a modification of the depth profile of the implanted substance in the matrix of the substrate 12.
• E1 denotes the energy of a first ion
• E2 denotes the energy of a second ion
• c denotes the doping concentration
• d denotes the depth in the substrate 12.
• the usual Gaussian distribution, labeled A is shown, which occurs without the use of an energy filter 20.
• a rectangular distribution which can be achieved with the use of an energy filter 20, is sketched as an example, labeled B.
• the in Fig. 5 The layouts and three-dimensional structures of energy filters 20 shown illustrate the fundamental possibilities of generating a variety of dopant depth profiles or defect depth profiles using energy filters 20.
• c denotes the dopant concentration
• d denotes the depth in the substrate 12.
• the filter structure profiles can, in principle, be combined with one another to obtain new filter structure profiles and thus new dopant depth profiles or defect depth profiles.
• Such energy filters 20 are generally made of silicon. They have a thickness of between 3 ⁇ m and 200 ⁇ m, preferably between 5 ⁇ m and 50 ⁇ m, and particularly preferably between 7 ⁇ m and 20 ⁇ m. They can be held in a filter frame (not shown). The filter frame can be interchangeably mounted in a filter holder (not shown).
• implantation with ions of nitrogen, phosphorus or hydrogen is particularly suitable.
• ion implantation into the substrate 12 occurs from only one side, here the front side of the substrate 12.
• the short, black-filled arrow indicates the ions of minimum energy transmitted through the energy filter 20, and the long, black-filled arrow indicates the ions of maximum energy transmitted through the energy filter 20.
• the resulting doping profile along section AA' is shown on the right in the coordinate system. c again represents the doping concentration.
• the doping profile is approximately uniform across the entire substrate 12.
• Ion implantation into the substrate 12 can also occur from the back side of the substrate 12.
• the substrate 12 itself is formed as the drift zone 21. No epitaxial deposition takes place.
• Fig. 7 The illustrated embodiment of the process step of doping the drift zone 21 is similar to the embodiment from Fig. 6 The only difference is in the shape of the doping profile, which has a shape rising towards the back of the substrate 12.
• the illustrated embodiment of the process step of doping the drift zone 21 is similar to the embodiment from Fig. 6
• the substrate 12 is doped from two opposite sides, i.e., the front and back of the substrate 12.
• a doping profile is realized from both the front and back of the substrate 12 by means of a suitably designed energy filter 20, with each doping profile being characterized by a concentration plateau P1, P2 and a doping slope S1, S2.
• S1, S2 can be used in addition to the one described in Fig. 8a
• the linear increase or decrease shown can also be formed as any curve shape.
• the plateaus P1 and P2 can be rising or falling, or designed as any curve shape.
• the range of nitrogen implantation in SiC is significantly limited with currently available industrial accelerators.
• a doped substrate thickness of up to 20 ⁇ m, and possibly even up to 30 ⁇ m can be achieved with available accelerators. This increases the dielectric strength of the semiconductor device being manufactured.
• Implantation from both sides is usually performed sequentially.
• the substrate 12 is typically rotated 180° between implantations so that the same beam device can be used.
• Fig. 8b shows an exemplary total doping profile of the substrate during implantation similar to that in Fig. 8a
• the total doping profile of drift zone 21 exhibits a depression in a central region of substrate 12. It could also exhibit a ridge at this location.
• the doping profile of drift zone 21 is essentially constant from a first marginal region of substrate 12 (left) towards the central region.
• the doping profile of drift zone 21 is essentially constant from a second marginal region of substrate 12 (right), opposite the first marginal region, towards the central region.
• the doping of the substrate 12 is used not only to create a drift zone 21, but also to create other areas of the semiconductor device 4.
• the doping profile can also be advantageous, as shown by the dashed line, for the doping profile to slope downwards from a second edge region of the substrate 12, opposite the first edge region, towards the central region when implanted from two sides. This allows, for example, the formation of a more heavily doped field-stop layer in the second edge region.
• the central region is generally within a range of between 20% and 80%, preferably between 30% and 70%, more preferably between 40% and 60%, of the thickness of the substrate 12.
• FIG. 9 Another advantageous embodiment is in Fig. 9
• the embodiment corresponds in essential parts to the embodiment according to Fig. 8a and 8b
• a doping profile is again realized from both the front and back sides of the substrate 12 by means of a suitably designed energy filter 20, each doping profile being characterized by a concentration plateau P1, P2 and a doping slope S1, S2.
• the advantage of this design is that variations in the thickness of the substrate 12 have only a minor effect on variations in the resulting total doping concentration, thus minimizing the formation of a peak or trough in the central region of the drift zone 21.
• the flatter S1 and S2 are designed, the smaller the resulting doping concentration fluctuations become.
• S1, S2 can be [missing information]
• Fig. 9 The linear increase or decrease shown can also be formed as any curve shape. Likewise, the plateaus P1 and P2 can be rising or falling, or formed as any curve shape.
• the energy-filtered implantation must be masked, or multiple masked energy-filtered implantations must be performed.
• a masking 26 is arranged on the front side of the substrate 12. This ensures that the area of the substrate 12 covered by the masking 26 is not doped.
• the masking 26 does not have to be rigidly connected to the substrate 12, but can also be implemented by sieve masks (not shown) arranged at a distance from the substrate 12.
• undoped areas 14 may remain in the substrate 12.
• Masking 26 can also be formed on opposite sides of the substrate 12, even simultaneously.
• An example of this is shown in Fig. 11 to be seen, in which a p-doped column 16 is formed in an n-doped drift zone 21, as is required for the fabrication of the semiconductor device 4 according to Fig. 15 is necessary.
• the ion beam 10 shown above is an ion beam for p-doping, for example with aluminum ions
• the ion beam 10 shown below is an ion beam for n-doping, for example with nitrogen ions.
• the in Fig. 12 The doping of a field stop layer 18 on the back side of the substrate 12, as outlined, is introduced into the substrate 12 before, simultaneously, or after the formation of the doping of the drift zone 21.
• the doping of the field stop layer 18 preferably occurs from the back side of the substrate 12, but can also be performed from the front side if the implantation process and the energy filter 20 are suitably configured.
• the field stop layer 18 is preferably n-doped. Nitrogen ions or phosphorus ions are particularly suitable for forming the field stop layer 18.
• the doping of the field stop layer 18 is more concentrated than that of the drift zone 21. Preferably, the doping of the field stop layer 18 is more than twice as concentrated as that of the drift zone 21.
• the thickness of the field stop layer 18 is between 0.5 ⁇ m and 6 ⁇ m, preferably between 0.8 ⁇ m and 5 ⁇ m. No epitaxy process is required for the formation of the field stop layer 18.
• a surface functional zone 24 is generated on the front side of the substrate 12 before, simultaneously, or after the formation of the drift zone 21 in the substrate 12 and likewise before, simultaneously, or after the formation of the field stop layer 18. This can be achieved by doping various regions of the front side of the substrate 12 by ion implantation using an energy filter 20; however, other techniques are also conceivable.
• the doping of these areas of the superficial functional zone 24 preferably takes place from the front of the substrate 12, but can also take place from the back if the implantation process and the energy filter 20 are appropriately designed.
• the thickness of the surface functional zone 24 is between 0.5 ⁇ m and 6 ⁇ m, preferably between 0.8 ⁇ m and 5 ⁇ m.
• the surface functional zone 24 can be configured in a variety of ways.
• All implantations described within the scope of the invention must be healed in an anneal process so that the doping atoms can be electrically activated.
• channel areas, p-n junctions, connection metallizations, etc. can be applied to the front side of substrate 12.
• a drain connection metallization and, if necessary, an n++-doped connection area can be arranged on the back side of substrate 12.
• FIG. 13 An example of a semiconductor device 4 with a vertical structure produced using the method according to the invention is shown in Fig. 13 depicted.
• a vertical semiconductor device structure can be produced, in particular for diodes (Schottky, MPS diode and pn diode) and MOSFETs with a surface functional zone 24 (IGBT, MOS transistor, channel area, p-n junction, Schottky diode), a drift zone 21 and a field stop layer 18, but without a carrier wafer.
• diodes Schottky, MPS diode and pn diode
• MOSFETs with a surface functional zone 24 (IGBT, MOS transistor, channel area, p-n junction, Schottky diode), a drift zone 21 and a field stop layer 18, but without a carrier wafer.
• This structure is characterized by the fact that its vertical extent corresponds exactly to the required width of the drift zone 21 plus the field stop layer 18 and the functional surface zone 24. Particularly noteworthy is the fact that this structure, when forming complete vertical high-voltage power devices, achieves the minimum conceivable chip thickness or substrate thickness 12.
• the surface functional zone 24 consists of a MOS channel region 31, a gate electrode 32, a p-body 33, and a source terminal region 34.
• the edge region 41 is undoped or has a lower doping profile than the active region 40, or more generally, the doping profile in the edge region 41 differs from the doping profile in the active region 40.
• a transition region 43 characterized by a doping gradient.
• the field stop layer 18 can only be located in the active region 40 and terminate at the transition region 43, or it can extend partially into the edge region 41 or completely across the edge region 41.
• Fig. 14 The construction of the edge area 41 shown (field plate edge 46) is only an example of other conceivable and known edge constructions, such as p-rings.
• FIG. 15 Another example of a semiconductor device 4 with a vertical structure produced using the method according to the invention is shown in Fig. 15 As shown. Identical reference symbols denote identical elements as in Fig. 13 .

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