WO2022128818A1 - Elektronisches halbleiterbauelement und verfahren zur herstellung eines vorbehandelten verbundsubstrats für ein elektronisches halbleiterbauelement - Google Patents
Elektronisches halbleiterbauelement und verfahren zur herstellung eines vorbehandelten verbundsubstrats für ein elektronisches halbleiterbauelement Download PDFInfo
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- WO2022128818A1 WO2022128818A1 PCT/EP2021/085296 EP2021085296W WO2022128818A1 WO 2022128818 A1 WO2022128818 A1 WO 2022128818A1 EP 2021085296 W EP2021085296 W EP 2021085296W WO 2022128818 A1 WO2022128818 A1 WO 2022128818A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
- H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
Definitions
- the invention relates to an electronic semiconductor component and a method for producing a pretreated composite substrate for an electronic semiconductor component.
- Discrete high-blocking power semiconductor devices with a nominal blocking voltage of more than 600V are generally constructed vertically in both silicon and SiC.
- diodes e.g. MPS (merged-pin Schottky) diodes, Schottky diodes or p-n diodes
- MPS merged-pin Schottky diodes
- Schottky diodes or p-n diodes this means that the cathode is arranged on the front side of the substrate and the anode on the back side of the substrate.
- a similar arrangement applies in the case of vertical power MOS (metal-oxide-semiconductor) devices.
- the gate and source electrodes are on the front of the substrate, the drain electrode on the back of the substrate.
- the actual transistor element or the channel area can be arranged parallel to the surface (D-MOS) or perpendicular to the surface (trench MOS). Special constructions have become established for SiC MOSFETs, e.g. trench transistors.
- the width of the drift zone for a 600 V MOSFET device in silicon will be approximately 50 ⁇ m.
- the width of the stress-absorbing layer can be somewhat reduced compared to "simple" vertical MOSFETs.
- the special feature of this type of vertical component is that the drift zone is characterized by alternating vertical p- and n-doped columns. In the off state, the additionally introduced p-doping compensates for the increased charge in the n-doped region, which determines the resistance between the source electrode and drain electrode when switched on. Thus, with the same blocking capability, the on-resistance can be reduced by a factor of 10 compared to conventional vertical MOS transistors.
- the actual transistor element, or the channel area can be arranged parallel to the surface (D-MOS) or perpendicular to the surface (trench MOS) in superjunction MOSFET architectures.
- D-MOS surface
- trench MOS surface perpendicular to the surface
- the active zones of all vertical power diodes or all power transistors are usually formed in monocrystalline epitaxial layers. These epitaxial layers are built up or deposited on crystalline carrier wafers. In this way, the doping and vertical extension (thickness) of the active epitaxial zone can be matched to the respective blocking voltage, and the highly doped carrier wafer can be optimized with regard to its doping in such a way that its contribution to the on-resistance is minimized.
- the production of the layer structure described above is complex and expensive, since the epitaxial layer deposition and also the provision of monocrystalline carrier wafers is extremely cost-intensive.
- the wafer surface is arranged at an angle of 4° to a direction perpendicular to the c-direction of the crystal structure.
- this increases the complexity and, on the other hand, reduces the performance of many structural elements of the semiconductor components to be introduced into the wafer, in particular the channel regions, Schottky junctions or switching p-n junctions.
- the charge carrier mobility is reduced at the 4° tilt.
- DE 10 2019 112 985 A1 proposes producing the semiconductor component without epitaxial deposition by splitting off a substrate from a SiC wafer and subsequent ion implantation of the drift zone using an energy filter.
- the present invention is based on the object of specifying an electronic semiconductor component which is powerful and has a high quality. In addition, it should be possible to produce it industrially with reduced effort and lower costs.
- a corresponding method for producing a pretreated composite substrate for the electronic semiconductor component is also specified.
- the electronic semiconductor component according to the invention which is preferably a vertical semiconductor component and more preferably a high blocking vertical semiconductor component, has a crystal made of monocrystalline SiC, the orientation of at least partial sections of a first surface of the crystal made of SiC being less than 0.5°, preferably by less than 0.3°, more preferably less than 0.1°, most preferably not at all from a direction perpendicular to the c-direction of the crystal structure of the crystal.
- the (0001) plane and the (0001) plane of the crystal structure are arranged perpendicular to the c-direction of the crystal structure.
- Any face or plane referred to herein as running in a direction perpendicular to the c-direction runs in either a C-plane (carbon-terminated) of the crystal structure or in a Si-plane (silicon-terminated) of the crystal structure .
- Any face or plane referred to herein as being in a direction perpendicular to the c-direction is in a (0001) plane or in a (0001) plane of the crystal structure.
- any face or plane identified herein as being in a direction parallel to the c-direction is perpendicular to the C-plane (carbon-terminated) of the crystal structure and perpendicular to the Si-plane (silicon-terminated) of the crystal structure .
- any surface or plane referred to herein as in a direction parallel to the c-direction, perpendicular to the (0001) plane and to the (0001) plane of the crystal structure is perpendicular to the (0001) plane and to the (0001) plane of the crystal structure.
- the first surface of the crystal applies that at least partial sections thereof can be arranged either in a C-plane (carbon-terminated) of the crystal structure (0001) or in a Si-plane (silicon-terminated) of the crystal structure (0001).
- the second surface of the crystal opposite the first surface of the crystal made of SiC, which is generally formed continuously, also deviates by less than 0.5°, preferably by less than 0.3°, more preferably by less than 0.1° , most preferably not at all, from a direction perpendicular to the c-direction of the crystal structure of the crystal.
- the electronic semiconductor component has an active component area that includes:
- At least partial areas of the second zone are preferably doped. These partial areas or the entire second zone are preferably p- or n-doped with a doping concentration of 1E15 cm' 3 to 5E17 cm' 3 .
- the second zone is doped with one of the following elements: nitrogen, phosphorus, boron or aluminum.
- At least partial areas of the first zone are preferably doped. It is preferred if at least these partial areas of the first zone are doped with one of the following elements: nitrogen (N), phosphorus (P), boron (B) or aluminum (Al).
- the first zone and the second zone are preferably doped with the same type of ion.
- first zone and the second zone are formed substantially based on the crystal of SiC.
- the thickness of the first zone is preferably between 0.5 ⁇ m and 3.0 ⁇ m.
- the thickness of the second zone is preferably between 2 ⁇ m and 50 ⁇ m, more preferably between 3 ⁇ m and 25 ⁇ m, particularly preferably between 3 ⁇ m and 15 ⁇ m.
- a doping concentration in an n-doped area of the first zone is preferably higher than in an n-doped area of the second zone facing the first zone, preferably by a factor of 1.5 to 100, particularly preferably by a factor of 2 to 10 higher.
- a doping concentration in a p-doped area of the first zone is preferably higher than a doping concentration in an n-doped area of the second zone facing the first zone, preferably by a factor of 2 to 1000, particularly preferably by a factor of 50 to 1000 higher.
- the second zone has an essentially constant dopant depth profile, starting from the first zone in the direction of the field-free contact zone or field stop zone.
- the second zone can have a stepwise increasing dopant depth profile, the steps in a region of the second zone facing the field-free contact zone or field stop zone being up to 40%, preferably up to 30%, of the total depth of the second zone.
- a concentration difference between the highest and the lowest level is preferably at least a factor of 10, preferably at least a factor of 100, more preferably at least a factor of 500, particularly preferably at least a factor of 1000.
- the depth of the flank regions of the steps is greater than the depth of the step plateaus.
- the second zone can have a dopant depth profile that increases continuously starting from the first zone in the direction of the field-free contact zone or field stop zone.
- the continuously increasing dopant depth profile of the second zone is preferably a profile according to the following formula: whereby
- Dmax is the maximum doping concentration
- a is a value between 10 and 10,000
- z is the distance from the first zone
- b is the thickness of the second zone
- f is a tolerance factor between 0.95 and 1.05
- Do is the background doping
- Vbr the breakdown voltage is, and where is.
- the step profile mentioned or the continuously increasing profile takes two aspects into account. On the one hand, an optimal compromise between the on-resistance and the given electric strength is achieved by this dopant progression. On the other hand, the doping profile towards the field-free contact zone or field stop zone has such a high concentration that field penetration is almost impossible.
- the two dopant depth profiles preferably have sloping flanks that overlap.
- the combination of both dopant depth profiles of the first zone and the second zone can be a constant profile, a profile that increases stepwise toward the field-free contact zone or field stop zone, or a profile that increases continuously toward the field-free contact zone or field stop zone.
- Particularly preferred is a profile in which there is a gradual drop in the doping profile from the first zone to the second zone and then a constant profile within the second zone, a profile that rises in steps toward the field-free contact zone or field stop zone, or a profile that is continuous toward the field-free contact zone or field stop zone rising profile.
- the electronic semiconductor component has a (field-free) carrier substrate on the side of the field-free contact zone or field stop zone facing away from the first zone, with the SiC crystal in the area of the field-free contact zone or field stop zone being connected to the carrier substrate by means of a permanent adhesive or bond connection is.
- the carrier substrate is thermally stable up to at least 1,500° C. and has a linear expansion coefficient that deviates from the linear expansion coefficient of SiC by at most 20%, preferably at most 10%.
- the carrier substrate is formed from polycrystalline SiC or graphite.
- the electronic semiconductor component can also be a self-supporting thin layer based on the SiC crystal without a carrier substrate.
- the electronic semiconductor component is provided with a non-active edge region which essentially completely surrounds the first and second zones laterally in all directions.
- the edge region is essentially undoped, apart from a field-reducing edge structure that may be present near the surface.
- the edge region apart from any field-reducing edge structure that may be present near the surface, is essentially undoped from the first surface and essentially from a depth at which the second zone begins to a depth at which the field-free contact zone or field stop zone, provided with the same doping concentration as the second zone or provided with a lower doping concentration than the second zone, preferably with a doping concentration that is at least 20% lower, more preferably with a doping concentration that is at least 50% lower.
- the field-free contact zone or field stop zone preferably has a vertical thickness of at most 2 ⁇ m, preferably at most 1 ⁇ m.
- the monocrystalline SiC is preferably of the hexagonal polytype 4H or ⁇ H.
- the crystal is a crystal of high quality, high purity, semi-insulating SiC material.
- An HT-CVD (high temperature chemical vapor deposition) material is preferred here.
- the A-plane of the crystal (1120) deviates by less than 0.5°, more preferably less than 0.3°, even more preferably less than 0.1°, most preferably not at all a direction perpendicular to the first surface of the crystal.
- the electronic semiconductor component is a trench MOSFET and the channel region deviates by less than 0.5°, more preferably by less than 0.3°, even more preferably by less than 0.1°, most preferably not at all. depends on the c-direction of the crystal structure of the crystal.
- the channel region is arranged essentially perpendicular to the first surface of the crystal.
- the channel region is arranged in an A-plane of the crystal.
- the electronic semiconductor component is a planar MOSFET and the channel region deviates by less than 0.5°, more preferably by less than 0.3°, even more preferably by less than 0.1°, most preferably not at all , from a direction perpendicular to the c-direction of the crystal structure of the crystal.
- the channel region runs parallel to the first surface of the crystal.
- the electronic semiconductor component is an MPS (merged PIN Schottky) diode and the plane parallel to the Schottky junction deviates by less than 0.5°, more preferably by less than 0.3°, even more preferably by less than 0.1°, most preferably not at all, from a direction perpendicular to the c-direction of the crystal structure of the crystal.
- MPS merged PIN Schottky
- the plane of the Schottky junction is arranged parallel to the first surface of the crystal.
- the electronic semiconductor component is a JFET transistor (Junction Field Effect Transistor), the interface at one or each p + -n junction being less than 0.5°, preferably less than 0.3° , more preferably by less than 0.1°, most preferably not at all, from a direction parallel to the c-direction of the crystal structure of the crystal.
- the electronic semiconductor component is a JFET transistor, the interface at one or each p + -n junction being less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, most preferably not at all, from a direction perpendicular to the c-direction of the crystal structure of the crystal.
- the method for producing a pretreated composite substrate which serves as the basis for further processing to form an electronic semiconductor component and comprises an acceptor substrate and a first section of a donor substrate, which has at least one doped layer, has the following steps: a) providing the donor substrate, comprising single crystal SiC; b) Doping a first layer in the donor substrate by means of ion implantation using an energy filter, the energy filter being a microstructured membrane with a predefined structure profile for setting a dopant depth profile caused by the implantation in the first layer in the donor substrate, with a predetermined dopant depth profile in the first layer during doping layer of the donor substrate is produced, the first layer extending from an outer surface of the donor substrate facing the ion beam to a predetermined doping depth, where a remaining part of the donor substrate joins; c) creating a predetermined breaking point in the donor substrate that runs essentially parallel to the outer surface of the donor substrate; d) providing the acceptor substrate and establishing a bond connection between the donor substrate and
- the first layer always consists of monocrystalline SiC.
- the donor substrate preferably consists entirely of monocrystalline SiC.
- the first layer preferably has a thickness of 3 to 15 ⁇ m. Ion implantation can reasonably be performed over a thickness of this magnitude.
- the donor substrate is a crystal of high quality, high purity, single crystal, semi-insulating SiC material.
- HT-CVD high temperature chemical vapor deposition
- the donor substrate is polytype 4H, 6H or 3C SiC. These polytypes have turned out to be advantageous for the production of semiconductor devices.
- the outer surface of the donor substrate facing the ion beam deviates by less than 0.5°, more preferably by less than 0.3°, even more preferably by less than 0.1°, most preferably not at all from a direction perpendicular to c - Direction of the crystal structure of the donor substrate.
- the advantage at approximately 0° lies in particular in the fact that the donor substrate can be severed parallel to the outer surface and thus more partial wafers can be obtained from a cylinder.
- the donor substrate preferably has a thickness of more than 100 ⁇ m, preferably more than 200 ⁇ m, more preferably more than 300 ⁇ m up to 15 cm, preferably up to 10 cm.
- the doping of the first layer provides p- or n-doping with a doping concentration or defect concentration in the first layer of 1E15 cm -3 to 5E17 cm -3 .
- This doping concentration or defect concentration is very well suited for the drift zone (active layer, power-consuming layer) of a large number of high-performance components.
- the doping can be constant over the thickness of the first layer or have a doping profile that deviates therefrom.
- the first layer is preferably doped with ions from one of the following elements: nitrogen, phosphorus, boron or aluminum.
- the primary energy range of the ion beam when doping the first layer is preferably between 1 MeV and 50 MeV.
- the doping of the first layer provides a constant dopant depth profile or a substantially constant dopant depth profile.
- the plateau is followed by a falling edge, i.e. in the area of the doping depth, the drop in the profile is not vertical or abrupt.
- the doping of the first layer provides a dopant depth profile that descends in steps from the outer surface of the donor substrate facing the ion beam, the steps in a near-surface area of the first layer facing the ion beam being up to 40%, preferably up to 30%, of the Total depth of the first layer are formed.
- a concentration difference between the highest and the lowest level is preferably at least a factor of 10, preferably at least a factor of 100, more preferably at least a factor of 500, particularly preferably at least a factor of 1000.
- the depth of the flank areas of the steps outweighs the depth of the step plateaus.
- the doping of the first layer provides a dopant depth profile that falls continuously from the outer surface of the donor substrate facing the ion beam.
- the continuously decreasing dopant depth profile is a profile based on the following formula: whereby
- Dmax is the maximum doping concentration
- a is a value between 10 and 10,000
- z is the distance from the outer surface
- b is the thickness of the first layer
- f is a tolerance factor between 0.95 and 1.05
- Do is the background doping
- Vbr is the breakdown voltage, and where is.
- the further step is preferred to produce a contact layer in a superficial area of the first layer or to apply a contact layer to the outer surface of the first layer, the bond connection between donor substrate and acceptor substrate being produced via the contact layer, and the following sequence resulting: Acceptor substrate, contact layer, remaining part of first layer or first layer, remaining part of donor substrate. This ensures a particularly good, low-impedance connection between the donor substrate and the acceptor substrate.
- the contact layer is preferably produced by ion implantation.
- a dopant concentration in the contact layer is preferably at least 100 times, preferably at least 1,000 times, more preferably at least 10,000 times, even more preferably at least 100,000 times above an average dopant concentration in the rest of the first layer or in the first layer. This achieves a bond connection with the lowest possible resistance and penetration of the field to the interface in the semiconductor component is avoided.
- a dopant concentration in the contact layer is more than 1 E17 cm' 3 , more preferably more than 1 E19 cm' 3 .
- the predetermined breaking point is preferably in the area of the first layer, particularly preferably in an end area of the first layer close to the predetermined doping depth, with the edge area particularly preferably not being thicker than 1 ⁇ m. In this way, as little doped material as possible remains on the donor substrate after splitting off.
- the predetermined breaking point is in the region of the remaining part of the donor substrate, and after step e) the further step is also carried out of carrying out an ion implantation into the composite substrate from the side facing away from the acceptor substrate. This has the advantage that an active zone can be formed with a greater overall thickness. Due to the superimposition of two different implantations that is made possible in this way, different preferred doping profiles can also be generated or preferred doping profiles can be generated step by step.
- the ion implantation into the composite substrate provides a dopant depth profile in an additional doped layer that reaches at least as far as the doped layer.
- the ion implantation into the composite substrate is carried out, for example, in such a way that the combination of both dopant depth profiles of the doped layer and the supplementary doped layer is a constant profile, a profile which increases stepwise towards the acceptor substrate or a profile which increases continuously towards the acceptor substrate.
- Other profile shapes are also conceivable.
- Flanks falling at an angle in the transition region of the two dopant depth profiles of the doped layer and the supplementary doped layer can overlap in this case.
- a configuration is particularly preferred in which the doping concentration in the supplementary doped layer is higher than in a region of the doped layer facing the supplementary doped layer, preferably by a factor of 1.5 to 100, particularly preferably by a factor of 2 to 10 higher.
- the doping concentration in the doped layer can in turn be a constant profile, a profile that rises in stages towards the acceptor substrate, or a profile that rises continuously towards the acceptor substrate.
- the predetermined breaking point is preferably produced by ion implantation of gap-triggering ions.
- the gap-triggering ions are preferably introduced over the entire width of the donor substrate in order to produce a separating surface that is as uniform as possible.
- the fission-initiating ions can be introduced over only part of the width of the donor substrate. This reduces the effort involved in ion implantation.
- the gap-triggering ions are preferably introduced only in an edge region of the donor substrate.
- the fission initiating ions are selected from the following: hydrogen (H or H 2 ), helium (He), boron (B).
- the ions that initiate the gap are high-energy ions with an energy between 0.5 and 10 MeV, preferably between 0.5 and 5 MeV, more preferably between 0.5 and 2 MeV.
- a particle dose of the fission-initiating ions is preferably between 1 E15 cm' 2 and 5E17 cm' 2 in each case. With this dose, a safe cleavage is achieved.
- the energy sharpness (AE/E) of the ion beam of the fission-initiating ions is preferably less than 10' 2 , more preferably less than 10' 4 . In this way it is ensured that the predetermined breaking point has a minimum thickness and the energy loss peak of the ions at the predetermined breaking point is as sharp as possible.
- the splitting of the donor substrate is preferably triggered by a temperature treatment of the composite substrate at a temperature of between 600°C and 1300°C, preferably between 750°C and 1200°C, more preferably between 850°C and 1050°C.
- a temperature treatment of the composite substrate at a temperature of between 600°C and 1300°C, preferably between 750°C and 1200°C, more preferably between 850°C and 1050°C.
- mechanical methods are also conceivable.
- the bonding connection is produced by thermal treatment of the composite substrate at a temperature of between 800° C. and 1,600° C., preferably between 900° C. and 1,300° C.
- both the production of the bonded connection and the splitting of the donor substrate are carried out by means of a heat treatment, with both steps being carried out simultaneously.
- a pretreatment of at least one, preferably both surfaces to be bonded preferably takes place before the step of producing the bond connection, in particular a wet-chemical treatment, plasma treatment or ion beam treatment.
- the acceptor substrate is preferably thermally stable up to at least 1,500° C. and has a coefficient of linear expansion which deviates from the coefficient of linear expansion of SiC by at most 20%, preferably by at most 10%. This effectively prevents the composite substrate from bending.
- the acceptor substrate is made of polycrystalline SiC or graphite.
- the surface of the composite substrate is preferably post-treated in the area of the predetermined breaking point, in particular by means of polishing and/or the removal of defects (close to the surface).
- an electronic semiconductor component which is preferably a vertical semiconductor component and more preferably a high blocking power vertical power semiconductor component, is produced from the pretreated composite substrate by introducing further structural elements of the semiconductor component into the composite substrate from the first surface or on the first surface or placed on it.
- Examples of structural elements are: active and passive areas of different doping (source, J-FET p-doped gate structure; MOSFET channel, shielding areas, pn junctions, resurf edge areas, source-gate contact areas, J-FET channel area), isolation oxides, Gate oxides, contact areas (metals, silicides), Schottky electrodes (metals, alloys), Ohmic electrodes, source-gate metallization or wiring, passivation layers, trenches or trenches for gate electrodes, bond pads, contact holes or contact trenches.
- FIG. 1 is a schematic cross-sectional view of a first embodiment of donor substrate that can be used in the method of the present invention.
- FIG. 3 is a schematic representation of the operation of an energy filter that can be used in the method of the invention.
- FIG. 5 schematically shows the course of the doping of the first layer of the donor substrate and a resulting doping profile of the donor substrate. 6 shows different possibilities of the doping profile of the first layer of the donor substrate.
- FIG. 7 schematically shows the production or application of a contact layer in the donor substrate.
- FIG. 13 schematically shows a cross section through an embodiment of the pretreated composite substrate according to the invention.
- FIG. 18 schematically shows the cross section of an alternative exemplary base structure of a semiconductor device according to the invention.
- FIG. 19 schematically shows the cross section of an embodiment of the semiconductor component according to the invention in the form of a planar MOS transistor.
- FIG. 21 schematically shows the cross section of an embodiment of the semiconductor component according to the invention in the form of a vertical merged PIN Schottky diode.
- FIG. 23 schematically shows the cross section of an embodiment of the semiconductor component according to the invention in the form of a vertical trench MOSFET.
- FIG. 25 schematically shows the cross section of an embodiment of the semiconductor component according to the invention in the form of a vertical superjunction MOSFET.
- the method according to the invention for the production of a pretreated composite substrate begins with the provision of a donor substrate 12 which comprises or consists entirely of monocrystalline silicon carbide (SiC), see FIGS. 1 and 2.
- a donor substrate 12 which comprises or consists entirely of monocrystalline silicon carbide (SiC), see FIGS. 1 and 2.
- the donor substrate 12 according to FIG. 1 preferably has a thickness of more than 100 ⁇ m, preferably more than 200 ⁇ m, more preferably more than 300 ⁇ m up to 15 cm, preferably up to 10 cm.
- it can be in the form of an undoped or weakly n-doped wafer rod, see FIG. 15.
- the outer surface of the donor substrate 12 has a 0° deviation from normal to the c-direction.
- the outer surface therefore runs in a plane (0001) or in a plane (0001) of the crystal structure.
- a first layer 21 is doped in the donor substrate 12 (see FIG. 5), which later has at least the function in the finished component the drift zone (also called active zone or stress absorbing zone) takes over or partly takes over.
- This doping of the first layer 21 in the donor substrate 12 takes place by means of ion implantation using an energy filter 20.
- the corresponding basic structure is shown in FIG.
- the second shows an irradiation chamber 8 in which a high vacuum is usually present.
- the donor substrate 12 to be doped is accommodated in a substrate holder 30 in the irradiation chamber 8 .
- the substrate holder 30 does not have to be stationary, but can optionally be provided with a device for translating the donor substrate 12 in x-y (in the plane perpendicular to the plane of the sheet).
- a wafer wheel, on which the donor substrates 12 to be implanted are fixed and which rotates during the implantation, also comes into consideration as the substrate holder 30 .
- a displacement of the substrate holder 30 in the beam direction (z-direction) can also be possible.
- the substrate holder 30 can optionally be provided with heating or cooling.
- FIG. 4 a rectangular distribution that can be achieved when using an energy filter 20 is sketched by way of example with reference symbol B.
- the layouts or three-dimensional structures of energy filters 20 shown in Fig. 4 show the basic possibilities of generating a large number of dopant depth profiles using energy filters 20, conc in turn designates the doping concentration and d in turn designates the depth in the donor substrate 12.
- the filter structure profiles can in principle be combined be combined in order to obtain new filter structure profiles and thus new dopant depth profiles.
- Such energy filters 20 are typically made of silicon. They have a thickness of between 3 ⁇ m and 200 ⁇ m, preferably between 5 ⁇ m and 50 ⁇ m and particularly preferably between 7 ⁇ m and 20 ⁇ m. They can be held in a filter frame (not shown). The filter frame can be interchangeably accommodated in a filter holder (not shown).
- implantation with ions of nitrogen or phosphorus is particularly suitable, while implantation with ions of boron or aluminum is particularly suitable for a p-doped layer.
- the short black filled arrow indicates the minimum energy ions transmitted through the energy filter 20 and the long black filled arrow indicates the maximum energy ions transmitted through the energy filter 20 .
- the resulting doping profile along the section A-A' is shown on the right in the coordinate system, conc stands for the doping concentration.
- the doping profile is based on the configuration of the donor substrate 12 according to FIG. 1 and is approximately uniform over the entire first layer 21 .
- the first layer 21 extends from the outer surface 23 of the donor substrate 12 facing the ion beam 10 to a predetermined doping depth T, where a remaining part 22 of the donor substrate 12 connects which is not affected by the ion implantation by means of the energy filter.
- the thickness of the first layer 21 preferably essentially corresponds to a previously determined thickness of the active layer in the later component or a combination of active layers Layer plus a field stop layer or a combination of active layer plus a field stop layer and a superficial functional zone.
- the overall thickness of the first layer 21 is thus determined by the type and, above all, by the voltage class of the semiconductor component to be produced. The higher the voltage class, the thicker the first layer 21 . For particularly high voltage classes, reference is made to FIG. 14 and the associated description.
- the thickness of the first layer 21 is preferably between 3 and 15 ⁇ m. This corresponds to the doping depth T of the preferred types of ions mentioned above in SiC that is currently reasonably possible.
- 6a to 6c show possible preferred doping profiles in the first layer 21 of the donor substrate 12.
- FIG. 7 shows the result of the optional step of producing a contact layer 24 in a superficial area of the first layer 21 or applying a contact layer 24 to the surface of the first layer 21 .
- the dopant concentration in the contact layer 24 is preferably at least 100 times, more preferably at least 1,000 times, more preferably at least 10,000 times, even more preferably at least 100,000 times above an average dopant concentration in the rest of the first layer 21 or in the first layer 21
- a further treatment of the surface e.g. physical etching back, can take place.
- a predetermined breaking point 26 is produced in the donor substrate 24.
- the predetermined breaking point 26 is in the example of FIG. 8 in the area of the first layer 21, preferably in an end region of the first layer 21 close to the predetermined doping depth T, with the predetermined breaking point 26 preferably no further than 1 ⁇ m, more preferably no further than 500 nm. particularly preferably no further than 100 nm from the doping depth T and thus from the end of the first layer 21 .
- the predetermined breaking point 26 should still be in the area of the plateau.
- the predetermined breaking point 26 is formed at a depth of approximately 5 ⁇ m, with an ion energy of 1.0 MeV at a depth of approximately 10 ⁇ m, and with an ion energy of 1.5 MeV at a depth of about 20 pm.
- the gap-triggering ions are introduced only over part of the width of the donor substrate 12, preferably only in one or in both edge areas of the donor substrate 12. In this way, the Predetermined breaking point 26 sections predefined.
- the donor substrate 12 is connected to the acceptor substrate 28 with the side of the first layer 21 first by means of a bond connection, as is sketched in FIG. 10 .
- the first layer 21 is thus arranged in an area between the acceptor substrate 28 and the remaining part 22 of the donor substrate 12 . It is irrelevant whether the donor substrate 12 is moved to the acceptor substrate 28 to create the bond connection, as shown in FIG.
- the intermediate result of the bonding process is shown in FIG. 10 at the bottom left.
- the layer sequence could be turned upside down, e.g. if the acceptor substrate 28 was moved to the donor substrate 12.
- a low-impedance bond connection is preferably produced by thermal treatment of the substrate obtained as an intermediate result at a temperature of between 800° C. and 1,600° C., more preferably between 900° C. and 1,300° C.
- Fig. 11 the step of splitting the donor substrate 12 in the area of the predetermined breaking point 26 is shown schematically, whereby a pretreated composite substrate 18 is produced, which comprises the acceptor substrate 28 and a doped layer 32 connected thereto, the doped layer 32 comprising at least one section of the first layer 21 of the donor substrate 12 comprises.
- the part 34 of the donor substrate 12 that has been split off from the acceptor substrate 28 is removed.
- the splitting of the donor substrate 12 is preferably triggered by a temperature treatment of the composite substrate 18 at a temperature of between 600°C and 1300°C, preferably between 750°C and 1200°C, more preferably between 850°C and 1050°C.
- a temperature treatment of the composite substrate 18 at a temperature of between 600°C and 1300°C, preferably between 750°C and 1200°C, more preferably between 850°C and 1050°C.
- gas bubbles are formed due to the implanted ions, which coalesce and lead to splitting off.
- external forces may be applied to the composite substrate 18 such that the donor substrate 12 fractures along the line of weakness 26 .
- a combination of Heat treatment and external forces may be necessary or helpful. In particular, if ions were only introduced into the donor substrate 12 in sections, the exertion of external forces is unavoidable.
- both the production of the bonding connection and the splitting of the donor substrate 12 take place by means of a temperature treatment, both steps can possibly be carried out simultaneously.
- the first surface of the composite substrate 18 can be post-treated in the area of the predetermined breaking point 26, in particular by polishing and/or removing defects.
- the step of healing the implantation defects 42 is already carried out when the part 34 of the donor substrate 12 is split off and/or when the bonded connection is formed between the donor substrate 12 and the acceptor substrate 28, if correspondingly high temperatures are used and in this way the radiation defects can be healed.
- the step of producing the bonding connection between the donor substrate 12 and the acceptor substrate 28 can also take place in two stages.
- a bonding process can take place with low bonding energy at low temperature and then, in a subsequent second partial step, solidification to produce a bond connection with high bonding strength or bonding energy at higher temperature and low contact resistance.
- the solidification can also take place, for example, during or after the splitting off, during or after the surface treatment of the composite substrate or during or after the healing of implantation defects.
- the doped layer 32 preferably has a thickness of 3 ⁇ m to 30 ⁇ m, more preferably 3 ⁇ m to 15 ⁇ m. It is preferably made of SiC of polytype 4H, 6H or 3C. The surface of the doped layer 32 preferably has a deviation of less than 0.5° from a normal to the c-direction.
- the doped layer 32 preferably has p- or n-doping with a doping concentration or defect concentration of 1E15 cm-3 to 5E17 cm-3.
- the doped layer 32 has preferably been doped with ions of one of the following elements as a dopant: N, P, B or Al.
- the dopant depth profile of the doped layer 32 preferably results essentially from a reversal of the dopant depth profile of the first layer 21 in the donor substrate 12.
- the implantation defect profile essentially follows the implanted impurity concentration depth profile.
- FIG. 14 shows an alternative configuration of the pretreated composite substrate 18 in cross-section and underneath it a dopant concentration profile along the section of the composite substrate 18 according to arrow F. This is particularly suitable for the production of very high blocking components, e.g. > 600 V.
- the active layer in embodiments as in FIG. 14 is formed by a combination of doped layer 32 and the supplementary doped layer 38 .
- any other doping profiles can also be formed by lining up and partially overlapping the doping profiles in doped layer 32 and supplementary doped layer 38 .
- the combined overall doping profile from the combination of both dopant depth profiles of the doped layer 32 and the supplementary doped layer 38 can also have a profile that rises in steps towards the acceptor substrate 28 or a towards the acceptor substrate 28 continuously increasing profile. Further particularly preferred doping profiles are described in more detail below with reference to FIG.
- reference numeral 48 designates the first portion of the donor substrate 12 which remains as part of the composite substrate 18 after cleavage, respectively.
- This first section 48 can be composed either of the doped layer 32 alone, if there is no supplementary doped layer 38 (Fig. 13), or of a combination of the doped layer 32 and the supplementary doped layer 38 (Fig. 14, Fig. 20 ).
- Such combined profiles are obtained in that the predetermined breaking point 26 in the donor substrate 12 is not produced within the first layer 21 but in the remaining part 22 of the donor substrate 12 that was not doped into the donor substrate 12 by means of ion implantation.
- ion implantation by energy filter 20 into the first layer 21 of the donor substrate 12 (and/or the supplemental doped layer 38 of the composite substrate 18) may use a mask 46 to remove one or more to produce non-doped regions 44 in the first layer 21 of the donor substrate 12 (and/or in the supplementary doped layer 38 of the composite substrate 18).
- the composite substrate 18 can become a finished semiconductor component 50 through further steps, for example through the implantation of further active regions, the production of oxides, the deposition of gate electrodes, contacts, lines or vias, etc.
- a crystal 53 made of SiC is attached to the carrier substrate 52 .
- This crystal 53 typically corresponds to the first portion 48 of the donor substrate 12 of the pretreated composite substrate 18.
- the crystal 53 has a first surface 58 on the side facing away from the carrier substrate 52 .
- This first surface 58 deviates less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, most preferably not at all from a direction perpendicular to the c-direction (arrow c) the crystal structure of the crystal 53.
- the electronic semiconductor component 50 comprises an active component region 64 which has a first zone 54 in the region of the first surface 58 and a second zone 56 adjoining the first zone 54 in the depth direction.
- the first zone 54 includes a near-surface shielding structure 60 or JFET structure in an area that includes at least portions of the first surface 58 of the crystal 53 .
- the shielding structure or J-FET structure is characterized by a p + /n junction that is interrupted in one direction, ie a p + region is formed in certain areas (not continuously) and as a rule cannot be cleared out.
- the areas with p+ doping are marked with reference number 68 .
- the second zone 56 comprises or consists of a stress-absorbing layer (also called a drift zone or active layer).
- the transition between the first zone 54 and the second zone 56 is indicated by the dashed line.
- the thickness of the second zone 56 is preferably between 2 ⁇ m and 50 ⁇ m.
- the semiconductor component 50 also includes a field-free contact zone or field stop zone 62 at the transition between the second zone 56 and the carrier substrate 52.
- This field stop zone 62 usually corresponds to the contact layer 24 of the pretreated composite substrate 18.
- the field-free contact zone or field stop zone 62 has a vertical thickness of no more than 2 ⁇ m, preferably no more than 1 ⁇ m.
- the second basic structure, shown in FIG. 18, of the semiconductor component 50 according to the invention corresponds in essential parts to the basic structure from FIG. 17.
- the same reference symbols denote the same elements.
- the difference is that the p + regions 60 are not buried regions but are continuous to the first surface 58 .
- all p-doped shielding structures 60 have several common features.
- the shielding structures 60 are not designed to be continuous parallel to the first surface 58, but instead are designed to be periodically interrupted. Due to the distance from the first surface 58, the distances are formed in such a way that the maximum tolerable field strength on the first surface 58 is reliably not exceeded in the “open” areas in blocking operation.
- the shielding structures 60 are connected to the source potential, gate potential or anode potential either directly or via lines (third dimension, not shown).
- the shielding structures 60 are either isolated (apart from the electrical connection) embedded in an n-region or, starting from the first surface 58, they are formed as doped regions with a high aspect ratio.
- the typical depths of the pn junction are between 500 nm and 3.0 pm.
- the shielding structures 60 are so highly doped that the areas are not cleared out even in the case of maximum blocking voltage.
- the spatial delimitation between the first zone 54 and the second zone 56 represented by the dashed line in FIG. 17 and FIG. The transition is commonly defined in this specification as parallel to the first surface 58.
- FIG. 19 shows a vertical power semiconductor component 50 in the form of a planar MOS transistor.
- the non-active edge region 66 is preferably nominally undoped.
- Reference number 52 continues to designate the carrier substrate, reference number 53 continues to designate the SiC crystal, reference number 54 continues to designate the first zone, reference number 56 continues to designate the second zone, reference number 62 continues to designate the field stop zone, reference number 52 continues to designate the carrier substrate, and reference number 68 continues to designate the p + regions of the shielding structure.
- a metal contact 71 is applied to the underside of the carrier substrate 52 .
- G denotes the gate electrode
- S denotes the source electrode
- D denotes the drain electrode.
- the first surface 58 is oriented essentially perpendicularly to the c-direction (arrow c) of the crystal structure of the crystal 53 . Minor deviations of up to 0.5° can be tolerated under certain circumstances. It also follows that the channel region 76 (shown dotted) which is parallel to the first surface 58 of the crystal 53 is deviated by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1° , most preferably not at all, deviates from a direction perpendicular to the c-direction of the crystal structure of the crystal 53.
- planar MOSFET In addition to the illustrated embodiment of the planar MOSFET, many other configurations of a planar MOSFET are known to those skilled in the art, which are also intended to be covered by the invention, as long as the first surface 58 of the crystal 53 is essentially perpendicular to the c-direction (arrow c) of the crystal structure of the Crystal 53 is aligned.
- the doping profile (conc) shown in FIG. 20 of the semiconductor component 50 from FIG. can also be constant, or it can be a profile that rises in steps in the end area of the second zone 56, as indicated by the dashed lines. It has already been described in detail above with reference to FIGS. 6a to 6c how such doping profiles are to be obtained.
- a doping concentration in a p + region 68 of the first zone 54 is preferably higher by a factor of 2 to 1000, particularly preferably by a factor of 50 to 1000, than a doping concentration in an n-doped region of the second zone 56 facing the first zone 54.
- the doping profile in the first zone 54 and the second zone 56 can be essentially flush with one another. This is self-explanatory if the first zone 54 and the second zone 56 were doped (as the doped layer 32 in the donor substrate 12) using the same implantation process. However, this is also possible if the first zone 54 is only doped in a subsequent implantation process (eg as a supplementary doped layer 38).
- the doping profiles of the second zone 56 from FIG. 20 can also be applied to the second zones 56 of all the other semiconductor components 50 described.
- FIG. 21 shows a vertical power semiconductor component 50 in the form of a vertical merged PIN Schottky diode (MPS diode).
- MPS diode vertical merged PIN Schottky diode
- the p+ regions 68 here run through the entire depth of the first zone 54 from the first surface 58 to the transition to the second zone 56.
- the first surface 58 is in turn formed continuously over the entire width of the semiconductor component 50 and is essentially perpendicular to the c- Direction (arrow c) of the crystal structure of the crystal 53 aligned.
- Numeral 78 denotes the Schottky material
- numeral 80 denotes a metal layer (anode).
- Metal contact 71 acts as a cathode.
- the MPS diode illustrated in FIG. 22 differs from the MPS diode from FIG from a depth at which the second zone 56 begins to a depth at which the field-free contact zone or field stop zone 62 lies, is provided with the same doping concentration as the second zone 56 or is provided with a lower doping concentration than the second zone 56, preferably at least 20% lower doping concentration, more preferably at least 50% lower dopant concentration.
- This doped part of the edge area 66 is marked with reference number 84 .
- Such a doped region 84 can also be present in other configurations of the semiconductor component 50 .
- FIG. 23 shows a vertical power semiconductor component 50 in the form of a vertical trench MOSFET.
- the same reference symbols designate the same elements as in FIG. 19.
- Reference symbol 86 designates a trench at least partially lined with a gate oxide
- reference symbol 88 designates p-doped regions
- reference symbol 90 designates n-doped regions
- reference symbol 92 designates the respective channel region (shown dotted).
- the channel region 92 deviates from the c-direction (arrow c) of the crystal structure by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, most preferably not at all 53 off. Likewise, the channel region 92 deviates from a direction perpendicular to the first surface 58 of the crystal 53 by less than 0.5°, preferably less than 0.3°, more preferably less than 0.1°, most preferably not at all . It is particularly preferred that the channel region 92 is arranged in an A plane of the crystal 53 .
- the embodiment of a vertical trench MOSFET shown in FIG. 24 differs from the embodiment according to FIG extending to the first surface 58, and the source electrodes S.
- many other configurations of trench MOSFETs are known to those skilled in the art, which should also be covered by the invention, as long as the first surface 58 of the crystal 53 is essentially perpendicular to the c-direction of the crystal structure of the crystal 53 is aligned.
- the p-doped pillars 94 in the second region 2 differ from the p+ regions 68 in the first region 54 in that they are in the stress-bearing region. This means that the p-doped columns 94 must be designed to be completely depletable. That is, in the blocking case, the space charge zone extends laterally both over the p-columns and the n-regions 95 in the second zone 56.
- the gate trenches 86 and the p+ regions (shielding structures) 68 are again designed as long trenches.
- the p-doped columns 94 in the second zone 56 are arranged perpendicular to the gate trenches 86 and the p+ regions 68, see the schematic plan view from FIG. 26.
- FIG. 27 shows a vertical power semiconductor component 50 in the form of a J-FET (Junction Field Effect Transistor).
- the same reference symbols denote the same elements or areas as in the previous figures.
- the p + regions 68 run in a U-shape around the likewise U-shaped gate contacts, and the relevant interfaces 96 between p + and n are shown in dotted form. These boundary surfaces 96 run perpendicular to the partial sections of the first surface 58.
- a crystal 53 from a thin layer of high-quality crystalline SiC material, which is suitable for forming devices 50 and whose surface is substantially perpendicular to the c-direction of the crystal structure of the crystal 53 is oriented temporarily during component production by a carrier, e.g. by means of temporary bond connections, to be stabilized or designed to be completely self-supporting. In these cases, there is no need for a carrier substrate 52 in the finished component 50.
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- 2021-12-10 EP EP21836128.5A patent/EP4264672A1/de active Pending
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EP0962963A1 (de) * | 1997-08-27 | 1999-12-08 | Matsushita Electric Industrial Co., Ltd. | Siliziumkarbid-substrat, dessen herstellung und halbleiterelement aus sic |
EP2040285A1 (de) * | 2007-09-19 | 2009-03-25 | S.O.I. TEC Silicon | Verfahren zur Herstellung eines Substrats mit gemischter Ausrichtung |
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DE112013001802T5 (de) * | 2012-03-30 | 2015-02-26 | Fuji Electric Co., Ltd. | Hochspannungshalbleitervorrichtung |
US20150053999A1 (en) * | 2013-08-23 | 2015-02-26 | Fuji Electric Co., Ltd. | Wide bandgap insulated gate semiconductor device |
DE102014118336A1 (de) * | 2013-12-13 | 2015-06-18 | Infineon Technologies Ag | Verbundstruktur und verfahren zum bilden einer verbundstruktur |
US20180166530A1 (en) * | 2016-12-08 | 2018-06-14 | Cree, Inc. | Power semiconductor devices having gate trenches and buried edge terminations and related methods |
US20190198659A1 (en) * | 2017-12-21 | 2019-06-27 | Cree, Inc. | Vertical semiconductor device with improved ruggedness |
WO2020032204A1 (ja) * | 2018-08-10 | 2020-02-13 | ローム株式会社 | SiC半導体装置 |
DE102019112985A1 (de) | 2019-05-16 | 2020-11-19 | mi2-factory GmbH | Verfahren zur Herstellung von Halbleiterbauelementen |
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US20240055472A1 (en) | 2024-02-15 |
EP4264672A1 (de) | 2023-10-25 |
JP2023553477A (ja) | 2023-12-21 |
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