WO2020224013A1 - 一种薄膜电晶体及其制作方法 - Google Patents

一种薄膜电晶体及其制作方法 Download PDF

Info

Publication number
WO2020224013A1
WO2020224013A1 PCT/CN2019/088513 CN2019088513W WO2020224013A1 WO 2020224013 A1 WO2020224013 A1 WO 2020224013A1 CN 2019088513 W CN2019088513 W CN 2019088513W WO 2020224013 A1 WO2020224013 A1 WO 2020224013A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
film transistor
manufacturing
thin film
transistor according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/088513
Other languages
English (en)
French (fr)
Inventor
谭志威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US16/495,157 priority Critical patent/US11233138B2/en
Publication of WO2020224013A1 publication Critical patent/WO2020224013A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks

Definitions

  • the invention relates to a display field technology, in particular to a thin film transistor and a manufacturing method thereof.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • the display panels are LCD and OLED.
  • TFT Thin Film Transistor
  • CF Color Filter
  • Its working principle is to change the rotation direction of liquid crystal molecules in the liquid crystal layer by applying voltage on the TFT substrate and the CF substrate to refract the light from the backlight module to produce a picture.
  • the main components of a TFT substrate are a gate electrode layer, an insulating layer, an active layer, a source and drain layer, and a pixel electrode layer.
  • a dry etching process is used in the process of making the active layer.
  • the amorphous silicon layer which is the material of the active layer, is etched.
  • the photoresist layer 20 protruding outward will hinder the dry etching gas from etching the amorphous silicon layer 21, making the etching After etching, the amorphous silicon layer 21 also protrudes outward, causing parasitic capacitance to be generated on the amorphous silicon layer 21, which reduces the yield of TFTs.
  • the present invention discloses a TFT and a method for preparing a TFT.
  • the photoresist layer is first etched to reduce the overall photoresist layer. And reduce the distance between the edge of the photoresist layer and the edge of the copper wire layer, so that the amorphous silicon layer will not be blocked by the photoresist when being etched, avoid parasitic capacitance, and improve the quality of the TFT.
  • a method for manufacturing a TFT includes: arranging a gate layer, an insulating layer, an amorphous silicon layer, a metal layer, a copper wire layer, and a photoresist layer on a base substrate; and complementing the base substrate outside the first area Perform the first wet etching to etch the metal layer and the copper wire layer outside the first area; perform the first dry etching on the complementary base substrate to etch the photoresist layer, The entire photoresist layer is thinned, and a trench with the copper wire layer at the bottom is formed in the first region; an oxidation protection layer is formed in the trench; The second dry etching is to etch the amorphous silicon layer to form an active layer; the second wet etching is performed on the base substrate to remove the oxide film layer and the oxide film in the first region.
  • the copper wire layer and the metal layer are etched to form a source and drain layer.
  • the material of the metal layer may be Mo, Ti, MoTi, MoTa, MoNb, MoW.
  • the oxidation protection layer of the channel is made by a plasma oxidation method or the copper wire layer at the channel is heated to at least 200 degrees Celsius, and then cooled by compressed air.
  • the edge of the photoresist layer is aligned with the edge of the copper wire layer.
  • the etching liquid used in the first wet etching is a copper acid etchant.
  • the etching liquid used in the second wet etching is a copper acid etchant.
  • the dry etching gas used in the second dry etching includes O2, CL2, and one or more of NF3, SF6, CHF3, and CF4.
  • the present invention also provides a TFT, including:
  • An active layer located on the insulating layer
  • the bottom surface of the channel is the clean active layer, and no other metal or metal compound remains.
  • one edge of the active layer is aligned with the outer edge of the source electrode.
  • one edge of the active layer is aligned with the outer edge of the drain.
  • the photoresist layer is dry-etched to form a channel with a copper wire layer at the bottom.
  • the edge of the photoresist layer is aligned with the edge of the copper wire, which prevents the protruding edge of the photoresist layer from obstructing the second dry etching gas to etch the amorphous silicon layer.
  • the generation of parasitic capacitance improves the aperture ratio and yield of TFT.
  • the present invention also adds a new manufacturing process to form an oxide protective layer at the channel to prevent the copper wire layer from reacting with the first dry etching gas Compounds are formed, which leads to incomplete etching when fabricating source and drain electrodes, which further improves the quality of TFTs.
  • FIG. 1 is a schematic diagram of the structure of the active layer of the thin film transistor in the prior art.
  • Fig. 2 is a process flow diagram of a method for manufacturing a thin film transistor in an embodiment of the present invention.
  • step S1 of the thin film transistor manufacturing method in the embodiment of the present invention is a schematic diagram of the structure of the device obtained in step S1 of the thin film transistor manufacturing method in the embodiment of the present invention.
  • step S2 is a schematic diagram of the structure of the device obtained in step S2 of the thin film transistor manufacturing method in the embodiment of the present invention.
  • step S3 of the thin film transistor manufacturing method in the embodiment of the present invention is a schematic diagram of the structure of the device obtained in step S3 of the thin film transistor manufacturing method in the embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the structure of the device obtained in step S4 of the thin film transistor manufacturing method in the embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the structure of the device obtained in step S5 of the thin film transistor manufacturing method in the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the structure of the device obtained in step S6 of the thin film transistor manufacturing method in the embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present invention.
  • the invention invents a TFT and a TFT manufacturing method to solve the technical problem of incomplete etching of the amorphous silicon layer due to the protruding protection of the photoresist in the process of manufacturing the active layer, thereby generating parasitic capacitance.
  • FIG. 2 The process flow chart of the manufacturing method of the TFT is shown in FIG. 2;
  • the method includes:
  • a gate electrode layer (not shown in the figure), an insulating layer (not shown in the figure), an amorphous silicon layer 10, a metal layer 11, and copper are sequentially fabricated on a complementary base substrate (not shown in the figure).
  • the first dry etching is performed on the base complement substrate (not shown in the figure), and the photoresist layer 13 is etched to make the whole photoresist layer 13 thinner.
  • a channel with the bottom of the copper wire layer 12 is formed in the first region 100, and the edge of the photoresist layer 13 is aligned with the edge of the copper wire layer 12;
  • an oxide protective layer 14 is formed on the channel
  • a second dry etching is performed on the base supplement substrate (not shown in the figure), and the amorphous silicon layer 10 outside the first region 100 is etched to form an active Layer 15, since the edge of the photoresist layer 13 is aligned with the edge of the copper wire layer 12, the photoresist layer 13 will not hinder the etching of the amorphous silicon layer 10 by the etching gas, so the The edge of the source layer 15 can be aligned with the edge of the metal layer 11 to avoid the generation of parasitic capacitance, thereby improving the aperture ratio and yield of the TFT;
  • a second wet etching is performed on the base complement substrate (not shown in the figure) to perform a second wet etching on the oxidation protection layer 14 and the copper wire layer in the first region 100 12 and the metal layer 11 are etched to form source and drain electrodes 16. Since the oxidation protection layer 14 isolates the copper wire layer 12 from contacting the etching gas of the second dry etching, there is no compound It is formed on the copper wire layer 12 in the first region 100, and then when the second wet etching is performed, a cleaner channel can be obtained, which improves the production yield of TFT.
  • the material of the metal layer 11 is Mo.
  • the manufacturing method of the oxidation protection layer of the channel is a plasma oxidation method.
  • the edge of the photoresist layer 13 is aligned with the edge of the copper wire layer 12.
  • the etching liquid used in the first wet etching is a copper acid etchant.
  • the etching liquid used in the second wet etching is a copper acid etchant.
  • the etching gas used in the second dry etching includes O2, CL2, and one or more of NF3, SF6, CHF3, and CF4.
  • the present invention also provides a TFT, including:
  • One complementary base substrate 30 is
  • An active layer 33 located on the insulating layer 32;
  • a source 34/drain 35 is located on the active layer 33, and a channel 36 exists between the source 34 and the drain 35.
  • the bottom surface of the channel 36 is the clean active layer 33, that is, no other metal or metal compound remains on the channel 36.
  • one edge of the active layer 33 is aligned with the outer edge of the source electrode 34; the other edge of the active layer 33 is aligned with the outer edge of the drain electrode 35.
  • the TFT provided by the present invention has no other metal or metal compound remaining on the surface of the channel between the source and drain, which improves the yield of the TFT.
  • the two edges of the active layer They are respectively aligned with the outer edges of the source electrode and the drain electrode, which reduces the amount of parasitic capacitance generated at the edge of the marginal layer and further improves the quality of the TFT.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

一种薄膜电晶体和其制作方法，包括：在一补底基板形成栅级层、绝缘层、非晶硅层、金属层、铜导线层以及光阻层。在制作有源层之前先对所述光阻层进行干刻蚀，形成一底部为所述铜导线层之沟道，同时使所述光阻层之边缘与所述金属层之边缘切齐，防止所述光阻层阻碍刻蚀气体对所述有源层刻蚀，提高了薄膜电晶体之开口率以及良率。在所述沟道处形成一氧化保护层，防止所述铜导线层与刻蚀气体反应形成化合物，使得后续能够得到较干净的沟道，提高了薄膜电晶体之良率。

Description

一种薄膜电晶体及其制作方法 技术领域
本发明涉及一种显示领域技术，尤其涉及一种薄膜电晶体及其制作方法。
 背景技术
随着显示技术领域的进步，人们对于液晶显示器(Liquid Crystal Display, LCD)以及有机发光二级体(Organic Light Emitting Diode, OLED)等平板显示器的要求也越来越高，显示面板为LCD及OLED的重要组成部份，以LCD为例，通常具有一薄膜电电晶体(Thin Film Transistor, TFT)及一彩色滤光片(Color Filter, CF)及两基板中间的液晶层(Liquid Crystal Layer)所组成，其工作原理是通过在TFT基板以及CF基板上施加电压来改变液晶层中液晶分子的旋转方向将背光模组的光线折射出来产生画面。
 技术问题
现有技术中，TFT基板主要的组成为栅电极层、绝缘层、有源层、源漏极层以及像素电极层，其中，在制作所述有源层的过程中会运用到干刻蚀工艺对所述有源层之材料非晶硅层进行刻蚀，如图1所示，此时向外突出的光阻层20会阻碍干刻蚀气体对非晶硅层21进行刻蚀，使刻蚀过后之所述非晶硅层21同样向外凸出，导致寄生电容产生在所述非晶硅层21上，降低了TFT的良率。
 技术解决方案
鉴于现有技术的不足，本发明揭露了一种TFT和一种TFT的制备方法，在对非晶硅层进行干刻蚀前，先对光阻层进行刻蚀，降低所述光阻层整体厚度，并使所述光阻层边缘和铜导线层边缘距离减小，使所述非晶硅层在被刻蚀时不会被光阻所阻挡，避免产生寄生电容，提升了TFT的品质。
具体方法如下：
一种TFT的制作方法，包括：在一衬底基板上设置栅极层、绝缘层、非晶硅层、金属层、铜导线层及光阻层；对第一区域外之所述补底基板进行第一次湿刻蚀，将第一区域外之所述金属层及所述铜导线层刻蚀；对所述补底基板进行第一次干刻蚀，将所述光阻层刻蚀，使整体所述光阻层变薄，并在所述第一区域内形成一底部为所述铜导线层之沟道；在所述沟道形成一氧化保护层；对所述补底基板进行第二次干刻蚀，将所述非晶硅层刻蚀，形成有源层；对所述补底基板进行第二次湿刻蚀，将所述第一区域内之所述氧化薄膜层、所述铜导线层和所述金属层进行刻蚀，形成源漏极层。
其中，所述金属层之材料可选为Mo、Ti、MoTi、MoTa、MoNb、MoW。
其中，所述沟道之所述氧化保护层制作方式为等离子氧化法或将所述沟道处的所述铜导线层加热至至少200摄氏度后，再通过压缩空气冷却。
其中，在第一次干刻蚀后，所述光阻层之边缘与所述铜导线层之边缘切齐。
其中，所述第一次湿刻蚀使用之刻蚀液体为铜酸刻蚀剂。
其中，所述第二次湿刻蚀使用之刻蚀液体为铜酸刻蚀剂。
其中， 所述第二次干刻蚀使用之刻干刻蚀气体包括O2 ，CL2以及NF3 、SF6 、CHF3 、CF4之其中一种或两种以上。
为了解决上述问题，本发明还提供一种TFT，包括：
一补底基板；
一栅电极，位于所述补底基板上；
一绝缘层，位于所述栅电极上；
一有源层，位于所述绝缘层上；
一源极/漏极，位于所述有源层之上，所述源极和所述漏极之间存在一沟道；
其中，所述沟道底部表面为干净的所述有源层，无其他金属或金属化合物残留。
其中，所述有源层之一边缘与所述源极之外边缘切齐。
其中，所述有源层之一边缘与所述漏极之外边缘切齐。
 有益效果
本发明提供的TFT和TFT的制作方法，在制作有源层的过程前，先对光阻层进行干刻蚀，形成一底部为铜导线层的沟道。此时，所述光阻层边缘与所述铜导线边缘切齐，避免了所述光阻层之凸出边缘阻碍了第二次干刻蚀气体对非晶硅层进行刻蚀之情形，减少寄生电容的产生，提高了TFT之开口率和良率，本发明还另外新增一道制程，在所述沟道处形成一氧化保护层，避免所述铜导线层与第一次干刻蚀气体反应形成化合物，从而导致制作源漏极时，出现刻蚀不完全的情况，进一步提升了TFT之品质。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中，制作薄膜电晶体之有源层的结构示意图。
图2为本发明实施例中，薄膜电晶体的制作方法的工艺流程图。
图3为本发明实施例中，薄膜电晶体制备方法的步骤S1所得到之器件的结构示意图。
图4为本发明实施例中，薄膜电晶体制备方法的步骤S2所得到之器件的结构示意图。
图5为本发明实施例中，薄膜电晶体制备方法的步骤S3所得到之器件的结构示意图。
图6为本发明实施例中，薄膜电晶体制备方法的步骤S4所得到之器件的结构示意图。
图7为本发明实施例中，薄膜电晶体制备方法的步骤S5所得到之器件的结构示意图。
图8为本发明实施例中，薄膜电晶体制备方法的步骤S6所得到之器件的结构示意图。
图9为本发明实施例提供的薄膜电晶体的结构示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述，在以下实施例中，在不同的图中，相同部份是以相同标号表示。
本发明发明一种TFT和一种TFT的制作方法，用以解决制作有源层的过程中，非晶硅层因光阻凸出保护而导致刻蚀不完全，从而产生寄生电容的技术问题。
所述TFT的制作方法的工艺流程图如图2所示；
所述方法包括：
S1、如图3所示，在一补底基板(图未标示)上依序制作栅电极层(图未标示)、绝缘层(图未标示)、非晶硅层10、金属层11、铜导线层12及光阻层13；
 S2、如图4所示，对所述补底基板(图未标示)进行第一次湿刻蚀，将第一区域100外之所述金属层11及所述铜导线层12刻蚀；
 S3、如图5所示，对所述补底基板(图未标示)进行第一次干刻蚀，将所述光阻层13刻蚀，使整体所述光阻层13变薄，在所述第一区域100内形成一底部为所述铜导线层12之沟道，并使所述光阻层13之边缘与所述铜导线层12之边缘切齐；
S4、如图6所示，在所述沟道上形成一氧化保护层14；
S5、如图7所示，对所述补底基板(图未标示)进行第二次干刻蚀，将所述第一区域100外之所述非晶硅层10进行刻蚀，形成有源层15，由于所述光阻层13之边缘与所述铜导线层12之边缘切齐，所述光阻层13不会阻碍刻蚀气体对非晶硅层10进行刻蚀，因此所述有源层15之边缘能与所述金属层11之边缘切齐，避免了寄生电容的产生，从而提高了TFT的开口率以及良率；
    S6、如图8所示，对所述补底基板(图未标示)进行第二次湿刻蚀，对所述第一区域100内之所述所述氧化保护层14、 所述铜导线层12以及所述金属层11进行刻蚀，形成源漏极16，由于所述氧化保护层14隔绝了所述铜导线层12与所述第二次干刻蚀之刻蚀气体接触，因此没有化合物形成在所述第一区域100内之所述铜导线层12上，之后在进行所述第二次湿刻蚀时，能够得到较干净的沟道，提升了TFT的生产良率。
具体地，所述金属层11之材料为Mo。
具体地，所述沟道之所述氧化保护层制作方式为等离子氧化法。
具体地，在第一次干刻蚀后，所述光阻层13之边缘与所述铜导线层12之边缘切齐。
具体地，所述第一次湿刻蚀使用之刻蚀液体为铜酸刻蚀剂。
具体地，所述第二次湿刻蚀使用之刻蚀液体为铜酸刻蚀剂。
具体地，所述第二次干刻蚀使用之刻蚀气体包括O2，CL2以及NF3 、SF6、CHF3、CF4之其中一种或两种以上。
如图9所示，本发明还提供一种TFT，包括：
一补底基板30；
一栅电极31，位于所述补底基板30上；
一绝缘层32，位于所述栅电极31上；
一有源层33，位于所述绝缘层32上；
一源极34/漏极35，位于所述有源层33之上，所述源极34和所述漏极35之间存在一沟道36。
具体地，所述沟道36底部表面为干净的所述有源层33，即所述沟道36上无其他金属或金属化合物残留。
具体地，所述有源层33之一边缘与所述源极34之外边缘切齐；所述有源层33之另一边缘与所述漏极35之外边缘切齐。
有益效果为：本发明所提供之TFT，在源极和漏极之间的沟道处表面处无其他金属或金属化合物残留，提升了TFT的良率，另外，所述有源层之两边缘分别与所述源极和所述漏极之外侧边缘切齐，降低了寄生电容产生在有缘层边缘的数量，进一步提升了TFT的品质。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (12)

  1. 一种薄膜电晶体的制作方法，所述方法包括：
    步驟1、在一衬底基板上设置栅极层、绝缘层、非晶硅层、金属层、铜导线层及光阻层；
    步驟2、对第一区域外之所述铜导线层及所述金属层进行湿刻蚀；
    步驟3、对所述光阻层进行干刻蚀，形成一底部为所述铜导线层之沟道；
    步驟4、对所述非晶硅层进行干刻蚀，形成有源层；
    步驟5、对所述沟道处之所述铜导线层和所述金属层进行湿刻蚀，形成源漏极。
  2. 根据权利要求1所述之薄膜电晶体的制作方法，其中，所述步驟1之所述金属层之材料可选为Mo、Ti、MoTi、MoTa、MoNb或MoW。
  3. 根据权利要求1所述之薄膜电晶体的制作方法，其中，所述步驟2之刻蚀液体包括铜酸刻蚀剂。
  4. 根据权利要求1所述之薄膜电晶体的制作方法，其中，所述步骤5之刻蚀液体包括铜酸刻蚀剂。
  5. 根据权利要求1所述之薄膜电晶体的制作方法，其中，所述步驟3之所述光阻层刻蚀后之边缘与所述铜导线层之边缘切齐。
  6. 根据权利要求1所述之薄膜电晶体的制作方法，其中，所述步驟4之刻蚀气体包括O 2，CL 2以及NF 3、SF 6、CHF 3、CF 4之其中一种或两种以上。
  7. 根据权利要求1所述之薄膜电晶体的制作方法，其中，所述步驟3还包括步驟31：在所述沟道处形成一氧化保护层。
  8. 根据权利要求7所述之薄膜电晶体的制作方法，其中，所述氧化保护层的形成方式为：以等离子氧化法处理所述铜导线层表面。
  9. 根据权利要求7所述之薄膜电晶体的制作方法，其中，所述氧化保护层的形成方式为：将所述沟道处的所述铜导线层加热至至少200摄氏度，再通过压缩空气冷却。
  10. 一种薄膜电晶体，包括：
    一补底基板；
    一栅电极，位于所述补底基板上；
    一绝缘层，位于所述栅电极上；
    一有源层，位于所述绝缘层上；
    一源极/漏极，位于所述有源层之上，所述源极和所述漏极之间存在一沟道；
    其中，所述沟道底部表面为干净的所述绝缘层，无其他金属或金属化合物残留。
  11. 根据权利要求10的薄膜电晶体，其中，所述有源层之一边缘与所述源极之外边缘切齐。
  12. 根据权利要求10的薄膜电晶体，其中，所述有源层之一边缘与所述源极之外边缘切齐。
PCT/CN2019/088513 2019-05-09 2019-05-27 一种薄膜电晶体及其制作方法 Ceased WO2020224013A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/495,157 US11233138B2 (en) 2019-05-09 2019-05-27 Thin film transistor and method of manufacturing same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910383608.X 2019-05-09
CN201910383608.XA CN110085520B (zh) 2019-05-09 2019-05-09 薄膜电晶体及其制作方法

Publications (1)

Publication Number Publication Date
WO2020224013A1 true WO2020224013A1 (zh) 2020-11-12

Family

ID=67419376

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/088513 Ceased WO2020224013A1 (zh) 2019-05-09 2019-05-27 一种薄膜电晶体及其制作方法

Country Status (3)

Country Link
US (1) US11233138B2 (zh)
CN (1) CN110085520B (zh)
WO (1) WO2020224013A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111029300B (zh) * 2019-11-19 2022-09-09 Tcl华星光电技术有限公司 薄膜晶体管基板的制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340758A (en) * 1990-10-05 1994-08-23 General Electric Company Device self-alignment by propagation of a reference structure's topography
CN104766859A (zh) * 2015-04-28 2015-07-08 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN107112363A (zh) * 2014-10-14 2017-08-29 韩国航空大学校产学协力团 薄膜电晶体制造方法及薄膜电晶体
CN107768307A (zh) * 2017-11-21 2018-03-06 深圳市华星光电半导体显示技术有限公司 背沟道蚀刻型tft基板及其制作方法
CN108198756A (zh) * 2017-12-26 2018-06-22 深圳市华星光电技术有限公司 薄膜晶体管的制备方法、阵列基板的制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148259B (zh) 2010-10-12 2014-04-16 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法和液晶显示器
KR101813719B1 (ko) * 2011-07-19 2017-12-29 엘지디스플레이 주식회사 박막트랜지스터 어레이 기판의 제조 방법
KR102030797B1 (ko) * 2012-03-30 2019-11-11 삼성디스플레이 주식회사 박막 트랜지스터 표시판 제조 방법
CN104617152A (zh) * 2015-01-27 2015-05-13 深圳市华星光电技术有限公司 氧化物薄膜晶体管及其制作方法
CN107658345B (zh) * 2017-09-22 2020-12-01 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置
CN108807421B (zh) * 2018-06-12 2020-11-24 深圳市华星光电技术有限公司 Tft阵列基板的制作方法及tft阵列基板
US10727256B2 (en) * 2018-10-24 2020-07-28 HKC Corporation Limited Method for fabricating array substrate, array substrate and display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340758A (en) * 1990-10-05 1994-08-23 General Electric Company Device self-alignment by propagation of a reference structure's topography
CN107112363A (zh) * 2014-10-14 2017-08-29 韩国航空大学校产学协力团 薄膜电晶体制造方法及薄膜电晶体
CN104766859A (zh) * 2015-04-28 2015-07-08 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN107768307A (zh) * 2017-11-21 2018-03-06 深圳市华星光电半导体显示技术有限公司 背沟道蚀刻型tft基板及其制作方法
CN108198756A (zh) * 2017-12-26 2018-06-22 深圳市华星光电技术有限公司 薄膜晶体管的制备方法、阵列基板的制备方法

Also Published As

Publication number Publication date
US20210336028A1 (en) 2021-10-28
CN110085520A (zh) 2019-08-02
US11233138B2 (en) 2022-01-25
CN110085520B (zh) 2020-12-08

Similar Documents

Publication Publication Date Title
US10192908B2 (en) TFT array manufacturing method of optimized 4M production process
CN107039351B (zh) Tft基板的制作方法及tft基板
US20210126022A1 (en) Array substrate and method for manufacturing same
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
CN104538352A (zh) 阵列基板及其制造方法、显示装置
WO2016101719A1 (zh) 阵列基板及其制作方法和显示装置
US9502235B2 (en) Thin film transistor, method for manufacturing the same, array substrate and display device
WO2015043282A1 (zh) 阵列基板及其制造方法和显示装置
JP2019537282A (ja) アレイ基板とその製造方法及び表示装置
WO2017219438A1 (zh) Tft基板的制造方法
WO2020082623A1 (zh) 薄膜晶体管及其制造方法
US10403654B2 (en) Mask for manufacturing TFT in 4M production process and TFT array manufacturing method of 4M production process
CN104022079A (zh) 薄膜晶体管基板的制造方法
CN109904173B (zh) 一种显示面板、显示面板的制造方法和显示装置
CN102054874B (zh) 薄膜晶体管及其制造方法
WO2021120378A1 (zh) 一种阵列基板及其制作方法
TW201715709A (zh) 顯示裝置
JP4967631B2 (ja) 表示装置
CN110085520B (zh) 薄膜电晶体及其制作方法
WO2019200834A1 (zh) Tft阵列基板的制作方法及tft阵列基板
US10749036B2 (en) Oxide semiconductor thin film transistor having spaced channel and barrier strips and manufacturing method thereof
US9171939B2 (en) Method for manufacturing thin-film transistor and thin-film transistor manufactured with same
CN105514123A (zh) Ltps阵列基板的制作方法
WO2020019606A1 (zh) Tft阵列基板及其制作方法
CN109616415A (zh) 低温多晶硅薄膜晶体管的制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19928097

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19928097

Country of ref document: EP

Kind code of ref document: A1