WO2020220423A1 - 显示面板及制作方法 - Google Patents

显示面板及制作方法 Download PDF

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Publication number
WO2020220423A1
WO2020220423A1 PCT/CN2019/088920 CN2019088920W WO2020220423A1 WO 2020220423 A1 WO2020220423 A1 WO 2020220423A1 CN 2019088920 W CN2019088920 W CN 2019088920W WO 2020220423 A1 WO2020220423 A1 WO 2020220423A1
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Prior art keywords
layer
display panel
oxide semiconductor
source
drain electrodes
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PCT/CN2019/088920
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English (en)
French (fr)
Inventor
卢马才
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/603,439 priority Critical patent/US12317591B2/en
Publication of WO2020220423A1 publication Critical patent/WO2020220423A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel and a manufacturing method.
  • TFT Thin Film Transistor
  • a-Si:H Hydrogenated amorphous silicon
  • IGZO indium gallium zinc oxide
  • the top gate self-aligned oxide semiconductor thin film transistor (TOP Gate IGZO TFT) has higher mobility, smaller parasitic capacitance and ground leakage current, and is more suitable as a current-driven display circuit.
  • TOP Gate IGZO The structure of the TFT is complicated. From the light-shielding layer to the pixel electrode layer, at least 8 photolithography processes are required, the number of masks required and the production process are large, resulting in high production costs and large-scale production.
  • the existing oxide film thin film transistors have complex structures, many manufacturing process flows, and high production costs. Therefore, it is necessary to provide a display panel and a manufacturing method to improve this defect.
  • the embodiments of the present disclosure provide a display panel and a manufacturing method thereof, which are used to solve the problems of complex structure, many manufacturing process flow and high production cost of the existing oxide film transistor.
  • the embodiments of the present disclosure provide a display panel, including:
  • Source and drain electrodes, the source and drain electrodes are arranged on the substrate;
  • a light-shielding layer is disposed on the substrate and is disposed on the same layer as the source and drain electrodes;
  • a dielectric layer is disposed on the substrate and covers the light shielding layer and the source and drain electrodes, the dielectric layer is provided with a first via hole and a second via hole, the first via hole and The second via holes respectively expose the source and drain electrodes and the surface of the light shielding layer on the side away from the substrate;
  • An oxide semiconductor layer, the oxide semiconductor layer is disposed on the dielectric layer, and is connected to the source and drain electrodes and the light shielding layer through the first via hole and the second via hole, respectively.
  • the display panel further includes a gate insulating layer, and the gate insulating layer is disposed on the oxide semiconductor layer.
  • a gate line layer is provided on the gate insulating layer, and the gate line layer is a stacked structure of molybdenum and copper or a stacked structure of aluminum and molybdenum.
  • the display panel further includes a passivation layer disposed on the dielectric layer and covering the gate line layer, the gate insulating layer, and the oxide semiconductor
  • a third via hole is provided on the passivation layer, and the third via hole exposes the surface of the oxide semiconductor layer away from the substrate.
  • a pixel electrode is provided on the passivation layer, and the pixel electrode is connected to the oxide semiconductor layer through the second via hole.
  • the source and drain electrodes and the light shielding layer are both a stacked structure of molybdenum and copper or a stacked structure of aluminum and molybdenum.
  • the material of the dielectric layer includes SiOx.
  • the material of the oxide semiconductor layer includes IGZO, IGTO, or IGZTO.
  • the embodiments of the present disclosure provide a display panel, including:
  • Source and drain electrodes, the source and drain electrodes are arranged on the substrate;
  • a light-shielding layer is disposed on the substrate and is disposed on the same layer as the source and drain electrodes;
  • a dielectric layer is disposed on the substrate and covers the light shielding layer and the source and drain electrodes, the dielectric layer is provided with a first via hole and a second via hole, the first via hole and The second via holes respectively expose the source and drain electrodes and the surface of the light shielding layer on the side away from the substrate;
  • An oxide semiconductor layer, the oxide semiconductor layer is disposed on the dielectric layer and connected to the source and drain electrodes and the light shielding layer through the first via hole and the second via hole, respectively;
  • a passivation layer is disposed on the dielectric layer and covers the oxide semiconductor layer, the passivation layer is provided with a third via hole, and the third via hole exposes the oxide The surface of the semiconductor layer on one side away from the substrate.
  • the display panel further includes a gate insulating layer and a gate line layer, the gate insulating layer is disposed on the oxide semiconductor layer, and the gate line layer is disposed on the gate.
  • the passivation layer covers the gate insulating layer and the gate line layer.
  • the gate line layer is a stacked structure of molybdenum and copper or a stacked structure of aluminum and molybdenum.
  • a pixel electrode is provided on the passivation layer, and the pixel electrode is connected to the oxide semiconductor layer through the second via hole.
  • the source and drain electrodes and the light shielding layer are both a stacked structure of molybdenum and copper or a stacked structure of aluminum and molybdenum.
  • the material of the dielectric layer includes SiOx.
  • the material of the oxide semiconductor layer includes IGZO, IGTO, or IGZTO.
  • the embodiments of the present disclosure also provide a manufacturing method of a display panel, including:
  • Step S10 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form source and drain electrodes and a light shielding layer;
  • Step S20 depositing and forming a dielectric layer on the substrate, the source and drain electrodes and the light shielding layer, and etching the dielectric layer to form a first via hole and a second via hole;
  • Step S30 depositing an oxide semiconductor layer on the dielectric layer, and patterning the oxide semiconductor layer;
  • Step S40 depositing and forming a gate insulating layer and a gate line layer on the oxide semiconductor layer;
  • Step S50 depositing and forming a passivation layer on the gate insulating layer, the gate line layer, the oxide semiconductor layer and the dielectric layer, and etching the passivation layer to form a third Vias;
  • Step S60 depositing and forming a pixel electrode layer on the passivation layer.
  • the first metal layer is a stacked structure of molybdenum and copper or a stacked structure of aluminum and molybdenum.
  • the material of the dielectric layer includes SiOx.
  • the material of the oxide semiconductor layer includes IGZO, IGTO, or IGZTO.
  • the source and drain electrodes and the light shielding layer are arranged on the same layer of the substrate, and the first metal layer is etched to form the source and drain electrodes and the light shielding layer at the same time.
  • the dielectric layer is arranged on the substrate and covers the light shielding layer and the source and drain electrode layers, so that the dielectric layer also functions as an isolation layer, thereby reducing the number of oxide thin film transistor film layers of the display panel, simplifying the film structure of the display panel, and Reduce the number of processes required for production and the number of masks used, thereby improving production efficiency and reducing production costs.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel provided in the first embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the circuit structure of the display panel provided by the first embodiment of the disclosure.
  • FIG. 3 is a schematic flow chart of a method for manufacturing a display panel provided in the second embodiment of the disclosure
  • FIG. 4 is a schematic diagram of a cross-sectional structure of the display panel in step S10 in the second embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a cross-sectional structure of the display panel in step S20 in the second embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a cross-sectional structure of the display panel in step S30 in the second embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a cross-sectional structure of the display panel in step S40 in the second embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a cross-sectional structure of the display panel in step S50 in the second embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a cross-sectional structure of the display panel provided in the second embodiment of the disclosure.
  • the embodiments of the present disclosure provide a display panel, which will be described in detail below with reference to FIGS. 1 to 2.
  • FIG. 1 is a schematic cross-sectional structure diagram of a display panel 100 provided by an embodiment of the disclosure.
  • the display panel 100 includes a substrate 110, source and drain electrodes 120, a light shielding layer 130, a dielectric layer 140 and an oxide semiconductor layer 150.
  • the source and drain electrodes 120 are provided on the substrate 110, the light shielding layer 130 is provided on the substrate 110, and the light shielding layer 130 and the source and drain electrodes 120 are provided on the same layer.
  • the dielectric layer 140 is disposed on the substrate 110 and covers the light shielding layer 130 and the source and drain electrodes 120, and the dielectric layer 140 is provided with a first via 141 and a second via 142, the The first via 141 and the second via 142 respectively expose the source and drain electrodes 120 and the surface of the light shielding layer 130 away from the substrate 110, and the oxide semiconductor layer 150 is disposed on the dielectric On the layer 140 and connected to the source and drain electrodes 120 and the light shielding layer 130 through the first via 141 and the second via 142, respectively.
  • the dielectric layer 140 covers the source and drain electrodes 120 and the light shielding layer 130, so that the dielectric layer 140 also functions as an isolation layer, thereby simplifying the film structure of the display panel 100.
  • the oxide semiconductor layer 150 includes a first oxide semiconductor 151 and a second oxide semiconductor 152.
  • the first oxide semiconductor 151 is connected to the source and drain electrodes 120 through the first via hole 141
  • the second oxide semiconductor 152 is connected to the light shielding layer 130 through the second via hole 142, so that the light shielding layer has a light shielding effect at the same time. It can also be used as the source electrode of the display panel driving TFT to simplify the film structure of the display panel 100.
  • the display panel 100 further includes a gate insulating layer 160, and the gate insulating layer 160 is disposed on the oxide semiconductor layer 150.
  • the material of the gate insulating layer 160 is SiOx.
  • the gate insulating layer 160 may also be a stacked structure of SiOx and SiNx.
  • the display panel 100 further includes a gate line layer 170, and the gate line layer 170 is disposed on the gate insulating layer 160.
  • the gate line layer 170 is a stacked structure of molybdenum and copper. In some embodiments, the gate line layer 170 may also be a stacked structure of aluminum and molybdenum.
  • the display panel 100 further includes a passivation layer 180, which is disposed on the dielectric layer 140 and covers the gate line layer 170 and the gate insulating layer 160 As well as the oxide semiconductor layer 150, a third via 181 is provided on the passivation protection layer, and the third via 181 exposes the surface of the oxide semiconductor layer 150 away from the substrate 110.
  • a passivation layer 180 which is disposed on the dielectric layer 140 and covers the gate line layer 170 and the gate insulating layer 160 As well as the oxide semiconductor layer 150, a third via 181 is provided on the passivation protection layer, and the third via 181 exposes the surface of the oxide semiconductor layer 150 away from the substrate 110.
  • the material of the passivation layer 180 may be SiOx or SiNx.
  • the passivation layer 180 may also be a stacked structure of SiOx and SiNx.
  • a pixel electrode 190 is provided on the passivation barrier 180, and the pixel electrode 190 is connected to the oxide semiconductor layer 150 through the third via 181.
  • the pixel electrode 190 is connected to the second oxide semiconductor 152 through the third via 181, so that the light shielding layer 130 can also serve as the source electrode of the display panel driving TFT, thereby simplifying the display panel 100 film structure.
  • the structure materials of the source and drain electrodes 120 and the light shielding layer 130 are the same, which not only can simplify the film structure of the display panel 100, but also can form the source and drain electrodes 120 and the light shielding layer through a single photolithography process 130, thereby reducing the production process.
  • the source and drain electrodes 120 and the light shielding layer 130 are both a stacked structure of molybdenum and copper or a stacked structure of aluminum and molybdenum.
  • the material of the dielectric layer 140 includes SiOx.
  • the dielectric layer 140 may also be a stacked structure of SiOx and SiNx.
  • the material of the oxide semiconductor layer 150 includes IGZO, IGTO or IGZTO.
  • FIG. 2 is a schematic diagram of the circuit structure of the display panel.
  • T1 is the driving TFT
  • T2 is the addressing TFT
  • CS is the storage capacitor
  • T1 converts the voltage of the gate into the current flowing through T1
  • T1 and the driving current device are in series, that is, the T1 current is the driving current device Current.
  • the gate voltage of T1 is the data voltage, which comes from the DATA line
  • T2 selectively connects the DATA signal to the gate of T1.
  • SCAN is an open signal
  • DATA enters the T1 grid
  • SCAN is an off signal
  • the T1 grid voltage has nothing to do with DATA.
  • the driving current device is an OLED. In some embodiments, the driving current device may also be a Micro LED.
  • the source and drain electrodes 120 and the light-shielding layer 130 are arranged in the same layer, and the pixel electrode 190 is connected to the light-shielding layer 130 through the second oxide semiconductor 152, so that the light-shielding layer has both light-shielding and driving functions of the display panel 100.
  • the dielectric layer 140 covers the source and drain electrodes 120 and the light shielding layer 130, so that the dielectric layer 140 also functions as an isolation layer, thereby simplifying the film of the display panel 100 Layer structure.
  • the embodiment of the present disclosure also provides a manufacturing method of the display panel 200, which will be described in detail below with reference to FIGS. 3 to 9.
  • the manufacturing method includes:
  • Step S10 as shown in FIG. 4, a substrate 210 is provided, a first metal layer is deposited and formed on the substrate 210, and the first metal layer is patterned to form source and drain electrodes 220 and a light shielding layer 230.
  • the first metal layer is a laminated structure of molybdenum and copper or a laminated structure of aluminum and molybdenum.
  • Step S20 As shown in FIG. 5, a dielectric layer 240 is deposited on the substrate 210, the source and drain electrodes 220 and the light shielding layer 230, and the dielectric layer 240 is etched to form a first via hole 241 and the second via 242.
  • the material of the dielectric layer 240 includes SiOx.
  • the dielectric layer 240 may also be a stacked structure of SiOx and SiNx.
  • step S30 as shown in FIG. 6, an oxide semiconductor layer 250 is deposited on the dielectric layer 240, and the oxide semiconductor layer 250 is patterned.
  • the material of the oxide semiconductor layer 250 is IGZO, IGTO or IGZTO.
  • the oxide semiconductor layer 250 is patterned to form a first oxide semiconductor 251 and a second oxide semiconductor 252 as shown in FIG. 6, and the first oxide semiconductor 251 is connected to each other through the first via 241
  • the source and drain electrodes 220 are connected, and the second oxide semiconductor 252 is connected to the light-shielding layer 230 through the second via 242, so that the light-shielding layer 230 can also serve as the source electrode of the driving TFT of the display panel 200 while having a light-shielding function. In this way, the film structure of the display panel 200 is simplified.
  • step S40 as shown in FIG. 7, a gate insulating layer and a gate line layer are deposited on the oxide semiconductor layer 250.
  • the material of the gate insulating layer 260 is SiOx.
  • the gate insulating layer 260 may also be a stacked structure of SiOx and SiNx.
  • the gate line layer 270 is a stacked structure of molybdenum and copper. In some embodiments, the gate line layer 270 may also be a stacked structure of aluminum and molybdenum.
  • a passivation layer 280 is deposited on the gate insulating layer 260, the gate line layer 270, the oxide semiconductor layer 250 and the dielectric layer 240, The passivation layer 280 is etched to form a third via 281. Wherein, the third via 281 exposes the surface of the oxide semiconductor layer 250 away from the substrate 210.
  • the material of the passivation layer 280 may be SiOx or SiNx. In some embodiments, the passivation layer 280 may also be a stacked structure of SiOx and SiNx.
  • Step S60 as shown in FIG. 9, a pixel electrode layer 290 is deposited on the passivation layer 280. Wherein, the pixel electrode layer 290 is connected to the second oxide semiconductor layer 250 through the third via 281.
  • the pixel electrode 290 is connected to the second oxide semiconductor 252 through the third via 281, so that the light shielding layer 230 can also serve as the source electrode of the display panel driving TFT, thereby simplifying the display panel 200 The film structure.
  • the source and drain electrodes 220 and the light shielding layer 230 are arranged on the same layer of the substrate 210, and the source and drain electrodes 220 and the light shielding layer 230 are simultaneously formed by etching the first metal layer, and the dielectric
  • the layer 240 is disposed on the substrate 210 and covers the light shielding layer 230 and the source and drain electrodes 220, so that the dielectric layer 240 also functions as an isolation layer, thereby reducing the number of film layers of the display panel 200, simplifying the film structure of the display panel 200, and Reduce the number of processes required for production and the number of masks used, thereby improving production efficiency and reducing production costs.

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示面板（100）及制作方法，显示面板（100）包括基板（110）、源漏电极（120）、遮光层（130）、电介质层（140）和氧化物半导体层（150），氧化物半导体层（150）设置于电介质层（140）上，并通过第一过孔（141）和第二过孔（142）分别与源漏电极（120）和遮光层（130）相连接，将源漏电极（120）和遮光层（130）设置于基板（100）的同一层上，并将电介质层（140）设置于基板（110）上并覆盖遮光层（130）和源漏电极（120）。

Description

显示面板及制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及制作方法。
 背景技术
显示装置产业作为具有发展潜力的电子信息产业，近年来发展迅速。其主流的有机发光二极管（Organic Light Emitting Diode, OLED）显示装置产业已成为了电子信息产业中的支柱产业之一。薄膜晶体管(Thin Film Transistor, TFT)是平板显示的核心器件，在OLED显示装置中，TFT通常作为选址开关器件。氢化非晶硅(a-Si：H)TFT是应用最为广泛的TFT技术，但受限于其低的载流子迁移率，该技术不能满足下一代OLED显示装置对高清画质的要求。TFT在OLED显示像素电路中具有至关重要的作用，它不仅作为选址开关，同时也为OLED发光器件提供驱动电流，这一特点使得OLED对TFT输出电流和迁移率提出了更高的要求。目前，被广泛研究面向下一代显示装置的TFT主流技术为以铟镓锌氧化物(indium gallium zinc oxide, IGZO)为代表的金属氧化物TFT。
 技术问题
顶栅自对准氧化物半导体薄膜晶体管（TOP Gate IGZO TFT）具有较高的迁移率和较小的寄生电容以及地漏电流，比较适合作为电流驱动显示电路。现有TOP Gate IGZO TFT的结构复杂，从遮光层到像素电极层，至少需要8道光刻工艺，所需要掩膜板的数目以及生产的工序较多，造成生产成本较高，无法进行大规模的生产。
综上所述，现有氧化膜薄膜晶体管的结构复杂、制作工艺流程较多，生产成本较高。故，有必要提供一种显示面板及制作方法来改善这一缺陷。
 技术解决方案
本揭示实施例提供一种显示面板及制作方法，用于解决现有氧化膜薄膜晶体管的结构复杂、制作工艺流程较多，生产成本较高的问题。
本揭示实施例提供一种显示面板，包括：
基板；
源漏电极，所述源漏电极设置于所述基板上；
遮光层，所述遮光层设置于所述基板上，且与所述源漏电极配置于同一层；
电介质层，所述电介质层设置于所述基板上并覆盖所述遮光层和所述源漏电极，所述电介质层上设有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出所述源漏电极和所述遮光层远离所述基板一侧的表面；以及
氧化物半导体层，所述氧化物半导体层设置于所述电介质层上，并通过所述第一过孔和所述第二过孔分别与所述源漏电极和所述遮光层相连接。
根据本揭示一实施例，所述显示面板还包括栅极绝缘层，所述栅极绝缘层设置于所述氧化物半导体层上。
根据本揭示一实施例，所述栅极绝缘层上设有栅极线层，所述栅极线层为钼和铜的叠层结构或者为铝和钼的叠层结构。
根据本揭示一实施例，所述显示面板还包括钝化层，所述钝化层设置于所述电介质层上并覆盖所述栅极线层、所述栅极绝缘层以及所述氧化物半导体层，所述钝化层上设有第三过孔，所述第三过孔暴露出所述氧化物半导体层远离所述基板一侧的表面。
根据本揭示一实施例，所述钝化层上设有像素电极，所述像素电极通过所述第二过孔与所述氧化物半导体层相连接。
根据本揭示一实施例，所述源漏电极和所述遮光层均为钼和铜的叠层结构或者铝和钼的叠层结构。
根据本揭示一实施例，所述电介质层的材料包括SiOx。
根据本揭示一实施例，所述氧化物半导体层的材料包括IGZO、IGTO或IGZTO。
本揭示实施例提供一种显示面板，包括：
基板；
源漏电极，所述源漏电极设置于所述基板上；
遮光层，所述遮光层设置于所述基板上，且与所述源漏电极配置于同一层；
电介质层，所述电介质层设置于所述基板上并覆盖所述遮光层和所述源漏电极，所述电介质层上设有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出所述源漏电极和所述遮光层远离所述基板一侧的表面；
氧化物半导体层，所述氧化物半导体层设置于所述电介质层上，并通过所述第一过孔和所述第二过孔分别与所述源漏电极和所述遮光层相连接；以及
钝化层，所述钝化层设置于所述电介质层上并覆盖所述氧化物半导体层，所述钝化层上设有第三过孔，所述第三过孔暴露出所述氧化物半导体层远离所述基板一侧的表面。
根据本揭示一实施例，所述显示面板还包括栅极绝缘层和栅极线层，所述栅极绝缘层设置于所述氧化物半导体层上，所述栅极线层设置于所述栅极绝缘层上，所述钝化层覆盖所述栅极绝缘层和所述栅极线层。
根据本揭示一实施例，所述栅极线层为钼和铜的叠层结构或者为铝和钼的叠层结构。
根据本揭示一实施例，所述钝化层上设有像素电极，所述像素电极通过所述第二过孔与所述氧化物半导体层相连接。
根据本揭示一实施例，所述源漏电极和所述遮光层均为钼和铜的叠层结构或者铝和钼的叠层结构。
根据本揭示一实施例，所述电介质层的材料包括SiOx。
根据本揭示一实施例，所述氧化物半导体层的材料包括IGZO、IGTO或IGZTO。
本揭示实施例还提供一种显示面板的制作方法，包括：
步骤S10：提供基板，在所述基板上沉积形成第一金属层，并图案化所述第一金属层，形成源漏电极和遮光层；
步骤S20：在所述基板、所述源漏电极和所述遮光层上沉积形成电介质层，并对所述电介质层进行刻蚀，形成第一过孔和第二过孔；
步骤S30：在所述电介质层上沉积形成氧化物半导体层，并对所述氧化物半导体层进行图案化处理；
步骤S40：在所述氧化物半导体层上沉积形成栅极绝缘层和栅极线层；
步骤S50：在所述栅极绝缘层、所述栅极线层、所述氧化物半导体层和所述电介质层上沉积形成钝化层，并对所述钝化层进行刻蚀，形成第三过孔；以及
步骤S60：在所述钝化层上沉积形成像素电极层。
根据本揭示一实施例，所述第一金属层为钼和铜的叠层结构或者为铝和钼的叠层结构。
根据本揭示一实施例，所述电介质层的材料包括SiOx。
根据本揭示一实施例，所述氧化物半导体层的材料包括IGZO、IGTO或IGZTO。
 有益效果
本揭示的有益效果：本揭示实施例将源漏电极和遮光层设置于基板的同一层上，利用对第一金属层的刻蚀，同时形成所述源漏电极和所述遮光层，并将电介质层设置于基板上并覆盖遮光层和源漏电极层，使得电介质层兼具隔离层的作用，以此减少显示面板的氧化物薄膜晶体管膜层的数量，简化显示面板的膜层结构，同时减少生产所需的工序以及掩膜板的使用数量，从而提高生产效率，降低生产成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示实施例一提供的显示面板的截面结构示意图；
图2为本揭示实施例一提供的显示面板的电路结构示意图；
图3为本揭示实施例二提供的显示面板制作方法的流程示意图；
图4为本揭示实施例二中步骤S10的显示面板的截面结构示意图；
图5为本揭示实施例二中步骤S20的显示面板的截面结构示意图；
图6为本揭示实施例二中步骤S30的显示面板的截面结构示意图；
图7为本揭示实施例二中步骤S40的显示面板的截面结构示意图；
图8为本揭示实施例二中步骤S50的显示面板的截面结构示意图；
图9为本揭示实施例二提供的显示面板的截面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
实施例一：
本揭示实施例提供一种显示面板，下面结合图1至图2进行详细说明。
如图1所示，图1为本揭示实施例提供的显示面板100的截面结构示意图。所述显示面板100包括基板110、源漏电极120、遮光层130、电介质层140和氧化物半导体层150。
在本实施例中，所述源漏电极120设置于所述基板110上，所述遮光层130设置于所述基板110上，并且所述遮光层130与所述源漏电极120设置于同一层。所述电介质层140设置于所述基板110上，并覆盖所述遮光层130和所述源漏电极120，所述电介质层140上设有第一过孔141和第二过孔142，所述第一过孔141和所述第二过孔142分别暴露出所述源漏电极120和所述遮光层130远离所述基板110一侧的表面，所述氧化物半导体层150设置于所述电介质层140上，并通过所述第一过孔141和所述第二过孔142分别与所述源漏电极120和所述遮光层130相连接。
具体地，所述电介质层140将所述源漏电极120和所述遮光层130覆盖，使得所述电介质层140同时具备隔离层的作用，从而简化了显示面板100的膜层结构。
具体的，所述氧化物半导体层150包括第一氧化物半导体151和第二氧化物半导体152。第一氧化物半导体151通过第一过孔141与源漏电极120相连接，第二氧化物半导体152通过第二过孔142与遮光层130相连接，使得所述遮光层在具备遮光作用的同时，还可以作为显示面板驱动TFT的源电极，以此简化显示面板100的膜层结构。
在本实施例中，所述显示面板100还包括栅极绝缘层160，所述栅极绝缘层160设置于所述氧化物半导体层150上。
进一步的，所述栅极绝缘层160的材料为SiOx，在一些实施例中，所述栅极绝缘层160也可以是SiOx和SiNx的叠层结构。
在本实施例中，所述显示面板100还包括栅极线层170，所述栅极线层170设置于所述栅极绝缘层160上。
进一步的，所述栅极线层170为钼和铜的叠层结构，在一些实施例中，所述栅极线层170也可以是铝和钼的叠层结构。
在本实施例中，所述显示面板100还包括钝化层180，所述钝化层180设置于所述电介质层140上，并且覆盖所述栅极线层170、所述栅极绝缘层160以及所述氧化物半导体层150，所述钝化保护层上设有第三过孔181，所述第三过孔181暴露出所述氧化物半导体层150远离所述基板110一侧的表面。
优选的，所述钝化层180的材料可以是SiOx或者SiNx，在一些实施例中，所述钝化层180也可以是SiOx和SiNx的叠层结构。
在本实施例中，所述钝化保180上设有像素电极190，所述像素电极190通过所述第三过孔181与所述氧化物半导体层150相连接。
具体的，所述像素电极190通过所述第三过孔181与所述第二氧化物半导体152相连接，使得所述遮光层130还可以作为显示面板驱动TFT的源电极，以此简化显示面板100的膜层结构。
优选的，所述源漏电极120和所述遮光层130得结构材料均相同，以此不仅可以简化显示面板100的膜层结构，同时可以通过一次光刻工艺，形成源漏电极120和遮光层130，从而减少生产的工序。
具体的，所述源漏电极120和所述遮光层130均为钼和铜的叠层结构或者铝和钼的叠层结构。
优选的，所述电介质层140的材料包括SiOx，在一些实施例中，所述电介质层140还可以为SiOx和SiNx的叠层结构。
优选的，所述氧化物半导体层150的材料包括IGZO、IGTO或IGZTO。
如图2所示，图2为所述显示面板的电路结构示意图。其中，T1为驱动TFT，T2为选址TFT，CS为储存电容，T1将栅极的电压转换为流经T1的电流，T1与驱动电流器件为串联结构，即T1电流也就是驱动电流器件的电流。T1栅极电压为数据电压，来自于DATA线，T2有选择性的将DATA信号接入到T1的栅极。当SCAN为开启信号时，DATA进入T1栅极，当SCAN为关闭信号时，T1栅极电压与DATA无关。
在本实施例中，驱动电流器件为OLED，在一些实施例中，所述驱动电流器件也可以是Micro LED。
本揭示实施例将源漏电极120与遮光层130设置于同一层中，并将像素电极190通过第二氧化物半导体152与遮光层130相连接，使遮光层同时具备遮光和作为显示面板100驱动TFT源电极的作用，同时，将所述电介质层140将所述源漏电极120和所述遮光层130覆盖，使得所述电介质层140同时具备隔离层的作用，从而简化了显示面板100的膜层结构。
实施例二：
本揭示实施例还提供一种显示面板200的制作方法，下面结合图3至图9进行详细说明。所述制作方法包括：
步骤S10，如图4所示，提供基板210，在所述基板210上沉积形成第一金属层，并图案化所述第一金属层，形成源漏电极220和遮光层230。
在本实施例中，所述第一金属层为钼和铜的叠层结构或者为铝和钼的叠层结构。
步骤S20：如图5所示，在所述基板210、所述源漏电极220和所述遮光层230上沉积形成电介质层240，并对所述电介质层240进行刻蚀，形成第一过孔241和第二过孔242。
在本实施例中，所述电介质层240的材料包括SiOx，在一些实施例中，所述电介质层240还可以为SiOx和SiNx的叠层结构。
步骤S30，如图6所示，在所述电介质层240上沉积形成氧化物半导体层250，并对所述氧化物半导体层250进行图案化处理。
在本实施例中，所述氧化物半导体层250的材料为IGZO、IGTO或IGZTO。具体地，对所述氧化物半导体层250进行图案化处理，形成如图6所示的第一氧化物半导体251和第二氧化物半导体252，第一氧化物半导体251通过第一过孔241与源漏电极220相连接，第二氧化物半导体252通过第二过孔242与遮光层230相连接，使得所述遮光层230在具备遮光作用的同时，还可以作为显示面板200驱动TFT的源电极，以此简化显示面板200的膜层结构。
步骤S40，如图7所示，在所述氧化物半导体层250上沉积形成栅极绝缘层和栅极线层。
在本实施例中，所述栅极绝缘层260的材料为SiOx，在一些实施例中，所述栅极绝缘层260也可以是SiOx和SiNx的叠层结构。
在本实施例中，所述栅极线层270为钼和铜的叠层结构，在一些实施例中，所述栅极线层270也可以是铝和钼的叠层结构。
步骤S50，如图8所示，在所述栅极绝缘层260、所述栅极线层270、所述氧化物半导体层250和所述电介质层240上沉积形成钝化层280，并对所述钝化层280进行刻蚀，形成第三过孔281。其中，所述第三过孔281暴露出所述氧化物半导体层250远离所述基板210一侧的表面。
在本实施例中，所述钝化层280的材料可以是SiOx或者SiNx，在一些实施例中，所述钝化层280也可以是SiOx和SiNx的叠层结构。
步骤S60，如图9所示，在所述钝化层280上沉积形成像素电极层290。其中，所述像素电极层290通过所述第三过孔281与第二氧化物半导体层250相连接。
具体地所述像素电极290通过所述第三过孔281与所述第二氧化物半导体252相连接，使得所述遮光层230还可以作为显示面板驱动TFT的源电极，以此简化显示面板200的膜层结构。
本揭示实施例将源漏电极220和遮光层230设置于基板210的同一层上，利用对第一金属层的刻蚀，同时形成所述源漏电极220和所述遮光层230，并将电介质层240设置于基板210上并覆盖遮光层230和源漏电极220，使得电介质层240兼具隔离层的作用，以此减少显示面板200膜层的数量，简化显示面板200的膜层结构，同时减少生产所需的工序以及掩膜板的使用数量，从而提高生产效率，降低生产成本。
综上所述，虽然本揭示以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为基准。

Claims (19)

  1. 一种显示面板，包括：
    基板；
    源漏电极，所述源漏电极设置于所述基板上；
    遮光层，所述遮光层设置于所述基板上，且与所述源漏电极配置于同一层；
    电介质层，所述电介质层设置于所述基板上并覆盖所述遮光层和所述源漏电极，所述电介质层上设有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出所述源漏电极和所述遮光层远离所述基板一侧的表面；以及
    氧化物半导体层，所述氧化物半导体层设置于所述电介质层上，并通过所述第一过孔和所述第二过孔分别与所述源漏电极和所述遮光层相连接。
  2. 如权利要求1所述的显示面板，其中，所述显示面板还包括栅极绝缘层，所述栅极绝缘层设置于所述氧化物半导体层上。
  3. 如权利要求2所述的显示面板，其中，所述栅极绝缘层上设有栅极线层，所述栅极线层为钼和铜的叠层结构或者为铝和钼的叠层结构。
  4. 如权利要求3所述的显示面板，其中，所述显示面板还包括钝化层，所述钝化层设置于所述电介质层上并覆盖所述栅极线层、所述栅极绝缘层以及所述氧化物半导体层，所述钝化层上设有第三过孔，所述第三过孔暴露出所述氧化物半导体层远离所述基板一侧的表面。
  5. 如权利要求4所述的显示面板，其中，所述钝化层上设有像素电极，所述像素电极通过所述第二过孔与所述氧化物半导体层相连接。
  6. 如权利要求1所述的显示面板，其中，所述源漏电极和所述遮光层均为钼和铜的叠层结构或者铝和钼的叠层结构。
  7. 如权利要求3所述的显示面板，其中，所述电介质层的材料包括SiOx。
  8. 如权利要求3所述的显示面板，其中，所述氧化物半导体层的材料包括IGZO、IGTO或IGZTO。
  9. 一种显示面板，包括：
    基板；
    源漏电极，所述源漏电极设置于所述基板上；
    遮光层，所述遮光层设置于所述基板上，且与所述源漏电极配置于同一层；
    电介质层，所述电介质层设置于所述基板上并覆盖所述遮光层和所述源漏电极，所述电介质层上设有第一过孔和第二过孔，所述第一过孔和所述第二过孔分别暴露出所述源漏电极和所述遮光层远离所述基板一侧的表面；
    氧化物半导体层，所述氧化物半导体层设置于所述电介质层上，并通过所述第一过孔和所述第二过孔分别与所述源漏电极和所述遮光层相连接；以及
    钝化层，所述钝化层设置于所述电介质层上并覆盖所述氧化物半导体层，所述钝化层上设有第三过孔，所述第三过孔暴露出所述氧化物半导体层远离所述基板一侧的表面。
  10. 如权利要求9所述的显示面板，其中，所述显示面板还包括栅极绝缘层和栅极线层，所述栅极绝缘层设置于所述氧化物半导体层上，所述栅极线层设置于所述栅极绝缘层上，所述钝化层覆盖所述栅极绝缘层和所述栅极线层。
  11. 如权利要求10所述的显示面板，其中，所述栅极线层为钼和铜的叠层结构或者为铝和钼的叠层结构。
  12. 如权利要求11所述的显示面板，其中，所述钝化层上设有像素电极，所述像素电极通过所述第二过孔与所述氧化物半导体层相连接。
  13. 如权利要求9所述的显示面板，其中，所述源漏电极和所述遮光层均为钼和铜的叠层结构或者铝和钼的叠层结构。
  14. 如权利要求9所述的显示面板，其中，所述电介质层的材料包括SiOx。
  15. 如权利要求9所述的显示面板，其中，所述氧化物半导体层的材料包括IGZO、IGTO或IGZTO。
  16. 一种显示面板的制作方法，包括：
    步骤S10：提供基板，在所述基板上沉积形成第一金属层，并图案化所述第一金属层，形成源漏电极和遮光层；
    步骤S20：在所述基板、所述源漏电极和所述遮光层上沉积形成电介质层，并对所述电介质层进行刻蚀，形成第一过孔和第二过孔；
    步骤S30：在所述电介质层上沉积形成氧化物半导体层，并对所述氧化物半导体层进行图案化处理；
    步骤S40：在所述氧化物半导体层上沉积形成栅极绝缘层和栅极线层；
    步骤S50：在所述栅极绝缘层、所述栅极线层、所述氧化物半导体层和所述电介质层上沉积形成钝化层，并对所述钝化层进行刻蚀，形成第三过孔；以及
    步骤S60：在所述钝化层上沉积形成像素电极层。
  17. 如权利要求16所述的显示面板的制作方法，其中，所述第一金属层为钼和铜的叠层结构或者为铝和钼的叠层结构。
  18. 如权利要求16所述的显示面板的制作方法，其中，所述电介质层的材料包括SiOx。
  19. 如权利要求16所述的显示面板的制作方法，其中，所述氧化物半导体层的材料包括IGZO、IGTO或IGZTO。
PCT/CN2019/088920 2019-04-30 2019-05-29 显示面板及制作方法 Ceased WO2020220423A1 (zh)

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