WO2020173053A1 - 阵列基板、其制备方法及显示屏 - Google Patents

阵列基板、其制备方法及显示屏 Download PDF

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Publication number
WO2020173053A1
WO2020173053A1 PCT/CN2019/100924 CN2019100924W WO2020173053A1 WO 2020173053 A1 WO2020173053 A1 WO 2020173053A1 CN 2019100924 W CN2019100924 W CN 2019100924W WO 2020173053 A1 WO2020173053 A1 WO 2020173053A1
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WIPO (PCT)
Prior art keywords
layer
insulating
sublayer
wiring
array substrate
Prior art date
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Ceased
Application number
PCT/CN2019/100924
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English (en)
French (fr)
Inventor
李阳
马应海
于锋
刘晓佳
张九占
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Yungu Guan Technology Co Ltd
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Yungu Guan Technology Co Ltd
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Publication of WO2020173053A1 publication Critical patent/WO2020173053A1/zh
Priority to US17/218,719 priority Critical patent/US11450692B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display screen.
  • the multilayer wiring in the fan-out area, and the multilayer wiring is insulated and separated by an insulating layer.
  • the insulating layer has defects such as depressions or gaps, these defects will affect the display effect of the display.
  • the embodiments of the present disclosure provide an array substrate, a preparation method thereof, and a display screen, so as to solve the problem of poor display effect of the display screen.
  • an embodiment of the present disclosure provides an array substrate, which includes a display area and a wiring area located on one side of the display area, wherein:
  • the wiring area includes a stacked upper wiring layer and a lower wiring layer, the upper wiring layer and the lower wiring layer are separated by an insulating layer group,
  • the insulating layer set includes an insulating sublayer and an insulating organic compensator formed on the insulating sublayer, and the insulating organic compensator is used to compensate for at least a partial depression of the upper surface of the insulating sublayer.
  • the array substrate provided by the embodiments of the present disclosure has the following advantages:
  • the insulating organic compensator is provided on the insulating sublayer, and the recesses in the insulating sublayer are filled with the insulating organic compensator, thereby preventing the metal used to form the upper wiring layer from entering the insulating sublayer.
  • the recesses it is possible to avoid the problem that the metal in the recesses is difficult to remove, thereby avoiding the short-circuit phenomenon caused by the metal used to form the upper wiring layer staying in the recesses, thereby reducing the adverse effects on the array substrate and improving The yield rate of the array substrate and the display effect of the narrow border display screen are improved.
  • the insulating organic compensator is an organic glue.
  • the organic glue is polyimide adhesive or acrylic diester anaerobic glue.
  • the insulating organic compensator covers the insulating sublayer.
  • the insulating organic compensator covers the entire upper surface or part of the upper surface of the insulating sublayer.
  • the lower wiring layer includes a first wiring sublayer, a second wiring sublayer, and a second wiring sublayer for separating the first wiring sublayer and the second wiring sublayer. Interlayer insulation layer of the trace sublayer.
  • the first wiring sublayer and the gate layer of the display area are arranged in the same layer, and the interlayer insulating layer is the same as the gate insulating layer of the display area. Layer settings.
  • a first recessed area is formed between a part of the interlayer insulating layer and the second wiring sublayer, and a part of the upper surface of the insulating sublayer forms a second Two recessed areas, the insulating organic compensator includes a filling part filled in the second recessed area.
  • the interlayer insulating layer covers the first wiring sublayer, and a portion corresponding to the first wiring sublayer forms a protrusion, and the protrusion
  • the first recessed area is formed between and the second wiring sublayer;
  • the insulating sublayer covers the interlayer insulating layer, the first recessed area and the second wiring sublayer, and the insulator
  • the portion of the layer corresponding to the first recessed area forms the second recessed area.
  • the insulating sub-layer further includes a flat area located around the second recessed area, and the insulating organic compensator further includes a flat sub-layer extending to the surface of the flat area.
  • the insulating sublayer includes a first dielectric layer and a second dielectric layer that are stacked.
  • the insulating sub-layer is a stack of two layers of a silicon oxide layer and a silicon nitride layer.
  • the array substrate includes a fan-out area on one side of the display area, and the wiring area is in the fan-out area.
  • the film layer of the fan-out area and the corresponding film layer of the display area are arranged in the same layer.
  • embodiments of the present disclosure provide a display screen, which includes a chip and the aforementioned array substrate.
  • an embodiment of the present disclosure provides a method of manufacturing an array substrate, including
  • the third metal layer is patterned to form a pattern including the upper wiring layer.
  • the first metal layer and the second metal layer are formed by evaporation, sputtering or physical vapor deposition.
  • the patterning processing method for the first metal layer, the second metal layer, and the third metal layer includes yellow light, etching or yellowing. Combination of light and etching.
  • the insulating organic compensator is formed by liquid solidification, and is formed in at least part of the depression on the upper surface of the insulating sub-layer and the area around the depression, or only Formed in the recess.
  • FIG. 1 is a schematic diagram of the structure of an array substrate
  • FIG. 2 is a schematic diagram of the structure of an array substrate and a chip in an embodiment of the disclosure
  • Figure 3 is a cross-sectional view of the fan-out area in Figure 2;
  • Figure 4 is a top view along the A-A plane in Figure 3;
  • FIG. 5 is a flowchart of a manufacturing method of an array substrate in an embodiment of the disclosure.
  • inventions of the present disclosure provide an array substrate, a preparation method thereof, and a display screen.
  • the array substrate includes a display area and a wiring area located on one side of the display area.
  • the upper wiring layer and the lower wiring layer, the upper wiring layer and the lower wiring layer are separated by an insulating layer group.
  • the insulating layer group includes an insulating sublayer and an insulating organic compensator formed on the insulating sublayer. At least part of the depression on the upper surface of the compensation insulating sub-layer.
  • an insulating organic compensator is provided on the insulating sublayer, and the recessed area in the insulating sublayer is filled with the insulating organic compensator, thereby preventing the metal used to form the upper wiring layer from entering the recessed area of the insulating sublayer. It can avoid the problem that the metal in the recessed area is difficult to remove, thereby avoiding the short circuit phenomenon caused by the metal used to form the upper wiring layer staying in the recess, thereby reducing the adverse effects on the array substrate and improving the array substrate The yield rate and the display effect of the narrow border display.
  • the first embodiment of the present disclosure provides an array substrate, the array substrate includes a display area 10 and a wiring area located on one side of the display area 10, the wiring area includes a stacked upper wiring layer 56 And the lower wiring layer 60, the upper wiring layer 56 and the lower wiring layer 60 are separated by an insulating layer group.
  • the insulating layer group includes an insulating sublayer 61 and an insulating organic compensator 57 formed on the insulating sublayer 61. The insulating organic compensator 57 is used to compensate at least part of the depression of the upper surface of the insulating sublayer 61.
  • the upper wiring layer 56 is formed above the insulating layer group.
  • the insulating layer group includes an insulating sublayer 61 and an insulating organic compensator 57, wherein the insulating organic compensator 57 is located between the upper wiring layer 56 and the insulating sublayer 61.
  • the insulating organic compensator 57 can compensate for the depression, thereby providing a flat formation surface for the upper wiring layer 56 and reducing or avoiding the influence on the display effect.
  • the insulating sub-layer is formed by a chemical vapor deposition (CVD) process
  • CVD chemical vapor deposition
  • the upper surface of the insulating sub-layer 61 is not Flat
  • the case where the upper surface of the insulating sublayer 61 is uneven due to the poor flatness of the substrate under the insulating sublayer 61 is described as an example.
  • the array substrate includes a lower wiring layer 60, an insulating sublayer 61 and an upper wiring layer 56 stacked in sequence.
  • the lower wiring layer 60 includes multiple wiring layers. Because the spacing L between the multiple wiring layers is small, and usually the spacing L is less than or equal to 1 ⁇ m, and each The thickness of the wiring layers is different, so there are obvious gaps between the wiring layers.
  • the insulating sub-layer 61 When the insulating sub-layer 61 is formed over the lower wiring layer 60 by a chemical vapor deposition process, the insulating sub-layer 61 is recessed at the position corresponding to the above-mentioned gap; when a metal layer is formed over the insulating sub-layer 61 by a physical vapor deposition (PCD) process , The metal powder will enter the recess.
  • PCD physical vapor deposition
  • FIG. 3 is a schematic diagram of the structure of the array substrate corresponding to the fan-out area 50 in this embodiment.
  • the wiring area includes an upper wiring layer 56 and a lower wiring layer 60 stacked in sequence.
  • the insulating layer group includes Between the upper wiring layer 56 and the lower wiring layer 60, an insulating organic compensator 57 and an insulating sublayer 61 are stacked in sequence.
  • the insulating sublayer 61 includes multiple dielectric layers.
  • the dielectric layer may be two layers.
  • the insulating sublayer 61 includes a first dielectric layer 54 and a second dielectric layer 55 that are stacked.
  • the insulating organic compensator 57 is used to compensate at least part of the depression of the upper surface of the insulating sublayer 61.
  • the insulating organic compensator 57 can be formed in the recess and the area around the recess, or it can be formed only in the recess.
  • the insulating organic compensator 57 can be formed by solidification of a liquid, for example, can be set as a colloid, using self-leveling The principle is to fill the recesses to provide a flat surface for the upper wiring layer 56.
  • the array substrate further includes a bending area 20, a pad area 30, and a fan-out area 50, and the wiring area may be disposed in the fan-out area 50.
  • the bending area 20, the pad area 30, and the fan-out area 50 are located on the lower side of the display area 10 in this embodiment.
  • the number of the fan-out areas 50 in this embodiment can be The number of fan-out regions 50 is not specifically limited in this embodiment.
  • the insulating organic compensator 57 is provided on the insulating sublayer 61, and the insulating organic compensator 57 can fill the recesses on the upper surface of the insulating sublayer 61, thereby preventing the upper wiring layer 56 from being damaged.
  • the metal enters the recess of the insulating sub-layer 61, so that the problem that the metal in the recess is difficult to remove can be avoided, thereby avoiding the short circuit phenomenon of the upper wiring layer 56 due to the metal staying in the recess, thereby reducing the damage to the array substrate.
  • the bad influence improves the yield rate of the array substrate and the display effect of the narrow border display screen.
  • the insulating organic compensator 57 is an organic glue.
  • the organic glue can fill the recess in the insulating sub-layer 61 during the flow process, avoiding the residue caused by the subsequent metal used to form the upper wiring layer 56 infiltrating the recess.
  • the organic glue can be a polyimide adhesive or an acrylate diester anaerobic glue.
  • the insulating organic compensator 57 covers the insulating sublayer 61.
  • the insulating organic compensator 57 may cover the entire upper surface of the insulating sub-layer 61 or part of the upper surface of the insulating sub-layer 61.
  • the lower wiring layer 60 includes a first wiring sublayer 51, a second wiring sublayer 53, and a wiring sublayer for separating the first wiring sublayer 51 and the second wiring sublayer 53.
  • the first recessed area 58 is formed between a part of the interlayer insulating layer 52 and the second wiring sub-layer 53.
  • a part of the upper surface of the insulating sub-layer 61 forms a second recessed area 59.
  • the organic compensator 57 includes a filling part filled in the second recessed area 59.
  • first wirings in the first wiring sublayer 51 there are multiple first wirings in the first wiring sublayer 51, and the multiple first wirings are arranged on the array substrate, for example, arranged at equal intervals and parallel to each other on the array substrate.
  • An interlayer insulating layer 52 is provided above the first wiring sublayer 51, and a second wiring sublayer 53 is provided above the interlayer insulating layer 52.
  • the interlayer insulating layer 52 is used to connect the first wiring
  • the sub-layer 51 and the second wiring sub-layer 53 are separated to prevent the first wiring sub-layer 51 and the second wiring sub-layer 53 from contacting and causing a short circuit. Since there is a gap between the first wiring sublayer 51 and the second wiring sublayer 53, a first recessed area 58 is formed between the interlayer insulating layer 52 and the second wiring sublayer 53.
  • the multiple second wirings in the second wiring sublayer 53 there are multiple second wirings in the second wiring sublayer 53, and the multiple second wirings are arranged on the interlayer insulating layer 52, for example, are arranged on the interlayer insulating layer 52 at equal intervals and parallel to each other.
  • the insulating sub-layer 61 is formed above the second wiring sub-layer 53 and the interlayer insulating layer 52. Therefore, the insulating sub-layer 61 forms a second recessed area 59 on the upper surface of the part corresponding to the first recessed area 58 to insulate the organic compensator 57 includes a filling part located in the second recessed area 59 to compensate for the second recessed area 59.
  • the interlayer insulating layer 52 covers the first wiring sublayer 51, and the portion corresponding to the first wiring sublayer 51 forms protrusions, and the protrusions and the second wiring sublayer 53 A first recessed region 58 is formed therebetween; an insulating sublayer 61 covers the interlayer insulating layer 52, the first recessed region 58 and the second wiring sublayer 53, and the portion of the insulating sublayer 61 corresponding to the first recessed region 58 forms a second recessed region 59 .
  • the insulating sublayer 61 further includes a flat area located around the second recessed area 59, and the insulating organic compensator 57 further includes a flat sublayer 571 extending to the surface of the flat area.
  • the insulating organic compensator 57 not only includes a filling part filled in the second recessed region 59, but also includes a flat sub-layer 571 covering the insulating sub-layer 61. Such an arrangement is convenient to use the principle of self-leveling to fabricate the insulating organic compensator 57, and to fill the second recessed area 59 more accurately.
  • the insulating sub-layer 61 is a stack of two layers of a silicon oxide layer and a silicon nitride layer.
  • the insulating sublayer 61 may be one or more dielectric layers, specifically, it includes a first dielectric layer 54 and a second dielectric layer 55, wherein the first dielectric layer 54 is a silicon oxide layer, and the second dielectric layer 55 is nitrogen.
  • the silicon layer Specifically, as shown in FIG. 3, the dielectric layer in this embodiment is provided with two layers, the first dielectric layer 54 is provided above the second wiring sublayer 53, and the second dielectric layer 55 is provided on the first dielectric layer 54.
  • the first dielectric layer 54 can be set as a silicon oxide layer
  • the second dielectric layer 55 can be set as a silicon nitride layer
  • the first dielectric layer 54 can also be set as a silicon nitride layer
  • the second dielectric layer 55 is also It can be provided as a silicon oxide layer.
  • the hierarchical structure of the array substrate is not limited to the above-mentioned hierarchical structure, and the levels can be increased or decreased as needed, and any one or more of the above-mentioned levels can also be selected as needed, and the arrangement order of the above-mentioned levels is not limited to the arrangement shown in FIG. 3 order.
  • the array substrate includes a fan-out area 50 on one side of the display area 10, and the wiring area is in the fan-out area 50.
  • the fan-out area 50 includes a first fan-out area 50a and a second fan-out area 50b disposed at intervals, and at least one of the bending area 20 and the pad area 30 is disposed in the first fan-out area 50a and the second fan-out area 50a. Out of area 50b.
  • the number of fan-out areas 50 may also be three, four, or five, and this embodiment does not specifically limit the number of fan-out areas 50. There are many ways to arrange the bending area 20 and the pad area 30.
  • the bending area 20 and the pad area 30 can both be arranged between the first fan-out area 50a and the second fan-out area 50b.
  • One of the bending area 20 and the pad area 30 is disposed between the first fan-out area 50a and the second fan-out area 50b.
  • the bending area 20 is provided between the first fan-out area 50a and the second fan-out area 50b. As shown in FIG. 2, in this embodiment, the bending area 20 is disposed between the first fan-out area 50a and the second fan-out area 50b, and the pad area 30 is disposed at the second fan-out area 50b away from the bending area 20. One side.
  • the first wiring sublayer 51 is provided in the same layer as the gate layer of the display area 10
  • the interlayer insulating layer 52 is provided in the same layer as the gate insulating layer of the display area 10. That is to say, the first wiring sublayer 51 and the gate layer are formed by the same patterning process, and the interlayer insulating layer 52 and the gate insulating layer are formed by the same patterning process, so as to reduce the masking process during the manufacturing process of the array substrate. Quantity.
  • the other film layers in the fan-out area are also arranged in the same layer as the corresponding film layers in the display area.
  • the dielectric layer in the fan-out area can be arranged in the same layer as the dielectric layer in the display area.
  • the manufacturing method of the array substrate provided in the first embodiment of the present disclosure includes:
  • S140 Perform a patterning process on the second metal layer to form a pattern including the second wiring sublayer 53;
  • FIG. 5 is a flow chart of the manufacturing method of the array substrate in the embodiment of the disclosure.
  • the step of forming the first metal layer in S100 it is usually necessary to provide a base substrate first so that the first metal The layer is formed in the non-display area of the base substrate.
  • the first metal layer may be formed on the base substrate by evaporation, sputtering or physical vapor deposition.
  • the processing method may be yellow light, etching, or a combination of yellow light and etching.
  • the interlayer insulating layer 52 is disposed above the first wiring sublayer 51 and covers the first wiring sublayer 51, and the interlayer insulating layer 52 is used to isolate the first wiring sublayer 51 from the second wiring
  • the sub-layer 53 prevents a short circuit between the two contacts.
  • the interlayer insulating layer 52 can be formed by evaporation, sputtering or chemical vapor deposition.
  • the second metal layer may be formed on the interlayer insulating layer 52 by evaporation, sputtering or physical vapor deposition.
  • the first metal layer may be formed in the display area 10 and the non-display area at the same time, wherein the first metal layer formed in the display area 10 is patterned to form a gate layer, and the first metal layer in the non-display area After the metal layer is patterned, the first wiring sub-layer 51 is formed.
  • the insulating sub-layer 61 can be made of silicon oxide or silicon nitride, the insulating sub-layer 61 can be provided as one or more layers, and the insulating sub-layer 61 covers the second wiring sub-layer 53 to separate the second wiring sub-layer 53.
  • the second wiring sublayer 53 and the upper wiring layer 56 are used to provide support for the upper wiring layer 56 at the same time.
  • the material of the insulating organic compensator 57 can be liquid organic glue, and the self-leveling principle of the liquid organic glue is used to fill the recess in the insulating sublayer 61.
  • the insulating organic compensator 57 can also cover the lining.
  • a third metal layer is formed on the insulating organic compensator 57, and the third metal layer is patterned.
  • the patterning method can be Yellow light, etching, or a combination of yellow light and etching, thereby forming the upper wiring layer 56.
  • the insulating organic compensator 57 can fill the recesses in the insulating sublayer 61, providing a flat support surface for subsequent formation of the third metal layer, and avoiding the formation of the third metal layer. Part of the metal entering the recess is difficult to remove, thereby avoiding the short-circuit phenomenon caused by the metal used to form the upper wiring layer 56 staying in the recess, reducing the adverse effects on the array substrate, and improving the display of the narrow-frame display effect.
  • the third metal layer is patterned, and the step of forming a pattern including the upper wiring layer 56 includes a yellowing step and an etching step, wherein the yellowing step includes the third metal layer Apply photoresist, expose and develop.
  • the etching step in this embodiment may be dry etching. Dry etching refers to an etching method in which plasma is generated by ionizing a specific gas, and the target is bombarded with plasma, so that the target generates target particles, and the target particles are separated from the target, thereby forming the required pattern.
  • the second embodiment of the present disclosure provides a display screen, which includes a chip 40 and the aforementioned array substrate. Further, the chip 40 and the bending area 20, the pad area 30 and the fan-out area 50 of the array substrate are located on the same side of the display area 10 of the array substrate, and the chip 40 is electrically connected to the display area 10. As shown in FIG. 2, the chip 40 is located on the side where the pad area 30 is located, and the chip 40 is electrically connected to the first wiring sublayer 51, the second wiring sublayer 53, and the upper wiring layer 56.
  • the display screen provided in this embodiment includes the array substrate provided in the first embodiment, and therefore has the advantage of the array substrate in the first embodiment, that is, it prevents the metal used to form the upper wiring layer 56 from entering the recess, thereby preventing The wiring in the upper wiring layer 56 is short-circuited, thereby improving the display effect of the display screen.
  • the display device using the narrow-frame display screen in this embodiment can be applied to different products, for example, it can be applied to products such as mobile phones, tablet computers, e-books, etc., which are not listed here.

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Abstract

一种阵列基板、其制备方法及显示屏，其中，阵列基板包括显示区（10）和位于显示区（10）一侧的走线区，走线区包括层叠的上层走线层（56）和下层走线层（60），上层走线层（56）和下层走线层（60）由绝缘层组间隔开，绝缘层组包括绝缘子层（61）和形成在绝缘子层上的绝缘有机补偿体（57），绝缘有机补偿体（57）用于补偿绝缘子层（61）上表面的至少部分凹陷。通过设置绝缘有机补偿体（57）来填充绝缘子层（61）中的凹陷，从而能够防止用于形成上层走线层（56）的金属进入到绝缘子层（61）的凹陷中，避免了因金属滞留在凹陷中而导致的短路现象，进而降低了对阵列基板的不良影响，提高了阵列基板的良品率以及显示屏的显示效果。

Description

阵列基板、其制备方法及显示屏 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、其制备方法及显示屏。
背景技术
随着显示技术的飞速发展，高屏占比的显示屏越来越受欢迎。目前较常用的一种显示屏是将扇出区(fan out area)、弯折区(bending area)、焊盘区(Pad area)和芯片设置在显示屏的同一侧，而其他三侧则不设置扇出区、弯折区或焊盘区，从而实现高屏占比。
在上述显示屏中，扇出区内存在多层走线，多层走线由绝缘层绝缘隔开，当绝缘层存在凹陷或缝隙等缺陷时，这些缺陷会影响显示屏的显示效果。
发明内容
本公开实施例提供一种阵列基板、其制备方法及显示屏，用以解决显示屏显示效果差的问题。
为了实现上述目的，一方面，本公开实施例提供了一种阵列基板，其包括显示区和位于所述显示区一侧的走线区，其中，
所述走线区包括层叠的上层走线层和下层走线层，所述上层走线层和所述下层走线层由绝缘层组间隔开，
所述绝缘层组包括绝缘子层和形成在所述绝缘子层上的绝缘有机补偿体，所述绝缘有机补偿体用于补偿所述绝缘子层上表面的至少部分凹陷。
与现有技术相比，本公开实施例提供的阵列基板具有如下优点：
本公开实施例提供的阵列基板中，通过在绝缘子层上设置绝缘有机补偿体，利用绝缘有机补偿体填充绝缘子层中的凹陷，从而能够防止用于形成上 层走线层的金属进入到绝缘子层的凹陷中，因此能够避免出现凹陷中的金属难以去除的问题，从而避免了因用于形成上层走线层的金属滞留在凹陷中而导致的短路现象，进而降低了对阵列基板的不良影响，提高了阵列基板的良品率以及窄边框显示屏的显示效果。
作为本公开实施例阵列基板的一种改进，所述绝缘有机补偿体为有机胶。
作为本公开实施例阵列基板的一种改进，所述有机胶为聚酰亚胺胶黏剂或丙烯酸双酯厌氧胶。
作为本公开实施例阵列基板的一种改进，所述绝缘有机补偿体覆盖所述绝缘子层。
作为本公开实施例阵列基板的一种改进，所述绝缘有机补偿体覆盖所述绝缘子层的整个上表面或者部分上表面。
作为本公开实施例阵列基板的一种改进，所述下层走线层包括第一走线子层、第二走线子层以及用于隔离开所述第一走线子层和所述第二走线子层的层间绝缘层。
作为本公开实施例阵列基板的一种改进，所述第一走线子层与所述显示区的栅极层同层设置，所述层间绝缘层与所述显示区的栅极绝缘层同层设置。
作为本公开实施例阵列基板的一种改进，所述层间绝缘层的部分区域与所述第二走线子层之间形成第一凹陷区，所述绝缘子层的上表面的部分区域形成第二凹陷区，所述绝缘有机补偿体包括填充于所述第二凹陷区的填充部。
作为本公开实施例阵列基板的一种改进，所述层间绝缘层覆盖所述第一走线子层，且对应所述第一走线子层的部分形成凸出体，所述凸出体与所述第二走线子层之间形成所述第一凹陷区；所述绝缘子层覆盖所述层间绝缘层、所述第一凹陷区和所述第二走线子层，所述绝缘子层对应所述第一凹陷区的部分形成所述第二凹陷区。
作为本公开实施例阵列基板的一种改进，所述绝缘子层还包括位于所述第二凹陷区周围的平坦区，所述绝缘有机补偿体还包括延伸至所述平坦区表面的平坦子层。
作为本公开实施例阵列基板的一种改进，所述绝缘子层包括层叠设置的第一电介质层和第二电介质层。
作为本公开实施例阵列基板的一种改进，所述绝缘子层为氧化硅层和氮 化硅层两层的叠层。
作为本公开实施例阵列基板的一种改进，所述阵列基板包括处于显示区一侧的扇出区，所述走线区处于所述扇出区内。
作为本公开实施例阵列基板的一种改进，所述扇出区的膜层与所述显示区的对应膜层同层设置。
另一方面，本公开实施例提供了一种显示屏，其包括芯片以及上述阵列基板。
本公开实施例提供的显示屏所具有的优点与上述阵列基板相对于现有技术所具有的优点相同，在此不再赘述。
再一方面，本公开实施例提供了一种制作阵列基板的方法，包括
形成第一金属层；
对所述第一金属层进行图案化处理，形成包括第一走线子层的图形；
在所述第一走线子层上形成覆盖所述第一走线子层的层间绝缘层；
在所述层间绝缘层上形成第二金属层；
对所述第二金属层进行图案化处理，形成包括第二走线子层的图形；
在所述第二走线子层上形成覆盖所述第二走线子层的绝缘子层；
利用自流平原理在所述绝缘子层上形成覆盖所述绝缘子层的绝缘有机补偿体；
在所述绝缘有机补偿体上形成第三金属层；
对所述第三金属层进行图案化处理，形成包括上层走线层的图形。
作为本公开实施例的制作阵列基板的方法的一种改进，所述第一金属层、第二金属层以蒸镀、溅射或物理气相沉积的方式形成。
作为本公开实施例的制作阵列基板的方法的一种改进，对所述第一金属层、第二金属层和第三金属层进行所述图案化处理的处理方式包括黄光、刻蚀或黄光与刻蚀相结合。
作为本公开实施例的制作阵列基板的方法的一种改进，所述绝缘有机补偿体通过液体凝固形成，形成在所述绝缘子层上表面的至少部分凹陷内以及所述凹陷周围的区域，或者只形成在所述凹陷内。
除了上面所描述的本公开实施例解决的技术问题、构成技术方案的技 术特征以及由这些技术方案的技术特征所带来的有益效果外，本公开实施例提供的阵列基板及显示屏所能够解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一部分实施例，这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为阵列基板的结构示意图；
图2为本公开实施例中阵列基板及芯片的结构示意图；
图3为图2中扇出区的剖视图；
图4为沿图3中A-A平面的俯视图；
图5为本公开实施例中阵列基板的制作方法的流程图。
具体实施方式
为了解决显示屏显示效果差的问题，本公开实施例提供了一种阵列基板、其制备方法及显示屏，其中阵列基板包括显示区和位于显示区一侧的走线区，走线区包括层叠的上层走线层和下层走线层，上层走线层和下层走线层由绝缘层组间隔开，绝缘层组包括绝缘子层和形成在绝缘子层上的绝缘有机补偿体，绝缘有机补偿体用于补偿绝缘子层上表面的至少部分凹陷。本公开实施例通过在绝缘子层上设置绝缘有机补偿体，利用绝缘有机补偿体填充绝缘子层中的凹陷区域，从而能够防止用于形成上层走线层的金属进入到绝缘子层的凹陷区域中，因此能够避免出现凹陷区域中的金属难以去除的问题，从而 避免了因用于形成上层走线层的金属滞留在凹陷中而导致的短路现象，进而降低了对阵列基板的不良影响，提高了阵列基板的良品率以及窄边框显示屏的显示效果。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本公开保护的范围。
实施例一
请参阅图2-图4，本公开实施例一提供了一种阵列基板，该阵列基板包括显示区10和位于显示区10一侧的走线区，走线区包括层叠的上层走线层56和下层走线层60，上层走线层56和下层走线层60由绝缘层组间隔开，绝缘层组包括绝缘子层61和形成在绝缘子层61上的绝缘有机补偿体57，绝缘有机补偿体57用于补偿绝缘子层61上表面的至少部分凹陷。
上层走线层56形成在绝缘层组的上方，当绝缘层组的上表面存在凹陷或缝隙等缺陷时，会影响显示屏的显示效果。在本实施例中，绝缘层组包括绝缘子层61和绝缘有机补偿体57，其中，绝缘有机补偿体57位于上层走线层56与绝缘子层61之间。当绝缘子层61的上表面存在凹陷时，绝缘有机补偿体57能够补偿所述凹陷，从而为上层走线层56提供平坦的形成表面，降低或避免对显示效果的影响。
绝缘子层61的上表面的凹陷的形成原因有多种，例如，在通过化学气相沉积(CVD)工艺形成绝缘子层时，由于位于绝缘子层61下方的基底平整度差，导致绝缘子层61上表面不平整；又如，由于沉积工艺存在误差，导致绝缘子层61上表面出现缝隙或凹陷。本实施例以由于绝缘子层61下方的基底平整度差而造成绝缘子层61上表面不平整的情况为例进行描述。
如图1所示的阵列基板，该阵列基板包括依次层叠设置的下层走线层60、绝缘子层61和上层走线层56。在显示屏尤其是窄边框的显示屏中，下层 走线层60包括多层走线层，由于多层走线层之间的间距L较小，且通常该间距L小于或等于1μm，而且各走线层的厚度不同，因此各走线层之间存在明显的缝隙。当通过化学气相沉积工艺在下层走线层60的上方形成绝缘子层61时，绝缘子层61对应于上述缝隙的部位形成凹陷；当在绝缘子层61上方通过物理气相沉积(PCD)工艺形成金属层时，金属粉末会进入到凹陷中，当对金属层进行刻蚀形成上层走线层56时，凹陷中的金属难以刻蚀或去除，导致金属残留在凹陷中，造成由金属层刻蚀而成的上层走线层56的走线之间容易短路。
本实施例中通过在绝缘子层61的上方设置绝缘有机补偿体57补偿凹陷，从而防止上层走线层56的走线在上述凹陷内发生短路。图3为本实施例中扇出区50对应的阵列基板的结构示意图，如图3所示，走线区包括依次层叠设置的上层走线层56和下层走线层60，绝缘层组包括位于上层走线层56与下层走线层60之间的、依次层叠设置的绝缘有机补偿体57和绝缘子层61。具体地，绝缘子层61包括多层电介质层，例如电介质层可以为两层，如图3所示，绝缘子层61包括层叠设置的第一电介质层54和第二电介质层55。
在本实施例中，绝缘有机补偿体57用于补偿绝缘子层61上表面的至少部分凹陷。具体地，绝缘有机补偿体57可以形成在上述凹陷内以及上述凹陷周围的区域，也可以只形成在上述凹陷内，绝缘有机补偿体57可以为液体凝固形成，例如可以设置为胶体，利用自流平原理对凹陷进行填充，从而为上层走线层56提供平坦的表面。
此外，阵列基板还包括弯折区20、焊盘区30和扇出区50，走线区可以设置在扇出区50内。以图2所示的阵列基板所在方位为例，本实施例中弯折区20、焊盘区30和扇出区50位于显示区10的下侧，本实施例中扇出区50的数量可以为多个，本实施例不对扇出区50的数量做具体限定。
综上所述，本公开实施例提供的阵列基板通过在绝缘子层61上设置绝缘有机补偿体57，绝缘有机补偿体57能够填充绝缘子层61上表面的凹陷，从而防止了上层走线层56的金属进入到绝缘子层61的凹陷中，因此能够避免 出现凹陷中的金属难以去除的问题，从而避免了上层走线层56由于金属滞留在凹陷中而导致的短路现象，进而降低了对阵列基板的不良影响，提高了阵列基板的良品率以及窄边框显示屏的显示效果。
在一种可能的实现方式中，绝缘有机补偿体57为有机胶。具体地，当绝缘有机补偿体57设置为有机胶时，有机胶在流动过程中能够填充绝缘子层61中的凹陷，避免了后续用于形成上层走线层56的金属渗入凹陷后导致的残留。进一步地，有机胶可以为聚酰亚胺胶黏剂，也可以为丙烯酸双酯厌氧胶。
在一种可能的实现方式中，绝缘有机补偿体57覆盖绝缘子层61。在本实施例中，绝缘有机补偿体57可以覆盖在绝缘子层61的整个上表面上，也可以覆盖在绝缘子层61的部分上表面上。
进一步地，如图3所示，下层走线层60包括第一走线子层51、第二走线子层53以及用于隔离开第一走线子层51和第二走线子层53的层间绝缘层52开，层间绝缘层52的部分区域与第二走线子层53之间形成第一凹陷区58，绝缘子层61的上表面的部分区域形成第二凹陷区59，绝缘有机补偿体57包括填充于第二凹陷区59的填充部。
本实施例中，第一走线子层51内的第一走线数量有多个，多个第一走线排布在阵列基板上，例如等间隔且相互平行排列在阵列基板上。第一走线子层51的上方设置有层间绝缘层52，层间绝缘层52的上方设置有第二走线子层53，本实施例中层间绝缘层52用于将第一走线子层51和第二走线子层53隔开，防止第一走线子层51和第二走线子层53接触导致短路。由于第一走线子层51与第二走线子层53之间存在间隙，因此层间绝缘层52与第二走线子层53之间形成第一凹陷区58。
第二走线子层53内的第二走线数量有多个，多个第二走线排布在层间绝缘层52上，例如等间隔且相互平行排列在层间绝缘层52上。绝缘子层61形成在第二走线子层53和层间绝缘层52的上方，因此，绝缘子层61在对应上述第一凹陷区58的部位的上表面形成第二凹陷区59，绝缘有机补偿体57包括位于第二凹陷区59内的填充部，用于补偿第二凹陷区59。
如图3和图4所示，层间绝缘层52覆盖第一走线子层51，且对应第一走线子层51的部分形成凸出体，凸出体与第二走线子层53之间形成第一凹 陷区58；绝缘子层61覆盖层间绝缘层52、第一凹陷区58和第二走线子层53，绝缘子层61对应第一凹陷区58的部分形成第二凹陷区59。在上述实施方式的基础上，绝缘子层61还包括位于第二凹陷区59周围的平坦区，绝缘有机补偿体57还包括延伸至平坦区表面的平坦子层571。在本实施方式中，绝缘有机补偿体57不仅包括填充在第二凹陷区59内的填充部，还包括覆盖在绝缘子层61上方的平坦子层571。这样的设置方式便于利用自流平原理制作绝缘有机补偿体57，更准确地填充第二凹陷区59。
在一种可能的实现方式中，绝缘子层61为氧化硅层和氮化硅层两层的叠层。例如，绝缘子层61可以为一层或多层电介质层，具体地，包括第一电介质层54和第二电介质层55，其中，第一电介质层54为氧化硅层，第二电介质层55为氮化硅层。具体地，如图3所示，本实施例中的电介质层设置有两层，第一电介质层54设置在第二走线子层53的上方，第二电介质层55设置在第一电介质层54的上方，第一电介质层54可以设置为氧化硅层，第二电介质层55可以设置为氮化硅层，此外，第一电介质层54也可以设置为氮化硅层，第二电介质层55也可以设置为氧化硅层。
阵列基板的层级结构不限于上述层级结构，还可以根据需要增加、减少层级，也可以根据需要选择上述层级中的任意一层或多层，且上述层级的排列顺序不限于图3所示的排列顺序。
在一种可能的实现方式中，阵列基板包括处于显示区10一侧的扇出区50，走线区处于扇出区50内。具体地，扇出区50包括间隔设置的第一扇出区50a和第二扇出区50b，弯折区20和焊盘区30中的至少一个设置在第一扇出区50a和第二扇出区50b之间。扇出区50的数量还可以为三个、四个或五个，本实施例不对扇出区50的数量做具体限定。弯折区20和焊盘区30的排列顺序有多种方式，例如，弯折区20和焊盘区30可以都设置在第一扇出区50a和第二扇出区50b之间，又如，弯折区20和焊盘区30中的一个设置在第一扇出区50a和第二扇出区50b之间。
进一步地，在上述实施方式的基础上，弯折区20设置在第一扇出区50a和第二扇出区50b之间。如图2所示，本实施例中弯折区20设置在第一扇出区50a和第二扇出区50b之间，焊盘区30设置在第二扇出区50b背离弯折区 20的一侧。
在一种可能的实现方式中，第一走线子层51与显示区10的栅极层同层设置，层间绝缘层52与显示区10的栅极绝缘层同层设置。也就是说，第一走线子层51和栅极层由同一次构图工艺形成，层间绝缘层52与栅极绝缘层由同一次构图工艺形成，以减少阵列基板制作过程中掩膜板的数量。扇出区的其他膜层也与显示区的对应膜层同层设置，例如，扇出区的电介质层可与显示区的电介质层同层设置。
请参阅图5，本公开实施例一提供的阵列基板的制作方法包括：
S100：形成第一金属层；
S110：对第一金属层进行图案化处理，形成包括第一走线子层51的图形；
S120：在第一走线子层51上形成覆盖第一走线子层51的层间绝缘层52；
S130：在层间绝缘层52上形成第二金属层；
S140：对第二金属层进行图案化处理，形成包括第二走线子层53的图形；
S150：在第二走线子层53上形成覆盖第二走线子层53的绝缘子层61；
S160：利用自流平原理在绝缘子层61上形成覆盖绝缘子层61的绝缘有机补偿体57；
S170：在绝缘有机补偿体57上形成第三金属层；
S180：对第三金属层进行图案化处理，形成包括上层走线层56的图形。
具体地，图5为本公开实施例中阵列基板的制作方法的流程图，如图5所示，在S100形成第一金属层的步骤中，通常需要先提供一衬底基板，使第一金属层形成在衬底基板的非显示区，具体地，第一金属层可以以蒸镀、溅射或物理气相沉积的方式形成在衬底基板上。在S110和S140中，对第一金属层和第二金属层进行图案化处理时，处理方式可以为黄光、刻蚀或黄光与刻蚀相结合。在S120中，层间绝缘层52设置在第一走线子层51上方并将第一走线子层51覆盖，层间绝缘层52用于隔绝第一走线子层51与第二走线子层53，防止两者接触发生短路，层间绝缘层52的形成方式可以为蒸镀、溅射或化学气相沉积。在S130中，第二金属层可以以蒸镀、溅射或物理气相沉积的方式形成在层间绝缘层52上。
在一种实现方式中，所述第一金属层可以同时形成在显示区10与非显示区，其中形成在显示区10的第一金属层图案化之后形成栅极层，非显示区的第一金属层图形化之后形成第一走线子层51。
在S150中，绝缘子层61可以采用氧化硅或氮化硅制成，绝缘子层61可以设置为一层或多层，绝缘子层61覆盖在第二走线子层53的上方，用于隔开第二走线子层53与上层走线层56，同时用于为上层走线层56提供支撑。在S160中，绝缘有机补偿体57的材料可以采用液态有机胶，通过液态有机胶的自流平原理，使其填充到绝缘子层61中的凹陷内，此外，绝缘有机补偿体57还可以覆盖在衬底基板的显示区10。在S170-S180中，待绝缘有机补偿体57凝固后，在绝缘有机补偿体57的上方形成第三金属层，并对第三金属层进行图案化处理，同样的，图案化处理的方式可以为黄光、刻蚀或黄光与刻蚀相结合，从而形成上层走线层56。
本实施例提供的阵列基板的制作方法中，绝缘有机补偿体57能够填充绝缘子层61中的凹陷，为后续第三金属层的形成提供了平整的支撑面，避免了在形成第三金属层时部分金属进入凹陷内难以去除，从而避免了因用于形成上层走线层56的金属滞留在凹陷中而导致的短路现象，降低了对阵列基板的不良影响，进而提高了窄边框显示屏的显示效果。
在一种可能的实现方式中，对第三金属层进行图案化处理，形成包括上层走线层56的图形的步骤包括黄光步骤和刻蚀步骤，其中，黄光步骤包括对第三金属层进行涂光刻胶、曝光和显影。本实施例中刻蚀步骤可以为干法刻蚀。干法刻蚀是指通过电离特定气体产生等离子体，用等离子体轰击靶材，使靶材产生靶材粒子，靶材粒子脱离靶材，从而形成所需要的图案的一种刻蚀方式。
实施例二
本公开实施例二提供了一种显示屏，其包括芯片40以及上述阵列基板。进一步地，芯片40与阵列基板的弯折区20、焊盘区30和扇出区50位于阵列基板的显示区10的同一侧，芯片40与显示区10电连接。如图2所示，芯片40位于焊盘区30所在的一侧，且芯片40与第一走线子层51、第二走线 子层53和上层走线层56电连接。
本实施例提供的显示屏包含实施例一所提供的阵列基板，因此具有实施例一中阵列基板所具有的优点，即避免了用于形成上层走线层56的金属进入到凹陷中，从而防止上层走线层56中的走线短路，进而提高了显示屏的显示效果。应用有本实施例中的窄边框显示屏的显示装置可以应用于不同的产品中，例如可以应用在手机、平板电脑、电子书等产品中，在此不一一列举说明。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同或相似部分相互参见即可。
在本说明书中，各实施例中描述的具体特征、结构或者材料可以以合适的方式相互结合。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。

Claims (20)

  1. 一种阵列基板，包括：
    显示区；和
    位于所述显示区一侧的走线区，其中，所述走线区包括层叠的上层走线层和下层走线层，所述上层走线层和所述下层走线层由绝缘层组间隔开，所述绝缘层组包括绝缘子层和形成在所述绝缘子层上的绝缘有机补偿体，所述绝缘有机补偿体用于补偿所述绝缘子层上表面的至少部分凹陷。
  2. 根据权利要求1所述的阵列基板，其中，所述绝缘有机补偿体为有机胶。
  3. 根据权利要求2所述的阵列基板，其中，所述有机胶为聚酰亚胺胶黏剂或丙烯酸双酯厌氧胶。
  4. 根据权利要求1所述的阵列基板，其中，所述绝缘有机补偿体覆盖所述绝缘子层。
  5. 根据权利要求4所述的阵列基板，其中，所述绝缘有机补偿体覆盖所述绝缘子层的整个上表面或者部分上表面。
  6. 根据权利要求4所述的阵列基板，其中，所述下层走线层包括第一走线子层、第二走线子层以及用于隔离开所述第一走线子层和所述第二走线子层的层间绝缘层。
  7. 根据权利要求6所述的阵列基板，其中，所述第一走线子层与所述显示区的栅极层同层设置，所述层间绝缘层与所述显示区的栅极绝缘层同层设置。
  8. 根据权利要求6所述的阵列基板，其中，所述层间绝缘层的部分区域与所述第二走线子层之间形成第一凹陷区，所述绝缘子层的上表面的部分区域形成第二凹陷区，所述绝缘有机补偿体包括填充于所述第二凹陷区的填充部。
  9. 根据权利要求8所述的阵列基板，其中，所述层间绝缘层覆盖所述第一走线子层，且对应所述第一走线子层的部分形成凸出体，所述凸出体与所述第二走线子层之间形成所述第一凹陷区。
  10. 根据权利要求8所述的阵列基板，其中，所述绝缘子层覆盖所述层间绝缘层、所述第一凹陷区和所述第二走线子层，所述绝缘子层对应所述第 一凹陷区的部分形成所述第二凹陷区。
  11. 根据权利要求9所述的阵列基板，其中，所述绝缘子层还包括位于所述第二凹陷区周围的平坦区，所述绝缘有机补偿体还包括延伸至所述平坦区表面的平坦子层。
  12. 根据权利要求1所述的阵列基板，其中，所述绝缘子层包括层叠设置的第一电介质层和第二电介质层。
  13. 根据权利要求11所述的阵列基板，其中，所述绝缘子层为氧化硅层和氮化硅层两层的叠层。
  14. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括处于显示区一侧的扇出区，所述走线区处于所述扇出区内。
  15. 根据权利要求14所述的阵列基板，其中所述扇出区的膜层与所述显示区的对应膜层同层设置。
  16. 一种显示屏，包括芯片以及权利要求1-15中任一项所述的阵列基板。
  17. 一种制备阵列基板的方法，包括
    形成第一金属层；
    对所述第一金属层进行图案化处理，形成包括第一走线子层的图形；
    在所述第一走线子层上形成覆盖所述第一走线子层的层间绝缘层；
    在所述层间绝缘层上形成第二金属层；
    对所述第二金属层进行图案化处理，形成包括第二走线子层的图形；
    在所述第二走线子层上形成覆盖所述第二走线子层的绝缘子层；
    利用自流平原理在所述绝缘子层上形成覆盖所述绝缘子层的绝缘有机补偿体；
    在所述绝缘有机补偿体上形成第三金属层；
    对所述第三金属层进行图案化处理，形成包括上层走线层的图形。
  18. 根据权利要求17所述的方法，其中，所述第一金属层、第二金属层以蒸镀、溅射或物理气相沉积的方式形成。
  19. 根据权利要求17所述的方法，其中，对所述第一金属层、第二金属层和第三金属层进行所述图案化处理的处理方式包括黄光、刻蚀或黄光与刻蚀相结合。
  20. 根据权利要求17所述的方法，其中，所述绝缘有机补偿体通过液体 凝固形成，形成在所述绝缘子层上表面的至少部分凹陷内以及所述凹陷周围的区域，或者只形成在所述凹陷内。
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