WO2020155588A1 - 掩膜条、阵列基板、显示屏及显示装置 - Google Patents

掩膜条、阵列基板、显示屏及显示装置 Download PDF

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Publication number
WO2020155588A1
WO2020155588A1 PCT/CN2019/098343 CN2019098343W WO2020155588A1 WO 2020155588 A1 WO2020155588 A1 WO 2020155588A1 CN 2019098343 W CN2019098343 W CN 2019098343W WO 2020155588 A1 WO2020155588 A1 WO 2020155588A1
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WO
WIPO (PCT)
Prior art keywords
mask
area
opening
electrode layer
layer
Prior art date
Application number
PCT/CN2019/098343
Other languages
English (en)
French (fr)
Inventor
刘明星
刘如胜
张兵
韩冰
赵莹
甘帅燕
高峰
Original Assignee
昆山国显光电有限公司
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Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2020155588A1 publication Critical patent/WO2020155588A1/zh
Priority to US17/152,995 priority Critical patent/US20210141304A1/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/0021—Reactive sputtering or evaporation
    • C23C14/0036—Reactive sputtering
    • C23C14/0042—Controlling partial pressure or flow rate of reactive or inert gases with feedback of measurements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80523—Multilayers, e.g. opaque multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80524—Transparent cathodes, e.g. comprising thin metal layers

Definitions

  • This application relates to the field of display, and in particular to a mask strip, an array substrate, a display screen and a display device.
  • Display terminals such as mobile phones and tablet computers need to integrate front cameras, earpieces, and infrared sensing elements. Therefore, you can set up front cameras, earpieces, and infrared sensing elements by slotting on the display terminal of the display terminal.
  • the slotted area of the display screen of Liu Haiping cannot be used to display the picture, or the camera can be set by opening a hole on the screen.
  • external light can enter the photosensitive element located below the screen through the opening on the screen, causing poor imaging effects. As such, the display screen of this display terminal is not a full screen.
  • the present application provides a mask strip, an array substrate, a display screen and a display device.
  • the first aspect of the present application provides a mask strip for the production of a light-emitting structure layer on an array substrate.
  • the mask strip includes a plurality of sub-mask plates, and the sub-mask plates include a first mask area and The second mask area, the first mask area has a first mask opening, the second mask area has a second mask opening, the density of the second mask opening is less than that of the first mask opening Density, and the size of at least part of the second mask opening is larger than the size of the first mask opening.
  • a second aspect of the present application provides an array substrate.
  • the array substrate includes a substrate, a first OLED area and a second OLED area.
  • the first OLED area includes: a first electrode layer formed on the substrate; a first light-emitting structure layer formed on the first electrode layer; a first pixel opening, the first light-emitting structure layer at least partially Arranged in the first pixel opening; a second electrode layer formed on the first light-emitting structure layer.
  • the second OLED area is an area of the array substrate excluding the first OLED area, and the second OLED area includes: a third electrode layer formed on the substrate; and a third electrode layer formed on the third electrode layer
  • the second light-emitting structure layer; the second pixel opening, the second light-emitting structure layer is partially disposed in the second pixel opening; the fourth electrode layer formed on the second light-emitting structure layer.
  • the pixel density of the first OLED area is greater than the pixel density of the second OLED area, and the first light-emitting structure layer and the second light-emitting structure layer are formed in the same process using the mask strips described above.
  • a third aspect of the present application provides a display screen, which includes the above-mentioned array substrate and a packaging structure covering the surface of the array substrate.
  • a fourth aspect of the present application provides a display device.
  • the display device includes a device body and the aforementioned display screen.
  • the device body has a device area; the display screen covers the device body; wherein the device area It is located below the second OLED area, and the device area is provided with a photosensitive device that collects light through the second OLED area.
  • Fig. 1 is a schematic top view of a sub-mask of a mask strip
  • FIG. 2 is a schematic top view of an embodiment of the mask strip of the present application.
  • FIG. 3 is a schematic top view of an embodiment of the sub-mask of the application.
  • FIG. 5 is a schematic top view of still another embodiment of the sub-mask of this application.
  • FIG. 6 is a schematic top view of still another embodiment of the sub-mask of this application.
  • FIG. 7 is a schematic top view of still another embodiment of the sub-mask of this application.
  • FIG. 8 is a schematic top view of still another embodiment of the sub-mask of this application.
  • FIG. 9 is a schematic top view of an embodiment of the second mask area of the sub-mask plate of this application.
  • FIG. 10 is a schematic cross-sectional view of an embodiment of the array substrate of this application.
  • FIG. 11 is a schematic top view of an embodiment of the first mask opening and the second mask opening of the application.
  • FIG. 12 is a schematic top view of another embodiment of the first mask opening and the second mask opening of the application.
  • FIG. 13 is a schematic top view of an embodiment of the third electrode layer of this application.
  • FIG. 14 is a schematic top view of still another embodiment of the first mask opening and the second mask opening of this application;
  • FIG. 15 is a schematic top view of still another embodiment of the first pixel opening and the first mask opening of this application;
  • 16 is a schematic top view of still another embodiment of the second pixel opening and the second mask opening of this application;
  • FIG. 17 is a schematic cross-sectional view of an embodiment of the display screen of this application.
  • FIG. 18 is a schematic front view of an embodiment of the display device of this application.
  • this application sets the display area corresponding to the photosensitive device as a transparent display area with low pixel density, so that the photosensitive device collects light through the transparent display area, while the normal display area outside the transparent display area remains the original pixel density.
  • the pixel density can be reduced by reducing the light-emitting structure of the display area corresponding to the photosensitive device, thereby obtaining a transparent display area with low pixel density.
  • the density of the second mask opening 21 of the second mask area 2 of the sub-mask of the mask strip corresponding to the transparent display area can be reduced, while the first mask opening 21 of the sub-mask corresponding to the normal display area can be reduced.
  • the density of the first mask opening 11 in the mask area 1 remains unchanged, and the density of the first mask opening (or second mask opening) can be understood as the first mask opening (or second mask opening) per unit area.
  • the number of membrane openings due to the difference of the opening density, when the mask stripe is opened, the stress on the boundary area between the first mask area 1 and the second mask area 2 of each sub-mask is not uniform, which is easy to be in this area. Wrinkles are formed, causing a high risk of color mixing at the junction of the normal display area and the transparent display area of the display screen.
  • the above-mentioned mask strip includes a plurality of sub-mask plates, and the plurality of sub-mask plates are connected to each other to form the entire mask strip.
  • this embodiment provides a mask strip, which is used for the production of a light-emitting structure layer on an array substrate.
  • the mask strip includes a plurality of sub-masks, and each sub-mask includes a first mask. Area and a second mask area, the first mask area has a first mask opening, the second mask area has a second mask opening, the density of the second mask opening is smaller than that of the first mask The density of the openings, and the size of at least part of the second mask openings is larger than the size of the first mask openings.
  • the density of the first mask openings in the first mask area is higher, and the density of the second mask openings in the second mask area is lower. If the size of the first mask opening is equal to the size of the second mask opening, Then the strength of the second mask area is greater. In this application, the size of at least part of the second mask opening is larger than the size of the first mask opening, thereby reducing the strength of the second mask area, making the second mask area The strength of is close to or equal to the strength of the first mask area.
  • the boundary area between the first mask area and the second mask area of the sub-mask is uniformly stressed, so the boundary area is not easy to produce wrinkles. Therefore, the risk of color mixing in the boundary area between the transparent display area and the normal display area of the display screen is reduced or eliminated.
  • the embodiment of the application provides a mask strip, which is used to fabricate a light-emitting structure layer of an array substrate.
  • the array substrate includes a substrate 3 and a first OLED area A and a second OLED area B located on the substrate.
  • the first OLED area A is a non-transparent display area. (Alternatively referred to as a normal display area), the second OLED area B is a transparent display area.
  • the mask strip includes a plurality of sub-mask plates 10, and the plurality of sub-mask plates 10 are connected to each other to form the entire mask strip.
  • the sub-mask 10 includes a first mask area 1a, a second mask area 2a, and a non-maskable functional area 9a.
  • the non-maskable functional area 9a serves as a connection area between the two sub-masks.
  • the area corresponding to the display screen is a non-display area, and is not used to make a light-emitting structure in the evaporation process.
  • the first mask area 1a is used to make a first light emitting structure layer in the first OLED area
  • the second mask area 2a is used to make a second light emitting structure layer in the second OLED area.
  • the first mask area 1a completely surrounds the second mask area 2a. In other embodiments, the first mask area may also partially surround the second mask area.
  • the first mask area 1a includes a plurality of first mask openings 11a
  • the second mask area 2a includes a plurality of second mask openings 21a.
  • Both the film opening 11a and the second mask opening 21a are circular, and the size of the second mask opening 21a is larger than the size of the first mask opening 11a.
  • the size here can refer to the radius or area of the circle.
  • the first mask opening and the second mask opening may have other shapes such as a square or a triangle, and the size may refer to an area or a side length.
  • the intensity of the second mask area 2a is reduced to be close to or equal to the intensity of the first mask area 1a, avoiding the The boundary area between the first mask area 1a and the second mask area 2a receives uneven force, thereby reducing or eliminating the risk of color mixing between the first OLED area and the second OLED area.
  • the arrangement rules of the second mask openings and the first mask openings are the same.
  • the arrangement rules of the second mask openings 21a and the first mask openings 11a shown in FIG. It is understood that the arrangement is the same, for example, they are all arranged in a straight line, or all arranged in the shape of " ⁇ ". In other embodiments, the arrangement rules of the second mask opening and the first mask opening may also be different.
  • the relationship between the size of the second mask opening 21a and the size of the first mask opening 11a can be adaptively adjusted by the difference in pixel density between the first OLED area and the second OLED area, so that the second mask area 2a
  • the intensity of is close to or equal to the intensity of the first mask area 1a.
  • the first mask opening 11b of the first mask area 1b of the sub-mask and the second mask opening 21b of the second mask area 2b are both rectangular, and the sub-mask
  • the first mask opening 11b of the first mask area 1b of the sub-mask and the second mask opening 21b of the second mask area 2b are both rectangular, and the sub-mask
  • the other structure of the membrane plate is the same as the embodiment shown in FIG. 3.
  • the structure of the first mask area 1c is the same as the structure of the first mask area 1a of the previous embodiment, and the second mask area 2c includes the central area of the second mask area 2c. At least two opening regions arranged in the outer region, and among the two adjacent opening regions, the size of the second mask opening near the opening region of the central region is smaller than that of the second mask opening region far from the central region. The size of the membrane opening. The open area away from the central area at least partially surrounds the open area close to the central area.
  • the second mask area 2c includes adjacent first opening areas 201c and second opening areas 202c.
  • the size of the second mask opening 211c of the first opening area 201c close to the central area is smaller than that of the area away from the central area.
  • the second mask area 2c further includes a third opening area 203c, the third opening area 203c is farther from the central area than the second opening area 202c, and the second mask area of the second opening area 202c
  • the size of the film opening 212c is smaller than the size of the third mask opening 213c of the third opening area 203c.
  • the first mask area 11c surrounds the third opening area 203c
  • the third opening area 203c surrounds the second opening area 202c
  • the second opening area 202c surrounds the first opening area 201c.
  • the second mask opening 211c of the first opening area 201c located in the central area of the second mask area 2c is equal to the size of the first mask opening 11c.
  • the size of the second mask opening in the opening area in the central area of the second mask area is larger than the size of the first mask opening.
  • the third opening area 203c, the second opening area 202c, and the The strength of an open area 201c decreases sequentially.
  • the strength of the first mask area 1c is approximately equal to the strength of the third opening area 203c
  • the strength of the third opening area 203c is slightly less than the strength of the second opening area 202c
  • the strength of the second opening area 202c is slightly less than that of the first opening area 201c.
  • the difference in intensity between two adjacent areas is small, so in each area of the sub-mask
  • the stress distribution is relatively uniform in the boundary area of the mask, and the color mixing phenomenon is not easy to occur between the areas of the array substrate generated by the mask strips and corresponding to the areas of the sub-mask.
  • the structure of the sub-mask shown in FIG. 6 is roughly the same as the structure of the sub-mask shown in FIG. 5, and the mask opening and the second mask area of the sub-mask shown in FIG. 5 are both circular.
  • the first mask area 1d and the second mask area 2d of the sub-mask shown in FIG. 6 are square, the first mask opening and the second mask opening are also square, and the second mask area 2d includes
  • the central area includes a first opening area 201d, a second opening area 202d, and a third opening area 203d arranged outward in sequence.
  • the shapes of the first mask area, the second mask area, the first mask opening, and the second mask opening can be changed according to actual needs, and the first mask opening and the second mask opening
  • the shape of the openings can be the same or different.
  • the first mask opening and the second mask opening are both square, or the first mask opening is square, and the second mask opening is round, oval, or dumbbell. Shape or gourd shape and other shapes.
  • the sub-mask includes a first mask area 1e, a second mask area 2e, and a non-maskable functional area 9e.
  • the second mask area 2e is located in the first mask area. Between 1e and non-masked functional area 9e.
  • the non-mask functional area 9e is provided with multiple through holes 91e.
  • the multiple through holes 91e have the same size, and the size of the through holes 91e is smaller than that of the second mask opening 21e of the second mask area 2e.
  • the size is larger than the size of the first mask opening 11e of the first mask area 1e.
  • the non-mask functional area 9f is provided with a through hole 91f.
  • the through hole 91f includes a first through hole 911f, a second through hole 912f, and a third through hole 913f arranged in a direction away from the second mask area 2f, and the first through hole
  • the sizes of 911f, the second through hole 912f, and the third through hole 913f are sequentially reduced.
  • the strength of the non-masked functional area gradually increases from a size close to the strength of the second mask area, thereby further ensuring the strength of each area of the entire sub-mask.
  • the distribution tends to be uniform, so that the entire sub-mask is uniformly stressed during the process of mask striping, and the risk of color mixing of the array substrate caused by the wrinkles of the factor mask is avoided.
  • the through hole shown in FIG. 7 or FIG. 8 can also be replaced by a recess, which can be understood as retaining a part of the material in the through hole, and the structure is similar to a blind hole.
  • recesses can also be used to replace part of the through holes.
  • the through hole or recess is round, oval, dumbbell, gourd or square, and the shape of the through hole or recess may be the same as the shape of the second mask opening, or it may be the same as that of the second mask.
  • the shape of the membrane opening is different.
  • the second mask area 2g is provided with a plurality of second mask openings 21g and a plurality of mask recesses 22g.
  • each of the mask recesses 22g is located between the adjacent second mask openings 21g, and the structure of the mask recesses 22g is similar to the recessed structure in the foregoing embodiment.
  • the strength of the second mask area 2g is close to or equal to the strength of the first mask area, which is beneficial to alleviate the internal stress of the sub-mask, thereby
  • the risk of color mixing between the first OLED area and the second OLED area of the array substrate is reduced, and the uneven force of the mask is also prevented from affecting the position accuracy of the second mask opening 21g.
  • the size of the mask recess 22g and the second mask opening 21g are the same, which is beneficial to simplify the manufacturing process of the sub-mask plate, and is also beneficial to uniform stress distribution in the second mask area 2g.
  • the second OLED area B (refer to FIG. 10) of the array substrate includes a plurality of pixel units, each pixel unit includes n sub-pixels, and the second mask area 2g includes configuration
  • n is equal to 3
  • the number of mask recesses in each second mask sub-region is two.
  • the n sub-pixels may be n sub-pixels with different colors. In other implementations, some of the n sub-pixels have the same color.
  • the distance between adjacent mask recesses 22g and second mask opening 21g is equal to the distance between two adjacent first mask openings, so that the strength of the second mask area 2g is closer to the first mask opening. The intensity of the mask area, thereby reducing the risk of color mixing.
  • the present application also provides an array substrate 100.
  • the array substrate includes a substrate 3 and a first OLED area A and a second OLED area B located on the substrate 3.
  • the first OLED area A is a non-transparent display area (or called a normal display area), and the second OLED area B is a transparent display area.
  • the first OLED area A may have a shape such as a circle, a square
  • the second OLED area B may have a shape such as a circle, a square, a drop shape, a bangs, etc.
  • the first OLED area A surrounds the second OLED area B.
  • the first OLED area partially surrounds the second OLED area.
  • the substrate 3 may include a substrate, a driving circuit layer (such as a thin film transistor), an organic layer, an inorganic layer, and other structures.
  • the portion of the substrate corresponding to the second OLED area B may not be provided with a driving circuit layer, but may be provided with other film layers or non- Wire the display area.
  • the first OLED area A includes a first electrode layer 4 formed on the substrate 3, a first light emitting structure layer 61 formed on the first electrode layer 4, and a second electrode formed on the first light emitting structure layer 61 Layer 7, the second OLED area B includes a third electrode layer 5 formed on the substrate 3, a second light emitting structure layer 62 formed on the third electrode layer 5, and a second light emitting structure layer 62 formed on the second light emitting structure layer 62
  • the four-electrode layer 8, the first light-emitting structure layer 61 and the second light-emitting structure layer 62 are formed in the same process using the sub-mask.
  • the substrate 3 may be a rigid substrate, such as a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate.
  • the substrate 3 may be a flexible substrate, such as a flexible PI substrate or the like.
  • the material of each conductive trace of the second OLED area may include a transparent material, and the third The light transmittance of the electrode layer and the fourth electrode layer is greater than 40%, further, the light transmittance of both is greater than 60%, and furthermore, the light transmittance of both is not less than 80%.
  • the material of the third electrode layer and the fourth electrode layer may include a transparent conductive metal oxide or a magnesium-silver mixture.
  • the material of the third electrode layer and the fourth electrode layer may include at least one of ITO (indium tin oxide), indium zinc oxide (IZ), silver-doped indium tin oxide, and silver-doped indium zinc oxide.
  • ITO indium tin oxide
  • IZ indium zinc oxide
  • the first electrode layer 4 and the third electrode layer 5 are anodes
  • the second electrode layer 7 and the fourth electrode layer 8 are cathodes.
  • the first electrode layer 4 and the third electrode layer 5 are cathodes
  • the second electrode layer 7 and the fourth electrode layer 8 are anodes.
  • the fourth electrode layer 8 is a surface electrode.
  • the fourth electrode layer 8 has a single-layer structure or a stacked-layer structure.
  • the fourth electrode layer 8 is a single-layer metal layer, or a single-layer metal mixture layer, or a single-layer transparent metal oxide layer, and when the fourth electrode layer When 8 is a laminated structure, the fourth electrode layer 8 is a laminate of a transparent metal oxide layer and a metal layer, or the fourth electrode layer 8 is a laminate of a transparent metal oxide layer and a metal mixture layer.
  • the fourth electrode layer 8 when the material of the fourth electrode layer 8 is doped with metal, and the thickness of the fourth electrode layer 8 is greater than or equal to 100 angstroms, and less than or equal to 500 angstroms, the fourth electrode layer 8 It is a whole continuous surface electrode, and the transparency of the fourth electrode layer 8 is greater than 40%; the material of the fourth electrode layer 8 is doped with metal, and the thickness of the fourth electrode layer 8 is greater than or equal to 100 angstroms , When less than or equal to 200 angstroms, the fourth electrode layer 8 is a continuous surface electrode, and the transparency of the fourth electrode layer 8 is greater than 40%; the material of the fourth electrode layer 8 is doped with metal, And when the thickness of the fourth electrode layer 8 is greater than or equal to 50 angstroms and less than or equal to 200 angstroms, the fourth electrode layer 8 is a continuous surface electrode, and the transparency of the fourth electrode layer 8 is greater than 50% When the material of the fourth electrode layer 8 is doped with metal, and the thickness of the fourth electrode layer 8 is greater than
  • the first OLED area A includes a first pixel opening 601
  • the second OLED area B includes a second pixel opening 602
  • the first light emitting structure layer is partially disposed in the first pixel opening 601
  • the second light-emitting structure layer is partially disposed in the second pixel opening 602.
  • the pixel opening is formed by a pixel defining layer (not shown) formed on the first electrode layer 4 and the third electrode layer 5, and the size of the pixel opening is determined Up the luminous area.
  • the first light-emitting structure layer and other parts of the second light-emitting structure layer are formed on the pixel defining layer.
  • the arrangement law of the second pixel openings 602 is the same as the arrangement law (or arrangement mode) of the first pixel openings 601.
  • the first OLED area A and the second OLED area B are both AMOLED areas.
  • the size of the second pixel opening 602 is the same as the size of the first pixel opening 601.
  • the driving circuits of the first electrode layer 4 in the first OLED area and the third electrode layer 5 in the second OLED area may both be 7T1C driving circuits.
  • the driving circuit of the third electrode layer 5 in the second OLED area is a 2T1C driving circuit; or, the driving circuit of the third electrode layer 5 in the second OLED area includes one TFT.
  • the array substrate includes scan lines and data lines, and when the driving circuit of the third electrode layer 5 in the second OLED area includes one TFT, the data line is electrically connected to the source of the TFT, and the third The electrode layer is electrically connected to the drain of the TFT, the scan line is electrically connected to the gate of the TFT, the scan line is used to control the on and off of the driving circuit, and the data line is in the driving When the circuit is turned on, a driving current is provided for the third electrode layer to control the light-emitting structure layer to emit light. Reduce the number of switching devices in the drive circuit to two or one.
  • the load current of the scan line and the load current of the data line are greatly reduced.
  • Reduce the requirements on the resistance of conductive circuit materials such as anodes, cathodes, scan lines, and data lines so that transparent materials can be used to make conductive circuits such as anodes, cathodes, scan lines, and data lines. This improves the performance of the display panel while ensuring the performance of the panel.
  • the first OLED area is an AMOLED area
  • the second OLED area is an AMOLED area or a PMOLED area.
  • the data line is electrically connected to the drain of the TFT
  • the third electrode layer is electrically connected to the source of the TFT
  • the scan line is electrically connected to the gate of the TFT.
  • the size of the second pixel opening 602a of the second OLED area B1 is larger than the size of the first pixel opening 601a of the first OLED area A1.
  • the third electrode layer of the second OLED area B1 includes a plurality of strip-shaped third electrodes 51a, as shown in FIG. 13.
  • Each stripe-shaped third electrode 51a corresponds to a plurality of second light emitting structures of the second light emitting structure layer 62, and the third electrodes 51a corresponding to the plurality of second light emitting structures can be driven by the same driving circuit, thereby reducing the number of driving circuits quantity.
  • the second pixel openings 602 and 602a shown in FIGS. 11 and 12 are square. In other embodiments, the shape of the second pixel opening is a circle, an ellipse, or a dumbbell shape.
  • the second OLED area B2 when the size of the second pixel opening is greater than the size of the first pixel opening, the second OLED area B2 includes at least one arrayed from the central area of the second OLED area B2 to the outer area. Two display areas, and in two adjacent display areas, the size of the second pixel opening of the display area close to the central area is smaller than the size of the second pixel opening of the display area far from the central area.
  • the second OLED area B2 includes a first display area B21, a second display area B22, and a third display area B23 that are sequentially arranged from the central area of the second OLED area B2 to the outer area.
  • the size of the second pixel opening 6021b of the first display area B21 is smaller than the size of the second pixel opening 6022b of the second display area B22, and the size of the second pixel opening 6022b of the second display area B22 is smaller than that of the third display area B23.
  • the second OLED area B2 may only be provided with the first display area and the second display area, or more display areas may be provided.
  • the size of the second pixel opening 6021b of the first display area is larger than the size of the first pixel opening 601b.
  • the size of the second pixel opening in the display area located in the central area of the second OLED area B may also be equal to the size of the first pixel opening.
  • the second mask opening 21b of the above-mentioned sub-mask is configured as the projection of the outer contour on the substrate 3 and the projection of the second pixel opening 602 on the substrate 3
  • the distance d2 of the outer contour is greater than the distance d1 between the outer contour of the projection of the first mask opening 11b of the sub-mask on the substrate 3 and the outer contour of the projection of the first pixel opening 601 on the substrate 3,
  • the value of the distance d1 is 3-6 microns
  • the value of the distance d2 is 8-15 microns.
  • the intensity of the first mask area 1b and the second mask area 2b of the sub-mask are close to the same, which is beneficial to eliminate the first OLED area of the array substrate Risk of color mixing with the second OLED area.
  • the present application also provides a display screen 200.
  • the display screen includes the array substrate 100 and a packaging structure 201 covering the surface of the array substrate.
  • Photosensitive devices such as cameras and sensors can be arranged under the second OLED area B, and the photosensitive devices can collect external light through the transparent second OLED area B, which ensures the performance of the photosensitive device while realizing the display function.
  • the present application also provides a display device.
  • the display device includes a device body C and a display screen 200 covering the device body.
  • the display device may be a mobile phone, a tablet computer, a notebook computer, etc., taking a mobile phone as an example.
  • the device body C may include components such as a casing, a circuit board, a battery, and a processor.
  • the device body C has a device area 300. The device area is located below the second OLED area, and the device area 300 is provided with a photosensitive device D that collects light through the second OLED area. Due to the high light transmittance of the second OLED area, it can ensure that the photosensitive device collects enough In order to ensure the performance of the photosensitive device.

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Abstract

一种掩膜条、阵列基板（100）、显示屏（200）及显示装置，掩膜条用于阵列基板（100）上的发光结构层的制作，掩膜条包括多个子掩膜版（10），子掩膜版（10）包括第一掩膜区（1）和第二掩膜区（2），第一掩膜区（1）具有第一掩膜开口（11），第二掩膜区（2）具有第二掩膜开口（21），第二掩膜开口（21）的密度小于第一掩膜开口（11）的密度，且至少部分第二掩膜开口（21）的尺寸大于第一掩膜开口（11）的尺寸。

Description

掩膜条、阵列基板、显示屏及显示装置 技术领域
本申请涉及显示领域，尤其涉及一种掩膜条、阵列基板、显示屏及显示装置。
背景技术
随着显示终端的快速发展，用户对屏占比的要求越来越高，使得显示终端的全面屏显示受到业界越来越多的关注。显示终端如手机、平板电脑等，由于需要集成诸如前置摄像头、听筒以及红外感应元件等，因此可通过在显示终端的显示屏上开槽，来设置前置摄像头、听筒以及红外感应元件等。但是如刘海屏的显示屏的开槽区域并不能用来显示画面，或者采用在屏幕上开孔的方式来设置摄像头等。对于实现摄像功能的电子设备来说，外界光线可通过屏幕上的开孔处进入位于屏幕下方的感光元件，引起不良的成像效果。如此，这种显示终端的显示屏不是全面屏。
发明内容
基于此，本申请提供一种掩膜条、阵列基板、显示屏及显示装置。
本申请的第一方面提供一种掩膜条，用于阵列基板上的发光结构层的制作，所述掩膜条包括多个子掩膜版，所述子掩膜版包括第一掩膜区和第二掩膜区，所述第一掩膜区具有第一掩膜开口，所述第二掩膜区具有第二掩膜开口，所述第二掩膜开口的密度小于第一掩膜开口的密度，且至少部分第二掩膜开口的尺寸大于所述第一掩膜开口的尺寸。
本申请第二方面提供一种阵列基板，所述阵列基板包括衬底以及第一OLED区域和第二OLED区域。所述第一OLED区域包括：形成于所述衬底上的第一电极层；形成于第一电极层上的第一发光结构层；第一像素开口，所述第一发光结构层至少部分地设置在所述第一像素开口内；形成于第一发光结构层上的第二电极层。所述第二OLED区域是所述阵列基板的除所述第一OLED区域之外的区域，第二OLED区域包括：形成在所述衬底上的第三电极层；形成于第三电极层上的第二发光结构层；第二像素开口，所述第二发光结构层部分地设置在所述第二像素开口内；形成于第二发光结构层上的第四电极层。所述第一OLED区域的像素密度大于第二OLED区域的像素密度，所述第一发光结构层及第二发光结构层采用如上所述的掩膜条在同一工艺中形成。
本申请的第三方面提供一种显示屏，所述显示屏包括如上所述的阵列基板以及覆盖于所述阵列基板表面的封装结构。
本申请的第四方面提供一种显示装置，所述显示装置包括设备本体及前述显示屏，所述设备主体具有器件区；所述显示屏覆盖在所述设备本体上；其中，所述器件区位于所述第二OLED区域下方，且所述器件区中设置有透过所述第二OLED区域进行光线采集的感光器件。
附图说明
图1为一种掩膜条的子掩膜版的俯视示意图；
图2为本申请掩膜条的一个实施例的俯视示意图；
图3为本申请子掩膜版的一个实施例的俯视示意图；
图4为本申请子掩膜版的又一个实施例的俯视示意图；
图5为本申请子掩膜版的再一个实施例的俯视示意图；
图6为本申请子掩膜版的再一个实施例的俯视示意图；
图7为本申请子掩膜版的再一个实施例的俯视示意图；
图8为本申请子掩膜版的再一个实施例的俯视示意图；
图9为本申请子掩膜版的第二掩膜区的一个实施例的俯视示意图；
图10为本申请阵列基板的一个实施例的剖视示意图；
图11为本申请第一掩膜开口及第二掩膜开口的一个实施例的俯视示意图；
图12为本申请第一掩膜开口及第二掩膜开口的又一个实施例的俯视示意图；
图13为本申请第三电极层的一个实施例俯视示意图；
图14为本申请第一掩膜开口及第二掩膜开口的再一个实施例的俯视示意图；
图15为本申请第一像素开口与第一掩膜开口的再一个实施例的俯视示意图；
图16为本申请第二像素开口与第二掩膜开口的再一个实施例的俯视示意图；
图17为本申请显示屏的一个实施例的截面示意图；以及
图18为本申请显示装置的一个实施例的正视示意图。
具体实施方式
在本申请使用的“一个”或者“一”等类似词语不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
为了实现全面屏，本申请将感光器件对应的显示区域设置为低像素密度的透明显示区域，使感光器件透过透明显示区域进行光线采集，而透明显示区域之外的正常显示区域则保持原像素密度。请参考图1，可以通过减少感光器件对应的显示区域的发光结构来降低像素密度，从而获得低像素密度的透明显示区。具体来说，可降低透明显示区域所对应的掩膜条的子掩膜版的第二掩膜区2的第二掩膜开口21的密度，而正常显示区域对应的子掩膜版的第一掩膜区1的第一掩膜开口11的密度保持不变，其中第一掩膜开口(或第二掩膜开口)的密度可理解为单位面积内的第一掩膜开口(或第二掩膜开口)的数量。进一步的，由于开口密度的差异，在掩膜条张网时，各子掩膜版的第一掩膜区1和第二掩膜区2的交界区域所受的应力不均匀，容易在该区域形成褶皱，造成显示屏的正常显示区域和透明显示区域的交界处产生混色的高风险。上述的掩膜条包括多个子掩膜版，而多个子掩膜版彼此相连形成整个掩膜条。
为解决上述技术问题，本实施例提供一种掩膜条，用于阵列基板上的发光结构层的制作，所述掩膜条包括多个子掩膜版，每个子掩膜版包括第一掩膜区和第二掩膜区，所述第一掩膜区具有第一掩膜开口，所述第二掩膜区具有第二掩膜开口，所述第二掩膜开口的密度小于第一掩膜开口的密度，且至少部分第二掩膜开口的尺寸大于所述第一掩膜开口的尺寸。
第一掩膜区的第一掩膜开口的密度较大，第二掩膜区的第二掩膜开口的密度较小，若第一掩膜开口的尺寸与第二掩膜开口的尺寸相等，则第二掩膜区的强度较大，本申请中至少部分第二掩膜开口的尺寸大于所述第一掩膜开口的尺寸，从而降低第二掩膜区的强度，使得第二掩膜区的强度接近或等于第一掩膜区的强度，掩膜条在张网时子掩膜版的第一掩膜区与第二掩膜区的交界区域受力均匀，因而交界区域不易产生褶皱，从而降低或消除显示屏的透明显示区域和正常显示区域的交界区域的混色风险。
本申请实施例提供一种掩膜条，用于制作阵列基板的发光结构层。如下文描述的图 10和图11所示，所述阵列基板包括衬底3及位于衬底上的第一OLED区域A及第二OLED区域B，所述第一OLED区域A为非透明显示区域(或者称为正常显示区域)，第二OLED区域B为透明显示区域。请参考图2，所述掩膜条包括多个子掩膜版10，多个子掩膜版10彼此相连形成整个掩膜条。
请参考图3，所述子掩膜版10包括第一掩膜区1a、第二掩膜区2a及非掩膜功能区域9a，非掩膜功能区9a作为两个子掩膜版的连接区，其对应于显示屏的区域为非显示区域，在蒸镀工艺中并不用来制作发光结构。所述第一掩膜区1a用于制作第一OLED区域的第一发光结构层，所述第二掩膜区2a用于制作第二OLED区域的第二发光结构层。所述第一掩膜区1a完全包围第二掩膜区2a，在其他实施例中，第一掩膜区也可以部分包围第二掩膜区。
请继续参照图3，本实施例中，所述第一掩膜区1a包括多个第一掩膜开口11a，第二掩膜区2a包括多个第二掩膜开口21a，所述第一掩膜开口11a及第二掩膜开口21a均呈圆形，所述第二掩膜开口21a的尺寸大于第一掩膜开口11a的尺寸。这里的尺寸，可以是指圆的半径或圆的面积。在其他实施例中，第一掩膜开口及第二掩膜开口可能呈方形、三角形等其他形状，尺寸可以指面积或边长。本实施例中，通过增大第二掩膜区2a的第二掩膜开口21a的尺寸，使得第二掩膜区2a的强度减小而接近或等于第一掩膜区1a的强度，避免第一掩膜区1a与第二掩膜区2a的交界区域受力不均，从而降低或消除第一OLED区域和第二OLED区域的混色风险。
在一些实施例中，所述第二掩膜开口和第一掩膜开口的排布规律相同，例如图3所示的第二掩膜开口21a及第一掩膜开口11a排布规律相同，可理解为排布方式相同，例如均呈直线排布，或均呈“品”字形排布。在其他实施例中，所述第二掩膜开口和第一掩膜开口的排布规律也可以不同。
第二掩膜开口21a的尺寸与第一掩膜开口11a的尺寸的关系，可通过第一OLED区域和第二OLED区域的像素密度的差异进行适应性的调节，以使第二掩膜区2a的强度接近或等于第一掩膜区1a的强度。
请参考图4，在另一实施例中，子掩膜版的第一掩膜区1b的第一掩膜开口11b及第二掩膜区2b的第二掩膜开口21b均呈矩形，子掩膜版的其他结构与图3所示的实施例相同。
请参考图5，第一掩膜区1c的结构与前述实施例的第一掩膜区1a结构相同，所述 第二掩膜区2c包括自所述第二掩膜区2c的中心区域依次向外部区域排列的至少两个开口区域，且相邻的两个开口区域中，靠近所述中心区域的开口区域的第二掩膜开口的尺寸，小于远离所述中心区域的开口区域的第二掩膜开口的尺寸。远离所述中心区域的开口区域至少部分包围靠近所述中心区域的开口区域。
如图5所示，第二掩膜区2c包括相邻的第一开口区域201c和第二开口区域202c，靠近中心区域的第一开口区域201c的第二掩膜开口211c的尺寸小于远离中心区域的第二开口区域202c的第二掩膜开口212c的尺寸。在一个实施例中，第二掩膜区2c还包括第三开口区域203c，所述第三开口区域203c较第二开口区域202c距离中心区域更远，所述第二开口区域202c的第二掩膜开口212c的尺寸小于第三开口区域203c的第三掩膜开口213c的尺寸。所述第一掩膜区11c包围第三开口区域203c，所述第三开口区域203c包围第二开口区域202c，所述第二开口区域202c包围第一开口区域201c。
请继续参照图5，位于所述第二掩膜区2c中心区域的第一开口区域201c的第二掩膜开口211c等于第一掩膜开口11c的尺寸。在其他实施例中，位于所述第二掩膜区中心区域的开口区域的第二掩膜开口的尺寸大于所述第一掩膜开口的尺寸。
在第二掩膜区由外向内的方向上(如图5箭头方向)，由于第二掩膜开口213c、212c、211c的尺寸依次减小，第三开口区域203c、第二开口区域202c、第一开口区域201c的强度依次减小。第一掩膜区1c的强度约等于第三开口区域203c的强度，第三开口区域203c的强度略小于第二开口区域202c的强度，第二开口区域202c的强度略小于第一开口区域201c的强度，换言之，在子掩膜版的整个区域上，各个区域的强度由外向内逐渐增大，两个相邻的区域之间的强度的差值很小，因而在子掩膜版的各区域的交界区域上，应力分布较为均匀，通过掩膜条生成的阵列基板的对应于子掩膜版的各区域的区域之间不易产生混色现象。
图6所示的子掩膜版的结构与图5所示的子掩膜版的结构大致相同，图5所示的子掩膜版的掩膜开口及第二掩膜区均为圆形，图6所示的子掩膜版的第一掩膜区1d及第二掩膜区2d呈方形，第一掩膜开口及第二掩膜开口也均呈方形，第二掩膜区2d包括由中心区域依次向外排列的第一开口区域201d、第二开口区域202d及第三开口区域203d。在其他实施例中，第一掩膜区、第二掩膜区、第一掩膜开口、第二掩膜开口的形状均可根据实际需求进行变化，并且第一掩膜开口、第二掩膜开口的形状可以相同，也可以不同，如第一掩膜开口及第二掩膜开口均呈方形，或者所述第一掩膜开口呈方形，第二掩膜开口呈圆形、椭圆形、哑铃形或葫芦形等形状。
请参考图7，本实施例中，子掩膜版包括第一掩膜区1e、第二掩膜区2e及非掩膜功能区9e，所述第二掩膜区2e位于第一掩膜区1e和非掩膜功能区9e之间。所述非掩膜功能区9e设有多个通孔91e，本实施例中，多个通孔91e的尺寸相等，通孔91e的尺寸小于第二掩膜区2e的第二掩膜开口21e的尺寸，且大于第一掩膜区1e的第一掩膜开口11e的尺寸。通过在非掩膜功能区9e设置通孔91e，使整个子掩膜版在掩膜条张网过程中受力均匀，避免因子掩膜版产生褶皱造成阵列基板的混色风险。
图8所示的子掩膜版中，第一掩膜区1f、第二掩膜区2f的结构与前述实施例中的第一掩膜区1e、第二掩膜区2e结构相同，不再赘述。非掩膜功能区9f设有通孔91f，通孔91f包括沿远离第二掩膜区2f方向排列的第一通孔911f、第二通孔912f及第三通孔913f，且第一通孔911f、第二通孔912f及第三通孔913f的尺寸依次减小。也就是说，在远离第二掩膜区2f的方向上，非掩膜功能区的强度从接近第二掩膜区的强度的大小逐渐增强，从而进一步确保整个子掩膜版的各区域的强度分布趋于均匀，使整个子掩膜版在掩膜条张网过程中受力均匀，避免因子掩膜版产生褶皱造成阵列基板的混色风险。
在其他实施例中，图7或图8所示的通孔也可以由凹陷来代替，凹陷可理解为保留通孔内的一部分材料，结构类似于盲孔。在一些实施例中，也可采用凹陷代替一部分通孔。通过设置凹陷，使整个子掩膜版在掩膜条张网过程中受力均匀，避免因子掩膜版产生褶皱造成阵列基板的混色风险。
在一个实施例中，所述通孔或凹陷呈圆形、椭圆形、哑铃形、葫芦形或方形，通孔或凹陷的形状可以与第二掩膜开口的形状相同，也可以与第二掩膜开口的形状不同。当通孔或凹陷的形状与第二掩膜开口的形状相同时，子掩膜版的应力分布更为均匀。
请结合图9，第二掩膜区2g设有多个第二掩膜开口21g及多个掩膜凹陷22g。本实施中，每个所述掩膜凹陷22g位于相邻的第二掩膜开口21g之间，所述掩膜凹陷22g的结构与前述实施例中的凹陷结构类似。通过在两个第二掩膜开口21g之间设置掩膜凹陷22g，使第二掩膜区2g的强度接近或等于第一掩膜区的强度，有利于缓解子掩膜版的内部应力，从而减小阵列基板的第一OLED区域与第二OLED区域的混色风险，同时也避免因子掩膜版受力不均而影响第二掩膜开口21g的位置精度。在一个实施例中，所述掩膜凹陷22g与所述第二掩膜开口21g的尺寸相等，如此有利于简化子掩膜版的制造过程，也有利于第二掩膜区2g应力分布均匀。
在一个实施例中，参考图9，所述阵列基板的第二OLED区域B(参考图10)包括多个像素单元，每个像素单元包括n个子像素，所述第二掩膜区2g包括配置为与像素 单元对应的多个第二掩膜子区域20g，每个第二掩膜子区域20g的掩膜凹陷22g的数量为n-1个，即比第二掩膜开口21g的数量少一个。例如当n等于3时，即，当第二掩膜开口21g的数量为3个时，每个第二掩膜子区域内的掩膜凹陷的数量为2个。在一些实施例中，n个子像素可以是n种颜色不同的子像素。在其他实施中，n个子像素中的部分子像素颜色相同。
在一个实施例中，相邻的掩膜凹陷22g和第二掩膜开口21g的间距等于相邻的两个第一掩膜开口的间距，从而使得第二掩膜区2g的强度更加接近第一掩膜区的强度，从而降低混色风险。
请参考图10，本申请还提供一种阵列基板100，所述阵列基板包括衬底3及位于所述衬底3上的第一OLED区域A及第二OLED区域B，所述第一OLED区域A为非透明显示区域(或者称为正常显示区域)，第二OLED区域B为透明显示区域。所述第一OLED区域A可以为圆形、方形等形状，所述第二OLED区域B可以为圆形、方形、水滴形、刘海形等形状，所述第一OLED区域A包围第二OLED区域B，在其他实施例中，所述第一OLED区域部分包围所述第二OLED区域。
所述衬底3可包括基板、驱动电路层(例如薄膜晶体管)、有机层、无机层等结构，第二OLED区域B对应的衬底部分可以不设置驱动电路层，而通过其他膜层或非显示区进行走线。所述第一OLED区域A包括形成于衬底3上的第一电极层4、形成于第一电极层4上的第一发光结构层61及形成于第一发光结构层61上的第二电极层7，所述第二OLED区域B包括形成于衬底3上第三电极层5、形成于第三电极层5上的第二发光结构层62及形成于第二发光结构层62上的第四电极层8，所述第一发光结构层61及第二发光结构层62采用所述子掩膜版在同一工艺中形成。
衬底3可以为刚性基板，例如玻璃基板、石英基板或者塑料基板等透明基板。在另一个实施例中，衬底3可以为柔性基板，例如柔性PI基板等。
在一个实施例中，为了提高第二OLED区域的光透过率，第二OLED区域的各导电走线(例如第三电极层5和第四电极层8)的材料可以包括透明材料，第三电极层及第四电极层的透光率大于40％，进一步的，二者的透光率大于60％，更进一步的，二者的透光率不小于80％。如第三电极层和第四电极层的材料可以包括透明导电金属氧化物或镁银混合物。举例来说，第三电极层和第四电极层的材料可以包括ITO(氧化铟锡)、氧化铟锌(IZ)、掺杂银的氧化铟锡、掺杂银的氧化铟锌中的至少一种。本实施例中，第一电极层4及第三电极层5为阳极，第二电极层7及第四电极层8为阴极。在其他实 施例中，第一电极层4及第三电极层5为阴极，第二电极层7及第四电极层8为阳极。
在一个实施例中，所述第四电极层8为面电极。可选的，所述第四电极层8为单层结构或叠层结构。当所述第四电极层8为单层结构时，所述第四电极层8为单层金属层、或单层金属混合物层、或单层透明金属氧化物层，当所述第四电极层8为叠层结构时，所述第四电极层8为透明金属氧化物层与金属层的叠层、或所述第四电极层8为透明金属氧化物层与金属混合物层的叠层。
在一个实施例中，所述第四电极层8材料中掺杂有金属，且所述第四电极层8的厚度大于或等于100埃，小于或等于500埃时，所述第四电极层8为整体连续的面电极，且所述第四电极层8的透明度大于40％；所述第四电极层8材料中掺杂有金属，且所述第四电极层8的厚度大于或等于100埃，小于或等于200埃时，所述第四电极层8为整体连续的面电极，且所述第四电极层8的透明度大于40％；所述第四电极层8材料中掺杂有金属，且所述第四电极层8的厚度大于或等于50埃，小于或等于200埃时，所述第四电极层8为整体连续的面电极，且所述第四电极层8的透明度大于50％；所述第四电极层8材料中掺杂有金属，且所述第四电极层8的厚度大于或等于50埃，小于或等于200埃时，所述第四电极层8为整体连续的面电极，且所述第四电极层8的透明度大于60％；当所述第四电极层8为单层结构时，所述单层金属层材料为Al、Ag，所述单层金属混合物层材料为Mg、Ag或掺杂Al的金属混合材料，所述透明金属氧化物为ITO或IZO。
请参考图11，所述第一OLED区域A包括第一像素开口601，所述第二OLED区域B包括第二像素开口602，所述第一发光结构层部分设于第一像素开口601内，所述第二发光结构层部分设于第二像素开口602内，像素开口由形成于第一电极层4及第三电极层5上的像素限定层(未图示)形成，像素开口的尺寸决定了发光面积。第一发光结构层及第二发光结构层其它部分形成于像素限定层上。所述第二像素开口602的排布规律与所述第一像素开口601的排布规律(或排布方式)相同。本实施例中，所述第一OLED区域A及第二OLED区域B均为AMOLED区域。
请结合图10及图11，所述第二像素开口602的尺寸与所述第一像素开口601的尺寸相同。所述第一OLED区域的第一电极层4及所述第二OLED区域的第三电极层5的驱动电路均可以为7T1C驱动电路。在一些实施例中，所述第二OLED区域的第三电极层5的驱动电路为2T1C驱动电路；或者，第二OLED区域的第三电极层5的驱动电路包含1个TFT。所述阵列基板包括扫描线和数据线，第二OLED区域的第三电极层5 的驱动电路包含1个TFT的情况下，所述数据线电性连接所述TFT的源极，所述第三电极层电性连接所述TFT的漏极，所述扫描线电性连接所述TFT的栅极，所述扫描线用于控制所述驱动电路的开启和关闭，所述数据线在所述驱动电路开启时，为所述第三电极层提供驱动电流，以控制所述发光结构层发光。将驱动电路中的开关器件减少至两个或一个，在简化面板结构复杂度，降低因面板结构间隙导致的衍射的程度的基础上，大大降低扫描线的负载电流以及数据线的负载电流，以降低对阳极、阴极、扫描线、数据线等导电线路材料的电阻的要求，使得可以采用透明材料制作阳极、阴极、扫描线、数据线等导电线路，在确保面板性能的同时，提高显示面板的透光度。所述第一OLED区域为AMOLED区域，第二OLED区域为AMOLED区域或PMOLED区域。在其他实施例中，所述数据线电性连接所述TFT的漏极，所述第三电极层电性连接所述TFT的源极，所述扫描线电性连接所述TFT的栅极。
在另一个实施例中，请参考图12，第二OLED区域B1的第二像素开口602a的尺寸大于第一OLED区域A1的第一像素开口601a的尺寸。对应的，第二OLED区域B1的第三电极层包括多个条状第三电极51a，如图13所示。每个条状第三电极51a对应于第二发光结构层62的多个第二发光结构，对应于多个第二发光结构的第三电极51a可通过同一个驱动电路进行驱动，从而减少驱动电路的数量。
图11及图12所示的第二像素开口602、602a呈方形，在其他实施例中的，所述第二像素开口的形状为圆形、椭圆形或哑铃形等形状。
请参考图14，所述第二像素开口的尺寸大于所述第一像素开口的尺寸时，所述第二OLED区域B2包括自所述第二OLED区域B2的中心区域依次向外部区域排列的至少两个显示区域，且相邻的两个显示区域中，靠近所述中心区域的显示区域的第二像素开口的尺寸，小于远离所述中心区域的显示区域的第二像素开口的尺寸。本实施例中，所述第二OLED区域B2包括自所述第二OLED区域B2的中心区域依次向外部区域排列的第一显示区域B21、第二显示区域B22、第三显示区域B23，所述第一显示区域B21的第二像素开口6021b的尺寸小于第二显示区域B22的第二像素开口6022b的尺寸，第二显示区域B22的第二像素开口6022b的尺寸小于第三显示区域B23的第二像素开口6023b的尺寸。在其他一些实施例中，第二OLED区域B2可以仅设置第一显示区域和第二显示区域，也可以设置更多的显示区域。
本实施例中，第一显示区域的第二像素开口6021b的尺寸大于第一像素开口601b的尺寸。在其他实施例中，位于所述第二OLED区域B的中心区域的显示区域的第二 像素开口的尺寸也可以等于所述第一像素开口的尺寸。
请结合图4、图15及图16，上述的子掩膜版的第二掩膜开口21b配置为在衬底3上的投影的外轮廓与第二像素开口602在衬底3上的投影的外轮廓的间距d2，大于所述子掩膜版的第一掩膜开口11b在衬底3上的投影的外轮廓与第一像素开口601在衬底3上的投影的外轮廓的间距d1，在一个实施例中，间距d1的取值为3～6微米，间距d2的取值为8～15微米。当间距d2的取值范围为8～15微米时，子掩膜版的第一掩膜区1b的强度和第二掩膜区2b的强度接近于相等，有利于消除阵列基板的第一OLED区域和第二OLED区域的混色风险。
本申请还提供一种显示屏200，如图17所示，所述显示屏包括所述阵列基板100及覆盖于所述阵列基板表面的封装结构201。所述第二OLED区域B下方可设置摄像头、传感器等感光器件，感光器件可通过透明的第二OLED区域B采集外界光线，在实现显示功能的同时，保证了感光器件的性能。
请结合图18，本申请还提供一种显示装置，所述显示装置包括设备主体C及覆盖于所述设备主体的显示屏200。所述显示装置可以是手机、平板电脑、笔记本电脑等设备，以手机为例，设备主体C可包括外壳、电路板、电池、处理器等元件，所述设备主体C具有器件区300，所述器件区位于第二OLED区域下方，且所述器件区300中设置有透过第二OLED区域进行光线采集的感光器件D，由于第二OLED区域的高透光性，可保证感光器件采集到足够的光线，从而保证感光器件的性能。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (20)

  1. 一种掩膜条，用于阵列基板上的发光结构层的制作，所述掩膜条包括多个子掩膜版，所述子掩膜版包括：
    第一掩膜区，所述第一掩膜区具有第一掩膜开口；和
    第二掩膜区，所述第二掩膜区具有第二掩膜开口，其中
    所述第二掩膜开口的密度小于所述第一掩膜开口的密度，且至少部分第二掩膜开口的尺寸大于所述第一掩膜开口的尺寸。
  2. 如权利要求1所述的掩膜条，其中，
    所述第二掩膜开口配置为在所述阵列基板上的投影的外轮廓与所述阵列基板的对应于所述第二掩膜开口的第二像素开口在阵列基板上的投影的外轮廓的间距为8～15微米。
  3. 如权利要求1所述的掩膜条，其中，
    所述第二掩膜开口和第一掩膜开口的排布规律相同。
  4. 如权利要求1所述的掩膜条，其中，所述第二掩膜区包括自所述第二掩膜区的中心区域依次向外部区域排列的至少两个开口区域，且相邻的两个开口区域中，靠近所述中心区域的开口区域的第二掩膜开口的尺寸，小于远离所述中心区域的开口区域的第二掩膜开口的尺寸。
  5. 如权利要求4所述的掩膜条，其中
    位于所述第二掩膜区中心区域的开口区域的第二掩膜开口的尺寸大于或等于所述第一掩膜开口的尺寸。
  6. 如权利要求1所述的掩膜条，其中，所述子掩膜版还包括非掩膜功能区，所述第二掩膜区位于所述非掩膜功能区和第一掩膜区之间，所述非掩膜功能区设有多个通孔或多个凹陷。
  7. 如权利要求6所述的掩膜条，其中
    所述多个通孔的尺寸彼此相等或多个凹陷的尺寸彼此相等；或
    所述多个通孔的尺寸或多个凹陷的尺寸沿远离第二掩膜区的方向逐渐减小。
  8. 如权利要求6所述的掩膜条，其中
    所述通孔或凹陷的尺寸小于所述第二掩膜区的所述第二掩膜开口的尺寸，且大于所述第一掩膜区的所述第一掩膜开口的尺寸。
  9. 如权利要求1所述的掩膜条，其中，所述第二掩膜区包括多个掩膜凹陷，所述掩膜凹陷位于相邻的所述第二掩膜开口之间。
  10. 如权利要求9所述的掩膜条，其中，
    所述掩膜凹陷与所述第二掩膜开口的尺寸相等。
  11. 如权利要求9所述的掩膜条，其中
    所述第二掩膜区包括配置为与阵列基板的像素单元对应的多个第二掩膜子区域，每个所述第二掩膜子区域的掩膜凹陷的数量比所述第二掩膜开口的数量少一个。
  12. 如权利要求9所述的掩膜条，其中
    相邻的掩膜凹陷和第二掩膜开口的间距等于相邻的两个第一掩膜开口的间距。
  13. 一种阵列基板，包括：
    衬底；
    第一OLED区域，，所述第一OLED区域包括：
    第一电极层，所述第一电极层形成于所述衬底上；
    第一发光结构层，所述第一发光结构层形成于第一电极层上；
    第一像素开口，所述第一发光结构层至少部分地设置在所述第一像素开口内；以及
    第二电极层，所述第二电极层形成于第一发光结构层上；以及
    第二OLED区域，所述第二OLED区域是所述阵列基板的除所述第一OLED区域之外的区域，第二OLED区域包括：
    第三电极层，所述第三电极层形成在所述衬底上；
    第二发光结构层，所述第二发光结构层形成于第三电极层上；
    第二像素开口，所述第二发光结构层至少部分地设置在所述第二像素开口内；以及
    第四电极层，所述第四电极层形成于第二发光结构层上；其中
    所述第一OLED区域的像素密度大于第二OLED区域的像素密度，所述第一发光结构层及第二发光结构层采用如权利要求1至12中任一项所述的掩膜条在同一工艺中形成。
  14. 如权利要求13所述的阵列基板，其中，所述第二像素开口的排布规律与所述第一像素开口的排布规律相同。
  15. 如权利要求13所述的阵列基板，其中
    所述第二像素开口的尺寸与所述第一像素开口的尺寸相同；或者，所述第二像素开口的尺寸大于所述第一像素开口的尺寸。
  16. 如权利要求15所述的阵列基板，其中
    所述第二像素开口的尺寸大于所述第一像素开口的尺寸时，所述第二OLED区域包括自所述第二OLED区域的中心区域依次向外部区域排列的至少两个显示区域，且相邻的两个显示区域中，靠近所述中心区域的显示区域的第二像素开口的尺寸，小于远离所述中心区域的显示区域的第二像素开口的尺寸。
  17. 如权利要求16所述的阵列基板，其中
    位于所述第二OLED区域中心区域的显示区域的第二像素开口的尺寸大于或等于所述第一像素开口的尺寸。
  18. 如权利要求13所述的阵列基板，其中，所述第一电极层及第三电极层为阳极，所述第二电极层及第四电极层为阴极；
    所述第三电极层包括多个第三电极，所述第四电极层为面电极；
    所述第四电极层为单层结构或叠层结构，所述第四电极层为单层结构时，所述第四电极层为单层金属层、或单层金属混合物层、或单层透明金属氧化物层，所述第四电极层为叠层结构时，所述第四电极层为透明金属氧化物层与金属层的叠层、或所述第四电极层为透明金属氧化物层与金属混合物层的叠层；
    所述第四电极层材料中掺杂有金属，且所述第四电极层的厚度大于或等于100埃，小于或等于500埃时，所述第四电极层的为整体连续的面电极，且所述第四电极层的透明度大于40％；
    所述第四电极层材料中掺杂有金属，且所述第四电极层的厚度大于或等于100埃，小于或等于200埃时，所述第四电极层为整体连续的面电极，且所述第四电极层的透明度大于40％；
    所述第四电极层材料中掺杂有金属，且所述第四电极层的厚度大于或等于50埃，小于或等于200埃时，所述第四电极层为整体连续的面电极，且所述第四电极层的透明度大于50％；
    所述第四电极层材料中掺杂有金属，且所述第四电极层的厚度大于或等于50埃，小于或等于200埃时，所述第四电极层为整体连续的面电极，且所述第四电极层的透明度大于60％；
    所述第四电极层为单层结构时，所述单层金属层材料为Al、Ag，所述单层金属混合物层材料为Mg、Ag或掺杂Al的金属混合材料，所述透明金属氧化物为ITO或IZO。
  19. 一种显示屏，包括：
    如权利要求13-18中任一项所述的阵列基板；以及
    封装结构，所述封装结构覆盖于所述阵列基板表面。
  20. 一种显示装置，包括：
    设备本体，所述设备本体具有器件区；以及
    如权利要求19所述的显示屏，所述显示屏覆盖在所述设备本体上；
    其中，所述器件区位于所述第二OLED区域下方，且所述器件区中设置有透过所述第二OLED区域进行光线采集的感光器件。
PCT/CN2019/098343 2019-01-31 2019-07-30 掩膜条、阵列基板、显示屏及显示装置 WO2020155588A1 (zh)

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