US20210141304A1 - Mask strips, array substrates and display screens - Google Patents

Mask strips, array substrates and display screens Download PDF

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Publication number
US20210141304A1
US20210141304A1 US17/152,995 US202117152995A US2021141304A1 US 20210141304 A1 US20210141304 A1 US 20210141304A1 US 202117152995 A US202117152995 A US 202117152995A US 2021141304 A1 US2021141304 A1 US 2021141304A1
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United States
Prior art keywords
mask
region
openings
electrode layer
layer
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Abandoned
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US17/152,995
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English (en)
Inventor
Mingxing Liu
Rusheng LIU
Bing Zhang
Bing Han
Ying Zhao
Shuaiyan GAN
Feng Gao
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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Assigned to KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD. reassignment KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GAN, Shuaiyan, GAO, FENG, HAN, BING, LIU, Mingxing, LIU, Rusheng, ZHANG, BING, ZHAO, YING
Publication of US20210141304A1 publication Critical patent/US20210141304A1/en
Abandoned legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/0021—Reactive sputtering or evaporation
    • C23C14/0036—Reactive sputtering
    • C23C14/0042—Controlling partial pressure or flow rate of reactive or inert gases with feedback of measurements
    • H01L27/3234—
    • H01L27/326—
    • H01L51/0011—
    • H01L51/5206—
    • H01L51/5221—
    • H01L51/5253—
    • H01L51/56—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask
    • H01L2251/558—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80523—Multilayers, e.g. opaque multilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80524—Transparent cathodes, e.g. comprising thin metal layers

Definitions

  • the present application relates to a field of displays, in particular to mask strips, array substrates, and display screens.
  • a display screen of the display terminal may be notched to place the front camera, the earphone, the infrared sensing element and the like.
  • a notched area of the display screen may not be used to display pictures.
  • a hole may be opened in the display screen to place the camera and the like.
  • external light may enter a photosensitive element placed below the screen through the hole in the screen. As such, the display screen of such a display terminal is not a full screen.
  • the present application provides a mask strip, an array substrate, and a display screen.
  • a first aspect of the present application provides a mask strip for fabricating a light emitting structure layer on an array substrate, the mask strip includes a plurality of sub-masks, and each of the plurality of sub-masks includes a first mask region having a plurality of first mask openings; and a second mask region having a plurality of second mask openings, wherein a density of the second mask openings in the second mask region is less than a density of the first mask openings in the first mask region, and a size of each of at least part of the second mask openings is larger than a size of each of the plurality of first mask openings.
  • a second aspect of the present application provides an array substrate.
  • the array substrate includes a substrate, a first OLED region and a second OLED region.
  • the first OLED region includes: a first electrode layer formed on the substrate; a first light emitting structure layer formed on the first electrode layer; a first pixel opening, at least partial of the first light emitting structure layer being disposed within the first pixel opening; and a second electrode layer formed on the first light emitting structure layer
  • the second OLED region includes: a third electrode layer formed on the substrate; a second light emitting structure layer formed on the third electrode layer; a second pixel opening, at least partial of the second light emitting structure layer being disposed within the second pixel opening; and a fourth electrode layer formed on the second light emitting structure layer.
  • a pixel density in the first OLED region is greater than a pixel density in the second OLED region, and the first light emitting structure layer and the second light emitting structure layer are fabricated in a same process by using the mask strip as described above.
  • a third aspect of the present application provides a display screen.
  • the display screen includes an array substrate mentioned before, and an encapsulation structure covering a surface of the array substrate.
  • FIG. 1 is a schematic top view of a sub-mask of a mask strip.
  • FIG. 2 is a schematic top view of an embodiment of a mask strip of the present application.
  • FIG. 3 is a schematic top view of an embodiment of a sub-mask of the present application.
  • FIG. 4 is a schematic top view of another embodiment of the sub-mask of the present application.
  • FIG. 5 is a schematic top view of yet another embodiment of the sub-mask of the present application.
  • FIG. 6 is a schematic top view of another embodiment of the sub-mask of the present application.
  • FIG. 7 is a schematic top view of another embodiment of the sub-mask of the present application.
  • FIG. 8 is a schematic top view of still another embodiment of the sub-mask of the present application.
  • FIG. 9 is a schematic top view of an embodiment of a second mask region of a sub-mask of the present application.
  • FIG. 10 is a schematic cross-sectional view of an embodiment of an array substrate of the present application.
  • FIG. 11 is a schematic top view of an embodiment of a first mask opening and a second mask opening of the present application.
  • FIG. 12 is a schematic top view of another embodiment of the first mask opening and the second mask opening of the present application.
  • FIG. 13 is a schematic top view of an embodiment of a third electrode layer of the present application.
  • FIG. 14 is a schematic top view of still another embodiment of the first mask opening and the second mask opening of the present application.
  • FIG. 15 is a schematic top view of another embodiment of a first pixel opening and the first mask opening of the present application.
  • FIG. 16 is a schematic top view of another embodiment of a second pixel opening and the second mask opening of the present application.
  • FIG. 17 is a schematic cross-sectional view of an embodiment of a display screen of the present application.
  • FIG. 18 is a schematic front view of an embodiment of a display device of the present application.
  • a display area corresponding to a photosensitive component is set as a transparent display area with a low pixel density, so that the photosensitive component collects light transmitting through the transparent display area, while a normal display area outside or around the transparent display area has a standard pixel density.
  • the pixel density may be reduced by reducing a number of light emitting structures of the display area corresponding to the photosensitive component, thereby the transparent display area with the low pixel density is obtained.
  • a density of second mask openings 21 in second mask region 2 of a sub-mask of a mask strip corresponding to the transparent display area may be reduced, while a density of first mask openings 11 in first mask region 1 of the sub-mask of the mask strip corresponding to the normal display area may remain unchanged, where the density of the first mask openings (or the second mask openings) may be interpreted as a number of the first mask openings (or second mask openings) per unit area of first mask region 1 (or of second mask region 2 ).
  • the above mask strip includes a plurality of sub-masks, and the plurality of sub-masks are connected with each other to form the mask strip as a whole.
  • an embodiment provides a mask strip for fabricating a light emitting structure layer on an array substrate.
  • the mask strip includes a plurality of sub-masks, and each of the sub-masks includes a first mask region and a second mask region.
  • the first mask region has a plurality of first mask openings
  • the second mask region has a plurality of second mask openings.
  • the density of the second mask openings in the second mask region is less than the density of the first mask openings in the first mask region, and a size of each of at least part of the second mask openings is larger than a size of each of the plurality of the first mask openings.
  • the density of the first mask openings in the first mask region is larger, and the density of the second mask openings in the second mask region is smaller. If the size of the first mask openings is equal to the size of the second mask openings, a strength of the second mask region is greater than a strength of the first mask region. In the present application, the size of each of the at least part of the second mask openings is larger than the size of each of the plurality of the first mask openings, thereby the strength of the second mask region is reduced and the second mask region is close to or equal to the strength of the first mask region.
  • the boundary area between the first mask region and the second mask region of the sub-mask is subjected to even stress, so that it is not easy for the wrinkle to form in the boundary area. Thereby, the risk of color mixing at the boundary area between the transparent display area and the normal display area of the display screen is reduced or eliminated.
  • Embodiments of the present application provide a mask strip, which is used for fabricating a light emitting structure layer of an array substrate.
  • the array substrate includes a substrate 3 , a first OLED region A located on the substrate 3 , and a second OLED region B located on the substrate 3 .
  • the first OLED region A is a non-transparent display area (also referred to as a normal display area), and the second OLED region B is a transparent display area.
  • the mask strip includes a plurality of sub-masks 10 , and the plurality of sub-masks 10 are connected with each other to form the mask strip as a whole.
  • sub-mask 10 includes a first mask region 1 a, a second mask region 2 a, and a non-mask functional region 9 a.
  • Non-mask functional region 9 a serves as a connection region between adjacent sub-masks.
  • Non-mask functional region 9 a is corresponding to a non-display area of the display screen, and a light emitting structure is not to be fabricated in an evaporation process on the non-mask functional region.
  • the first light emitting structure layer of the first OLED region is fabricated on first mask region 1 a, and the second light emitting structure layer of the second OLED region is fabricated on second mask region 2 a.
  • First mask region 1 a completely surrounds second mask region 2 a. In other embodiments, the first mask region may partially surround the second mask region.
  • first mask region 1 a includes a plurality of first mask openings 11 a
  • second mask region 2 a includes a plurality of second mask openings 21 a.
  • a shape of a first mask opening 11 a and a shape of a second mask opening 21 a are both circular, and a size of second mask opening 21 a is larger than a size of first mask opening 11 a.
  • the size here may refer to radius or area of a circle of the mask opening.
  • the first mask opening and the second mask opening may be in another shape such as square and triangle, and the size of the mask opening may refer to an area or a side length of the mask opening.
  • an arrangement pattern of the second mask openings is substantially same as an arrangement pattern of the first mask openings, for example, the arrangement pattern of second mask openings 21 a is roughly the same as the arrangement pattern of first mask openings 11 a shown in FIG. 3 .
  • the mask openings are all arranged in a straight line, or the mask openings are in triangular arrangement.
  • the arrangement pattern of the second mask openings is different from the arrangement pattern of the first mask openings.
  • a relationship between the size of second mask openings 21 a and the size of first mask openings 11 a may be adjusted adaptively by a difference in pixel density between the first OLED region and the second OLED region, so that the strength of second mask region 2 a is close to or equal to the strength of first mask region 1 a.
  • first mask openings 11 b in first mask region 1 b of the sub-mask and the shape of second mask openings 21 b in second mask region 2 b of the sub-mask are both rectangular, and other structures of the sub-mask are same as the structures in the embodiment shown in FIG. 3 .
  • first mask region 1 c is same as that of first mask region 1 a in the embodiment of FIG. 3
  • second mask region 2 c includes at least two regions with openings and arranged sequentially from a center region to an outer region in second mask region 2 c.
  • a size of the second mask openings in the region with openings close to the center region is smaller than a size of the second mask openings in the region with openings away from the center region.
  • the region with openings away from the center region at least partially surrounds the region with openings close to the center region.
  • second mask region 2 c includes first region with openings 201 c and second region with openings 202 c that are adjacent to each other, and the size of second mask openings 211 c in the first region with openings 201 c close to the center region is smaller than the size of second mask openings 212 c in the second region with openings 202 c away from the center region.
  • second mask region 2 c further includes a third region with openings 203 c, and a distance between third region with openings 203 c and the center region is farther than a distance between second region with openings 202 c and the center region.
  • a size of second mask openings 212 c in the second region with openings 202 c is smaller than a size of second mask openings 213 c in third region with openings 203 c.
  • First mask region 11 c surrounds third region with openings 203 c
  • third region with openings 203 c surrounds second region with openings 202 c
  • second region with openings 202 c surrounds first region with openings 201 c.
  • a size of second mask openings 211 c in first region with openings 201 c located in the center region of second mask region 2 c is equal to the size of the first mask openings 11 c. In other embodiments, the size of the second mask openings 211 c in first region with openings 201 c located in the center region of second mask region 2 c is larger than the size of the first mask openings.
  • a strength of third region with openings 203 c, a strength of second region with openings 202 c and a strength of first region with openings 201 c are increased sequentially.
  • the strength of the first mask region 1 c is substantially equal to that of the third region with openings 203 c.
  • the strength of third region with openings 203 c is slightly less than the strength of second region with openings 202 c, and the strength of second region with openings 202 c is slightly less than the strength of first region with openings 201 c.
  • the structure of the sub-mask shown in FIG. 6 is substantially same as the structure of the sub-mask shown in FIG. 5 .
  • the shape of the mask openings and the shape of the second mask region of the sub-mask shown in FIG. 5 are both circular.
  • a shape of first mask region 1 d and a shape of second mask region 2 d of the sub-mask shown in FIG. 6 are square, and the shape of the first mask openings and the shape of the second mask openings are both square.
  • Second mask region 2 d includes first region with openings 201 d, second region with openings 202 d, and third region with openings 203 d sequentially arranged outwards from a center region.
  • the shapes of the first mask region and the second mask region, and the shapes of the first mask openings and the second mask openings may be changed according to actual needs, and the shape of the first mask openings may be same as or different from the shape of the second mask openings, for example, the shape of the first mask openings and the shape of the second mask openings are all square, or the shape of the first mask openings is square, and the shape of the second mask openings is circular, oval, dumbbell-shaped or gourd-shaped.
  • the sub-mask includes first mask region 1 e, second mask region 2 e and non-mask functional region 9 e, where second mask region 2 e is located between first mask region 1 e and non-masked functional region 9 e.
  • Non-mask functional region 9 e is provided with a plurality of through holes 91 e.
  • sizes of the plurality of through holes 91 e are equal, and the size of the through hole 91 e is smaller than a size of second mask opening 21 e in second mask region 2 e and larger than a size of first mask opening 11 e in first mask region 1 e.
  • Non-mask functional region 9 f is provided with a plurality of through holes 91 f.
  • Through holes 91 f includes first through holes 911 f, second through holes 912 f, and third through holes 913 f arranged in a direction away from second mask region 2 f, and a size of first through holes 911 f, a size of second through holes 912 f and a size of third through holes 913 f are sequentially reduced.
  • the strength of the non-mask functional region gradually increases from the strength of the second mask region, thereby the strength distribution of each region across the entire sub-mask is even, so that the entire sub-mask is subjected to even stress during the tensioning process of the mask strip, and the risk of color mixing of the array substrate caused by wrinkling of the sub-mask is avoided.
  • the through holes shown in FIG. 7 or FIG. 8 may be replaced by recesses.
  • the recesses may be understood as retaining a part of material of the through hole, and the structure of a recess is similar to a blind hole.
  • the recesses may be used instead of some of the through holes.
  • the shape of the through holes or recesses is circular, oval, dumbbell-shaped, gourd-shaped, or square.
  • the shape of the through holes or recesses may be same as or different from the shape of the second mask openings. When the shape of the through holes or recesses is same as the shape of the second mask openings, the stress distribution of the sub-mask is more even.
  • the second mask region 2 g is provided with a plurality of second mask openings 21 g and a plurality of mask recesses 22 g.
  • each of mask recesses 22 g is located between adjacent second mask openings 21 g, and the structure of mask recesses 22 g is similar to the structure of the recesses in the foregoing embodiment.
  • the strength of second mask region 2 g is close to or equal to the strength of the first mask region, which is beneficial to alleviate internal stress of the sub-mask, thereby the risk of color mixing between the first OLED region and the second OLED region of the array substrate is reduced, and at the same time, position accuracy of second mask openings 21 g affected by the uneven stress of the sub-mask is avoided.
  • the size of mask recesses 22 g is same as the size of second mask openings 21 g, which is beneficial to simplify the fabricating process of the sub-mask and to make the stress distribution in the second mask region 2 g even.
  • the second OLED region B (refer to FIG. 10 ) of the array substrate includes a plurality of pixel units, each pixel unit includes n sub-pixels, and second mask region 2 g includes a plurality of second mask sub-regions 20 g, each of which is corresponding to one pixel unit.
  • the number of mask recesses 22 g in each second mask sub-region 20 g is n-1, that is, the number of mask recesses 22 g is less than the number of second mask openings 21 g by one.
  • n is equal to 3, that is, when the number of second mask openings 21 g is three, the number of mask recesses in each second mask sub-region is two.
  • n sub-pixels may be different sub-pixels in n colors. In other implementations, some of the n sub-pixels have a same color.
  • a distance between mask recess 22 g and adjacent second mask opening 21 g is equal to a distance between adjacent two first mask openings, thereby the strength of second mask region 2 g is more approximate to the strength of the first mask region, further reducing the risk of color mixing.
  • the present application also provides an array substrate 100 .
  • the array substrate includes a substrate 3 , a first OLED region A located on substrate 3 , and a second OLED region B located on substrate 3 .
  • the first OLED region A is a non-transparent display area (or referred to as a normal display area), and the second OLED region B is a transparent display area.
  • the first OLED region A may be in a shape of circle, square, etc.
  • the second OLED region B may be in a shape of circle, square, water drop, notch-shaped or fringe-shaped, etc.
  • the first OLED region A surrounds the second OLED region B. In other embodiments, the first OLED region partially surrounds the second OLED region.
  • Substrate 3 may include a base substrate, a driving circuit layer (such as a thin film transistor), an organic layer, an inorganic layer, and other structures.
  • the portion of the substrate corresponding to the second OLED region B may not be provided with the driving circuit layer, but wiring for the portion may be configured in other film layers or non-display area.
  • the first OLED region A includes a first electrode layer 4 formed on substrate 3 , a first light emitting structure layer 61 formed on first electrode layer 4 , and a second electrode layer 7 formed on first light emitting structure layer 61 .
  • the second OLED region B includes a third electrode layer 5 formed on substrate 3 , a second light emitting structure layer 62 formed on third electrode layer 5 , and a fourth electrode layer 8 formed on second light emitting structure layer 62 .
  • First light emitting structure layer 61 and second light emitting structure layer 62 are formed in a same process using the sub-mask.
  • Substrate 3 may be a rigid substrate, for example, a transparent substrate such as a glass substrate, a quartz substrate, or a plastic substrate.
  • substrate 3 may be a flexible substrate, such as a flexible Polyimide (PI) substrate.
  • PI Polyimide
  • materials of conductive wires in the second OLED region may include transparent materials.
  • the light transmittance of the third electrode layer and the light transmittance of the fourth electrode layer are greater than 40%. Further, the light transmittance of the two is greater than 60%. Still further, the light transmittance of the two is not less than 80%.
  • the materials of the third electrode layer and the fourth electrode layer may include a transparent conductive metal oxide or a magnesium-silver mixture.
  • the materials of the third electrode layer and the fourth electrode layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZ), silver-doped indium tin oxide, and silver-doped indium zinc oxide.
  • first electrode layer 4 and third electrode layer 5 are anodes
  • second electrode layer 7 and fourth electrode layer 8 are cathodes.
  • first electrode layer 4 and third electrode layer 5 are cathodes
  • second electrode layer 7 and fourth electrode layer 8 are anodes.
  • fourth electrode layer 8 is a planar electrode.
  • fourth electrode layer 8 has a single-layer structure or a stacked structure. If fourth electrode layer 8 has a single-layer structure, the fourth electrode layer 8 is one of the following: a single-layer metal layer, a single-layer metal mixture layer, and a single-layer transparent metal oxide layer. If fourth electrode layer 8 has a stacked structure, the fourth electrode layer 8 is one of the following: a stack of transparent metal oxide layer and metal layer, and a stack of transparent metal oxide layer and metal mixture layer.
  • the fourth electrode layer 8 when a material of fourth electrode layer 8 is doped with metal, and a thickness of fourth electrode layer 8 is greater than or equal to 100 ⁇ and less than or equal to 500 ⁇ , the fourth electrode layer 8 is an overall continuous planar electrode, and a transmittance of fourth electrode layer 8 is greater than 40%.
  • the material of fourth electrode layer 8 is doped with metal, and the thickness of fourth electrode layer 8 is greater than or equal to 100 ⁇ and less than or equal to 200 ⁇
  • the fourth electrode layer 8 is an overall continuous planar electrode, and the transmittance of fourth electrode layer 8 is greater than 40%.
  • fourth electrode layer 8 When the material of fourth electrode layer 8 is doped with metal, the thickness of fourth electrode layer 8 is greater than or equal to 50 ⁇ and less than or equal to 200 ⁇ , the fourth electrode layer 8 is an overall continuous planar electrode, and the transmittance of fourth electrode layer 8 is greater than 50%. When the material of fourth electrode layer 8 is doped with metal, and the thickness of fourth electrode layer 8 is greater than or equal to 50 ⁇ and less than or equal to 200 ⁇ , the fourth electrode layer 8 is an overall continuous planar electrode, and the transmittance of fourth electrode layer 8 is greater than 60%.
  • fourth electrode layer 8 has a single-layer structure
  • the material of the single-layer metal layer is Al or Ag
  • the material of the single-layer metal mixture layer is Mg, Ag or Al-doped metal mixed material
  • the material of single-layer transparent metal oxide layer is ITO or IZO.
  • the first OLED region A includes a plurality of first pixel openings 601
  • the second OLED region B includes a plurality of second pixel openings 602 .
  • a portion of the first light emitting structure layer is disposed in each of the plurality of first pixel openings 601
  • a portion of the second light emitting structure layer is disposed in each of the plurality of second pixel openings 602 .
  • the pixel openings are formed by a pixel defining layer (not shown) formed on first electrode layer 4 and third electrode layer 5 , and a light emitting area is determined by a size of each pixel opening.
  • first light emitting structure layer and the second light emitting structure layer are formed on a portion of the pixel defining layer without pixel openings.
  • An arrangement pattern of second pixel openings 602 is same as an arrangement pattern (or arrangement manner) of first pixel openings 601 .
  • both the first OLED region A and the second OLED region B are AMOLED (Active Matrix Organic Light Emitting Diode) areas.
  • a size of second pixel openings 602 is same as a size of first pixel openings 601 .
  • the driving circuit of first electrode layer 4 in the first OLED region and the driving circuit of third electrode layer 5 in the second OLED region may both be 7T1C (7 transistors and 1 capacitor) driving circuits.
  • the driving circuit of third electrode layer 5 in the second OLED region is a 2T1C driving circuit; or, the driving circuit of third electrode layer 5 in the second OLED region includes a TFT.
  • the array substrate includes scan lines and data lines.
  • the driving circuit of third electrode layer 5 in the second OLED region includes a TFT
  • the data line is electrically connected with a source of the TFT
  • the third electrode layer is electrically connected with a drain of the TFT
  • the scan line is electrically connected with a gate of the TFT.
  • the scan line is used to control the on and off of the driving circuit
  • the data line is used to, when the driving circuit is turned on, provide driving current to the third electrode layer to control the light emitting structure layer to emit light.
  • a number of switching components (for example, transistors) in the driving circuit is reduced to two or one.
  • the first OLED region is an AMOLED area
  • the second OLED region is an AMOLED area or a PMOLED (Passive matrix Organic Light Emitting Diode) area.
  • the data line is electrically connected with the drain of the TFT
  • the third electrode layer is electrically connected with the source of the TFT
  • the scan line is electrically connected with the gate of the TFT.
  • a size of each of the plurality of second pixel openings 602 a in the second OLED region B 1 is larger than a size of each of the plurality of first pixel openings 601 a in the first OLED region A 1 .
  • the third electrode layer of the second OLED region B 1 includes a plurality of strip-shaped third electrodes 51 a , as shown in FIG. 13 .
  • Each strip-shaped third electrode 51 a corresponds to a plurality of second light emitting structures of second light emitting structure layer 62 , and each strip-shaped third electrode 51 a corresponding to the plurality of second light emitting structures may be driven by one same driving circuit, thereby the number of driving circuits is reduced.
  • Second pixel openings 602 and 602 a shown in FIG. 11 and FIG. 12 have a square shape. In other embodiments, the shape of the second pixel openings is circular, oval, or dumbbell-shaped.
  • the second OLED region B 2 when the size of the second pixel openings is larger than the size of the first pixel openings, the second OLED region B 2 includes at least two display areas arranged sequentially from a center region to an outer region in the second OLED B 2 , and in two adjacent display areas, the size of the second pixel openings in a display area close to the center region is smaller than the size of the second pixel openings in a display area away from the center region.
  • the second OLED region B 2 includes a first display area B 21 , a second display area B 22 and a third display area B 23 arranged sequentially from the center region to the outer region in the second OLED region B 2 .
  • a size of each of a plurality of second pixel openings 6021 b in first display area B 21 is smaller than a size of each of a plurality of second pixel openings 6022 b in second display area B 22
  • the size of each of the plurality of second pixel openings 6022 b in second display area B 22 is smaller than a size of each of a plurality of second pixel openings 6023 b in third display area B 23 .
  • the second OLED region B 2 may be provided with only the first display area and the second display area, or may be provided with more display areas.
  • the size of the second pixel openings 6021 b in the first display area is larger than the size of first pixel openings 601 b .
  • the size of the second pixel openings in the center region of the second OLED region B may also be equal to the size of the first pixel openings.
  • a second distance between a first outer contour of projection of second mask opening 21 b in the above sub-mask on substrate 3 and a second outer contour of projection of second pixel opening 602 on substrate 3 mask is d2
  • a first distance between a third outer contour of projection of first mask opening 11 b in the above sub-mask on substrate 3 and a fourth outer contour of projection of first pixel opening 601 on substrate 3 mask is d1, where d2 is larger than d1.
  • the range of d1 is 3 ⁇ m-6 ⁇ m
  • the range of d2 is 8 ⁇ m-15 ⁇ m.
  • the strength of first mask region 1 b of the sub-mask is approximately equal to the strength of second mask region 2 b of the sub-mask, which is beneficial to eliminate the risk of color mixing between the first OLED region and the second OLED region of the array substrate.
  • the present application also provides a display screen 200 .
  • the display screen includes an array substrate 100 and an encapsulation structure 201 covering a surface of the array substrate.
  • a photosensitive component such as a camera and a sensor may be provided below the second OLED region B, and the photosensitive component may collect external light transmitting through the transparent second OLED region B.
  • a display function is realized while performance of the photosensitive component is ensured.
  • the present application further provides a display device.
  • the display device includes a device main body C and a display screen 200 covering the device main body.
  • the display device may be a device such as a mobile phone, a tablet computer, a notebook computer, etc.
  • the device main body C may include components such as a housing, a circuit board, a battery, a processor, etc.
  • the device main body C has a component area 300 .
  • the component area is located below the second OLED region, and the component area 300 is provided with a photosensitive component D that collects light transmitting through the second OLED region. Due to the high light transmittance of the second OLED region, collecting enough light by the photosensitive component may be ensured, thereby the performance of the photosensitive component is ensured.

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