WO2020151375A1 - 显示器件的驱动方法及显示器件 - Google Patents

显示器件的驱动方法及显示器件 Download PDF

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Publication number
WO2020151375A1
WO2020151375A1 PCT/CN2019/123036 CN2019123036W WO2020151375A1 WO 2020151375 A1 WO2020151375 A1 WO 2020151375A1 CN 2019123036 W CN2019123036 W CN 2019123036W WO 2020151375 A1 WO2020151375 A1 WO 2020151375A1
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Prior art keywords
time
data
signal
display device
gate
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PCT/CN2019/123036
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English (en)
French (fr)
Inventor
魏雪琴
聂春扬
戴珂
李瑞莲
朱立新
闫冰冰
杨燕
黄文杰
洪青桦
孙伟
刘蕊
陈明
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19911184.0A priority Critical patent/EP3916712A4/en
Priority to CN201980002806.5A priority patent/CN112005295B/zh
Priority to US16/767,000 priority patent/US11322111B2/en
Publication of WO2020151375A1 publication Critical patent/WO2020151375A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the embodiment of the present disclosure relates to a driving method of a display device and a display device.
  • a general thin film transistor liquid crystal display includes an array substrate, a counter substrate, and a liquid crystal layer located between the array substrate and the counter substrate.
  • the electrodes on the array substrate drive the deflection of the liquid crystal molecules in the liquid crystal layer, thereby realizing the display function.
  • a thin film transistor liquid crystal display includes a plurality of gate lines and a plurality of data lines intersecting each other to define a plurality of pixel units, each pixel unit includes a thin film transistor and a pixel electrode, and the gate of the thin film transistor is connected to the corresponding gate line , The source of the thin film transistor is connected to the corresponding data line, and the drain of the thin film transistor is connected to the pixel electrode.
  • the embodiment of the present disclosure provides a driving method of a display device and a display device.
  • the driving method of the display device includes: respectively inputting a gate signal with a length of a first time to the gate line; and respectively inputting a data signal to the data line to drive the display device to display, and the signal input terminal along the gate line to the signal input terminal far away In the direction of one end, relative to the start time of inputting the data signal to the data line closest to the signal input terminal, the start time of inputting the data signal to the data line far from the signal input terminal is delayed by a second time, and the second time is less than the first time.
  • At least one embodiment of the present disclosure provides a method for driving a display device, wherein the display device includes a plurality of gate lines and a plurality of data lines arranged in a cross, each of the gate lines includes a signal input terminal, and the driving method includes: Respectively input a gate signal with a length of the first time to the gate line; and respectively input a data signal to the data line to drive the display device to display, and a signal input terminal along the gate line to a distance away from the signal In the direction of one end of the input terminal, among the M data lines crossing the gate line, relative to the start time of inputting the data signal to the first data line closest to the signal input terminal of the gate line, The start time of the input data signal of the m-th data line is delayed by a second time, and the second time is less than the first time, wherein M and m are both positive integers greater than or equal to 2, and m is less than or equal to M.
  • the multiple data lines include N data line groups, and in each data line group, the start of inputting a data signal to each data line At the same time, along the direction from the signal input end of the gate line to the end far away from the signal input end, the second time in the N data line groups increases as the distance from the signal input end increases Gradually increase, N is a positive integer greater than or equal to 1.
  • the n is a positive integer, and 1 ⁇ n ⁇ N.
  • the overall delay time TCLK of each gate line satisfies the following formula:
  • TCLK (2j ⁇ Tj+2j-1 ⁇ Tj-1+...+22 ⁇ T2+21 ⁇ T1+20 ⁇ T0+k) ⁇ 2t
  • t is the signal clock period
  • k is the correction base
  • T0, T1, T2 together with Tj has a value range of 1 or
  • j has a value range of 4-8
  • k has a value range of 0-10 .
  • the value of j is 4, 6, or 8.
  • the display device includes N source drivers configured to load the data signal to the plurality of data lines, and the driving method includes: The N source drivers drive the N data line groups respectively.
  • the plurality of gate lines include a plurality of first gate lines and a plurality of second gate lines arranged in one-to-one correspondence, and the The signal input terminal is located at the first edge of the display device, and the signal input terminal of the second gate line is located at the second edge of the display device opposite to the first edge.
  • the second gate line is configured to load the gate signals of the same timing.
  • the first gate lines and the second gate lines arranged in a one-to-one correspondence are connected.
  • the display device further includes: a plurality of pixel units defined by the intersection of the plurality of gate lines and the plurality of data lines, each of the pixel units It includes a thin film transistor, the gate of the thin film transistor is connected to the gate line, and the source of the thin film transistor is connected to the data line.
  • the gate signal is a first pulse signal; the data signal is a second pulse signal.
  • the inputting data signals to the data lines separately further includes:
  • the start time of inputting the negative polarity data signal to the mth data line is delayed by a second time
  • the The start time for s data lines to input a positive polarity data signal is delayed by a third time
  • the second time and the third time are both less than the first time
  • the second time is greater than the third time
  • the difference between the second time and the third time is less than the effective level duration in one data signal period; where m and s are both positive integers greater than or equal to 2, and both m and s are less than or equal to M.
  • the difference between the second time and the third time is ⁇ t, and the ⁇ t is equal to the off time of the switching device corresponding to the negative polarity data signal The time difference of the off time of the switching device corresponding to the positive polarity data signal.
  • the m ⁇ s, the start time of inputting the negative polarity data signal to the mth data line is delayed by the second time
  • the The start time of the positive polarity data signal input to the sth data line is delayed by the third time
  • the second time is greater than the third time
  • the difference between the second time and the third time is less than one data The effective level duration in the signal period.
  • the m s, the first frame delayed from the start time of the negative polarity data signal input to the m-th data line in the first frame
  • the second time is greater than the third time delayed from the start time of inputting the positive polarity data signal to the s-th data line in the second frame, and the difference between the second time and the third time is less than one data The effective level duration in the signal period.
  • At least one embodiment of the present disclosure provides a display device, which includes a plurality of gate lines and a plurality of data lines arranged crosswise, each of the gate lines includes a signal input terminal, the display device further includes a driver, the driver is configured to For driving the display panel to display, the driver includes: at least one gate driver configured to respectively input a gate signal having a length of a first time to the gate line; and at least one source driver configured to respectively The data line inputs data signals to drive the display device to display, along the signal input end of the gate line to the end far away from the signal input end, and along the signal input end of the gate line to the end far away from the signal input end In the direction of one end, among the M data lines crossing the gate line, relative to the start time of inputting the data signal to the first data line closest to the signal input end of the gate line, the direction The start time of the input data signal of each of the data lines is delayed by a second time, and the second time is less than the first time, wherein M and m are both positive integer
  • the driver further includes: a delay driver configured to make the source driver move from the signal input terminal along the gate line to the end far away from the signal input terminal , In the direction from the signal input end of the gate line to the end far away from the signal input end, among the M data lines crossing the gate line, relative to the first line closest to the signal input end
  • the start time of the data signal input to the data line, the start time of the data signal input to the m-th data line is delayed by a second time, the second time is less than the first time, wherein both M and m are greater than A positive integer equal to 2, m is less than or equal to M.
  • the plurality of data lines includes N data line groups
  • the at least one source driver includes N source drivers, and is configured to load the plurality of data lines.
  • the N source drivers are configured to drive N data line groups, respectively, along the direction from the signal input end of the gate line to the end far away from the signal input end, in the N data line group The second time of gradually increases as the distance from the signal input terminal increases.
  • the source driver is further configured to input a positive polarity data signal or a negative polarity data signal to the data line;
  • the start time of inputting the negative polarity data signal to the mth data line is delayed by a second time
  • the The start time of s data lines inputting a positive polarity data signal is delayed by a third time
  • the second time is greater than the third time
  • the second time and the third time are both less than the first time
  • the difference between the second time and the third time is less than the effective level duration in one data signal period; where m and s are both positive integers greater than or equal to 2, and both m and s are less than or equal to M.
  • the driver further includes a delay driver configured to make the source driver move from the signal input terminal along the gate line to the end far away from the signal input terminal , Relative to the start time of inputting a data signal to the first data line closest to the signal input terminal, the start time of inputting a negative data signal to the mth data line is delayed by a second time, and The start time of each of the data lines inputting a positive polarity data signal is delayed by a third time, the second time is greater than the third time, and the difference between the second time and the third time is less than one data signal period The effective level duration within.
  • a delay driver configured to make the source driver move from the signal input terminal along the gate line to the end far away from the signal input terminal , Relative to the start time of inputting a data signal to the first data line closest to the signal input terminal, the start time of inputting a negative data signal to the mth data line is delayed by a second time, and The start time of each of the data lines inputting a positive polarity
  • the delay driver includes a timing controller, and the timing controller is configured to output a data transmission control signal
  • the source driver further includes a reserved register configured to control the start time of the positive polarity data signal or the negative polarity data signal in response to the data transmission control signal, so that the The start time for inputting a negative polarity data signal to the data line is delayed by a second time, and the start time for inputting a positive polarity data signal to the sth data line is delayed by a third time, and the second time is greater than the third time And the difference between the second time and the third time is less than the effective level duration in one data signal period.
  • Figure 1 is a schematic diagram of a display device
  • Figure 2 is a schematic diagram of another display device
  • Fig. 3 is a simulation effect diagram of signal delay superposition of gate line and data line of a display device
  • Figure 4 is a waveform diagram of a signal on a gate line and a data line of a display device
  • FIG. 5 is a schematic plan view of a display device according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a driving method of a display device according to an embodiment of the present disclosure
  • FIG. 7 is a waveform diagram of signals on a gate line and a data line on a display device according to an embodiment of the present disclosure
  • FIG. 8 is a second time variation curve diagram of a data line group in a driving method of a display device according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram showing the compensation effect of the signal delay on the gate line and the data line by a driving method of a display device according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a driver according to an embodiment of the present disclosure.
  • Figure 11 is a waveform diagram of the positive and negative data signals of the Oxide panel
  • Figure 12 is a waveform diagram of the gate signal of the Oxide panel
  • FIG. 13 is a waveform diagram of an ideal data signal and a gate signal near the gate driver
  • FIG. 14 is a waveform diagram of an ideal data signal and a gate signal far from the gate driver
  • 15 is a waveform diagram of the attenuated data signal and the gate signal near the gate driver
  • 16 is a waveform diagram of the attenuated data signal and the gate signal far from the gate driver
  • 17 is a waveform diagram of the attenuated data signal and the gate signal far from the gate driver in the driving method of the display device provided by an embodiment of the present disclosure
  • FIG. 18 is a schematic diagram of another driver provided according to an embodiment of the present disclosure.
  • 4K display devices (4K resolution display devices, 4K resolution can include 4096 ⁇ 3112, 3656 ⁇ 2664 and other standards) are becoming increasingly saturated in the display market, and 8K display devices have become Research hotspots of major manufacturers.
  • the resolution of 8K reaches the pixel size of 7680 ⁇ 4320, which is 4 times the resolution of 4K, which can bring fine and high-quality picture quality.
  • Fig. 1 is a schematic diagram of a display device
  • Fig. 2 is a schematic diagram of another display device.
  • the display device includes a display panel 100, a gate driver 200, and a source driver 300.
  • the display panel 100 includes an array substrate, a counter substrate, gate lines, and data lines;
  • the gate driver 200 may be a GOA (Gate On Array) circuit, which is arranged on the array substrate, and may be arranged on two opposite edges of the display device to make The signal on the driving gate line may propagate from two opposite edges of the display device to the middle of the display device;
  • the source driver 300 may be a chip on film (COF).
  • Figure 1 shows a schematic diagram of the signal delay on the data line. As shown in Figure 1, in the extension direction of the data line, relative to the signal on the part of the data line close to the signal input terminal, the signal on the part of the data line far from the signal input terminal, that is, the signal on the part far away from the source driver 300 will be There is a delay.
  • Figure 2 shows a schematic diagram of the signal delay on the gate line.
  • the signal on the part of the gate line far from the signal input terminal that is, the signal on the part far away from the gate driver 200, will be relative to the signal on the part of the gate line close to the signal input terminal. There is a delay.
  • FIG. 3 shows a simulation effect diagram of signal delay superposition on the gate line and the data line of a display device.
  • the signal delay of the gate line and the signal delay of the data line are superimposed, the signal on the end of the gate line far from the signal input end of the gate line and the signal on the end of the data line far away from the signal input end of the data line Will not match, resulting in insufficient charging time, resulting in insufficient charging.
  • the Block splitting phenomenon and Mura defect in the triangle area in Figure 3 are more obvious.
  • Fig. 4 shows a waveform diagram of signals on the gate line and the data line of a display device.
  • the signal on the part of the gate line close to the signal input terminal is shown as line 1 in Figure 4
  • the signal on the part of the gate line far from the signal input terminal is shown as line 2 in Figure 4, due to the impedance of the gate line, etc. Therefore, the signal on the part of the gate line away from the signal input terminal will be delayed and deformed.
  • the voltage of the signal on the gate line is greater than a certain value (for example, V 0 )
  • the thin film transistor can be turned on, causing the gate line to be far away from the signal input
  • the effective charging time of the signal on the part of the terminal is less than the effective charging time of the signal on the part of the gate line close to the signal input terminal.
  • the effective charging area of the data signal and the signal on the part of the gate line close to the signal input terminal is larger than that of the data signal and the part of the gate line far from the signal input terminal
  • the effective charging area of the signal above results in that the charging time of the pixel unit corresponding to the part of the gate line far from the signal input terminal is shorter than the charging time of the pixel unit corresponding to the part of the gate line close to the signal input terminal, and the charging effect is larger.
  • the embodiments of the present disclosure provide a driving method, a driver, and a display device of a display device.
  • the display device includes a plurality of gate lines and a plurality of data lines arranged crosswise, each gate line includes a signal input terminal, and the driving method includes: inputting gate lines with a length of a first time to the gate lines respectively.
  • the start time of the input data signal of the first data line closest to the signal input end of the gate line, the start time of the data signal input to the mth data line is delayed by a second time, and the second time is less than the first time, where M, m Both are positive integers greater than or equal to 2, and m is less than or equal to M, so that the signal on the data line can match the signal attenuation and delay of the gate line, thereby reducing the data line corresponding to the signal input end of the gate line closer on the one hand
  • the charging time of the pixel unit on the other hand, the charging time of the pixel unit corresponding to the data line that is farther from the signal input end of the gate line is increased, so that the pixel unit arranged along the extension direction of the gate line in the entire display device is The uniformity of charging time is improved,
  • FIG. 5 is a schematic plan view of a display device according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a driving method of a display device according to an embodiment of the present disclosure.
  • FIG. 7 is a waveform diagram of a signal on a gate line and a data line on a display device according to an embodiment of the present disclosure.
  • the display device includes a plurality of gate lines 120 and a plurality of data lines 130 arranged crosswise, each gate line 120 includes a signal input terminal 127, and the plurality of data lines 130 are arranged along the extending direction of the gate line 120, such as As shown in FIG. 6, the driving method includes the following steps S501-S502.
  • S501 Input gate signals with a length of the first time to the gate lines respectively. It should be noted that the aforementioned “length” refers to the duration of the gate signal.
  • S502 Input data signals to the data lines respectively to drive the display device for display, along the direction from the signal input end of the gate line to the end far away from the signal input end, among the M data lines crossing the gate line, relative to the closest direction
  • the start time of the data signal input to the first data line of the signal input end of the gate line, the start time of the data signal input to the m-th data line is delayed by a second time, and the second time is less than the first time, where M and m are both A positive integer greater than or equal to 2, and m is less than or equal to M.
  • the data line for comparing the on-times mentioned above corresponds to one of the multiple gate lines; that is, when a gate signal with a length of the first time is input to one of the multiple gate lines, along the gate From the signal input end of the line to the end far away from the signal input end, among the M data lines crossing the gate line, relative to the start time of inputting the data signal to the first data line closest to the signal input end of the gate line,
  • the start time of inputting a data signal to the m-th data line is delayed by a second time, and the second time is less than the first time, where both M and m are positive integers greater than or equal to 2, and m is less than or equal to M.
  • the signal on the part of the gate line close to the signal input terminal is shown as line 1 in FIG. 7, and the signal on the part of the gate line far from the signal input terminal As shown by line 2 in Figure 7, due to the impedance of the gate line and other reasons, the signal on the part of the gate line far from the signal input terminal will be delayed and deformed.
  • the voltage of the signal on the gate line is greater than a certain value (for example, V 0 )
  • V 0 In order to turn on the thin film transistor, which causes the effective charging time of the signal on the part of the gate line far from the signal input terminal to be less than the effective charging time of the signal on the part of the gate line close to the signal input terminal.
  • the effective charging area of the data signal and the signal on the part of the gate line close to the signal input terminal is larger than that of the data signal and the gate line
  • the effective charging area of the signal on the part far away from the signal input terminal on the upper part of the gate line causes the charging time of the pixel unit corresponding to the part of the gate line close to the signal input terminal to be shorter than the charging time of the pixel cell corresponding to the part of the gate line far from the signal input terminal.
  • the effect is quite different; and when the data signal shown in line 4 (the data signal of the present disclosure) is input to the data line through the source driver, the data signal is delayed for a second time relative to the data line shown in line 3, namely Relative to the start time of the data signal input to the m-th data line, the second time is delayed by a second time, which is less than the first time, so that the signal on the data line can match the signal attenuation and delay of the gate line, thereby increasing the distance from the gate line
  • first time and the second time in the present disclosure both refer to a time period, rather than a certain moment.
  • the plurality of data lines 130 may be divided into N groups of data line groups 135, that is, the plurality of data lines 130 include N groups of data line groups 135.
  • the start time of data signal input to each data line 130 is the same, that is, in each data line group 135, there is no delay between the start time of data signal input to each data line 130.
  • the second time in the N data line groups gradually increases as the distance from the signal input terminal increases. As the distance from the signal input terminal increases, the delay of the signal on the gate line also gradually increases.
  • the overall uniformity of the charging time of the pixel units arranged along the extension direction of the gate line in the display device further reduces or even eliminates the block splitting phenomenon caused by uneven charging and the mura defect caused by uneven charging rate.
  • the uniformity of the charging time of the pixel units arranged in the extending direction of the gate line further reduces or even eliminates the block splitting phenomenon caused by uneven charging and the mura defect caused by uneven charging rate.
  • n is a positive integer, and 1 ⁇ n ⁇ N.
  • the overall delay time T CLK of each gate line satisfies the following formula:
  • T CLK (2 j ⁇ T j +2 j-1 ⁇ T j-1 +...+2 2 ⁇ T 2 +2 1 ⁇ T 1 +2 0 ⁇ T 0 +k) ⁇ 2t,
  • t is the signal clock period
  • k is the correction base
  • the value range of T j is 1 or 0, the value range of j is 4-8, and the value of k
  • the range is 0-10.
  • the value range of the aforementioned signal clock period t may be 5-10 ⁇ s.
  • the value of j is 4, 6, or 8.
  • the value of j is 4, the amount of calculation is small.
  • the value of j is 8, the overall delay time of the gate line is larger, which is suitable for calculation of larger size and higher resolution display devices and has better effect. it is good.
  • the display device includes N source drivers 300 configured to load data signals to a plurality of data lines 130.
  • the driving method includes: using N source drivers 300 to drive N data line groups 135 respectively. Therefore, there is no delay between the start time of each source driver 300 inputting the data signal to each data line 130, and the start time of the data line 130 inputting the data signal of different source drivers 300 is different, so that the calculation pressure of each source driver 300 can be reduced. .
  • the display device further includes a plurality of pixel units 140 defined by the intersection of a plurality of gate lines 120 and a plurality of data lines 130, and each pixel unit 140 includes a thin film transistor 150.
  • the gate 151 is connected to the gate line 120
  • the source 152 of the thin film transistor 150 is connected to the data line 130.
  • the gate signal on the gate line 120 can turn on the thin film transistor 150, so that the data signal on the data line 130 can flow from the source 152 of the thin film transistor 150 to the drain 153 of the thin film transistor 150, and be loaded on the pixel electrode (not shown) ⁇ ) ⁇
  • the gate signal is a first pulse signal; the data signal is a second pulse signal.
  • the plurality of gate lines 120 includes a plurality of first gate lines 121 and a plurality of second gate lines 122 arranged in one-to-one correspondence, and the signal input terminal 1217 of the first gate line 121 is located at the first gate line of the display device.
  • the signal input terminal 1227 of the second gate line 122 is located at the second edge 162 of the display device opposite to the first edge 161, and the correspondingly arranged first gate line 121 and the second gate line 122 are configured to load the same timing The gate signal.
  • first gate lines 121 and the second gate lines 122 arranged in a one-to-one correspondence may also be connected. It should be noted that, at this time, the first gate line 121 and the second gate line 122 can independently calculate the overall delay time, or can calculate the overall delay time separately.
  • the first gate line 121 and the second gate line 122 arranged in one-to-one correspondence can be used as a whole to calculate the overall delay time T CLK , and the data line 130 arranged across the first gate line 121 can be divided It is an N/2 data line group, and the data lines 130 disposed across the second gate line 122 can be divided into N/2 groups.
  • FIG. 8 is a graph showing a second time variation of a data line group in a method for driving a display device according to an embodiment of the present disclosure.
  • the value of N can be 24, that is, the data line includes 24 data line groups; at this time, from the signal input end of the first gate line to the direction away from the signal input end, it crosses the first gate line
  • the second time of the set N/2 data line groups can be respectively: 0, T CLK /N, 2T CLK /N,...(N/2-1)T CLK /N; signal input from the second gate line From the end to the direction away from the signal input end, the second time of the N/2 data line groups intersecting the second gate line can be: 0, T CLK /N, 2T CLK /N, ...
  • FIG. 9 is a schematic diagram of the compensation effect of the signal delay on the gate line and the data line by a driving method of a display device according to an embodiment of the present disclosure.
  • the delay compensation area formed by the second time variation curve of the data line group as shown in FIG. 9 can just match the triangular area where the signal delay and superimposition of the gate line and the data line shown in FIG. 3, so as to realize the entire display device.
  • the charging rate or uniformity of the charging effect of the pixel unit is maximized, thereby improving the block splitting phenomenon caused by uneven charging and the mura defect caused by uneven charging rate.
  • the slope of the second time variation curve of the data line group in FIG. 8 can be adjusted according to actual conditions, and the magnitude of the slope can be determined according to the driving capability of the source driver. The higher the slope, the larger the size of the second time, which can be specifically determined according to the impedance of the data line of the display device.
  • the second time change curve of the data line group may be continuous or discontinuous, it may be a straight line with a consistent slope, or a curve or a broken line with a varying slope. The embodiments of the present disclosure include but are not limited to this.
  • the second time change curve of the data line group can be changed according to the change of the signal on the gate line of the display device.
  • FIG. 10 is a schematic diagram of a driver according to an embodiment of the present disclosure.
  • the driver 700 includes at least one gate driver 200 and at least one source driver 300; the gate driver 200 is configured to input a gate signal with a length of a first time to the gate line; the source driver 300 is configured to respectively
  • the data line inputs a data signal to drive the display device to display, along the signal input end of the gate line to the end far away from the signal input end, relative to the start time of the data signal input to the data line closest to the signal input end, to the direction away from the signal input end
  • the start time of the data line input data signal is delayed by the second time, the second time is less than the first time, so that the signal on the data line can match the signal attenuation and delay of the gate line, thereby increasing the distance from the signal input end of the gate line.
  • the charging time of the pixel unit corresponding to the far data line improves the uniformity of the charging time of the pixel unit arranged along the extension direction of the gate line in the entire display device, thereby reducing or even eliminating the block division caused by uneven charging. Screen phenomenon and Mura failure caused by uneven charging rate.
  • the driver further includes a delay driver 600 configured to cause the source driver 300 to move from the signal input terminal along the gate line to the end away from the signal input terminal, and from the signal input terminal along the gate line to the signal input terminal away from the signal.
  • a delay driver 600 configured to cause the source driver 300 to move from the signal input terminal along the gate line to the end away from the signal input terminal, and from the signal input terminal along the gate line to the signal input terminal away from the signal.
  • the start time of the input data signal is delayed by a second time, which is less than the first time, where M and m are both positive integers greater than or equal to 2, and m is less than or equal to M.
  • the gate driver and the source driver can be the usual gate driver and source driver.
  • the delay driver 600 is added to make the source driver 300 move from the signal input end along the gate line to the end far away from the signal input end.
  • the delay driver 600 is added to make the source driver 300 move from the signal input end along the gate line to the end far away from the signal input end.
  • the delay driver 600 is added to make the source driver 300 move from the signal input end along the gate line to the end far away from the signal input end.
  • the delay driver 600 is added to make the source driver 300 move from the signal input end along the gate line to the end far away from the signal input end.
  • the start time of the signal, the start time of inputting the data signal to the m-th data line is delayed by a second time, and the second time is less than the first time.
  • the plurality of data lines includes N data line groups
  • at least one source driver 300 includes N source drivers 300 configured to load data signals to the plurality of data lines
  • the N source drivers 300 are configured to
  • the N data line groups are driven respectively along the signal input end of the gate line to the end away from the signal input end, and the second time in the N data line groups gradually increases as the distance from the signal input end increases.
  • An embodiment of the present disclosure further provides a display device, including any of the above-mentioned drivers, so that the uniformity of the charging time of the pixel units arranged along the extension direction of the gate line in the entire display device can be improved, thereby reducing or even eliminating Block split screen phenomenon caused by uneven charging and Mura failure caused by uneven charging rate.
  • the display device may be a product with a display function such as a TV, a computer, a navigator, a notebook computer, a mobile phone, and an electronic photo album.
  • a display function such as a TV, a computer, a navigator, a notebook computer, a mobile phone, and an electronic photo album.
  • the resolution of the display device is Ultra High Definition (UHD), for example, the resolution is greater than or equal to 4K*2K.
  • the resolution of the display device is greater than or equal to 8K*4K.
  • 4K*2K means having a physical resolution of 3840 ⁇ 2160
  • 8K*4K means having a physical resolution of 7680 ⁇ 4320.
  • the above example illustrates delaying the start time of data signal input to the data line to eliminate block splitting caused by uneven charging and Mura defects caused by uneven charging rate.
  • the delay of the start time of the input data signal in the present disclosure may mean delaying the start time of the data signal of all data lines except the first data line closest to the gate signal input terminal, or only The start time of the data signal of the part of the data line except the first data line closest to the gate signal input terminal is delayed, and the other part is not delayed.
  • Figure 11 specifically shows the simulation waveform of the positive and negative data signals of the Oxide panel.
  • the upper half of the curve in the figure is the voltage waveform of the positive data signal
  • the lower half of the curve is the voltage waveform of the negative data signal.
  • 1 represents the data signal waveform of the data line close to the source driver
  • p 2 and p 3 both represent the data signal waveforms of the data lines in two different columns far away from the source driver. It can be seen that the signal of the data line close to the source driver is approximately Square wave, and the data line signal far away from the source driver has been distorted and changed into an approximately sinusoidal waveform. The farther away from the source driver the more serious the waveform distortion of the data signal.
  • L 1 represents a curve close to the gate drive signal of the gate line
  • L 2 represents a signal from the gate driver
  • the gate can be seen also in the transmission of the signal waveform Distortion will occur and it will change into an arc wave.
  • the voltage change is gradually decreasing.
  • the gate signal L drops vertically or approximately vertically.
  • the gate signal voltage Vg should be reduced to positive data at approximately the same time.
  • the signal voltage Vs and the negative data signal voltage Vs that is, the TFT corresponding to the positive data signal will be turned off at the intersection a of the gate signal L and the positive data line signal P'in the figure, and the negative data signal corresponds to The TFT will be turned off at the intersection point b of the gate signal L and the negative data signal P" in the figure.
  • Point a and point b correspond to the same time, that is, the TFTs corresponding to the positive and negative data signals are turned off at the same time of.
  • the gate signal L has a slope due to attenuation.
  • the gate signal L first decreases to point a intersecting with the positive data signal P', and the positive data signal corresponds to TFT turns off; then the gate signal L drops to point b where it intersects with the negative data signal P", and then the TFT corresponding to the negative data signal turns off.
  • the time corresponding to point a is earlier than point b
  • the corresponding time that is, the TFT corresponding to the positive data signal is turned off earlier than the TFT corresponding to the negative data signal.
  • the gate signal drops vertically or close to vertical.
  • the gate signal voltage Vg should be reduced to less than the positive polarity at the same time.
  • the Vs corresponding to the data signal and the Vs corresponding to the negative data signal that is, the TFT corresponding to the positive data signal and the negative data signal are turned off at the same time, that is, the TFT corresponding to the positive data signal will be shown in the figure
  • the gate signal L and the positive data signal P'are turned off at point a, and the TFT corresponding to the negative data signal will be turned off at the point b where the gate signal L and the negative data signal P" intersect, point a Corresponds to the same moment as point b.
  • the TFTs corresponding to the positive data signal and the negative data signal are not turned off at the same time.
  • the gate signal L has a slope due to attenuation.
  • the gate signal L first drops to point a intersecting with the positive data signal P', and the TFT corresponding to the positive data signal Turn off; then the gate signal L drops to point b where it intersects with the negative data signal P", and the TFT corresponding to the negative data signal turns off.
  • the time corresponding to point a is earlier than the time corresponding to point b, that is, the positive data
  • the corresponding TFT turns off earlier than the TFT corresponding to the negative polarity data.
  • the attenuation of the gate signal will cause the TFT corresponding to the positive polarity data to turn off earlier than the TFT corresponding to the negative polarity data.
  • Vth is 0V.
  • Vth is not 0V, for example, when Vth is 1V, it means that when Vg-Vs ⁇ 1V, the TFT will be turned off.
  • the gate signal voltage drops to slightly greater than the data signal voltage, the TFT will turn off.
  • the TFT corresponding to the positive data signal is turned off at the position before the intersection a of the gate signal L and the positive data signal P', and the TFT corresponding to the negative data signal is also at the gate signal L and The position before the intersection point b of the negative polarity data signal P" turns off.
  • the turn-off time of the TFT corresponding to the positive polarity data is still earlier than the turn-off time of the TFT corresponding to the negative polarity data. It will not be repeated here.
  • the simulation experiment on the Oxide panel shows that at the position far away from the source driver as shown in Figure 16, the turn-off time of the TFT corresponding to the positive data signal is about 1.8 ⁇ s, and the turn-off time of the TFT corresponding to the negative data signal At about 2.2 ⁇ s, the time difference ⁇ t between the two turn-offs is about 0.4 ⁇ s.
  • TFT corresponding to the positive data signal is turned off earlier than the TFT corresponding to the negative data signal.
  • a simulation experiment was performed on a-Si display panel. At a location far away from the source driver, the TFT turn-off time corresponding to the positive data signal is about 1.8 ⁇ s, and the TFT turn-off time corresponding to the negative data signal is about 2.5 ⁇ s, positive and negative.
  • the turn-off time difference ⁇ t of the polarity data signal is approximately 0.7 ⁇ s.
  • the negative polarity data signal will be longer than the positive polarity data signal during charging, which will cause inconsistent pixel display effects.
  • the charging time is extremely precious. The difference in charging time of 0.4 ⁇ s-0.7 ⁇ s will greatly reduce the charging efficiency of the pixel and affect the high-frequency display effect.
  • the charging time of the pixel column receiving the positive polarity data signal is short, while the charging time of the pixel column receiving the negative polarity data signal is long.
  • the charging time of the positive polarity data signal in the previous frame is short, and the charging time of the negative polarity data signal in the next frame is long, which will also cause display abnormalities and affect the display effect.
  • the display device driving method of the embodiment of the present disclosure has been further improved, that is, in the method, respectively inputting data signals to the data lines further includes:
  • the start time of inputting the negative polarity data signal to the m-th data line is delayed by a second time, and to the s-th data line
  • the start time of the input positive data signal is delayed by the third time, the second time and the third time are both less than the first time, the second time is greater than the third time, and the difference between the second time and the third time is less than Effective level duration in one data signal period;
  • n and s are both positive integers greater than or equal to 2, and both m and s are less than or equal to M.
  • the present application delays the start time of the negative data signal by a time greater than the start time of the positive data signal, that is, delays the negative data signal relative to the positive data signal into the data line , Thus shortening the negative data charging time, keeping the positive and negative data signal charging duration consistent, offsetting the difference in charging time.
  • both the second time and the third time represent a time period.
  • the third time can be equal to 0 or greater than 0. Since the second time is greater than the third time, the second time must be greater than 0. That is to say, the scheme includes two cases.
  • the time is more delayed than the start time of the positive polarity data signal (second time>third time).
  • the first case is taken as an example for specific description.
  • FIG. 17 shows a waveform diagram in which the start time of the negative data signal is delayed backward relative to the start time of the positive data signal.
  • the upper curve P'in the figure is positive.
  • the data line signal, the lower curve P" is the negative data line signal, and the arc curve L is the gate signal far away from the gate drive circuit.
  • the positive data signal input starts at the same time, and the negative
  • ⁇ t 1 needs to be less than the effective level duration in one data cycle, otherwise it means that the negative data signal is delayed too much. Before the negative data signal is input, the TFT has been turned off, resulting in no charging of the pixel, causing display abnormal.
  • the time is equal to the TFT off time corresponding to the negative polarity data signal and the TFT off time corresponding to the positive polarity data signal.
  • the charging duration of the negative polarity data signal is equal to the charging duration of the positive polarity data signal.
  • this embodiment by controlling the different start times of the positive and negative data signals input to the data line, the difference in positive and negative data charging caused by the difference in the turn-off time of the TFT is eliminated, and a uniform and stable display effect is ensured. Especially for high-frequency display technology, this method greatly improves the charging efficiency of positive and negative data when the scanning time of each line is short.
  • the start time of inputting a negative polarity data signal to the mth data line is delayed by a second time
  • the start time of inputting a positive polarity data signal to the sth data line is delayed by a third time.
  • the second time is greater than the third time
  • the difference between the second time and the third time is less than the effective level duration in one data signal period, which means that the positive polarity data signal and the negative polarity data are input to the data lines of different columns. signal.
  • the driving method of the display device can be used to adjust the charging time of two sub-pixels with opposite data polarities.
  • the two sub-pixels may include a first sub-pixel and a second sub-pixel located in different columns, that is,
  • the display driving method can be used for display driving in a column inversion mode to adjust the charging time of different sub-pixels.
  • the data line inputs positive data signals to the first part of sub-pixels and negative data signals to the second part of sub-pixels.
  • the first part of sub-pixels TFT is turned off, the second part of sub-pixels The TFT has not been completely turned off, resulting in inconsistent charging effects of the two sub-pixels and uneven display effects.
  • This embodiment can delay the overall input time of the negative data signal input to the data line, so that the positive data signal of the first part of the sub-pixels and the second part of the negative data signal of the sub-pixels have the same charging time, thereby ensuring the two parts of sub-pixels
  • the charging effect is the same, thus ensuring the same display effect.
  • the first part of the sub-pixels and the second part of the sub-pixels may be arranged alternately in sequence, or the first part of the sub-pixels and the second part of the sub-pixels may be separately arranged in regions. Regardless of the format, when the data polarity between the columns is opposite, the driving method can ensure that the display effect between the columns with the opposite data polarity is consistent.
  • first part of sub-pixels and the second part of sub-pixels are only used to divide the sub-pixels, and the correspondence between the two and the positive polarity data signal and the negative polarity data signal can also be interchanged, that is, The first part of the sub-pixels receives negative polarity data signals, and the second part of the sub-pixels receives positive polarity data signals.
  • the display driving method can also be used for display driving in the frame inversion mode.
  • the source driver inputs a positive polarity data signal to a data line in the first frame, and inputs a negative polarity data signal to the data line in the second frame.
  • the traditional frame inversion driving method since the data polarities of the first frame and the second frame are opposite, the time difference between TFT turn-off will cause the same sub-pixel to charge inconsistencies in the two frames, resulting in uneven brightness and poor display effect.
  • This embodiment can delay the start time of inputting the negative polarity data signal to the data line in the second frame, so that the charging duration of the positive polarity data signal in the first frame is consistent with the charging duration of the negative polarity data signal in the second frame. Therefore, the charging effect of the data signals in the two frames is consistent, thereby ensuring the consistent display effect.
  • first frame and the second frame are only used to divide the time, and the correspondence between the two and the positive polarity data signal and the negative polarity data signal can also be interchanged, that is, the first frame direction
  • the data line inputs a negative polarity data signal
  • the second frame inputs a positive polarity data signal to the data line.
  • the delay of the negative data signal is the overall delay, that is, the input time of the negative data signal of the entire column of sub-pixels is delayed as a whole, or the delay of all sub-pixels of the entire screen The input time of the negative data signal is delayed as a whole.
  • the gate signal will also have a relative delay, which will affect the size of ⁇ t. Therefore, in order to ensure that the adjustable range of ⁇ t can cover multiple panels at the same time, the reserved shift register should be used.
  • the adjustable range is greater than 1.5 ⁇ s.
  • the above description is based on the example that the start time of the positive polarity data signal is not delayed, and only the start time of the negative polarity data signal is delayed.
  • the positive polarity data signal is also processed When delayed (that is, the third time>0), as long as the start time of the negative data signal is further delayed compared to the start time of the positive data signal (second time>third time), the difference in charging time can also be eliminated The problem is not repeated here.
  • the source driver 300 is configured to respectively input a positive polarity data signal or a negative polarity data signal to the data line to drive the display device for display, as opposed to the signal input terminal closest to the
  • the driver 700 further includes a delay driver 600 configured to make the source driver 300 in the direction from the signal input terminal along the gate line to the end far away from the signal input terminal, relative to the direction closest to
  • a delay driver 600 configured to make the source driver 300 in the direction from the signal input terminal along the gate line to the end far away from the signal input terminal, relative to the direction closest to
  • the start time when the first data line of the signal input terminal inputs the data signal, the start time when the negative polarity data signal is input to the mth data line is delayed by the second time, and the start time when the positive polarity data signal is input to the sth data line
  • the time is delayed by a third time, and the second time is greater than the third time and less than the effective level duration in one data signal period.
  • the delay driver 600 includes a timing controller 610 configured to output data transmission control signals; the source driver 300 also includes a reserved register 310, which is configured to It is configured to control the start time of the positive polarity data signal or the negative polarity data signal in response to the data transmission control signal, so that the start time of the negative polarity data signal input to the mth data line is delayed by a second time, and the input to the sth data line
  • the start time of the positive data signal is delayed by a third time, and the second time is greater than the third time and less than the effective level duration in one data signal period.
  • the timing controller 610 is used to output a data transmission control signal specifying the timing of the data signal to the source driver 300, and the source driver 300 responds to the data transmission control signal to start the input of the data signal to the data line.
  • the time is delayed so that the data signal is input to the data line according to the preset timing. Modify the input time of negative polarity data or positive polarity data in the timing controller, and further set the corresponding register for latching and delaying the data, so as to realize the delay of the data signal.
  • the reserved register 310 set in the source driver can be used to adjust the data signal.
  • the source driver usually sets a part of the reserved register 310 to expand it under certain circumstances.
  • a shift register reserved in the source driver 300 can be used to achieve data delay or advance.
  • the shift register can sequentially shift the registered data to the left or right under the action of a clock signal, thereby realizing signal delay or advancement.
  • the reserved register 310 is an eight-bit shift register.
  • each byte will have a change of 2package (5ns), so the range of the positive and negative polarity data charging length difference ⁇ t that can be adjusted by the eight-bit shift register can reach 1.2 ⁇ s. It can meet the adjustment of a-Si display panel and Oxide display panel. It not only realizes the purpose of signal adjustment, but also does not need to set up a separate register. This method only occupies the internal reserved 1-byte register to complete the setting. New functional IP needs to be added, which consumes less resources and reduces design costs.
  • the source driver 300 may also include a shift register circuit, a latch circuit, a D/A conversion circuit, and a gamma correction circuit, etc., for outputting data signals, which will not be repeated here.
  • the display device may be a device using an amorphous silicon liquid crystal display panel or a metal oxide liquid crystal display panel. Since the charging effect of the positive and negative electrodes of these two display panels is not consistent, the problem of inconsistent charging effects is obvious.
  • the time difference ⁇ t is between 0.4 and 0.7 ⁇ s. Therefore, the above display device can achieve a more ideal display effect.
  • the display device can also use other liquid crystal panels, such as low-temperature polysilicon (p-Si) display panels, monocrystalline silicon (c-Si) display panels, etc., as long as there is a difference in the off time of the positive and negative data signals.
  • the problem of inconsistent charging time can all be driven by the driving method of the present disclosure, and will not be listed here.
  • the present disclosure does not specifically limit the application of the display device.
  • the display device can be used for any products or components with display functions such as mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, etc.

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Abstract

一种显示器件的驱动方法及显示器件。显示器件的驱动方法包括：分别向栅线（120）输入长度为第一时间的栅极信号（L）（S501）；分别向数据线（130）输入数据信号以驱动显示器件进行显示，沿栅线（120）的信号输入端（127）到远离信号输入端（127）的一端的方向，在与栅线（120）交叉的并依次间隔排布的M条数据线（130）中，相对于向最靠近栅线（120）的信号输入端（127）的第一条数据线（130）输入数据信号的开始时间，向第m条数据线（130）输入数据信号的开始时间延后第二时间，第二时间小于第一时间（S502）。该驱动方法可减弱甚至消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。

Description

[根据细则37.2由ISA制定的发明名称]　显示器件的驱动方法及显示器件
本申请要求于2019年01月25日递交的第201910074232.4号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示器件的驱动方法及显示器件。
背景技术
随着显示技术的不断发展，薄膜晶体管液晶显示器(TFT-LCD)逐渐成为市场的主流。通常的薄膜晶体管液晶显示器包括阵列基板、对置基板以及位于阵列基板和对置基板之间的液晶层。通过阵列基板上的电极驱动液晶层中的液晶分子偏转，从而实现显示功能。
通常，薄膜晶体管液晶显示器包括相互交叉设置的多条栅线和多条数据线，以限定出多个像素单元，各像素单元包括薄膜晶体管和像素电极，薄膜晶体管的栅极与对应的栅线相连，薄膜晶体管的源极与对应的数据线相连，薄膜晶体管的漏极与像素电极相连。通过向栅线输入扫描信号，向数据线输入数据信号，以分时的方式驱动该显示器进行显示。
发明内容
本公开实施例提供一种显示器件的驱动方法及显示器件。该显示器件的驱动方法包括：分别向栅线输入长度为第一时间的栅极信号；以及分别向数据线输入数据信号以驱动显示器件进行显示，沿栅线的信号输入端到远离信号输入端的一端的方向，相对于向最靠近信号输入端的数据线输入数据信号的开始时间，向远离信号输入端的数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间，从而可减弱甚至消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。
本公开至少一个实施例提供一种显示器件的驱动方法中，所述显示器件包括交叉设置的多条栅线和多条数据线，各所述栅线包括信号输入端，所述驱动方法包括：分别向所述栅线输入长度为第一时间的栅极信号；以及分别向所述数据线输入数据信号以驱动所述显示器件进行显示，沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，在与所述栅线交叉的M条所述数据线中，相对于向最靠近所述栅线的信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入数据信号的开始时间延后第二时间，所述第二时间小于所述第一时间，其中M、m均为大于等于2的正整数，m小于等于M。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述多条数据线包括N组数据线组，在各 所述数据线组中，向各所述数据线输入数据信号的开始时间相同，沿所述栅线的所述信号输入端到远离所述信号输入端的一端的方向，所述N组数据线组中的所述第二时间随着与所述信号输入端的距离增加而逐渐增加，N为大于等于1的正整数。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述驱动方法还包括：确定各所述栅线的整体延迟时间TCLK；以及将所述整体延迟时间均分为N份，所述N组数据线组中第n组数据线组中的所述第二时间y＝(n-1)×TCLK/N。所述n为正整数，且1≤n≤N。
例如，在本公开一实施例提供的显示器件的驱动方法中，各所述栅线的整体延迟时间TCLK满足以下公式：
TCLK＝(2j×Tj+2j-1×Tj-1+…+22×T2+21×T1+20×T0+k)×2t，
其中，t为信号时钟周期，k为补正基数，T0、T1、T2.....Tj取值范围是1或0，j的取值范围为4-8，k的取值范围0-10。
例如，在本公开一实施例提供的显示器件的驱动方法中，j的取值为4，6，或8。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述显示器件包括N个源驱动器，被配置为向所述多条数据线加载所述数据信号，所述驱动方法包括：使用所述N个源驱动器分别驱动所述N组数据线组。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述多条栅线包括一一对应设置的多条第一栅线和多条第二栅线，所述第一栅线的信号输入端位于所述显示器件的第一边缘，所述第二栅线的信号输入端位于所述显示器件的与第一边缘相对的第二边缘，对应设置的所述第一栅线和所述第二栅线被配置为加载同一时序的所述栅极信号。
例如，在本公开一实施例提供的显示器件的驱动方法中，一一对应设置的所述第一栅线和所述第二栅线相连。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述显示器件还包括：所述多条栅线和所述多条数据线交叉限定的多个像素单元，各所述像素单元包括薄膜晶体管，所述薄膜晶体管的栅极与所述栅线相连，所述薄膜晶体管的源极与所述数据线相连。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述栅极信号为第一脉冲信号；所述数据信号为第二脉冲信号。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述分别向数据线输入数据信号还包括：
向所述数据线输入正极性数据信号或负极性数据信号；
其中，相对于向最靠近所述信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间、第三时间均小于所述第一时间，所述第二时间大于所述第三时间， 且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长；其中m、s均为大于等于2的正整数，且m和s均小于等于M。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述第二时间和所述第三时间的差为Δt，所述Δt等于所述负极性数据信号对应的开关器件关断时间与所述正极性数据信号对应的开关器件关断时间的时间差。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述m≠s，向所述第m条数据线输入负极性数据信号的开始时间延后所述第二时间，向所述第s条数据线输入正极性数据信号的开始时间延后所述第三时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
例如，在本公开一实施例提供的显示器件的驱动方法中，所述m＝s，在第一帧时向所述第m条数据线输入负极性数据信号的开始时间延后的所述第二时间大于在第二帧时向所述第s条数据线输入正极性数据信号的开始时间延后的所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
本公开至少一个实施例提供一种显示器件，包括交叉设置的多条栅线和多条数据线，各所述栅线包括信号输入端，所述显示器件还包括驱动器，所述驱动器被配置为用于驱动所述显示面板显示，所述驱动器包括：至少一个栅驱动器，被配置为分别向所述栅线输入长度为第一时间的栅极信号；以及至少一个源驱动器，被配置为分别向所述数据线输入数据信号以驱动显示器件进行显示，沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，在与所述栅线交叉的M条所述数据线中，相对于向最靠近所述栅线的信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入数据信号的开始时间延后第二时间，所述第二时间小于所述第一时间，其中M、m均为大于等于2的正整数，m小于等于M。
例如，本公开一实施例提供的显示器件中，所述驱动器还包括：延迟驱动器，被配置为使得所述源驱动器在沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，在与所述栅线交叉的M条所述数据线中，相对于向最靠近所述信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入数据信号的开始时间延后第二时间，所述第二时间小于所述第一时间，其中M、m均为大于等于2的正整数，m小于等于M。
例如，在本公开一实施例提供的显示器件中，所述多条数据线包括N组数据线组，所述至少一个源驱动器包括N个源驱动器，被配置为向所述多条数据线加载所述数据信号，所述N个源驱动器被配置为分别驱动N组数据线组，沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，所述N组数据线组中的所述第二时间随着与所述信号输入端的距离增加而逐渐增加。
例如，在本公开一实施例提供的显示器件中，所述源驱动器还被配置为向所述数据线输入正极性数 据信号或负极性数据信号；
其中，相对于向最靠近所述信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间大于所述第三时间，所述第二时间、第三时间均小于所述第一时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长；其中m、s均为大于等于2的正整数，且m和s均小于等于M。
例如，在本公开一实施例提供的显示器件中，所述驱动器还包括延迟驱动器，被配置为使得所述源驱动器在沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，相对于向最靠近所述信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
例如，在本公开一实施例提供的显示器件中，所述延迟驱动器包括时序控制器，所述时序控制器被配置为输出数据传输控制信号；
所述源驱动器还包括预留寄存器，所述预留寄存器被配置为响应所述数据传输控制信号控制所述正极性数据信号或所述负极性数据信号的开始时间，以使向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示器件的示意图；
图2为另一种显示器件的示意图；
图3为一种显示器件的栅线和数据线上信号延迟叠加的模拟效果图；
图4为一种显示器件的栅线和数据线上信号的波形图；
图5为根据本公开一实施例提供的一种显示器件的平面示意图；
图6为根据本公开一实施例提供的一种显示器件的驱动方法的流程图；
图7为根据本公开一实施例提供的一种显示器件上栅线和数据线上信号的波形图；
图8为根据本公开一实施例提供的一种显示器件的驱动方法中数据线组的第二时间的变化曲线图；
图9为根据本公开一实施例提供一种显示器件的驱动方法对栅线和数据线上信号延迟的补偿效果示意图；
图10为根据本公开一实施例提供的一种驱动器的示意图；
图11为Oxide面板正负极性数据信号的波形图；
图12为Oxide面板的栅极信号的波形图；
图13为理想的数据信号与靠近栅驱动器的栅极信号的波形图；
图14为理想的数据信号与远离栅驱动器的栅极信号的波形图；
图15为衰减的数据信号与靠近栅驱动器的栅极信号的波形图；
图16为衰减的数据信号与远离栅驱动器的栅极信号的波形图；
图17为本公开一实施例提供的显示器件的驱动方法中衰减的数据信号与远离栅驱动器的栅极信号的波形图；
图18为根据本公开一实施例提供的另一种驱动器的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
随着显示器件的分辨率不断的提高，4K显示器件(4K分辨率的显示器件，4K分辨率可包括4096×3112、3656×2664等多种标准)在显示市场上日趋饱和，8K显示器件成为了各大厂商的研究热点。例如，8K的分辨率达到7680×4320的像素尺寸，是4K分辨率的4倍，从而能够带来细腻的高品质画质。
另一方面，大尺寸显示器件成为8K分辨率技术的热门载体。然而，大尺寸、高分辨率的显示器件存在面板充电率问题。以8K分辨率大尺寸的显示器件为例，一行像素的开启时间只有3.7μs，而实际有效的像素充电时间则更少，并且显示器件的分辨率越高，单位面积内所要驱动的像素则越多，从而导致显示器件的整个面板无法有效充电。通过调整充电时间的方法，因受限于充电时间短的问题，在8K分辨率、大尺寸的显示器件上效果有限。对于一些功耗较大的图片，极易产生Block分屏现象和因充电率不均所造成的Mura不良。因此，怎样在有限的时间内使得显示器件的整个面板上的各个像素的充电能力均一性最大化，以消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良是目前亟待解决的问 题。
在研究中，本申请的发明人注意到上述问题产生的原因主要是因为显示器件的信号线(例如，栅线和数据线)因阻抗会产生信号衰减和延迟。图1为一种显示器件的示意图；图2为另一种显示器件的示意图。如图1和2所示，该显示器件包括显示面板100、栅驱动器200和源驱动器300。显示面板100包括阵列基板、对置基板、栅线和数据线；栅驱动器200可为GOA(Gate On Array)电路，设置在阵列基板上，并且可设置在显示器件的两个相对的边缘以使得驱动栅线上的信号可从显示器件的两个相对的边缘向显示器件的中部传播；源驱动器300可为覆晶薄膜(COF)。图1示出了数据线上信号延迟的示意图。如图1所示，在数据线的延伸方向，相对于数据线上靠近信号输入端的部分上的信号，数据线上远离信号输入端的部分上的信号，即远离源驱动器300的部分上的信号会产生延迟。图2示出了栅线上信号延迟的示意图。如图2所示，在栅线的延伸方向，相对于栅线上靠近信号输入端的部分上的信号，栅线上远离信号输入端的部分上的信号，即远离栅驱动器200的部分上的信号会产生延迟。
图3示出了一种显示器件的栅线和数据线上信号延迟叠加的模拟效果图。如图3所示，当栅线的信号延迟与数据线的信号延迟叠加后，栅线上远离栅线的信号输入端的一端上的信号和数据线上远离数据线的信号输入端的一端上的信号会不匹配，导致充电时间不足，从而产生充电不足。如图3所示，图3中的三角区域Block分屏现象和Mura不良较为明显。图4示出了一种显示器件的栅线和数据线上信号的波形图。如图4所示，栅线上靠近信号输入端的部分上的信号如图4中线1所示，栅线上远离信号输入端的部分上的信号如图4中线2所示，由于栅线的阻抗等因此，栅线上远离信号输入端的部分上的信号会产生延迟和变形，当栅线上的信号的电压大于一定的值(例如，V 0)才能打开薄膜晶体管，从而导致栅线上远离信号输入端的部分上的信号的有效充电时间小于栅线上靠近信号输入端的部分上的信号的有效充电时间。当通过源驱动器向数据线输入如线3所示的数据信号时，该数据信号与栅线上靠近信号输入端的部分上的信号的有效充电面积大于该数据信号与栅线上远离信号输入端的部分上的信号的有效充电面积，从而导致栅线上远离信号输入端的部分对应的像素单元的充电时间比栅线上靠近信号输入端的部分对应的像素单元的充电时间短，充电效果差异较大。
本公开实施例提供一种显示器件的驱动方法、驱动器以及显示器件。在该显示器件的驱动方法中，显示器件包括交叉设置的多条栅线和多条数据线，各栅线包括信号输入端，该驱动方法包括：分别向栅线输入长度为第一时间的栅极信号；以及分别向数据线输入数据信号以驱动显示器件进行显示，沿栅线的信号输入端到远离信号输入端的一端的方向，在与该栅线交叉的M条数据线中，相对于向最靠近栅线的信号输入端的第一条数据线输入数据信号的开始时间，向第m条数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间，其中M、m均为大于等于2的正整数，m小于等于M，从而可使得数据线上的信号可匹配栅线的信号衰减和延迟，从而一方面减小距离栅线的信号输入端较近的数据线对应的像素单元的充电时间，另一方面增加距离栅线的信号输入端较远的数据线对应的像素单元的充电时 间，从而使得整个显示器件中沿栅线的延伸方向上排布的像素单元的充电时间的均一性提高，从而减弱甚至消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。
下面，结合附图对本公开实施例提供的显示器件的驱动方法、驱动器和显示器件进行详细的说明。
图5为根据本公开一实施例提供的一种显示器件的平面示意图。图6为根据本公开一实施例提供的一种显示器件的驱动方法的流程图。图7为根据本公开一实施例提供的一种显示器件上栅线和数据线上信号的波形图。
如图5所示，该显示器件包括交叉设置的多条栅线120和多条数据线130，各栅线120包括信号输入端127，多条数据线130沿栅线120的延伸方向排列，如图6所示，该驱动方法包括以下步骤S501-S502。
S501：分别向栅线输入长度为第一时间的栅极信号。需要说明的是，上述的“长度”是指栅极信号的持续时间。
S502：分别向数据线输入数据信号以驱动显示器件进行显示，沿栅线的信号输入端到远离信号输入端的一端的方向，在与该栅线交叉的M条数据线中，相对于向最靠近栅线的信号输入端的第一条数据线输入数据信号的开始时间，向第m条数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间，其中M、m均为大于等于2的正整数，m小于等于M。需要说明的是，上述进行开启时间比较的数据线是对应多条栅线中的一条数据线；即，向多条栅线中的一条输入长度为第一时间的栅极信号时，沿该栅线的信号输入端到远离信号输入端的一端的方向，在与该栅线交叉的M条数据线中，相对于向最靠近栅线的信号输入端的第一条数据线输入数据信号的开始时间，向第m条数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间，其中M、m均为大于等于2的正整数，m小于等于M。
在本公开实施例提供的显示器件的驱动方法中，如图7所示，栅线上靠近信号输入端的部分上的信号如图7中线1所示，栅线上远离信号输入端的部分上的信号如图7中线2所示，由于栅线的阻抗等原因，栅线上远离信号输入端的部分上的信号会产生延迟和变形，当栅线上的信号的电压大于一定的值(例如，V 0)才能打开薄膜晶体管，从而导致栅线上远离信号输入端的部分上的信号的有效充电时间小于栅线上靠近信号输入端的部分上的信号的有效充电时间。当通过源驱动器向数据线输入如线3(通常的数据信号)所示的数据信号时，该数据信号与栅线上靠近信号输入端的部分上的信号的有效充电面积大于该数据信号与栅线上远离信号输入端的部分上的信号的有效充电面积，从而导致栅线上靠近信号输入端的部分对应的像素单元的充电时间比栅线上远离信号输入端的部分对应的像素单元的充电时间短，充电效果差异较大；而当通过源驱动器向数据线输入如线4(本公开的数据信号)所示的数据信号时，该数据信号相对于线3所示的数据线延后第二时间，即相对于向第m条数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间，可使得数据线上的信号可匹配栅线的信号衰减和延迟，从而增加距离栅线的信号输入端较远的数据线对应的像素单元的充电时间，从而使得整个显示器件中沿栅线的延伸方向上排布的像素单元的充电时间的均一性提高，从而减弱甚至消除因充电不均导致的Block分屏现象和因充 电率不均所造成的Mura不良。
需要说明的是，本公开中的第一时间和第二时间均指时间段，而非某时刻。
例如，在一些示例中，如图5所示，多条数据线130可划分为N组数据线组135，即，多条数据线130包括N组数据线组135。在各数据线组135中，向各数据线130输入数据信号的开始时间相同，也就是说，在各数据线组135中，向各数据线130输入数据信号的开始时间互相之间没有延迟。沿栅线的信号输入端到远离信号输入端的一端的方向，N组数据线组中的第二时间随着与信号输入端的距离增加而逐渐增加。随着与信号输入端的距离的增加，栅线上的信号的延迟也逐渐增加，因此通过将N组数据线组中的第二时间随着与信号输入端的距离增加而逐渐增加，可进一步提高整个显示器件中沿栅线的延伸方向上排布的像素单元的充电时间的均一性，从而进一步减弱甚至消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。
例如，在一些示例中，驱动方法还包括：确定各栅线的整体延迟时间T CLK；以及将整体延迟时间均分为N份，N组数据线组中第n组数据线组中的第二时间y＝(n-1)×T CLK/N，从而使得N组数据线组中的第二时间随着与信号输入端的距离增加而逐渐增加的量更均匀，从而进一步提高整个显示器件中沿栅线的延伸方向上排布的像素单元的充电时间的均一性，从而进一步减弱甚至消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。
例如，N的取值可为24，即数据线130包括24组数据线组135；此时，24组数据线组135的第n组数据线组中的第二时间y＝(n-1)×T CLK/24。其中，n为正整数，且1≤n≤N。
例如，在一些示例中，各栅线的整体延迟时间T CLK满足以下公式：
T CLK＝(2 j×T j+2 j-1×T j-1+…+2 2×T 2+2 1×T 1+2 0×T 0+k)×2t，
其中，t为信号时钟周期，k为补正基数，T 0、T 1、T 2.....T j取值范围是1或0，j的取值范围为4-8，k的取值范围0-10。
在该驱动方法中，随着T 0、T 1、T 2.....T j的取值不同，可获得不同的整体延迟时间，并通过上述驱动方法驱动显示器件进行显示，从而可根据显示器件的显示效果得到Block分屏现象和Mura不良较弱的T 0、T 1、T 2.....T j的值。另外，由于T 0、T 1、T 2.....T j的值可用一个二进制的数值来表示，因此便于进行计算和存储。另外，补正基数k可保证该栅线的整体延迟时间具有一个最小的补正值。需要说明的是，由于影响栅线上信号延迟的因素较多，并且不同显示器件的具体参数不同，采用上述公式计算栅线的整体延迟时间，仅需要调节j值便可便利地进行计算，因此具有简单、有效等优点。
例如，当显示器件为8k分辨率75寸的显示器件时，k的取值范围可为4-6，又例如，k＝5。
例如，上述的信号时钟周期t的取值范围可为5-10μs。
需要说明的是，上述的k、t的具体取值范围可根据显示器件的具体参数确定，本公开实施例包括但不限于上述的取值范围。
例如，在一些示例中，j的取值为4，6，或8。当j的取值为4时，计算量较小，当j的取值为8时，栅线的整体延迟时间较大，适合对较大尺寸和较高分辨率的显示器件进行计算并且效果较好。
例如，如图5所示，该显示器件包括N个源驱动器300，被配置为向多条数据线130加载数据信号，驱动方法包括：使用N个源驱动器300分别驱动N组数据线组135。由此，每个源驱动器300向各数据线130输入数据信号的开始时间互相之间没有延迟，不同源驱动器300数据线130输入数据信号的开始时间不同，从而可降低各源驱动器300的计算压力。
例如，在一些示例中，如图5所示，显示器件还包括多条栅线120和多条数据线130交叉限定的多个像素单元140，各像素单元140包括薄膜晶体管150，薄膜晶体管150的栅极151与栅线120相连，薄膜晶体管150的源极152与数据线130相连。从而，栅线120上的栅极信号可打开薄膜晶体管150，使得数据线130上的数据信号可从薄膜晶体管150的源极152流向薄膜晶体管150的漏极153，并加载在像素电极(未示出)上。
例如，在一些示例中，栅极信号为第一脉冲信号；数据信号为第二脉冲信号。
例如，如图5所示，多条栅线120包括一一对应设置的多条第一栅线121和多条第二栅线122，第一栅线121的信号输入端1217位于显示器件的第一边缘161，第二栅线122的信号输入端1227位于显示器件的与第一边缘161相对的第二边缘162，对应设置的第一栅线121和第二栅线122被配置为加载同一时序的栅极信号。
例如，在一些示例中，一一对应设置的第一栅线121和第二栅线122也可相连。需要说明的是，此时，第一栅线121和第二栅线122可独立计算整体延迟时间，也可分别计算整体延迟时间。
例如，如图5所示，一一对应设置的第一栅线121和第二栅线122可作为一个整体计算整体延迟时间T CLK，并且与第一栅线121交叉设置的数据线130可分为N/2组数据线组，与第二栅线122交叉设置的数据线130可分为N/2组。此时，可将整体延迟时间T CLK均分为N份，与第一栅线121交叉设置的N/2组数据线组中第n1组数据线组中的第二时间y1＝(n1-1)×T CLK/N，与第二栅线122交叉设置的N/2组数据线组中第n2组数据线组中的第二时间y2＝(n2-1)×T CLK/N。
图8为根据本公开一实施例提供的一种显示器件的驱动方法中数据线组的第二时间的变化曲线图。如图8所示，N的取值可为24，即数据线包括24组数据线组；此时，从第一栅线的信号输入端到远离信号输入端的方向上，与第一栅线交叉设置的N/2组数据线组的第二时间可分别为：0、T CLK/N、2T CLK/N、…(N/2-1)T CLK/N；从第二栅线的信号输入端到远离信号输入端的方向上，与第二栅线交叉设置的N/2组数据线组的第二时间可分别为：0、T CLK/N、2T CLK/N、…(N/2-1)T CLK/N。图9为根据本公开一实施例提供一种显示器件的驱动方法对栅线和数据线上信号延迟的补偿效果示意图。如图9所示的数据线组的第二时间的变化曲线形成的延迟补偿区域刚好可与图3所示的栅线和数据线上信号延迟叠加的三角形区域匹配，从而可实现整个显示器件内像素单元的充电率或充电效果的均一性的最大化，进而改善因充电不均导致 的Block分屏现象和因充电率不均所造成的Mura不良。
需要说明的是，图8中的数据线组的第二时间的变化曲线的斜率可根据实际情况进行调整，斜率的大小可根据源驱动器的驱动能力决定的。斜率越高，第二时间的大小就越大，具体可根据显示器件的数据线的阻抗大小来决定。另外，数据线组的第二时间的变化曲线可为连续的，也可为不连续的曲线，可以是斜率一致的直线也可以是斜率有变化的曲线或者折线，本公开实施例包括但不限于此。数据线组的第二时间的变化曲线可根据显示器件的栅线上的信号变化情况进行变更。
图10为根据本公开一实施例提供一种驱动器的示意图。如图10所示，该驱动器700包括至少一个栅驱动器200和至少一个源驱动器300；栅驱动器200被配置为向栅线输入长度为第一时间的栅极信号；源驱动器300被配置为分别向数据线输入数据信号以驱动显示器件进行显示，沿栅线的信号输入端到远离信号输入端的一端的方向，相对于向最靠近信号输入端的数据线输入数据信号的开始时间，向远离信号输入端的数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间，从而可使得数据线上的信号可匹配栅线的信号衰减和延迟，从而增加距离栅线的信号输入端较远的数据线对应的像素单元的充电时间，从而使得整个显示器件中沿栅线的延伸方向上排布的像素单元的充电时间的均一性提高，从而减弱甚至消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。
例如，在一些示例中，该驱动器还包括延迟驱动器600，被配置为使得源驱动器300在沿栅线的信号输入端到远离信号输入端的一端的方向，沿该栅线的信号输入端到远离信号输入端的一端的方向，在与栅线交叉的并依次间隔排布的M条数据线中，相对于向最靠近信号输入端的第一条数据线输入数据信号的开始时间，向第m条数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间，其中M、m均为大于等于2的正整数，m小于等于M。也就是说，在该驱动器中，栅驱动器和源驱动器可采用通常的栅驱动器和源驱动器，通过增设延迟驱动器600使得源驱动器300在沿栅线的信号输入端到远离信号输入端的一端的方向，沿该栅线的信号输入端到远离信号输入端的一端的方向，在与栅线交叉的并依次间隔排布的M条数据线中，相对于向最靠近信号输入端的第一条数据线输入数据信号的开始时间，向第m条数据线输入数据信号的开始时间延后第二时间，第二时间小于第一时间。
例如，在一些示例中，多条数据线包括N组数据线组，至少一个源驱动器300包括N个源驱动器300，被配置为向多条数据线加载数据信号，N个源驱动器300被配置为分别驱动N组数据线组，沿栅线的信号输入端到远离信号输入端的一端的方向，N组数据线组中的第二时间随着与信号输入端的距离增加而逐渐增加。
本公开一实施例还提供一种显示器件，包括上述任一种驱动器，从而可使得整个显示器件中沿栅线的延伸方向上排布的像素单元的充电时间的均一性提高，从而减弱甚至消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。
例如，在一些示例中，该显示器件可为电视机、电脑、导航仪、笔记本电脑、手机、电子相册等具 有显示功能的产品。
例如，在一些示例中，该显示器件的分辨率为超高清(UHD)，例如分辨率大于等于4K*2K。又例如，该显示器件的分辨率大于等于8K*4K。此处4K*2K表示拥有3840×2160的物理分辨率，8K*4K表示拥有7680×4320的物理分辨率。
以上示例说明了通过延迟向数据线输入数据信号的开始时间，以消除因充电不均导致的Block分屏现象和因充电率不均所造成的Mura不良。需要说明的是，本公开对输入数据信号开始时间的延迟可以是指，对除最靠近栅极信号输入端的第一条数据线以外的所有数据线的数据信号开始时间都进行延迟，也可以只对除最靠近栅极信号输入端的第一条数据线以外的部分数据线的数据信号开始时间进行延迟，而另一部分不进行延迟。
然而，申请人发现，数据信号分为正极性数据信号和负极性数据信号，针对不同极性的数据信号，如果进行相同的延迟，仍然可能存在充电不均的现象。具体如下。
图11具体示出了Oxide面板正负极性数据信号的仿真波形图，图中上半部分曲线均为正极性数据信号的电压波形，下半部分曲线均为负极性数据信号的电压波形，p 1表示靠近源驱动器的数据线的数据信号波形，p 2和p 3均分别表示远离源驱动器的两条不同列的数据线的数据信号波形，可以看出靠近源驱动器的数据线的信号近似为方波，而远离源驱动器的数据线信号已失真变化为近似正弦状波形，越是远离源驱动器的数据信号波形失真越严重。图12具体示出了Oxide面板栅极信号的波形，其中曲线L 1表示靠近栅驱动器的栅线信号，曲线L 2表示远离栅驱动器的栅线信号，可以看出栅极信号波形在传输中也会发生失真从而变化为弧形波，在TFT关断阶段，由于栅极信号衰减，其电压变化呈逐渐下降的曲线状。
对于TFT而言，其关断的条件是栅极信号电压Vg与数据信号电压Vs差小于Vth，即Vg-Vs＜Vth，此时TFT关断，否则开启。由于Vth通常约为0～1V，为了便于描述，以下以Vth为0V为例进行说明。当Vth＝0V时，也就是说，当栅极信号电压Vg减小至小于数据信号电压Vs时，数据信号对应的TFT就会关断。
以图13中所示的理想的方波数据信号为例，在靠近栅驱动器处，栅极信号L垂直或近似垂直下降，此时栅极信号电压Vg应在接近同一时刻减小至正极性数据信号电压Vs和负极性数据信号电压Vs，也就是说，正极性数据信号对应的TFT会在图中栅极信号L和正极性数据线信号P’的交点a处关断，负极性数据信号对应的TFT会在图中栅极信号L和负极性数据信号P”的交点b处关断，a点和b点对应同一时刻，即正极性数据信号和负极性数据信号对应的TFT是同时关断的。
但由于远离栅驱动器的栅极信号具有衰减，因此远离栅驱动器的位置处，正极性数据信号和负极性数据信号对应的TFT并非同时关断。如图14所示，在远离栅驱动器处，栅极信号L因为衰减而具有斜坡，此时栅极信号L先降低到与正极性数据信号P’相交的a点，此时正极性数据信号对应的TFT关断；然后栅极信号L降低到与负极性数据信号P”相交的b点，此时负极性数据信号对应的TFT才关断，由图可知， a点对应的时间早于b点对应的时间，即正极性数据信号对应的TFT早于负极性数据信号对应的TFT关断。
同理，以图15中所示的失真后的数据信号为例，在靠近栅驱动器处，栅极信号垂直或接近垂直下降，此时栅极信号电压Vg应在同一时刻减小至小于正极性数据信号对应的Vs和负极性数据信号对应的Vs，即正极性数据信号和负极性数据信号对应的TFT是同时关断的，也就是说，正极性数据信号对应的TFT会在图中所示的栅极信号L和正极性数据信号P’相交的a点处关断，负极性数据信号对应的TFT会在栅极信号L和负极性数据信号P”相交的b点处关断，a点和b点对应同一时刻。
对于失真后的数据信号，在远离栅驱动器的位置处，正极性数据信号和负极性数据信号对应的TFT也并非同时关断。如图16所示，在远离栅驱动器处，栅极信号L因为衰减而具有斜坡，此时栅极信号L先降低到与正极性数据信号P’相交的a点，正极性数据信号对应的TFT关断；然后栅极信号L降低到与负极性数据信号P”相交的b点，负极性数据信号对应的TFT才关断，a点对应的时间早于b点对应的时间，即正极性数据对应的TFT早于负极性数据对应的TFT关断。
可见，栅极信号的衰减会导致正极性数据对应的TFT早于负极性数据对应的TFT关断。
需要注意的是，上述示例都是以Vth为0V时进行的说明，当Vth不为0V时，例如，Vth为1V时，意味着Vg-Vs＜1V时，TFT就会关断，也就是说，栅极信号电压降低至比数据信号电压略大时，TFT就会关断。对应图13-16的波形，正极性数据信号对应的TFT是在栅极信号L和正极性数据信号P’交点a之前的位置关断，负极性数据信号对应的TFT也是在栅极信号L和负极性数据信号P”交点b之前的位置关断。但正极性数据对应的TFT的关断时间仍然早于负极性数据对应的TFT的关断时间。此处不再赘述。
对Oxide面板进行仿真实验得知，在图16所示的远离源驱动器的位置处，正极性数据信号对应的TFT关断的时间大约在1.8μs，而负极性数据信号对应的TFT关断的时间大约在2.2μs，二者关断的时间差Δt约为0.4μs。
同理，其他显示面板，例如a-Si显示面板，也存在同样的问题，即正极性数据信号对应的TFT早于负极性数据信号对应的TFT关断。对a-Si显示面板进行仿真实验，在远离源驱动器的位置处，正极性数据信号对应的TFT关断时间约在1.8μs，负极性数据信号对应的TFT关断时间约在2.5μs，正负极性数据信号的关断时间差Δt大约为0.7μs。
由于正极性数据对应的TFT早于负极性数据对应的TFT关断，因此会导致负极性数据信号充电时长长于正极性数据信号，从而引起像素显示效果不一致。尤其对于高频显示技术而言，充电时间极为宝贵，0.4μs-0.7μs的充电时间差异会大幅降低像素的充电效率，影响高频显示效果。
对应于液晶显示面板的液晶分子的翻转模式，在列翻转模式下，接收正极性数据信号的像素列充电时间短，而接收负极性数据信号的像素列充电时间长，当上一行像素结束扫描而开启下一行像素扫描时，会出现上一行正极性数据所对应的像素已经关断，而上一行负极性数据所对应的像素还未关断，使此处 像素显示发生异常。在帧翻转模式下，对于同一个像素而言，上一帧正极性数据信号充电时间短，而下一帧负极性数据信号充电时间长，由此也会导致显示异常，影响显示效果。
基于以上问题，本公开实施方式的显示器件驱动方法进行了进一步的改进，即在该方法中，分别向数据线输入数据信号还包括：
向数据线输入正极性数据信号或负极性数据信号；
其中，相对于向最靠近信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条数据线输入负极性数据信号的开始时间延后第二时间，向第s条数据线输入正极性数据信号的开始时间延后第三时间，第二时间、第三时间均小于第一时间，第二时间大于所述第三时间，且第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长；
其中m、s均为大于等于2的正整数，且m和s均小于等于M。
具体而言，本申请使负极性数据信号的开始时间向后延迟的时间大于正极性数据信号的开始时间向后延迟的时间，即，将负极性数据信号相对于正极性数据信号延迟输入数据线，由此缩短了负极性数据充电时间，使正负极数据信号充电时长保持一致，抵消了充电时间差。
需要说明的是，第二时间和第三时间都表示一个时间段。其中，第三时间可以等于0，也可以大于0，由于第二时间大于第三时间，因此第二时间必然大于0。也就是说该方案包含两种情况，第一种情况是，不对正极性数据信号的开始时间进行延迟(即第三时间＝0)，只对负极性数据信号的开始时间进行延迟(即第二时间＞0)，第二种情况是，对正极性数据信号和负极性数据信号的开始时间都进行延迟(即第三时间＞0，且第二时间＞0)，只是负极性数据信号的开始时间相对于正极性数据信号的开始时间延迟更多(第二时间＞第三时间)。以下，以第一种情况为例进行具体说明。
参考图17，以衰减后的数据信号为例，示出了相对于正极性数据信号的开始时间，将负极性数据信号的开始时间向后延迟的波形图，图中上方曲线P’为正极性数据线信号，下方曲线P”为负极性数据线信号，弧形曲线L为远离栅极驱动电路的栅极信号。由图中可以看出，在正极性数据信号输入开始时间不变，将负极性数据信号相对于正极性数据信号整体向右平移Δt 1的时长(即第二时间-第三时间＝Δt 1)，就可以缩短正负极性数据信号充电时长的差异。需要说明的是，Δt 1需要小于一个数据周期内的有效电平时长，否则意味着负极性数据信号向后延迟的过多，在输入负极性数据信号前，TFT已经关断，导致没有对像素进行充电，引起显示异常。
进一步地，当Δt 1＝Δt时，也就是说当负极性数据信号相比正极性数据信号延迟的时间等于负极性数据信号对应的TFT关断时间与正极性数据信号对应的TFT关断时间的时间差(即前述的Δt)时，负极性数据信号充电时长和正极性数据信号充电时长相等。
因此，本实施方式通过控制数据线输入正负数据信号的不同开始时间，消除因TFT关断时间差异导致的正负极性数据充电差异，保证了均匀稳定的显示效果。尤其对于高频显示技术而言，在每一行扫描 时间较短的情况下，该方法大大提高了正负极性数据的充电效率。
例如，在一些示例中，m≠s时，向第m条数据线输入负极性数据信号的开始时间延后第二时间，向第s条数据线输入正极性数据信号的开始时间延后第三时间，第二时间大于第三时间，且第二时间和第三时间的差小于一个数据信号周期内的有效电平时长，即表示对不同列的数据线分别输入正极性数据信号和负极性数据信号。该显示器件的驱动方法可以用于调节数据极性相反的两部分子像素的充电时间，这两部分子像素可以是包括位于不同列的第一部分子像素和第二部分子像素，也就是说，该显示驱动方法可以用于列翻转模式的显示驱动，以达到对不同子像素的充电时间的调节。在传统驱动方式中，在同一时刻，数据线向第一部分子像素输入正极性数据信号，向第二部分子像素输入负极性数据信号，第一部分子像素TFT关断时，第二部分子像素的TFT还未完全关断，由此导致两部分子像素充电效果不一致，显示效果不均匀。本实施方式可以延迟向数据线输入负极性数据信号整体的输入时间，使第一部分子像素的正极性数据信号与第二部分子像素的负极性数据信号充电时间一致，由此保证两部分子像素的充电效果一致，进而保证显示效果一致。
第一部分子像素和第二部分子像素可以是依次交替排列的形式，也可以是第一部分子像素和第二部分子像素单独分区域设置的形式。无论哪一种形式，列与列之间数据极性相反时，采用该驱动方法可以保证数据极性相反的列与列之间的显示效果一致。
本领域技术人员可以理解的是，第一部分子像素、第二部分子像素仅用于对子像素进行划分，二者和正极性数据信号、负极性数据信号的对应关系也可以互换，即，第一部分子像素接收负极性数据信号，第二部分子像素接收正极性数据信号。
例如，在一些示例中，m＝s时，表示对同一条数据线先后分别输入正极性数据信号和负极性数据信号，即在第一帧时向第m条数据线输入负极性数据信号的开始时间延后的第二时间大于在第二帧时向第s条数据线输入正极性数据信号的开始时间延后的第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。该显示驱动方法还可以用于帧翻转模式的显示驱动。具体而言，源驱动器在第一帧时向一数据线输入正极性数据信号，在第二帧时向该数据线输入负极性数据信号。在传统帧翻转驱动方式中，由于第一帧和第二帧的数据极性相反，TFT关断的时间差会导致同一子像素在两帧内充电时长不一致，造成亮度不均，显示效果不佳。本实施方式可以延迟在第二帧时向数据线输入负极性数据信号的开始时间，使第一帧时的正极性数据信号的充电时长与第二帧时的负极性数据信号的充电时长保持一致，由此使得两帧内的数据信号充电效果一致，进而保证显示效果一致。
本领域技术人员可以理解的是，第一帧、第二帧仅用于对时间进行划分，二者和正极性数据信号、负极性数据信号的对应关系也可以互换，即，第一帧向数据线输入负极性数据信号，第二帧向数据线输入正极性数据信号。
需要注意的是，本公开的两种实施方式中，负极性数据信号的延迟都是整体延迟，即整列子像素的 负极性数据信号的输入时间整体向后延迟，或整幅画面所有子像素的负极性数据信号的输入时间整体向后延迟。
需要注意的是，对于不同的显示面板，栅极信号也会存在相对的延迟，进而影响Δt的大小，所以为了确保Δt的可调范围能够同时覆盖多种面板，应使预留的移位寄存器的可调范围大于1.5μs。
还需要说明的是，上述是以正极性数据信号的开始时间不延迟，只延迟负极性数据信号的开始时间为例进行的说明，本领域技术人员可以理解的是，当正极性数据信号也进行延迟时(即第三时间＞0)，只要能保证负极性数据信号的开始时间相比正极性数据信号的开始时间又进一步延迟(第二时间＞第三时间)，也能达到消除充电时间差异的问题，此处不再赘述。
基于上述显示控制方法，本公开实施方式的显示装置中，源驱动器300被配置为分别向数据线输入正极性数据信号或负极性数据信号以驱动显示器件进行显示，相对于向最靠近信号输入端的第一条数据线输入数据信号的开始时间，向第m条数据线输入负极性数据信号的开始时间延后第二时间，向第s条数据线输入正极性数据信号的开始时间延后第三时间，第二时间大于第三时间，且小于一个数据信号周期内的有效电平时长；其中m、s均为大于等于2的正整数。
例如，在一些示例中，如图10所示，驱动器700还包括延迟驱动器600，被配置为使得源驱动器300在沿栅线的信号输入端到远离信号输入端的一端的方向，相对于向最靠近信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条数据线输入负极性数据信号的开始时间延后第二时间，向第s条数据线输入正极性数据信号的开始时间延后第三时间，第二时间大于第三时间，且小于一个数据信号周期内的有效电平时长。
例如，在一些示例中，如图18所示，延迟驱动器600包括时序控制器610，时序控制器610被配置为输出数据传输控制信号；源驱动器300还包括预留寄存器310，预留寄存器310被配置为响应数据传输控制信号控制正极性数据信号或负极性数据信号的开始时间，以使向第m条数据线输入负极性数据信号的开始时间延后第二时间，向第s条数据线输入正极性数据信号的开始时间延后第三时间，第二时间大于第三时间，且小于一个数据信号周期内的有效电平时长。
具体而言，在TFT驱动电路中，时序控制器610用于向源驱动器300输出规定有数据信号时序的数据传输控制信号，源驱动器300响应该数据传输控制信号对数据信号向数据线输入的开始时间进行延时处理，以使数据信号按照预设的时序输入数据线。修改时序控制器中负极性数据或正极性数据的输入时间，并进一步设置相应的寄存器用于对数据进行锁存和延时，即可实现数据信号的延迟。
为了减少耗用的资源量，可以利用源驱动器中设置的预留寄存器310来实现对数据信号的调整。具体而言，通常源驱动器会设置部分预留寄存器310，以在特定情况下对其进行扩展。本实施方式可以利用源驱动器300中预留的移位寄存器来实现数据延迟或提前，移位寄存器可以在时钟信号的作用下使寄存的数据依次左移或右移，从而实现信号延迟或提前。
例如，在一些示例中，预留寄存器310为八位移位寄存器。例如，在4Gbps的带宽条件下，每一个字节会有2package(5ns)的变化，由此该八位移位寄存器可以调节的正负极性数据充电长差Δt的范围可以达到1.2μs，完全能够满足对a-Si显示面板和Oxide显示面板的调节，不仅实现信号调节的目的，也无需额外设置单独的寄存器，该方式仅占用内部预留的1-byte的寄存器即完成了设定，不需要增加新的功能IP，耗用资源量较少，减少了设计成本。
需要说明的是，源驱动器300内部还可以包括移位寄存器电路、锁存器电路、D/A变换电路，以及伽马校正电路等，用于输出数据信号，此处不再赘述。
在本公开示例中，显示装置可以为采用非晶硅液晶显示面板或金属氧化物液晶显示面板的装置，由于这两种显示面板的正负极充电效果不一致的问题较明显，如前所述，时间差Δt在0.4～0.7μs，因此，上述显示装置能达到更理想的显示效果。在其他实施方式中，显示装置还可以采用其他液晶面板，例如低温多晶硅(p-Si)显示面板、单晶硅(c-Si)显示面板等，只要存在由于正负极数据信号关断时间差导致的充电时长不一致的问题，均可以采用本公开的驱动方法进行驱动，此处不再一一列举。
本公开对于显示装置的适用不做具体限制。该显示装置可以用于手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种显示器件的驱动方法，其中，所述显示器件包括交叉设置的多条栅线和多条数据线，各所述栅线包括信号输入端，所述驱动方法包括：
    分别向所述栅线输入长度为第一时间的栅极信号；以及
    分别向所述数据线输入数据信号以驱动所述显示器件进行显示，
    其中，沿所述栅线远离所述信号输入端的方向，在与所述栅线交叉的M条所述数据线中，相对于向最靠近所述栅线的信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入数据信号的开始时间延后第二时间，
    所述第二时间小于所述第一时间，其中M、m均为大于等于2的正整数，m小于等于M。
  2. 根据权利要求1所述的显示器件的驱动方法，其中，所述多条数据线包括N组数据线组，
    在各所述数据线组中，向各所述数据线输入数据信号的开始时间相同，
    沿所述栅线的所述信号输入端到远离所述信号输入端的一端的方向，所述N组数据线组中的所述第二时间随着与所述信号输入端的距离增加而逐渐增加，其中N为大于等于1的正整数。
  3. 根据权利要求2所述的显示器件的驱动方法，其中，所述驱动方法还包括：
    确定各所述栅线的整体延迟时间T CLK；以及
    将所述整体延迟时间均分为N份，所述N组数据线组中第n组数据线组中的所述第二时间y＝(n-1)×T CLK/N，其中，所述n为正整数，且1≤n≤N。
  4. 根据权利要求3所述的显示器件的驱动方法，其中，各所述栅线的整体延迟时间T CLK满足以下公式：
    T CLK＝(2 j×T j+2 j-1×T j-1+…+2 2×T 2+2 1×T 1+2 0×T 0+k)×2t，
    其中，t为信号时钟周期，k为补正基数，T 0、T 1、T 2.....T j取值范围是1或0，j的取值范围为4-8，k的取值范围0-10。
  5. 根据权利要求4所述的显示器件的驱动方法，其中，j的取值为4，6，或8。
  6. 根据权利要求2-5中任一项所述的显示器件的驱动方法，其中，所述显示器件包括N个源驱动器，被配置为向所述多条数据线加载所述数据信号，所述驱动方法包括：
    使用所述N个源驱动器分别驱动所述N组数据线组。
  7. 根据权利要求1-6中任一项所述的显示器件的驱动方法，其中，所述多条栅线包括一一对应设置的多条第一栅线和多条第二栅线，
    所述第一栅线的信号输入端位于所述显示器件的第一边缘，所述第二栅线的信号输入端位于所述显示器件的与第一边缘相对的第二边缘，
    对应设置的所述第一栅线和所述第二栅线被配置为加载同一时序的所述栅极信号。
  8. 根据权利要求7所述的显示器件的驱动方法，其中，一一对应设置的所述第一栅线和所述第二栅线相连。
  9. 根据权利要求1-8中任一项所述的显示器件的驱动方法，其中，所述显示器件还包括：所述多条栅线和所述多条数据线交叉限定的多个像素单元，各所述像素单元包括薄膜晶体管，
    其中，所述薄膜晶体管的栅极与所述栅线相连，所述薄膜晶体管的源极与所述数据线相连。
  10. 根据权利要求1-9中任一项所述的显示器件的驱动方法，其中，所述栅极信号为第一脉冲信号；所述数据信号为第二脉冲信号。
  11. 根据权利要求1所述的显示器件的驱动方法，其中，分别向所述数据线输入数据信号还包括：
    向所述数据线输入正极性数据信号或负极性数据信号；
    其中，相对于向最靠近所述栅线的信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间、第三时间均小于所述第一时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长；
    其中m、s均为大于等于2的正整数，且m和s均小于等于M。
  12. 根据权利要求11所述的显示器件的驱动方法，其中，所述第二时间和所述第三时间的差为Δt，所述Δt等于所述负极性数据信号对应的开关器件关断时间与所述正极性数据信号对应的开关器件关断时间的时间差。
  13. 根据权利要求11所述的显示器件的驱动方法，其中，所述m≠s，向所述第m条数据线输入负极性数据信号的开始时间延后所述第二时间，向所述第s条数据线输入正极性数据信号的开始时间延后所述第三时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
  14. 根据权利要求11所述的显示器件的驱动方法，其中，所述m＝s，在第一帧时向所述第m条数据线输入负极性数据信号的开始时间延后的所述第二时间大于在第二帧时向所述第s条数据线输入正极性数据信号的开始时间延后的所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
  15. 一种显示器件，包括交叉设置的多条栅线和多条数据线，各所述栅线包括信号输入端；所述显示器件还包括驱动器，所述驱动器被配置为用于驱动所述显示面板显示，所述驱动器包括：
    至少一个栅驱动器，被配置为分别向所述栅线输入长度为第一时间的栅极信号；以及
    至少一个源驱动器，被配置为分别向所述数据线输入数据信号以驱动显示器件进行显示，
    其中，沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，在与所述栅线交叉的M条所 述数据线中，相对于向最靠近所述栅线的信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入数据信号的开始时间延后第二时间，
    所述第二时间小于所述第一时间，其中M、m均为大于等于2的正整数，m小于等于M。
  16. 根据权利要求15所述的显示器件，其中，所述驱动器还包括：
    延迟驱动器，被配置为使得所述源驱动器在沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，在与所述栅线交叉的M条所述数据线中，相对于向最靠近所述信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入数据信号的开始时间延后第二时间，
    所述第二时间小于所述第一时间，其中M、m均为大于等于2的正整数，m小于等于M。
  17. 根据权利要求15或16所述的显示器件，其中，所述多条数据线包括N组数据线组，所述至少一个源驱动器包括N个源驱动器，被配置为向所述多条数据线加载所述数据信号，所述N个源驱动器被配置为分别驱动N组数据线组，沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，所述N组数据线组中的所述第二时间随着与所述信号输入端的距离增加而逐渐增加。
  18. 根据权利要求15所述的显示器件，其中，所述源驱动器还被配置为向所述数据线输入正极性数据信号或负极性数据信号；
    其中，相对于向最靠近所述栅线的信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间、第三时间均小于所述第一时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长；
    其中m、s均为大于等于2的正整数。
  19. 根据权利要求18所述的显示器件，其中，所述驱动器还包括：
    延迟驱动器，被配置为使得所述源驱动器在沿所述栅线的信号输入端到远离所述信号输入端的一端的方向，相对于向最靠近所述信号输入端的第一条所述数据线输入数据信号的开始时间，向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
  20. 根据权利要求19所述的显示器件，其中，所述延迟驱动器包括时序控制器，所述时序控制器被配置为输出数据传输控制信号；
    所述源驱动器还包括预留寄存器，所述预留寄存器被配置为响应所述数据传输控制信号控制所述正极性数据信号或所述负极性数据信号的开始时间，以使向第m条所述数据线输入负极性数据信号的开始时间延后第二时间，向第s条所述数据线输入正极性数据信号的开始时间延后第三时间，所述第二时间大于所述第三时间，且所述第二时间和所述第三时间的差小于一个数据信号周期内的有效电平时长。
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