WO2020144737A1 - データ通信装置及びデータ通信方法 - Google Patents

データ通信装置及びデータ通信方法 Download PDF

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Publication number
WO2020144737A1
WO2020144737A1 PCT/JP2019/000188 JP2019000188W WO2020144737A1 WO 2020144737 A1 WO2020144737 A1 WO 2020144737A1 JP 2019000188 W JP2019000188 W JP 2019000188W WO 2020144737 A1 WO2020144737 A1 WO 2020144737A1
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WO
WIPO (PCT)
Prior art keywords
data
bits
serial
circuit
address
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Application number
PCT/JP2019/000188
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English (en)
French (fr)
Japanese (ja)
Inventor
田中　進
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to PCT/JP2019/000188 priority Critical patent/WO2020144737A1/ja
Priority to JP2020565047A priority patent/JP7052087B2/ja
Priority to CN201980087067.4A priority patent/CN113272795B/zh
Publication of WO2020144737A1 publication Critical patent/WO2020144737A1/ja

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming

Definitions

  • the present invention relates to a data communication device and a data communication method.
  • a data communication device that executes serial communication is used for writing control commands and reading status or data.
  • full duplex communication is generally performed in order to improve responsiveness.
  • Patent Document 1 the storage data of a plurality of built-in registers are selected based on the register address information stored in the serial reception data, and the selected register is selected.
  • a configuration is used in which data is transmitted as serial transmission data of the same packet.
  • the baud rate of the serial communication system is prevented from being lowered by the configuration in which the register circuits are separately arranged for even addresses and odd addresses.
  • Patent Document 1 Although continuous access to registers with continuous addresses can be speeded up, there is a concern that it is not possible to speed up reading of one-time register data.
  • the present invention has been made to solve such a problem, and an object of the present invention is to perform serial communication in a read data selection process using a plurality of bits of addresses by transmitting and receiving serial data in synchronization with a clock. It is to prevent the decrease of the baud rate and the freedom of the communication format.
  • a data communication device that operates in synchronization with a clock, including a reception circuit, a register circuit, a register select circuit, and a transmission circuit.
  • the receiving circuit receives the serial data in synchronization with the clock.
  • the register circuit includes an address composed of a plurality of bits and stores a plurality of received data selected by the address.
  • the register select circuit selects read data from the plurality of received data stored in the register circuit in synchronization with the clock according to the address included in the plurality of bits received as the serial data by the receiving circuit every clock cycle.
  • the transmission circuit transmits the read data selected by the register select circuit as serial data in synchronization with the clock.
  • the register select circuit selects a plurality of candidate data from a plurality of received data based on some of the plurality of bits and a plurality of candidates based on the remaining bits excluding some of the plurality of bits.
  • the selection of read data from the data is executed in different clock cycles.
  • a data communication method for transmitting/receiving serial data in synchronization with a clock which comprises an address for selecting read data from a plurality of data stored in a register circuit.
  • a plurality of bits forming the address for receiving a part of the plurality of bits as serial data at each clock cycle and selecting read data from a register circuit that stores a plurality of received data selected by the address.
  • Some of the bits are received as serial data for each clock cycle, a plurality of candidate data is selected from the plurality of data based on the received some bits, and some of the plurality of bits of the address are selected.
  • the remaining bits except the bits are received as serial data, and the read data is selected from the plurality of candidate data in a clock cycle after the clock cycle in which the plurality of candidate data is selected based on the received remaining bits. , The selected read data is transmitted as serial data every clock cycle.
  • the present invention by transmitting and receiving serial data in synchronization with a clock, it is possible to prevent the processing of selecting read data from a plurality of data stored in a register in accordance with a plurality of bits of address from being concentrated in one clock cycle. It is possible to prevent a decrease in the baud rate of serial communication and a decrease in the degree of freedom of the communication format.
  • FIG. 3 is a block diagram illustrating the configuration of the data communication device according to the first embodiment.
  • 5 is an example of an operation waveform diagram of the data communication device according to the first embodiment.
  • FIG. 9 is a block diagram illustrating a configuration of a register select circuit according to a comparative example.
  • FIG. 4 is an example of an operation waveform diagram of a data communication device including the register select circuit shown in FIG. 3.
  • FIG. 6 is a block diagram illustrating a configuration of a data communication device according to a second embodiment.
  • FIG. FIG. 7 is an example of an operation waveform diagram of the data communication device according to the second embodiment.
  • FIG. 1 is a block diagram illustrating the configuration of the data communication device according to the first embodiment.
  • data communication apparatus 100 includes serial reception circuit 101 for receiving serial reception data SDI from an external device such as an electronic device, and serial transmission data SDO to the external device. And a serial transmission circuit 106 for transmitting.
  • the data communication device 100 includes a register circuit 103 that stores transmission/reception data, a serial communication control circuit 104 that controls the serial reception circuit 101 and the serial transmission circuit 106, and a serial timing control circuit 105 that generates timings for serial reception and serial transmission. And further.
  • the serial reception circuit 101 has a shift register 102 for serial reception.
  • the serial transmission circuit 106 has a shift register 115 for serial transmission.
  • the shift register 102 operates in synchronization with the serial clock CLK and receives the serial reception data SDI.
  • the shift register 115 operates in synchronization with the serial clock CLK common to the shift register 102 and outputs the serial transmission data SDO.
  • the register circuit 103 can store 2 n pieces of received data that can be selected according to an n-bit (n: natural number of 3 or more) address. Each of the received data is composed of k bits (k: natural number of 2 or more).
  • the register circuit 103 includes 2 n registers (not shown) selected by an n-bit address, and each register can store k-bit received data.
  • K bits (8 bits) of received data are output from the data communication device 100 as serial transmission data SDO.
  • the serial transmission circuit 106 further includes a register select circuit 107 that selects one read data RDAT from the 2 n pieces of data (received data) of the register circuit 103.
  • the register select circuit 107 has first-stage selectors 108 and 109 and a second-stage selector 114. Each of the first-stage selectors 108 and 109 and the second-stage selector 114 is controlled by the serial communication control circuit 104 so as to operate in synchronization with the serial clock CLK.
  • the selectors 108 and 109 of the first stage select 128(2 (n-1) ):1 (128 to 1) based on the addresses A1 to A7 of the addresses A0 to A7.
  • the selection of the candidate data DAT0 and DAT1 by the first stage selectors 108 and 109 is executed in the same clock cycle, and in the clock cycle, the candidate data DAT0 and DAT1 are input to the second stage selector 114. ..
  • the k-bit read data RDAT selected by the register select circuit 107 based on the input addresses A0 to A7 is input to the shift register 115.
  • the shift register 115 outputs each bit of the k-bit read data RDAT as serial transmission data SDO in synchronization with the serial clock CLK.
  • FIG. 2 is an operation waveform diagram of the data communication device 100 according to the first embodiment.
  • FIG. 2 shows the contents of the serial reception data SDI and the serial transmission data SDO in each cycle (clock cycle) of the serial clock CLK.
  • the clock cycle of "Don't Care (DC)" to which another command or data can be assigned is shaded.
  • the serial reception data SDI from the external device is input to the serial reception circuit 101 in synchronization with the falling edge of the serial clock CLK.
  • the shift register 102 inside the serial reception circuit 101 captures the serial reception data SDI in synchronization with the rising edge of the serial clock CLK.
  • serial received data SDI is a read command (RCM) from the value of the serial received bit taken in the clock cycle including the time t0.
  • the addresses A7 to A1 are determined from the value of the serial reception bit fetched in the clock cycle including the times t1 to t7.
  • the undetermined address A0 is determined from the value of the serial reception bit fetched in the clock cycle including the time t8.
  • the confirmed address A0 is input to the second-stage selector 114.
  • the selector 114 of the second stage determines the read data RDAT by selecting one of the candidate data DAT0 and DAT1 from the selectors 108 and 109 of the first stage in the clock cycle in accordance with the determined address A0.
  • the register select circuit 107 determines the read data RDAT in the clock cycle after the clock cycle for selecting the candidate data DAT0 and DAT1. That is, the register select circuit 107 determines the read data RDAT by stepwise selection from 2 n pieces of data divided into a plurality of clock cycles.
  • the shift register 115 serially outputs the bits RD7 to RD0 forming the read data as the serial transmission data SDO in each clock cycle including the times t9 to t16.
  • the serial transmission data SDO is set to “Don't Care (DC)”.
  • the serial reception data SDI is “Don't Care (DC)”.
  • FIG. 3 shows the configuration of the register select circuit according to the comparative example.
  • n 8 addresses A0 to A7 and receives 2 n data (of the register circuit 103) in one clock cycle.
  • Register the register select circuit 107 directly outputs the read data RDAT similar to the selector 114 of the second stage in FIG. 1 to the shift register 115.
  • 256:1 (2 n :1) register selection is performed within two clock cycles, whereas in the configuration of the comparative example, one clock cycle is selected. It is necessary to perform register selection of the same scale within.
  • a dummy bit may be provided between the address A0 and the bit RD7 of the read data RDAT, which may lower the flexibility of the communication format. To be done.
  • the read command (RCM) and the addresses A0 to A7 are fetched in the clock cycle including the times t0 to t8 similar to FIG. 2, so that the addresses A0 to A7 are changed in the clock cycle including the time t8.
  • the selection is performed according to the addresses A0 to A7.
  • the bits RD7 to RD0 forming the read data RDAT to be read may be undetermined in the clock cycle including the next time t9. In this case, in the clock cycle including the next time t10, the shift is performed.
  • the register 115 is ready for output. Therefore, in the clock cycle including the times t10 to t17, the bits RD7 to RD0 forming the read data are serially output as the serial transmission data SDO.
  • the data communication apparatus it is possible to execute the 2 n :1 selection process using a plurality of clock cycles by using each partial bit of the n-bit address. Therefore, it is possible to prevent a decrease in the baud rate of the serial communication speed of full-duplex communication and a decrease in the degree of freedom of the communication format.
  • the addresses A1 to A7 for selecting the candidate data DAT0 and DAT1 out of the multi-bit addresses A0 to A7 correspond to an example of “partial bits”.
  • the address A0 for selecting the read data RDAT from the candidate data DAT0 and DAT1 corresponds to one embodiment of the "remaining bits”.
  • FIG. 5 is a block diagram for explaining the configuration of the data communication device according to the second embodiment.
  • data communication apparatus 200 according to the second embodiment is different from data communication apparatus 100 (FIG. 1) according to the first embodiment in that serial transmission circuit 106 is replaced with serial transmission circuit 206. It differs in that it is equipped with.
  • the serial transmission circuit 206 has a register select circuit 207 and a shift register 115 similar to that in FIG.
  • the configuration of the other parts of data communication apparatus 200 according to Embodiment 2 is similar to that of data communication apparatus 100 (FIG. 1) according to Embodiment 1, and therefore detailed description will not be repeated.
  • An example will be described in which one of the data (register) is selected and the read data RDAT composed of k bits (8 bits) is output from the data communication device 200 as the serial transmission data SDO.
  • the register select circuit 207 has first stage selectors 208 to 211, second stage selectors 212 and 213, and a third stage selector 214.
  • the selectors 208 to 214 are controlled by the serial communication control circuit 104 so as to operate in synchronization with the serial clock CLK.
  • the selection of the candidate data DAT00 to DAT11 by the first stage selectors 208 to 211 is executed in the same clock cycle, and in the clock cycle, the candidate data DAT00 and DAT01 are input to the second stage selector 212.
  • the candidate data DAT10 and DAT11 are input to the selector 213 in the second stage. That is, the candidate data DAT00, DAT01, DAT10, and DAT11 are selected by the addresses A2 to A7 from the 2 n pieces of data (reception data) stored in the register circuit 103.
  • the second-stage selector 212 selects one of the candidate data DAT00 and DAT01 from the first-stage selectors 208 and 209 based on the input address A1 and outputs it as candidate data DAT0.
  • the selection of the candidate data DAT0 and DAT1 by the selectors 212 and 213 of the second stage is executed in the same clock cycle, and in the clock cycle, the candidate data DAT0 and DAT1 are input to the selector 214 of the third stage. ..
  • the k-bit read data RDAT selected by the register select circuit 207 in three clock cycles based on the input addresses A0 to A7 is input to the shift register 115.
  • the shift register 115 outputs each bit of the k-bit read data RDAT as serial transmission data SDO in synchronization with the serial clock CLK.
  • FIG. 6 is an operation waveform diagram of the data communication device 200 according to the second embodiment.
  • the read command (RCM) and the addresses A2 to A7 are fetched in the same clock cycle including the times t0 to t6 as in FIG.
  • the clock cycle including the time t6 since 2 bits of the n-bit address, that is, the addresses A0 and A1 in this case, are undetermined, there are four possibilities for the reception data to be read from the register circuit 103. .. Therefore, in the clock cycle, the addresses A2 to A7 are input to the first stage selectors 208 to 211.
  • the undetermined address A1 is determined from the value of the serial reception bit fetched in the clock cycle including the next time t7.
  • the confirmed address A1 is input to the selectors 212 and 213 in the second stage.
  • the selector 212 of the second stage selects one of the candidate data DAT00 and DAT01 according to the confirmed address A1 in the clock cycle and outputs it as the candidate data DAT0 to the selector 214 of the third stage.
  • the selector 213 in the second stage selects one of the candidate data DAT10 and DAT11 according to the determined address A1 in the clock cycle and outputs it as the candidate data DAT1 to the selector 214 in the third stage.
  • the undetermined address A0 is determined from the value of the serial reception bit fetched in the clock cycle including the next time t8.
  • the confirmed address A0 is input to the selector 214 of the third stage.
  • the selector 214 of the third stage determines one of the candidate data DAT0 and DAT1 from the selectors 212 and 213 of the second stage as the read data RDAT according to the determined address A0.
  • the shift register 115 can output the bits RD7 to RD0 forming the read data RDAT as the serial transmission data SDO in each clock cycle (falling edge of the serial clock CLK) including the times t9 to t16.
  • the partial processing of 2 n :1 is performed by using a plurality of clock cycles by using a part of bits of the n-bit address. It is possible to prevent a decrease in baud rate of serial communication speed of duplex communication and a decrease in degree of freedom of communication format. That is, it is possible to perform communication in which a register read command is received from an external device and read data is returned from the register circuit 103 in the same packet in accordance with a predetermined full-duplex serial communication format.
  • the addresses A2 to A7 for selecting the candidate data DAT00 to DAT11 including the candidate data DAT0 and DAT1 out of the plural-bit addresses A0 to A7 are "partial bits".
  • the addresses A0 and A1 for determining the read data DAT from the candidate data DAT00 to DAT11 correspond to one embodiment of the "remaining bits”. That is, as shown in the second embodiment, the selection of "read data” based on the remaining bits from the "candidate data" selected based on some of the bits is executed over a plurality of clock cycles. May be done.
  • the division number m (m: natural number of (2 ⁇ m ⁇ n)) can be set arbitrarily.
  • the number of registers arranged increases as the number of divisions increases, the number of divisions m can be determined in consideration of the trade-off between the communication speed and the circuit scale.
  • 100, 200 data communication device 101 serial reception circuit, 102 shift register (for serial reception), 115 shift register (for serial transmission), 103 register circuit, 104 serial communication control circuit, 105 serial timing control circuit, 106, 206 serial Transmitter circuit, 107, 110, 207 register select circuit, 108, 109, 114, 208-214 selector, A0-A7 address, CLK serial clock, DAT0, DAT00, DAT1, DAT01, DAT10, DAT11 candidate data, RD0-RD7 bits (Read data), RDAT read data, SDI serial receive data, SDO serial send data.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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PCT/JP2019/000188 2019-01-08 2019-01-08 データ通信装置及びデータ通信方法 WO2020144737A1 (ja)

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PCT/JP2019/000188 WO2020144737A1 (ja) 2019-01-08 2019-01-08 データ通信装置及びデータ通信方法
JP2020565047A JP7052087B2 (ja) 2019-01-08 2019-01-08 データ通信装置及びデータ通信方法
CN201980087067.4A CN113272795B (zh) 2019-01-08 2019-01-08 数据通信装置以及数据通信方法

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6417284A (en) * 1987-07-09 1989-01-20 Nippon Electric Ic Microcomput Storage device
JPH04160445A (ja) * 1990-10-23 1992-06-03 Nec Corp メモリ集積回路
JP2008054053A (ja) * 2006-08-24 2008-03-06 Toshiba Corp 通信装置

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JP2000049623A (ja) * 1998-07-30 2000-02-18 Oki Electric Ind Co Ltd 伝送方法、多重送信回路、多重受信回路、多重送受信回路
JP4160445B2 (ja) 2003-05-26 2008-10-01 松下電器産業株式会社 画像処理システム及び画像処理方法
JP3920830B2 (ja) * 2003-09-19 2007-05-30 三洋電機株式会社 インターフェース回路、データ処理回路、データ処理システム、集積回路
JP2005352568A (ja) * 2004-06-08 2005-12-22 Hitachi-Lg Data Storage Inc アナログ信号処理回路、並びに、そのデータレジスタ書換方法とそのデータ通信方法
CN101405709B (zh) * 2006-03-23 2011-01-19 松下电器产业株式会社 通信控制装置及方法
JP2010039503A (ja) * 2008-07-31 2010-02-18 Panasonic Corp シリアルメモリ装置及び信号処理システム
JP5319572B2 (ja) * 2010-02-23 2013-10-16 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー メモリ装置
JP6417284B2 (ja) 2015-06-16 2018-11-07 株式会社沖データ インクジェットプリンター

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6417284A (en) * 1987-07-09 1989-01-20 Nippon Electric Ic Microcomput Storage device
JPH04160445A (ja) * 1990-10-23 1992-06-03 Nec Corp メモリ集積回路
JP2008054053A (ja) * 2006-08-24 2008-03-06 Toshiba Corp 通信装置

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CN113272795A (zh) 2021-08-17
JP7052087B2 (ja) 2022-04-11
JPWO2020144737A1 (ja) 2021-10-28

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