WO2020144737A1

WO2020144737A1 - Data communication device and data communication method

Info

Publication number: WO2020144737A1
Application number: PCT/JP2019/000188
Authority: WO
Inventors: 田中　進
Original assignee: 三菱電機株式会社
Priority date: 2019-01-08
Filing date: 2019-01-08
Publication date: 2020-07-16
Also published as: JP7052087B2; JPWO2020144737A1; CN113272795A; CN113272795B

Abstract

According to the present invention, a shift register (102) receives, as serial reception data (SDI) for each cycle of a serial clock (CLK), each bit of an address (A0 – A7) for selecting readout data (RDAT) from a plurality of pieces of data stored in a register circuit (103). A register selection circuit (107) executes, in different clock cycles, a selection of a plurality of pieces of candidate data (DAT1, DAT0) from among a plurality of pieces of data based on some bits (A1-A7) among the address (A0-A7), and a selection of the readout data (RDAT) from among the plurality of candidate data (DAT1, DAT0) based on the remaining bit (A0) among the plurality of bits. A shift register (115) outputs, as serial transmission data (SDO) for each cycle of the serial clock (CLK), a plurality of bits that form the selected readout data (RDAT).

Description

Data communication device and data communication method

The present invention relates to a data communication device and a data communication method.

In electronic devices, etc., a data communication device that executes serial communication is used for writing control commands and reading status or data. In such a data communication device, full duplex communication is generally performed in order to improve responsiveness.

In particular, as in Japanese Patent Laid-Open No. 9-50691 (Patent Document 1), the storage data of a plurality of built-in registers are selected based on the register address information stored in the serial reception data, and the selected register is selected. A configuration is used in which data is transmitted as serial transmission data of the same packet.

In such a high-speed serial communication system, in a configuration in which a large amount of register data is stored, selection of register data for generating serial transmission data from serially received register address information can be performed within a required time. It may not be completed. In such a case, it is necessary to reduce the baud rate or reduce the degree of freedom of the serial communication format by separating the register address of the serial reception data from the bit position of the register data of the serial transmission data. There is a concern that

For example, in the semiconductor memory device described in Patent Document 1, the baud rate of the serial communication system is prevented from being lowered by the configuration in which the register circuits are separately arranged for even addresses and odd addresses.

JP-A-9-50691

However, with the configuration of Patent Document 1, although continuous access to registers with continuous addresses can be speeded up, there is a concern that it is not possible to speed up reading of one-time register data.

The present invention has been made to solve such a problem, and an object of the present invention is to perform serial communication in a read data selection process using a plurality of bits of addresses by transmitting and receiving serial data in synchronization with a clock. It is to prevent the decrease of the baud rate and the freedom of the communication format.

According to an aspect of the present invention, a data communication device that operates in synchronization with a clock, including a reception circuit, a register circuit, a register select circuit, and a transmission circuit. The receiving circuit receives the serial data in synchronization with the clock. The register circuit includes an address composed of a plurality of bits and stores a plurality of received data selected by the address. The register select circuit selects read data from the plurality of received data stored in the register circuit in synchronization with the clock according to the address included in the plurality of bits received as the serial data by the receiving circuit every clock cycle. The transmission circuit transmits the read data selected by the register select circuit as serial data in synchronization with the clock. The register select circuit selects a plurality of candidate data from a plurality of received data based on some of the plurality of bits and a plurality of candidates based on the remaining bits excluding some of the plurality of bits. The selection of read data from the data is executed in different clock cycles.

According to still another aspect of the present invention, there is provided a data communication method for transmitting/receiving serial data in synchronization with a clock, which comprises an address for selecting read data from a plurality of data stored in a register circuit. A plurality of bits forming the address for receiving a part of the plurality of bits as serial data at each clock cycle and selecting read data from a register circuit that stores a plurality of received data selected by the address Some of the bits are received as serial data for each clock cycle, a plurality of candidate data is selected from the plurality of data based on the received some bits, and some of the plurality of bits of the address are selected. The remaining bits except the bits are received as serial data, and the read data is selected from the plurality of candidate data in a clock cycle after the clock cycle in which the plurality of candidate data is selected based on the received remaining bits. , The selected read data is transmitted as serial data every clock cycle.

According to the present invention, by transmitting and receiving serial data in synchronization with a clock, it is possible to prevent the processing of selecting read data from a plurality of data stored in a register in accordance with a plurality of bits of address from being concentrated in one clock cycle. It is possible to prevent a decrease in the baud rate of serial communication and a decrease in the degree of freedom of the communication format.

FIG. 3 is a block diagram illustrating the configuration of the data communication device according to the first embodiment. 5 is an example of an operation waveform diagram of the data communication device according to the first embodiment. FIG. 9 is a block diagram illustrating a configuration of a register select circuit according to a comparative example. FIG. 4 is an example of an operation waveform diagram of a data communication device including the register select circuit shown in FIG. 3. FIG. 6 is a block diagram illustrating a configuration of a data communication device according to a second embodiment. FIG. FIG. 7 is an example of an operation waveform diagram of the data communication device according to the second embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and the description thereof will not be repeated in principle.

Embodiment 1.
FIG. 1 is a block diagram illustrating the configuration of the data communication device according to the first embodiment.

Referring to FIG. 1, data communication apparatus 100 according to the first exemplary embodiment includes serial reception circuit 101 for receiving serial reception data SDI from an external device such as an electronic device, and serial transmission data SDO to the external device. And a serial transmission circuit 106 for transmitting.

The data communication device 100 includes a register circuit 103 that stores transmission/reception data, a serial communication control circuit 104 that controls the serial reception circuit 101 and the serial transmission circuit 106, and a serial timing control circuit 105 that generates timings for serial reception and serial transmission. And further.

The serial reception circuit 101 has a shift register 102 for serial reception. The serial transmission circuit 106 has a shift register 115 for serial transmission. The shift register 102 operates in synchronization with the serial clock CLK and receives the serial reception data SDI. The shift register 115 operates in synchronization with the serial clock CLK common to the shift register 102 and outputs the serial transmission data SDO.

The register circuit 103 can store 2 ⁿ pieces of received data that can be selected according to an n-bit (n: natural number of 3 or more) address. Each of the received data is composed of k bits (k: natural number of 2 or more). For example, the register circuit 103 includes 2 ⁿ registers (not shown) selected by an n-bit address, and each register can store k-bit received data. In the following, it is assumed that n=8 and k=8, and one of the 2 ⁸ =256 received data (registers) stored in the register circuit 103 is selected by the addresses A0 to A7. , K bits (8 bits) of received data are output from the data communication device 100 as serial transmission data SDO.

The serial transmission circuit 106 further includes a register select circuit 107 that selects one read data RDAT from the 2 ⁿ pieces of data (received data) of the register circuit 103. The register select circuit 107 has first-

stage selectors

108 and 109 and a second-stage selector 114. Each of the first-

stage selectors

108 and 109 and the second-stage selector 114 is controlled by the serial communication control circuit 104 so as to operate in synchronization with the serial clock CLK.

The

selectors

108 and 109 of the first stage select 128(2 ^(n-1) ):1 (128 to 1) based on the addresses A1 to A7 of the addresses A0 to A7. As a result, the selector 108 of the first stage outputs the input addresses A1 to A7 and DAT0 selected by A0="0" as candidate data. Similarly, the selector 109 of the first stage outputs DAT1 selected by the inputted addresses A1 to A7 and A0=“1” as candidate data. That is, the candidate data DAT0 and DAT1 are selected by the addresses A1 to A7 from the 2 ⁿ pieces of data stored in the register circuit 103.

The selection of the candidate data DAT0 and DAT1 by the

first stage selectors

108 and 109 is executed in the same clock cycle, and in the clock cycle, the candidate data DAT0 and DAT1 are input to the second stage selector 114. ..

The second stage selector 114 selects one of the candidate data DAT0 and DAT1 from the

first stage selectors

108 and 109 as the read data RDAT based on the input address A0, and outputs it to the shift register 115. For example, when the input address A0=“0”, the candidate data DAT0 is selected, while when the input address A0=“1”, the candidate data DAT1 is selected.

As a result, the k-bit read data RDAT selected by the register select circuit 107 based on the input addresses A0 to A7 is input to the shift register 115. The shift register 115 outputs each bit of the k-bit read data RDAT as serial transmission data SDO in synchronization with the serial clock CLK.

FIG. 2 is an operation waveform diagram of the data communication device 100 according to the first embodiment. FIG. 2 shows the contents of the serial reception data SDI and the serial transmission data SDO in each cycle (clock cycle) of the serial clock CLK. In the figure, the clock cycle of "Don't Care (DC)" to which another command or data can be assigned is shaded.

Referring to FIG. 2, the serial reception data SDI from the external device is input to the serial reception circuit 101 in synchronization with the falling edge of the serial clock CLK. The shift register 102 inside the serial reception circuit 101 captures the serial reception data SDI in synchronization with the rising edge of the serial clock CLK.

ㆍIt is confirmed that the serial received data SDI is a read command (RCM) from the value of the serial received bit taken in the clock cycle including the time t0. Further, the addresses A7 to A1 are determined from the value of the serial reception bit fetched in the clock cycle including the times t1 to t7.

In the clock cycle including time t7, one bit of the n-bit address, here address A0, is undetermined, so there are two possibilities for the data to be read from the register circuit 103. Therefore, in the clock cycle, the addresses A1 to A7 are input to the

first stage selectors

108 and 109. As a result, the

selectors

108 and 109 of the first stage have the candidate data DAT0 corresponding to the confirmed addresses A1 to A7 and the unconfirmed A0="0" within the clock cycle, and the confirmed addresses A1 to A7. The candidate data DAT1 corresponding to undetermined A0=“1” is selected and output to the selector 114 of the second stage.

The undetermined address A0 is determined from the value of the serial reception bit fetched in the clock cycle including the time t8. The confirmed address A0 is input to the second-stage selector 114. The selector 114 of the second stage determines the read data RDAT by selecting one of the candidate data DAT0 and DAT1 from the

selectors

108 and 109 of the first stage in the clock cycle in accordance with the determined address A0. In this way, the register select circuit 107 determines the read data RDAT in the clock cycle after the clock cycle for selecting the candidate data DAT0 and DAT1. That is, the register select circuit 107 determines the read data RDAT by stepwise selection from 2 ⁿ pieces of data divided into a plurality of clock cycles.

As a result, in the clock cycle including the time t9, the bits RD7 to RD0 forming the read data RDAT selected according to the addresses A0 to A7 are fixed. Therefore, the shift register 115 serially outputs the bits RD7 to RD0 forming the read data as the serial transmission data SDO in each clock cycle including the times t9 to t16.

Further, in the clock cycle including the times t0 to t8 when the command and the addresses A0 to A7 are fetched as the serial reception data SDI, the serial transmission data SDO is set to “Don't Care (DC)”. On the other hand, in the clock cycle including the times t9 to t16 when the bits RD7 to RD0 forming the read data RDAT are transmitted as the serial transmission data SDO, the serial reception data SDI is “Don't Care (DC)”. It is said that

As a result, in the data communication device according to the first embodiment, according to the full-duplex serial communication format composed of the command 1 bit, the address 8 bits (n=8) and the data 8 bits (k=8), Communication can be performed in which a register read command is received from a device and read data from the register circuit 103 is returned in the same packet.

FIG. 3 shows the configuration of the register select circuit according to the comparative example.
With reference to FIG. 3, the register select circuit 110 of the comparative example receives n-bit (n=8) addresses A0 to A7 and receives 2 ⁿ data (of the register circuit 103) in one clock cycle. Register). That is, the register select circuit 107 directly outputs the read data RDAT similar to the selector 114 of the second stage in FIG. 1 to the shift register 115. As a result, in the data communication device of the first embodiment, 256:1 (2 ⁿ :1) register selection is performed within two clock cycles, whereas in the configuration of the comparative example, one clock cycle is selected. It is necessary to perform register selection of the same scale within.

Therefore, if the selection process by the register select circuit 110 of the comparative example is not in time, it is necessary to reduce the frequency of the serial clock CLK, and there is a concern that the serial communication speed may be reduced.

On the other hand, if the serial clock frequency is kept the same, as shown in FIG. 4, a dummy bit may be provided between the address A0 and the bit RD7 of the read data RDAT, which may lower the flexibility of the communication format. To be done.

Referring to FIG. 4, the read command (RCM) and the addresses A0 to A7 are fetched in the clock cycle including the times t0 to t8 similar to FIG. 2, so that the addresses A0 to A7 are changed in the clock cycle including the time t8. Determine. On the other hand, ^{assuming that the} 256:1 (2 ⁿ :1) selection process by the register select circuit 110 requires two clock cycles as in FIG. 3, in the comparative example, the selection is performed according to the addresses A0 to A7. The bits RD7 to RD0 forming the read data RDAT to be read may be undetermined in the clock cycle including the next time t9. In this case, in the clock cycle including the next time t10, the shift is performed. The register 115 is ready for output. Therefore, in the clock cycle including the times t10 to t17, the bits RD7 to RD0 forming the read data are serially output as the serial transmission data SDO.

As a result, in the operation waveform of FIG. 4, during the clock cycle in which the serial transmission of the bits RD7 to RD0 forming the read data RDAT is started from the clock cycle in which the address is fixed, the serial reception data SDI and the serial transmission data SDO are transmitted. Both of them become "Don't Care (DC)" (clock cycle including time t9 in FIG. 4) occurs. This reduces the degree of freedom of the communication format due to an increase in the serial bit length and the like.

On the other hand, according to the data communication apparatus according to the first embodiment, it is possible to execute the 2 ⁿ :1 selection process using a plurality of clock cycles by using each partial bit of the n-bit address. Therefore, it is possible to prevent a decrease in the baud rate of the serial communication speed of full-duplex communication and a decrease in the degree of freedom of the communication format.

In the first embodiment, the addresses A1 to A7 for selecting the candidate data DAT0 and DAT1 out of the multi-bit addresses A0 to A7 correspond to an example of “partial bits”. The address A0 for selecting the read data RDAT from the candidate data DAT0 and DAT1 corresponds to one embodiment of the "remaining bits".

Embodiment 2.
In the first embodiment, the n-bit address is divided into two, and the register selection based on (n-1) bits and the register selection based on 1 bit are executed stepwise using two clock cycles. I explained an example. However, this division number m is not limited to 2, and may be an arbitrary natural number of 2 or more (2≦m<n). In the second embodiment, a configuration example in which m=3 will be described.

FIG. 5 is a block diagram for explaining the configuration of the data communication device according to the second embodiment.
Referring to FIG. 5, data communication apparatus 200 according to the second embodiment is different from data communication apparatus 100 (FIG. 1) according to the first embodiment in that serial transmission circuit 106 is replaced with serial transmission circuit 206. It differs in that it is equipped with. The serial transmission circuit 206 has a register select circuit 207 and a shift register 115 similar to that in FIG. The configuration of the other parts of data communication apparatus 200 according to Embodiment 2 is similar to that of data communication apparatus 100 (FIG. 1) according to Embodiment 1, and therefore detailed description will not be repeated. In the second embodiment, as in the first embodiment, it is assumed that n=8 and k=8, and 2 ⁸ =256 data stored in the register circuit 103 by the addresses A0 to A7. An example will be described in which one of the data (register) is selected and the read data RDAT composed of k bits (8 bits) is output from the data communication device 200 as the serial transmission data SDO.

The register select circuit 207 has first stage selectors 208 to 211,

second stage selectors

212 and 213, and a third stage selector 214. The selectors 208 to 214 are controlled by the serial communication control circuit 104 so as to operate in synchronization with the serial clock CLK.

The first stage selectors 208 to 211 select 64(2 ^(n-2) ): 1 (64 to 1) based on the addresses A2 to A7 of the addresses A0 to A7. In this selection, since the addresses A0 and A1 are undetermined, there are four ways (A0,A1)=(0,0), (0,1), (1,0), and (1,1). The possibilities remain.

The first-stage selector 208 outputs the candidate data DAT00 selected by the input addresses A2 to A7 and A1="0", A0="0". Similarly, the selector 209 of the first stage outputs the candidate data DAT01 selected by the inputted addresses A2 to A7 and A1="0", A0="1". The selector 210 of the first stage outputs the candidate data DAT10 selected by the input addresses A2 to A7 and A1="1", A0="0", and the selector 211 of the first stage outputs the candidate data DAT10. The candidate data DAT11 selected by the input addresses A2 to A7 and A1="1", A0="1" is output. The selection of the candidate data DAT00 to DAT11 by the first stage selectors 208 to 211 is executed in the same clock cycle, and in the clock cycle, the candidate data DAT00 and DAT01 are input to the second stage selector 212. The candidate data DAT10 and DAT11 are input to the selector 213 in the second stage. That is, the candidate data DAT00, DAT01, DAT10, and DAT11 are selected by the addresses A2 to A7 from the 2 ⁿ pieces of data (reception data) stored in the register circuit 103.

The second-stage selector 212 selects one of the candidate data DAT00 and DAT01 from the first-

stage selectors

208 and 209 based on the input address A1 and outputs it as candidate data DAT0. Similarly, the selector 213 of the second stage selects one of the candidate data DAT10 and DAT11 from the

selectors

210 and 211 of the first stage based on the input address A1 and outputs it as the candidate data DAT1. In this selection, since the address A0 is undetermined, there are two possibilities of A0="0" and "1".

The selection of the candidate data DAT0 and DAT1 by the

selectors

212 and 213 of the second stage is executed in the same clock cycle, and in the clock cycle, the candidate data DAT0 and DAT1 are input to the selector 214 of the third stage. ..

The third-stage selector 214 selects one of the candidate data DAT0 and DAT1 from the second-

stage selectors

212 and 213 as the read data RDAT based on the input address A0, and outputs it to the shift register 115. For example, when the input address A0="0", the candidate data DAT0 is output, while when the input address A0="1", the candidate data DAT1 is output.

As a result, the k-bit read data RDAT selected by the register select circuit 207 in three clock cycles based on the input addresses A0 to A7 is input to the shift register 115. The shift register 115 outputs each bit of the k-bit read data RDAT as serial transmission data SDO in synchronization with the serial clock CLK.

FIG. 6 is an operation waveform diagram of the data communication device 200 according to the second embodiment.
Referring to FIG. 6, the read command (RCM) and the addresses A2 to A7 are fetched in the same clock cycle including the times t0 to t6 as in FIG. In the clock cycle including the time t6, since 2 bits of the n-bit address, that is, the addresses A0 and A1 in this case, are undetermined, there are four possibilities for the reception data to be read from the register circuit 103. .. Therefore, in the clock cycle, the addresses A2 to A7 are input to the first stage selectors 208 to 211.

As a result, the

first stage selectors

208 and 209 determine the confirmed addresses A2 to A7, the undetermined candidate data DAT00 with A1="0" and A0="0", and the confirmed address in the clock cycle. The candidate data DAT01 of A2 to A7 and undetermined A1="0" and A0="1" are respectively output to the selector 212 of the second stage.

Similarly, the

selectors

210 and 211 of the first stage receive the confirmed addresses A2 to A7, the undetermined candidate data DAT10 of A1="1" and A0="0", and the confirmed address in the clock cycle. The candidate data DAT11 of A2 to A7 and undetermined A1="1" and A0="1" are output to the selector 213 in the second stage.

-The undetermined address A1 is determined from the value of the serial reception bit fetched in the clock cycle including the next time t7. The confirmed address A1 is input to the

selectors

212 and 213 in the second stage. The selector 212 of the second stage selects one of the candidate data DAT00 and DAT01 according to the confirmed address A1 in the clock cycle and outputs it as the candidate data DAT0 to the selector 214 of the third stage. Similarly, the selector 213 in the second stage selects one of the candidate data DAT10 and DAT11 according to the determined address A1 in the clock cycle and outputs it as the candidate data DAT1 to the selector 214 in the third stage.

Further, the undetermined address A0 is determined from the value of the serial reception bit fetched in the clock cycle including the next time t8. The confirmed address A0 is input to the selector 214 of the third stage. In the clock cycle, the selector 214 of the third stage determines one of the candidate data DAT0 and DAT1 from the

selectors

212 and 213 of the second stage as the read data RDAT according to the determined address A0. Also in the second embodiment, the register select circuit 207 in the clock cycle later than the clock cycle for selecting candidate data DAT0, DAT1, and to accept the read data RDAT, divided into a plurality of clock cycles, ^{2 n} It is understood that the read data RDAT is determined by the stepwise selection from the individual data.

As a result, as in FIG. 2, in the clock cycle including the next time t9, the bits RD7 to RD0 forming the read data RDAT selected according to the addresses A0 to A7 are fixed. Therefore, the shift register 115 can output the bits RD7 to RD0 forming the read data RDAT as the serial transmission data SDO in each clock cycle (falling edge of the serial clock CLK) including the times t9 to t16.

As described above, also in the data communication apparatus according to the second embodiment, the partial processing of 2 ⁿ :1 is performed by using a plurality of clock cycles by using a part of bits of the n-bit address. It is possible to prevent a decrease in baud rate of serial communication speed of duplex communication and a decrease in degree of freedom of communication format. That is, it is possible to perform communication in which a register read command is received from an external device and read data is returned from the register circuit 103 in the same packet in accordance with a predetermined full-duplex serial communication format.

In the second embodiment, the addresses A2 to A7 for selecting the candidate data DAT00 to DAT11 including the candidate data DAT0 and DAT1 out of the plural-bit addresses A0 to A7 are "partial bits". Corresponding to. Further, the addresses A0 and A1 for determining the read data DAT from the candidate data DAT00 to DAT11 correspond to one embodiment of the "remaining bits". That is, as shown in the second embodiment, the selection of "read data" based on the remaining bits from the "candidate data" selected based on some of the bits is executed over a plurality of clock cycles. May be done.

Further, in the first and second embodiments, an example in which m=2 and m=3 when dividing the 2 ⁿ :1 register selection processing by the n-bit address into m stages has been described, respectively. As described above, the division number m (m: natural number of (2≦m<n)) can be set arbitrarily. However, since the number of registers arranged increases as the number of divisions increases, the number of divisions m can be determined in consideration of the trade-off between the communication speed and the circuit scale.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

100, 200 data communication device, 101 serial reception circuit, 102 shift register (for serial reception), 115 shift register (for serial transmission), 103 register circuit, 104 serial communication control circuit, 105 serial timing control circuit, 106, 206 serial Transmitter circuit, 107, 110, 207 register select circuit, 108, 109, 114, 208-214 selector, A0-A7 address, CLK serial clock, DAT0, DAT00, DAT1, DAT01, DAT10, DAT11 candidate data, RD0-RD7 bits (Read data), RDAT read data, SDI serial receive data, SDO serial send data.

Claims

A data communication device that operates in synchronization with a clock,
A receiving circuit for receiving serial data in synchronization with the clock,
A register circuit including an address composed of a plurality of bits and storing a plurality of received data selected by the address;
A register that selects read data from the plurality of received data stored in the register circuit in synchronization with the clock according to the address included in the plurality of bits received as the serial data by the receiving circuit in each clock cycle. Select circuit,
A transmission circuit for transmitting the read data selected by the register select circuit as serial data in synchronization with the clock,
The register select circuit selects a plurality of candidate data from the plurality of received data based on some of the plurality of bits, and selects remaining bits of the plurality of bits excluding the some of the bits. A data communication device, which performs selection of the read data from the plurality of candidate data based on different clock cycles.
The register select circuit is
When some of the bits of the address are received by the receiving circuit, the selection of the plurality of candidate data is performed from the plurality of received data, and after the selection of the plurality of candidate data, the remaining bits are received by the receiving circuit. Performing a selection of the read data from the plurality of candidate data as received by a circuit,
The data communication device according to claim 1, wherein the read data is selected in a clock cycle in which the reception circuit completes reception of the plurality of bits of the address.
The transmission circuit starts transmission of the serial data including a plurality of bits forming the read data in a clock cycle subsequent to a clock cycle in which the reception of the plurality of bits is completed. Data communication device.
A data communication method for transmitting and receiving serial data in synchronization with a clock,
In order to select read data from a register circuit that stores a plurality of received data selected by an address, a part of a plurality of bits forming the address is received as the serial data every clock cycle,
Selecting a plurality of candidate data from the plurality of received data based on the received part of the bits,
Receiving the remaining bits excluding the some bits of the plurality of bits of the address as the serial data,
Selecting the read data from the plurality of candidate data in a clock cycle after the clock cycle of selecting the plurality of candidate data based on the received remaining bits,
A data communication method, wherein the selected read data is transmitted as the serial data every clock cycle.
The data communication method according to claim 4, wherein the transmission of the serial data including a plurality of bits forming the read data is started from a clock cycle next to a clock cycle in which the reception of the plurality of bits of the address is completed.