WO2020136973A1 - シリコンエピタキシャルウェーハの製造方法及びシリコンエピタキシャルウェーハ - Google Patents

シリコンエピタキシャルウェーハの製造方法及びシリコンエピタキシャルウェーハ Download PDF

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WO2020136973A1
WO2020136973A1 PCT/JP2019/030722 JP2019030722W WO2020136973A1 WO 2020136973 A1 WO2020136973 A1 WO 2020136973A1 JP 2019030722 W JP2019030722 W JP 2019030722W WO 2020136973 A1 WO2020136973 A1 WO 2020136973A1
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wafer
silicon
less
epitaxial layer
plane
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English (en)
French (fr)
Japanese (ja)
Inventor
昌幸 石橋
みどり 吉田
大介 丸岡
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Sumco Corp
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Sumco Corp
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Priority to KR1020217016881A priority Critical patent/KR102508213B1/ko
Priority to CN201980086171.1A priority patent/CN113544817B/zh
Priority to US17/296,281 priority patent/US11990336B2/en
Priority to DE112019006437.1T priority patent/DE112019006437T5/de
Publication of WO2020136973A1 publication Critical patent/WO2020136973A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/16—Controlling or regulating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/14—Preparing bulk and homogeneous wafers by setting crystal orientation

Definitions

  • the present invention relates to a silicon epitaxial wafer manufacturing method and a silicon epitaxial wafer.
  • the carrier mobility in a pMOS transistor is higher than that of a wafer having a ⁇ 100 ⁇ plane as a main surface, so that the pMOS transistor can be sped up.
  • the epitaxial wafer is used as a material for high-performance devices because the epitaxial layer has very few defects. Therefore, the epitaxial wafer having the ⁇ 110 ⁇ plane as the main surface is expected as a material for high-performance devices such as MPU (Patent Document 1).
  • the DIC method is a method capable of detecting the number of step-like minute defects having an uneven shape in which the height or depth of the wafer surface exceeds a predetermined threshold value, for example, 2 nm.
  • the defect is a defect having a width of 30 to 200 ⁇ m and a height of about 2 to 90 nm, which is difficult to detect in other detection modes.
  • the problem to be solved by the present invention is to provide a silicon epitaxial wafer manufacturing method and a silicon epitaxial wafer capable of suppressing DIC defects.
  • the present invention relates to a silicon epitaxial wafer in which an epitaxial layer is vapor-phase grown on the main surface of a silicon single crystal wafer whose main surface is a ⁇ 110 ⁇ surface or a surface whose off-angle from the ⁇ 110 ⁇ surface is less than 1 degree.
  • a method for producing a silicon epitaxial wafer wherein the temperature of the silicon single crystal wafer is set to 1100° C. to 1135° C., and the epitaxial layer is vapor-grown at a growth rate of 2.0 ⁇ m/min to 3.0 ⁇ m/min.
  • the main surface of the silicon single crystal wafer is a surface having an off angle from the ⁇ 110 ⁇ plane of more than 0 degree and less than 1 degree.
  • the surface of the epitaxial layer may be mirror-polished.
  • a polishing liquid containing abrasive grains having a grain size of 20 nm or less and to perform mirror polishing with a polishing allowance of more than 0 and 0.2 ⁇ m or less.
  • the present invention is a silicon epitaxial wafer in which an epitaxial layer is grown on a silicon single crystal substrate having a ⁇ 110 ⁇ plane or a plane whose off-angle from the ⁇ 110 ⁇ plane is less than 1 degree as a main surface,
  • the number of minute step defects on the surface of the epitaxial layer observed using a differential interference contrast method is 1.5/300 mm wafer or less,
  • the main surface of the silicon single crystal wafer is a surface having an off angle from the ⁇ 110 ⁇ plane of more than 0 degree and less than 1 degree.
  • the haze level (measured in SP2 and DWO mode) of the surface of the epitaxial layer is more preferably 0.4 ppm or less.
  • the silicon single crystal wafer is more preferably a wafer to which boron is added and the resistivity of which is adjusted to 1 m ⁇ cm to 100 m ⁇ cm.
  • the present invention it is possible to provide a silicon epitaxial wafer manufacturing method and a silicon epitaxial wafer capable of suppressing DIC defects.
  • FIG. 6 is a graph showing the growth rate and growth temperature (wafer temperature) of Examples 1 to 6 of the present invention and Comparative Examples 1 to 6. It is a graph which shows the temperature of a wafer, the growth rate, and the relationship between a DIC defect.
  • FIG. 1 is a graph showing the growth rate and growth temperature (wafer temperature) of Examples 1 to 6 of the present invention and Comparative Examples 1 to 6.
  • the method for manufacturing a silicon epitaxial wafer according to the present embodiment has an epitaxial layer on the main surface of a silicon single crystal wafer whose main surface is a ⁇ 110 ⁇ surface or a surface having an off angle from the ⁇ 110 ⁇ surface of less than 1 degree. It is a vapor phase growth.
  • a wafer having an off-angle of 1 degree or more from the ⁇ 110 ⁇ plane of the main surface has insufficient device characteristics such as high carrier mobility.
  • a preferable wafer to which the manufacturing method of this embodiment is applied is Silicon single crystal wafer whose main surface is a surface whose off-angle from the ⁇ 110 ⁇ plane is 0 degree, or silicon single crystal whose main surface is a surface whose off-angle from the ⁇ 110 ⁇ plane is more than 0 degree and less than 1 degree It is a wafer.
  • silicon single crystal wafer whose off-angle from the ⁇ 110 ⁇ plane is more than 0 degree and less than 1 degree is used as the main surface, not only the DIC defect but also the PV value of the surface roughness of the epitaxial layer is improved. Can be made smaller.
  • the method for manufacturing a silicon epitaxial wafer of the present embodiment on the main surface of the silicon single crystal wafer having a crystal plane described above, in vapor phase growing an epitaxial layer, the temperature of the wafer and the growth rate of the epitaxial layer, the wafer
  • the temperature is set to 1100° C. to 1135° C. and the growth rate of the epitaxial layer is set to 2.0 ⁇ m/min to 3.0 ⁇ m/min. More specifically, it is in the range shown in Examples 1 to 6 of FIG. 1 and is 1100° C. ⁇ 2.0 ⁇ m. /Min to 1135° C. ⁇ 3.0 ⁇ m/min.
  • the temperature of the wafer is the actual temperature of the wafer placed in the chamber of the vapor phase growth apparatus, and is controlled by the power supplied to the heating lamp or the like.
  • the growth rate of the epitaxial layer is the film thickness of the epitaxial layer formed on the main surface of the wafer per unit time, and the reaction gas (for example, silicon tetrachloride SiCl 4 or tritium chloride) supplied into the chamber of the vapor phase growth apparatus is used. It is controlled by the concentration of chlorosilane (such as SiHCl 3 ) per unit time (concentration and flow rate of source gas).
  • FIG. 2 shows that the growth rate of the epitaxial layer is set to two levels, that is, a relatively slow condition and a fast condition, and the wafer temperature is set to two levels, that is, a relatively high temperature and a low temperature, respectively.
  • the wafer temperature is set to a relatively low temperature of 1100° C. to 1135.
  • the temperature is preferably set to °C.
  • the number of micro step defects on the surface of the epitaxial layer observed using the differential interference contrast method is 1.5/300 mm wafer or less, and the epitaxial step observed using a white microscope. Silicon epitaxial wafers with a PV value of the surface roughness of the layer of less than 10 nm can be obtained.
  • the surface of the epitaxial layer may be mirror-polished after the epitaxial layer is vapor-phase grown.
  • a polishing liquid containing abrasive grains having a particle diameter of 20 nm or less can be used to perform mirror polishing with a polishing allowance of more than 0 and 0.2 ⁇ m or less.
  • the silicon single crystal wafer may be a wafer in which boron is added and the resistivity is adjusted to 1 m ⁇ cm to 100 m ⁇ cm.
  • a p-type silicon single crystal ingot having a main axis orientation of ⁇ 110> and a diameter of 305 mm was manufactured by a silicon single crystal pulling apparatus using the CZ method. This ingot was ground to a diameter of 300 mm and then subjected to notch processing to cut out a plurality of blocks having a resistivity of 1 to 100 m ⁇ cm. This block was sliced using a wire saw so that the inclination of the ⁇ 110 ⁇ plane was 0° and 0.35° of the off angle with respect to the inclination azimuth ⁇ 100>.
  • the wafer taken out from the CVD equipment was immediately passivated with SC-1 cleaning solution.
  • a part of the obtained epitaxial wafer was polished on the surface of the epitaxial surface by more than 0 and 0.2 ⁇ m or less using a one-side polishing apparatus and a polishing liquid containing abrasive grains having a grain size of 20 nm or less.
  • ⁇ DIC defect density>> The measurement of the minute step defect density on the surface of the epitaxial layer was performed by a differential interference contrast (DIC) method. Specifically, the measurement was performed in a DIC mode (a measurement mode by the DIC method) using a wafer surface inspection device (Surfscan SP3 manufactured by KLA-Tencor). In the measurement, the threshold value of the height of the step-like microdefects having the uneven shape was set to 3 nm, and the number of step-like microdefects exceeding this threshold value (per 300 mm wafer) was obtained.
  • DIC differential interference contrast
  • PV value of surface roughness The PV value (Peak to Valley) showing the roughness of the surface of the epitaxial layer was determined by a white microscope.
  • the white microscope splits the LED beam with a half mirror and irradiates it on the reference surface and the sample surface. While swinging this in the Z direction, there is no interference between the beam returning from the reference surface and the beam returning from the sample surface.
  • the 3D image is obtained by forming an image with the strongest point as the focal position.
  • ⁇ haze value >> The haze value of the surface of the epitaxial layer was measured by a DWO mode (Dark Field Wide Oblique mode, dark field wide oblique incidence mode) using a surface inspection device (Surfscan SP2 manufactured by KLA-Tencor).
  • the wafer temperature and the growth rate of the epitaxial layer are set as follows. If the temperature is set to 1100° C. to 1135° C. and the growth rate of the epitaxial layer is set to 2.0 ⁇ m/min to 3.0 ⁇ m/min, the DIC defect density becomes 1.5 or less per 300 mm wafer. In addition to being possible, the PV value of the surface roughness can be made less than 10 nm.
  • the main surface of the silicon single crystal wafer is a surface whose off-angle from the ⁇ 110 ⁇ plane is more than 0 degree and less than 1 degree, specifically, 0.35 degree, with respect to the surface roughness PV.
  • the value can be further improved to 4 nm or less.
  • the haze level before mirror-polishing is about 0.4 ppm, whereas the haze level can be improved to about 0.03 ppm.
  • Quality control such as (Light Point Defects, bright spot defects) becomes possible.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
PCT/JP2019/030722 2018-12-27 2019-08-05 シリコンエピタキシャルウェーハの製造方法及びシリコンエピタキシャルウェーハ Ceased WO2020136973A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020217016881A KR102508213B1 (ko) 2018-12-27 2019-08-05 실리콘 에피택셜 웨이퍼의 제조 방법 및 실리콘 에피택셜 웨이퍼
CN201980086171.1A CN113544817B (zh) 2018-12-27 2019-08-05 硅外延晶片的制造方法和硅外延晶片
US17/296,281 US11990336B2 (en) 2018-12-27 2019-08-05 Silicon epitaxial wafer production method and silicon epitaxial wafer
DE112019006437.1T DE112019006437T5 (de) 2018-12-27 2019-08-05 Siliziumepitaxialwaferherstellungsverfahren und siliziumepitaxialwafer

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JP2018245109A JP7063259B2 (ja) 2018-12-27 2018-12-27 シリコンエピタキシャルウェーハの製造方法
JP2018-245109 2018-12-27

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WO2025192168A1 (ja) * 2024-03-15 2025-09-18 信越半導体株式会社 シリコン基板の熱処理方法

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JP7629154B2 (ja) * 2022-01-26 2025-02-13 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
US20230326752A1 (en) * 2022-04-08 2023-10-12 Sumco Corporation Flat epitaxial wafer having minimal thickness variation

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JP2015162522A (ja) * 2014-02-26 2015-09-07 株式会社Sumco エピタキシャルシリコンウェーハの製造方法及びエピタキシャルシリコンウェーハ

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WO2025192168A1 (ja) * 2024-03-15 2025-09-18 信越半導体株式会社 シリコン基板の熱処理方法

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