WO2020133998A1 - 贴片式电容及其制作方法 - Google Patents

贴片式电容及其制作方法 Download PDF

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Publication number
WO2020133998A1
WO2020133998A1 PCT/CN2019/094160 CN2019094160W WO2020133998A1 WO 2020133998 A1 WO2020133998 A1 WO 2020133998A1 CN 2019094160 W CN2019094160 W CN 2019094160W WO 2020133998 A1 WO2020133998 A1 WO 2020133998A1
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Prior art keywords
electrode
sub
pin
layer
insulating layer
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PCT/CN2019/094160
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English (en)
French (fr)
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何成功
戴立杰
左成杰
何军
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安徽安努奇科技有限公司
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Priority claimed from CN201822220448.0U external-priority patent/CN209071139U/zh
Priority claimed from CN201811613733.7A external-priority patent/CN109473282A/zh
Application filed by 安徽安努奇科技有限公司 filed Critical 安徽安努奇科技有限公司
Publication of WO2020133998A1 publication Critical patent/WO2020133998A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors

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  • the embodiments of the present application relate to the technical field of electronic components, for example, to a chip capacitor and a manufacturing method thereof.
  • SMD capacitors are commonly used in a variety of electronic products.
  • the size and electrical performance of SMD capacitors directly affect the size and performance of electronic products with integrated SMD capacitors. This makes how SMD capacitors can be miniaturized and The electrical characteristics of high withstand voltage become a crucial issue.
  • the present application provides a chip capacitor and a method for manufacturing the same, which improves the pressure resistance of the chip capacitor. It is conducive to achieving the miniaturization of the chip capacitor, and is conducive to accurately controlling the size of the chip capacitor and improving The accuracy of the chip capacitor is also helpful to reduce the resistance of the chip capacitor and improve the quality factor (Q value) of the chip capacitor.
  • an embodiment of the present application provides a chip capacitor.
  • the chip capacitor includes:
  • a stacked structure which includes a first metal layer, an insulating layer, and a second metal layer that are sequentially spaced along the stacking direction, and the patterned metal structures located in the adjacent metal layers respectively form the first One electrode and the second electrode;
  • the second electrode includes a first sub-electrode and a second sub-electrode, the patterned metal structure constituting the first sub-electrode and the patterned metal structure constituting the second sub-electrode are located on the same first metal layer or A second metal layer; along the lamination direction, the vertical projection of the first electrode partially overlaps with the vertical projection of the first sub-electrode, the vertical projection of the first electrode and the vertical projection of the second sub-electrode There is partial overlap, and the vertical projection of the first sub-electrode does not overlap with the vertical projection of the second sub-electrode.
  • the thickness of the insulating layer is smaller than the thickness of the first metal layer and the second metal layer.
  • the chip capacitor further includes a pin layer on a side of the second electrode away from the first electrode, the pin layer including the first pin and In the second pin, the first sub-electrode is electrically connected to the first pin, and the second sub-electrode is electrically connected to the second pin.
  • At least one insulating layer is included between the pin layer and the second electrode, and the first sub-electrode passes through the insulating layer between the pin layer and the second electrode
  • the first via structure is electrically connected to the first pin
  • the second sub-electrode passes through the second via structure and the second lead in the insulating layer between the pin layer and the second electrode Foot electrical connection.
  • the first pin includes a first pad structure and a first patterned metal structure on the first pad structure, the first sub-electrode and the first patterned metal Structural electrical connection;
  • the second pin includes a second pad structure and a second patterned metal structure on the second pad structure, and the second sub-electrode is electrically connected to the second patterned metal structure.
  • the first electrode is a full-face electrode
  • the first sub-electrode and the second sub-electrode are bulk electrodes.
  • the material constituting the insulating layer includes at least one of the following: silicon nitride, aluminum oxide, and tantalum oxide.
  • an embodiment of the present application further provides a method for manufacturing a chip capacitor, which is used to manufacture the chip capacitor in the first aspect.
  • the method for manufacturing a chip capacitor includes:
  • the chip capacitor further includes a pin layer on a side of the second electrode away from the first electrode, the pin layer is provided with a first pin and a Two pins
  • the manufacturing method further includes: after forming the patterned metal structure constituting the second electrode on the first insulating layer and before removing the substrate or grinding the substrate,
  • first sub-electrode passes through the first via structure and the first One pin is electrically connected
  • second sub-electrode is electrically connected to the second pin through a second via structure located in the second insulating layer.
  • the first pin includes a first pad structure and a first patterned metal structure on the first pad structure, the first sub-electrode and the first patterned metal Structural electrical connection;
  • the second pin includes a second pad structure and a second patterned metal structure on the second pad structure, and the second sub-electrode is electrically connected to the second patterned metal structure.
  • the first electrode is a full-face electrode
  • the first sub-electrode and the second sub-electrode are bulk electrodes.
  • the material constituting the insulating layer includes at least one of the following: silicon nitride, aluminum oxide, and tantalum oxide.
  • Embodiments of the present application provide a chip capacitor and a method for manufacturing the same.
  • Setting a chip capacitor includes a stacked structure.
  • the stacked structure includes a first metal layer, an insulating layer, and a second metal layer that are sequentially spaced along the stacking direction.
  • the patterned metal structure in the adjacent metal layer forms the first electrode and the second electrode of the chip capacitor
  • the second electrode includes the first sub-electrode and the second sub-electrode, the patterned metal structure and the composition of the first sub-electrode
  • the patterned metal structure of the second sub-electrode is located on the same first metal layer or second metal layer, along the stacking direction, the vertical projection of the first electrode partially overlaps with the vertical projection of the first sub-electrode, and the vertical projection of the first electrode It partially overlaps with the vertical projection of the second sub-electrode, and the vertical projection of the first sub-electrode does not overlap with the vertical projection of the second sub-electrode, that is, the first electrode and the first sub-electrode and the second sub-electrode There is a facing part, and the first electrode and the first sub-electrode and the first electrode and the second sub-electrode all form a capacitance structure.
  • the patch type is improved
  • the voltage resistance of the capacitor and can be made into a chip capacitor using a semiconductor process, which is conducive to achieving the miniaturization of the chip capacitor, is also conducive to accurately controlling the size of the chip capacitor, and improving the accuracy of the chip capacitor. At the same time, it also helps to reduce the resistance of the chip capacitor and improve the Q value of the chip capacitor.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of a chip capacitor provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a chip capacitor provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a chip capacitor provided by an embodiment of the present application.
  • An embodiment of the present application provides a chip capacitor.
  • the chip capacitor includes a stacked structure, and the stacked structure includes a first metal layer, an insulating layer, and a second metal layer that are sequentially spaced along the stacking direction and are located in adjacent metal layers.
  • the patterned metal structure forms the first electrode and the second electrode of the chip capacitor.
  • the second electrode includes a first sub-electrode and a second sub-electrode.
  • the patterned metal structure constituting the first sub-electrode and the patterned metal structure constituting the second sub-electrode are located on the same first metal layer or second metal layer.
  • the vertical projection of the first electrode partially overlaps, the vertical projection of the first electrode partially overlaps the vertical projection of the second sub-electrode, and the vertical projection of the first sub-electrode and the second sub-electrode
  • the vertical projection of the electrodes does not overlap.
  • SMD capacitors are commonly used in a variety of electronic products.
  • the size and electrical performance of SMD capacitors directly affect the size and performance of electronic products with integrated SMD capacitors. This makes how SMD capacitors can be miniaturized and The electrical characteristics of high withstand voltage become a crucial issue.
  • the chip capacitor provided by the embodiment of the present application includes a stacked structure, and the stacked structure includes a first metal layer, an insulating layer and a second metal layer that are sequentially spaced along the stacking direction, and a patterned metal structure located in an adjacent metal layer forms a patch
  • the first electrode and the second electrode of the chip capacitor, the second electrode includes the first sub-electrode and the second sub-electrode, the patterned metal structure constituting the first sub-electrode and the patterned metal structure constituting the second sub-electrode are located at the same A metal layer or a second metal layer, along the stacking direction, the vertical projection of the first electrode partially overlaps the vertical projection of the first sub-electrode, the vertical projection of the first electrode partially overlaps the vertical projection of the second sub-electrode, and The vertical projection of the first sub-electrode does not overlap with the vertical projection of the second sub-electrode, that is, the first electrode, the first sub-electrode, and the second sub
  • Chip capacitors are conducive to achieving miniaturization of chip capacitors, and are also conducive to accurately controlling the size of chip capacitors, improving the accuracy of chip capacitors, reducing the equivalent series resistance of capacitors, and improving the performance of chip capacitors. Q value.
  • FIG. 1 is a schematic diagram of a three-dimensional structure of a chip capacitor provided by an embodiment of the application
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a chip capacitor provided by an embodiment of the application.
  • the chip capacitor includes a stacked structure including a layer of insulating layer 1 and two layers of metal layer 2 spaced along the stacking direction XX′.
  • the insulating layer is not shown in FIG.
  • the patterned metal structure in the metal layer 2 forms the first electrode 3 and the second electrode 4 of the chip capacitor, where the first electrode 3 can be set in the first metal layer 21 and the second electrode 4 can be in the second metal layer 22 in.
  • the second electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42.
  • the patterned metal structure constituting the first sub-electrode 41 and the patterned metal structure constituting the second sub-electrode 42 are located on the same second metal layer 22.
  • the vertical projection of the first electrode 3 partially overlaps with the vertical projection of the first sub-electrode 41 and the vertical projection of the second sub-electrode 42, that is, along the stacking direction of the stacked structure XX', the first The first sub-electrode 41 of the first electrode 3 and the second electrode 4 and the second sub-electrode 42 of the first electrode 3 and the second electrode 4 are directly facing each other.
  • the first sub-electrode 41 forms a capacitor structure
  • the second sub-electrode 42 of the first electrode 3 and the second electrode 4 forms another capacitor structure.
  • the first electrode 3 may be provided as a full-surface electrode, and the first sub-electrode 41 and the second sub-electrode 42 may be block electrodes. That is, by setting the first electrode 3 as a complete planar electrode, the capacitance formed by the first sub-electrode 41 and the first electrode 3, and the capacitance formed by the second sub-electrode 42 and the first electrode 3 can use the first The electrodes 3 are electrically connected to form a series structure.
  • the embodiments of the present application do not limit the specific shapes of the first electrode 3, the first sub-electrode 41, and the second sub-electrode 42, and ensure that the first electrode 3 and the first sub-electrode are along the stacking direction XX′ of the stacked structure. Both the electrode 41 and the second sub-electrode 42 only need to be provided facing each other.
  • the material constituting the insulating layer 1 includes at least one of silicon nitride SiN x , aluminum oxide AlO x and tantalum oxide TaO x , x>0.
  • the material constituting the insulating layer 1 includes at least one of silicon nitride SiN x , aluminum oxide AlO x and tantalum oxide TaO x , x>0.
  • it includes at least one of silicon nitride, aluminum oxide, and tantalum oxide.
  • the insulating layer 1 between the first metal layer 21 and the second metal layer 22 plays an insulating role to realize the electrical insulation of the first metal layer 21 and the second metal layer 22, thereby achieving the patch In the capacitor, the electrical insulation between the first electrode 3 and the second electrode 4, that is, between the first electrode 3 and the first sub-electrode 41 of the second electrode 4, and between the first electrode 3 and the second electrode 4
  • the second sub-electrode 42 is electrically insulated, while the insulating layer 1 serves as a dielectric layer between the first electrode 3 and the second electrode 4 of the chip capacitor, that is, serves as the first of the first electrode 3 and the second electrode 4
  • the second electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42, so that the first electrode 3 and the second electrode 4 form a series capacitance structure, that is, the first electrode 3 and the second electrode 4
  • the capacitor structure formed by the first sub-electrode 41 in series is connected in series with the capacitor structure formed by the first sub-electrode 3 and the second sub-electrode 42 of the second electrode 4, and the capacitor formed by the two full-surface electrodes includes only one layer of dielectric Layer supply breakdown, the series capacitor structure formed by the first electrode 3 and the first sub-electrode 41 and the second sub-electrode 42 includes two dielectric layers to supply breakdown, which is beneficial without changing the volume of the chip capacitor , Improve the voltage resistance of chip capacitors.
  • chip capacitors are chip multilayer ceramic capacitors (Muiti-layer Ceramic Capacitors, MLCC), which are sintered with multi-layer ceramic materials, the production process is rough, and it is impossible to accurately control the chip capacitors. The size, the accuracy and Q value of the chip capacitor are low, and it is difficult to achieve the miniaturization of the chip capacitor.
  • an insulating layer 1 and two metal layers 2 spaced along the lamination direction XX′ are used to form a chip capacitor, and the patterned metal structure in the two metal layers 2 forms the first in the chip capacitor.
  • One electrode 3, the first sub-electrode 41 of the second electrode 4, and the second sub-electrode 42 of the second electrode 4 can be made into a chip capacitor by a semiconductor process, which is beneficial to the miniaturization of the chip capacitor At the same time, it is beneficial to accurately control the size of the chip capacitor, improve the accuracy of the chip capacitor, reduce the equivalent series resistance of the capacitor, and increase the Q value of the chip capacitor.
  • the thickness of the insulating layer 1 may be smaller than the thickness of the metal layer 2, that is, the first metal layer 21 and the second metal layer may be disposed
  • the thickness of the insulating layer 1 between 22 is smaller than the thickness of the first metal layer 21 and the second metal layer 22, that is, the thickness of the dielectric layer in the chip capacitor is smaller than that of the first electrode 3 and the second electrode 4
  • the thicknesses of the sub-electrode 41 and the second sub-electrode 42 are beneficial to increase the capacitance density of the chip capacitor, to obtain a larger capacitance per unit area, and to further increase the Q value of the chip capacitor.
  • the chip capacitor may further include a pin layer 5 on the side of the second electrode 4 away from the first electrode 3, the pin layer 5 is provided with In the first pin 51 and the second pin 52, the first sub-electrode 41 is electrically connected to the first pin 51, and the second sub-electrode 42 is electrically connected to the second pin 52.
  • the first sub-electrode 41 provided with a chip capacitor is electrically connected to the first pin 51
  • the second sub-electrode 42 is electrically connected to the second pin 52
  • the first pin 51 and the second pin 52 are used as a chip capacitor
  • Two terminals electrically connected to other electronic components so that a capacitor structure formed by the first electrode 3 and the first sub-electrode 41 is formed inside the chip capacitor in series with the capacitor structure formed by the first electrode 3 and the second sub-electrode 42 relationship.
  • At least one insulating layer may be provided between the pin layer 5 and the second electrode 4, and FIG. 2 is exemplarily provided between the pin layer 5 and the second electrode 4 Including an insulating layer 6, the first sub-electrode 41 is electrically connected to the first pin 51 through the first via structure 61 in the insulating layer 1 between the pin layer 5 and the second electrode 4, the second sub-electrode 42 is electrically connected to the second pin 52 through the second via structure 62 in the insulating layer 6 between the pin layer 5 and the second electrode 4.
  • the insulating layer 6 between the pin layer 5 and the second electrode 4 is used to achieve electrical insulation between the first sub-electrode 41 and the first pin 51 without an electrical connection, and to realize the second sub-electrode 42 and the second pin 52 No electrical insulation of the electrical connection is required.
  • the first pin 51 may include a first pad structure 511 and a first patterned metal structure 512 on the first pad structure 511, and the first sub-electrode 41 It is electrically connected to the first patterned metal structure 512.
  • the second pin 52 includes a second pad structure 521 and a second patterned metal structure 522 on the second pad structure 521, and the second sub-electrode 42 is electrically connected to the second patterned metal structure 522.
  • the first sub-electrode 41 is electrically connected to the first patterned metal structure 512 to realize the electrical connection between the first sub-electrode 41 and the first pin 51
  • the second sub-electrode 42 is electrically connected to the second patterned metal structure 522 to realize the first
  • the two sub-electrodes 42 are electrically connected to the second pin 52.
  • the materials constituting the first pad structure 511 and the second pad structure 521 may be solder, which facilitates the soldering of the chip capacitor on the printed circuit board, and the first pattern constituting the first pin 51 may be provided
  • the material of the metallized metal structure 512 and the second patterned metal structure 522 constituting the second pin 52 are the same as the material of each metal layer 2 constituting the stacked structure.
  • the embodiment of the present application does not limit the materials that constitute the metal layer 2 in the stacked structure, that is, the materials that constitute the first electrode 3, the first sub-electrode 41, and the second sub-electrode 42, and a metal with high conductivity can be used. Materials or metal oxide materials to maximize the Q value of chip capacitors.
  • FIG. 3 is a method of manufacturing a chip capacitor provided by an embodiment of the present application. Schematic diagram of the process. As shown in FIG. 3, the manufacturing method of the chip capacitor includes:
  • Step 110 Form a substrate.
  • the substrate can be 8-inch wafer, 12-inch wafer or 500mm x 500mm size wafer and other larger size wafers, the shape of the substrate can be round, square, rectangular, etc.
  • the material of the substrate may be at least one of silicon, glass, quartz, ceramic, or organic.
  • Step 120 Form a patterned metal structure constituting the first electrode on the substrate.
  • a patterned metal structure constituting the first electrode 3 is formed on the substrate (the substrate not shown in FIGS. 1 and 2 ), which can be electroplated or sputtered, or firstly through physical or chemical A method such as vapor deposition first deposits a first metal layer 21, and then performs a patterning process on the formed first metal layer 21, for example, an etching process is used to form a patterned metal structure that constitutes the first electrode 3.
  • the patterned metal structure constituting the first electrode 3 may be formed by an electroplating process. The electroplating process can form a metal film layer with a large thickness, which is beneficial to increase the Q value of the chip capacitor.
  • Step 130 Form a first insulating layer on the patterned metal structure constituting the first electrode.
  • the first insulating layer 1 is formed on the patterned metal structure constituting the first electrode 3.
  • the material constituting the first insulating layer 1 includes at least one of silicon nitride SiN x , aluminum oxide AlO x and tantalum oxide TaO x , when the material constituting the first insulating layer 1
  • the silicon nitride is SiN x
  • the first insulating layer 1 can be formed by a chemical vapor deposition process, for example, the first insulating layer 1 can be formed by a plasma enhanced chemical vapor deposition method, and the deposition temperature required by the plasma enhanced chemical vapor deposition is low , Has little effect on the structure and physical properties of the film layer, the thickness and composition uniformity of the formed film layer is good, and the film layer is dense and has strong adhesion.
  • the material constituting the first insulating layer 1 is aluminum oxide AlO x or tantalum oxide TaO x
  • the first insulating layer 1 may be formed by using an atomic layer
  • the first insulation may also be made according to the shapes of the first sub-electrode 41 and the second sub-electrode 42
  • Layer 1 forms a corresponding patterned structure to ensure that the first insulating layer 1 can play an insulating role, so as to achieve the first electrode 3 and the first sub-electrode 41, and between the first electrode 3 and the second sub-electrode 42 Electrical insulation is sufficient.
  • Step 140 Form a patterned metal structure constituting the second electrode on the first insulating layer.
  • a plating or sputtering process or first deposit a second metal layer 22 by physical or chemical vapor deposition, etc., and then perform a patterning process on the formed second metal layer 22, for example
  • An etching process is used to form a patterned metal structure constituting the second electrode 4 to form the first sub-electrode 41 and the second sub-electrode 42.
  • an electroplating process can be used to form the patterned metal structure that constitutes the second electrode 4.
  • the electroplating process can form a metal film layer with a large thickness, which is beneficial to increase the Q value of the chip capacitor.
  • Step 150 Remove the substrate or grind the substrate.
  • the chip capacitor further includes a pin layer 5 on the side of the second electrode 4 away from the first electrode 3.
  • the pin layer 5 is provided with a One pin 51 and the second pin 52.
  • the above manufacturing method may further include the pattern constituting the second electrode 4 after forming the patterned metal structure constituting the second electrode 4 on the first insulating layer 1 and before the removing the substrate or grinding the substrate.
  • the second insulating layer 6 is formed on the metallized structure, and the first via structure and the second via structure are formed on the set position of the second insulating layer 6, and the first pin 51 and the first lead are formed on the second insulating layer 6 Two pins 52.
  • the first sub-electrode 41 is electrically connected to the first pin 51 through the first via structure 61 in the second insulating layer 6, and the second sub-electrode 42 is connected to the first via structure 62 in the second insulating layer 6
  • the second pin 52 is electrically connected.
  • the materials constituting the first pin 51 and the second pin 52 fill the first electrode on the second insulating layer 6 Via structure 61 and second via structure 62, the first sub-electrode 41 is electrically connected to the first pin 51 through the first via structure 61 in the second insulating layer 6, and the second sub-electrode 42 is positioned through the second insulation
  • the second via structure 62 in layer 6 is electrically connected to the second pin 52.
  • the first pin 51 includes a first pad structure 511 and a first patterned metal structure 512 on the first pad structure 511
  • the second pin 52 includes a second solder
  • the disk structure 521 and the second patterned metal structure 522 located on the second pad structure 521 can be formed on the second insulating layer 6 with the first patterned metal structure 512 and the second patterned metal structure 522 first, and then A corresponding pad structure is formed on a patterned metal structure 512 and a second patterned metal structure 522, and the metal structures in the first pin 51 and the second pin 52 can be set to have the same shape as the corresponding pad structure. At the same time to achieve patterning to simplify the process.
  • the substrate or the substrate can be removed, that is, stripped over the patterned metal structure constituting the first electrode 3 Or grinding the substrate above the patterned metal structure constituting the first electrode 3 to form a complete chip capacitor.
  • the metal layer 2 and the insulating layer 1 can be cut to form a standard surface-mount device size, such as 0201, 01005 or a smaller size surface-mount device.
  • the thickness of the first insulating layer 1 may be smaller than the thickness of the first metal layer 21 and the second metal layer 22.
  • the first pin may include a first pad structure and a first patterned metal structure on the first pad structure, the first sub-electrode and the first patterned Metal structure electrical connection;
  • the second pin includes a second pad structure and a second patterned metal structure on the second pad structure, and the second sub-electrode is electrically connected to the second patterned metal structure.
  • the first electrode may be a full-face electrode, and the first sub-electrode and the second sub-electrode are bulk electrodes.
  • the material constituting the insulating layer may include at least one of the following: silicon nitride, aluminum oxide, and tantalum oxide.
  • the chip capacitor provided by the embodiment of the present application includes a stacked structure.
  • the stacked structure includes an insulating layer and two metal layers spaced apart along the stacking direction, and the patterned metal structure located in the adjacent metal layer forms the chip capacitor.
  • the first electrode and the second electrode, the second electrode includes a first sub-electrode and a second sub-electrode, the patterned metal structure constituting the first sub-electrode and the patterned metal structure constituting the second sub-electrode are located in the same first metal layer Or the second metal layer, along the stacking direction, there is a partial overlap between the vertical projection of the first electrode and the vertical projection of the first sub-electrode and the vertical projection of the second sub-electrode, ie the first electrode and the first sub-electrode and the second sub-electrode
  • the electrodes are all facing each other, and the first electrode and the first sub-electrode and the first electrode and the second sub-electrode all form a capacitance
  • the patch is improved
  • the pressure resistance of built-in capacitors on the other hand, the use of semiconductor technology to make chip capacitors is conducive to achieving the miniaturization of chip capacitors, it is also conducive to accurately controlling the size of chip capacitors, and improving the Accuracy, and can reduce the equivalent series resistance of the capacitor, improve the Q value of the chip capacitor.

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Abstract

一种贴片式电容及其制作方法，贴片式电容包括层叠结构，层叠结构包括沿层叠方向间隔设置的绝缘层和金属层，位于相邻金属层中的第一电极和第二电极；第二电极包括第一子电极和第二子电极；沿层叠方向，第一电极的垂直投影与第一子电极的垂直投影以及第二子电极的垂直投影均存在部分重叠。

Description

贴片式电容及其制作方法
本申请要求在2018年12月27日提交中国专利局、申请号为201811613733.7和201822220448.0的中国专利申请的优先权，上述申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及电子元件技术领域，例如涉及一种贴片式电容及其制作方法。
背景技术
随着用户对电子产品小型化要求的提高，电子产品的集成度逐渐提高，这就对电子产品中所包含的电子元件的尺寸提出了更高的要求，电子元件如何兼顾小型化以及电子元件本身的电学性能成为亟待解决的问题。
贴片式电容普遍应用在多种电子产品中，贴片式电容的尺寸与电学性能直接影响集成有贴片式电容的电子产品的尺寸与性能，这就使得贴片式电容如何兼顾小型化以及高耐压的电学特性成为至关重要的问题。
发明内容
本申请提供一种贴片式电容及其制作方法，提高了贴片式电容的耐压性，在有利于实现贴片式电容小型化的同时，有利于精确控制贴片式电容的尺寸，提高贴片式电容的精度，同时也有利于降低贴片式电容的电阻，提高贴片式电容的品质因数(Q值)。
第一方面，本申请实施例提供了一种贴片式电容，贴片式电容包括：
层叠结构，所述层叠结构包括沿层叠方向依次间隔设置的第一金属层、绝缘层和第二金属层，位于相邻的金属层中的图案化金属结构分别形成所述贴片式电容的第一电极和第二电极；
所述第二电极包括第一子电极和第二子电极，构成所述第一子电极的图案化金属结构和构成所述第二子电极的图案化金属结构位于同一所述第一金属层或者第二金属层；沿所述层叠方向，所述第一电极的垂直投影与所述第一子电 极的垂直投影部分重叠、所述第一电极的垂直投影与所述第二子电极的垂直投影均存在部分重叠、以及所述第一子电极的垂直投影与所述第二子电极的垂直投影不重叠。
在一实施例中，沿所述层叠方向，所述绝缘层的厚度小于所述第一金属层以及所述第二金属层的厚度。
在一实施例中，沿所述层叠方向，所述贴片式电容还包括位于所述第二电极远离所述第一电极一侧的引脚层，所述引脚层包括第一引脚和第二引脚，所述第一子电极与所述第一引脚电连接，所述第二子电极与所述第二引脚电连接。
在一实施例中，所述引脚层与所述第二电极之间包括至少一层绝缘层，所述第一子电极通过所述引脚层与所述第二电极之间绝缘层中的第一过孔结构与所述第一引脚电连接，所述第二子电极通过所述引脚层与所述第二电极之间绝缘层中的第二过孔结构与所述第二引脚电连接。
在一实施例中，所述第一引脚包括第一焊盘结构和位于所述第一焊盘结构上的第一图案化金属结构，所述第一子电极与所述第一图案化金属结构电连接；
所述第二引脚包括第二焊盘结构和位于所述第二焊盘结构上的第二图案化金属结构，所述第二子电极与所述第二图案化金属结构电连接。
在一实施例中，所述第一电极为整面电极，所述第一子电极与所述第二子电极为块状电极。
在一实施例中，构成所述绝缘层的材料包括以下至少一种：硅的氮化物、铝的氧化物和钽的氧化物。
第二方面，本申请实施例还提供了一种贴片式电容的制作方法，用于制作第一方面的贴片式电容，贴片电容的制作方法包括：
形成衬底；
在所述衬底上形成构成所述第一电极的图案化金属结构；
在构成所述第一电极的图案化金属结构上形成第一绝缘层；
在所述第一绝缘层上形成构成所述第二电极的图案化金属结构；
去除所述衬底或研磨所述衬底。
在一实施例中，沿层叠方向，所述贴片式电容还包括位于所述第二电极远离所述第一电极一侧的引脚层，所述引脚层设置有第一引脚和第二引脚；
所述制作方法还包括：在所述第一绝缘层上形成构成所述第二电极的图案化金属结构之后以及在所述去除所述衬底或研磨所述衬底之前，
在构成所述第二电极的图案化金属结构上形成第二绝缘层并在所述第二绝缘层的设定位置上形成所述第一过孔结构和所述第二过孔结构；
在所述第二绝缘层上形成所述第一引脚和所述第二引脚，其中，所述第一子电极通过位于所述第二绝缘层中的第一过孔结构与所述第一引脚电连接，所述第二子电极通过位于所述第二绝缘层中的第二过孔结构与所述第二引脚电连接。
在一实施例中，所述第一引脚包括第一焊盘结构和位于所述第一焊盘结构上的第一图案化金属结构，所述第一子电极与所述第一图案化金属结构电连接；
所述第二引脚包括第二焊盘结构和位于所述第二焊盘结构上的第二图案化金属结构，所述第二子电极与所述第二图案化金属结构电连接。
在一实施例中，所述第一电极为整面电极，所述第一子电极与所述第二子电极为块状电极。
在一实施例中，构成所述绝缘层的材料包括以下至少一种：硅的氮化物、铝的氧化物和钽的氧化物。
本申请实施例提供了一种贴片式电容及其制作方法，设置贴片式电容包括层叠结构，层叠结构包括沿层叠方向依次间隔设置的第一金属层、绝缘层和第二金属层，位于相邻金属层中的图案化金属结构形成贴片式电容的第一电极和第二电极，第二电极包括第一子电极和第二子电极，构成第一子电极的图案化金属结构和构成第二子电极的图案化金属结构位于同一第一金属层或者第二金属层，沿层叠方向，第一电极的垂直投影与第一子电极的垂直投影部分重叠、所述第一电极的垂直投影与所述第二子电极的垂直投影部分重叠、以及所述第一子电极的垂直投影与所述第二子电极的垂直投影不重叠，即第一电极与第一子电极与第二子电极均存在正对部分，第一电极与第一子电极以及第一电极与第二子电极均形成电容结构，通过将第二电极分为第一子电极以及第二子电极，提高了贴片式电容的耐压性，且可以采用半导体工艺制成贴片式电容，在有利于实现贴片式电容小型化的同时，有利于精确控制贴片式电容的尺寸，提高贴片式电容的精度，同时也有利于降低贴片式电容的电阻，提高贴片式电容的Q值。
附图说明
图1为本申请一实施例提供的一种贴片式电容的立体结构示意图。
图2为本申请一实施例提供的一种贴片式电容的剖面结构示意图。
图3为本申请一实施例提供的一种贴片式电容的制作方法的流程示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。本说明书中，相同或相似的附图标号代表相同或相似的结构、元件或流程。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本申请实施例提供了一种贴片式电容，贴片式电容包括层叠结构，层叠结构包括沿层叠方向依次间隔设置的第一金属层、绝缘层和第二金属层，位于相邻金属层中的图案化金属结构形成贴片式电容的第一电极和第二电极。第二电极包括第一子电极和第二子电极，构成第一子电极的图案化金属结构和构成第二子电极的图案化金属结构位于同一第一金属层或者第二金属层。沿层叠方向，第一电极的垂直投影部分重叠、所述第一电极的垂直投影与所述第二子电极的垂直投影部分重叠、以及所述第一子电极的垂直投影与所述第二子电极的垂直投影不重叠。
随着用户对电子产品小型化要求的提高，电子产品的集成度逐渐提高，这就对电子产品中所包含的电子元件的尺寸提出了更高的要求，电子元件如何兼顾小型化以及电子元件本身的电学性能成为亟待解决的问题。贴片式电容普遍应用在多种电子产品中，贴片式电容的尺寸与电学性能直接影响集成有贴片式电容的电子产品的尺寸与性能，这就使得贴片式电容如何兼顾小型化以及高耐压的电学特性成为至关重要的问题。
本申请实施例提供的贴片式电容包括层叠结构，层叠结构包括沿层叠方向依次间隔设置的第一金属层、绝缘层和第二金属层，位于相邻金属层中的图案化金属结构形成贴片式电容的第一电极和第二电极，第二电极包括第一子电极 和第二子电极，构成第一子电极的图案化金属结构和构成第二子电极的图案化金属结构位于同一第一金属层或者第二金属层，沿层叠方向，第一电极的垂直投影与第一子电极的垂直投影部分重叠、所述第一电极的垂直投影与第二子电极的垂直投影部分重叠、以及所述第一子电极的垂直投影与所述第二子电极的垂直投影不重叠，即第一电极与第一子电极与第二子电极均存在正对部分，第一电极与第一子电极以及第一电极与第二子电极均形成电容结构，通过将第二电极分为第一子电极以及第二子电极，提高了贴片式电容的耐压性，且可以采用半导体工艺制成贴片式电容，在有利于实现贴片式电容小型化的同时，有利于精确控制贴片式电容的尺寸，提高贴片式电容的精度，降低电容的等效串联电阻，提高贴片式电容的Q值。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下，所获得的所有其他实施例，都属于本申请保护的范围。
图1为本申请一实施例提供的一种贴片式电容的立体结构示意图，图2为本申请实施例提供的一种贴片式电容的剖面结构示意图。结合图1和图2，贴片式电容包括层叠结构，层叠结构包括沿层叠方向XX’间隔设置的一层绝缘层1和两层金属层2，图1中未示出绝缘层，位于相邻金属层2中的图案化金属结构形成贴片式电容的第一电极3和第二电极4，这里可以设置第一电极3位于第一金属层21中，第二电极4位于第二金属层22中。第二电极4包括第一子电极41和第二子电极42，构成第一子电极41的图案化金属结构和构成第二子电极42的图案化金属结构位于同一第二金属层22。
沿层叠结构的层叠方向XX’，第一电极3的垂直投影与第一子电极41的垂直投影以及第二子电极42的垂直投影均存在部分重叠，即沿层叠结构的层叠方向XX’，第一电极3与第二电极4中的第一子电极41，以及第一电极3与第二电极4中的第二子电极42均存在正对部分，第一电极3与第二电极4中的第一子电极41形成一电容结构，第一电极3与第二电极4中的第二子电极42形成另一电容结构。
示例性地，结合图1和图2，可以设置第一电极3为整面电极，第一子电极41与第二子电极42为块状电极。即通过将第一电极3设置为一块完整的面状电极，第一子电极41和第一电极3所构成的电容，与第二子电极42和第一电极3所构成的电容可以利用第一电极3实现电连接，形成串联结构。需要说明的是，本申请实施例对第一电极3、第一子电极41以及第二子电极42的具体形状不作限定，确保沿层叠结构的层叠方向XX’，第一电极3与第一子电极41以及第二子电极42均存在正对设置的部分即可。
示例性地，可以设置构成绝缘层1的材料包括硅的氮化物SiN x、铝的氧化物AlO x和钽的氧化物TaO x中的至少一种，x>0。例如，包括氮化硅、氧化铝和氧化钽中的至少一种。结合图1和图2，位于第一金属层21和第二金属层22之间的绝缘层1起到绝缘作用，实现第一金属层21与第二金属层22的电绝缘，进而实现贴片式电容中第一电极3与第二电极4之间的电绝缘，即第一电极3与第二电极4中的第一子电极41之间，以及第一电极3与第二电极4中的第二子电极42之间的电绝缘，同时绝缘层1充当贴片式电容第一电极3与第二电极4之间的介电层，即充当第一电极3与第二电极4中的第一子电极41形成的电容结构，以及第一电极3与第二电极4中的第二子电极42形成的电容结构的介电层。
结合图1和图2，设置第二电极4包括第一子电极41和第二子电极42，使得第一电极3与第二电极4形成串联电容结构，即第一电极3与第二电极4中的第一子电极41形成的电容结构，与第一电极3与第二电极4中的第二子电极42形成的电容结构串联，相对于两整面电极构成的电容仅包含一层介电层供给击穿，第一电极3与第一子电极41以及第二子电极42形成的串联电容结构包含两层介电层供给击穿，这样有利于在不改变贴片式电容体积的前提下，提升贴片式电容的耐压性。
另外，目前普遍采用的贴片式电容为片式多层陶瓷电容器(Muiti-layer Ceramic Capacitors，MLCC)，其采用多层陶瓷材料烧结而成，制作工艺较粗糙，无法精确控制贴片式电容的尺寸，贴片式电容精度与Q值较低，且很难实现贴 片式电容的小型化。本申请实施例利用沿层叠方向XX’间隔设置的一层绝缘层1和两层金属层2形成贴片式电容，位于两层金属层2中的图案化金属结构形成贴片式电容中的第一电极3、第二电极4中的第一子电极41以及第二电极4中的第二子电极42，可以采用半导体工艺制成贴片式电容，在有利于实现贴片式电容小型化的同时，有利于精确控制贴片式电容的尺寸，提高贴片式电容的精度，降低电容的等效串联电阻，提高贴片式电容的Q值。
在一实施例中，结合图1和图2，沿层叠结构的层叠方向XX’，可以设置绝缘层1的厚度小于金属层2的厚度，即可以设置位于第一金属层21与第二金属层22之间的绝缘层1的厚度小于第一金属层21以及第二金属层22的厚度，即设置贴片式电容中的介电层的厚度小于第一电极3、第二电极4中第一子电极41以及第二子电极42的厚度，有利于提高贴片式电容的电容密度，在单位面积内获得更大的电容，同时有利于进一步提高贴片式电容的Q值。
在一实施例中，结合图1和图2，沿层叠方向XX’，贴片式电容还可以包括位于第二电极4远离第一电极3一侧的引脚层5，引脚层5设置有第一引脚51和第二引脚52，第一子电极41与第一引脚51电连接，第二子电极42与第二引脚52电连接。设置贴片式电容的第一子电极41与第一引脚51电连接，第二子电极42与第二引脚52电连接，第一引脚51与第二引脚52作为贴片式电容与其它电子元件电连接的两个端点，使得贴片式电容内部形成第一电极3与第一子电极41形成的电容结构，与第一电极3与第二子电极42形成的电容结构的串联关系。
在一实施例中，结合图1和图2，可以设置引脚层5与第二电极4之间包括至少一层绝缘层，图2示例性地设置引脚层5与第二电极4之间包括一层绝缘层6，第一子电极41通过引脚层5与第二电极4之间的绝缘层1中的第一过孔结构61与第一引脚51实现电连接，第二子电极42通过引脚层5与第二电极4之间的绝缘层6中的第二过孔结构62与第二引脚52实现电连接。引脚层5与第二电极4之间的绝缘层6用于实现第一子电极41与第一引脚51无需电连接部分的电绝缘，以及实现第二子电极42与第二引脚52无需电连接部分的电绝 缘。
在一实施例中，结合图1和图2，可以设置第一引脚51包括第一焊盘结构511和位于第一焊盘结构511上的第一图案化金属结构512，第一子电极41与第一图案化金属结构512电连接。第二引脚52包括第二焊盘结构521和位于第二焊盘结构521上的第二图案化金属结构522，第二子电极42与第二图案化金属结构522电连接。第一子电极41与第一图案化金属结构512电连接从而实现第一子电极41与第一引脚51的电连接，第二子电极42与第二图案化金属结构522电连接从而实现第二子电极42与第二引脚52的电连接。示例性地，构成第一焊盘结构511以及第二焊盘结构521的材料可以是焊锡，便于贴片式电容在印刷电路板上的焊接，可以设置构成第一引脚51中的第一图案化金属结构512材料以及构成第二引脚52中的第二图案化金属结构522均与构成层叠结构中每层金属层2的材料相同。
需要说明的是，本申请实施例对构成层叠结构中金属层2的材料，即构成第一电极3、第一子电极41和第二子电极42的材料不作限定，可以选用电导率高的金属材料或金属氧化物材料，以最大程度上提高贴片式电容的Q值。
本申请一实施例还提供了一种贴片式电容的制作方法，用于制作上述实施例的贴片式电容，图3为本申请一实施例提供的一种贴片式电容的制作方法的流程示意图。如图3所示，贴片式电容的制作方法包括：
步骤110、形成衬底。
形成衬底，该衬底可以是8寸晶圆、12寸晶圆或者500mm x 500mm尺寸的晶圆等更大尺寸的晶圆，衬底的形状可以是圆形，方型，长方形等，构成衬底的材料可以是硅、玻璃、石英、陶瓷或有机物中的至少一种。
步骤120、在衬底上形成构成第一电极的图案化金属结构。
结合图1和图2，在衬底(图1和图2中未示出衬底)上形成构成第一电极3的图案化金属结构，可以利用电镀或者溅射工艺，或者先通过物理或化学气相沉积等方法先沉积一层第一金属层21，再对形成的第一金属层21进行构图工艺，例如采用刻蚀工艺形成构成第一电极3的图案化金属结构。可以采用电镀工艺 形成构成第一电极3的图案化金属结构，电镀工艺能形成厚度较大的金属膜层，有利于提高贴片式电容的Q值。
步骤130、在构成第一电极的图案化金属结构上形成第一绝缘层。
结合图1和图2，在构成第一电极3的图案化金属结构上形成第一绝缘层1。示例性地，可以设置构成第一绝缘层1的材料包括硅的氮化物SiN x、铝的氧化物AlO x和钽的氧化物TaO x中的至少一种，当构成第一绝缘层1的材料为硅的氮化物SiN x时，可以采用化学气相沉积工艺形成第一绝缘层1，例如可以采用等离子增强化学气相沉积方法制作形成第一绝缘层1，等离子增强化学气相沉积需要的沉积温度较低，对膜层的结构和物理性质影响较小，形成的膜层厚度以及成分均匀性较好，且膜层较致密，附着力强。当构成第一绝缘层1的材料为铝的氧化物AlO x或钽的氧化物TaO x时，可以采用原子层沉积或金属有机化学气相沉积工艺形成第一绝缘层1。
示例性地，由于第一子电极41和第二子电极42通过对第二电极4进行图案化工艺形成，因此，也可以根据第一子电极41和第二子电极42的形状使第一绝缘层1形成相应的图案化结构，确保第一绝缘层1能够起到绝缘作用，以实现第一电极3与第一子电极41之间，以及第一电极3与第二子电极42之间的电绝缘即可。
步骤140、在第一绝缘层上形成构成第二电极的图案化金属结构。
结合图1和图2，同样可以利用电镀或者溅射工艺，或者先通过物理或化学气相沉积等方法先沉积一层第二金属层22，再对形成的第二金属层22进行构图工艺，例如采用刻蚀工艺形成构成第二电极4的图案化金属结构，以形成第一子电极41和第二子电极42。同样的，可以采用电镀工艺形成构成第二电极4的图案化金属结构，电镀工艺能形成厚度较大的金属膜层，有利于提高贴片式电容的Q值。
步骤150、去除衬底或研磨衬底。
在一实施例中，结合图1和图2，沿层叠方向XX’，贴片式电容还包括位于第二电极4远离第一电极3一侧的引脚层5，引脚层5设置有第一引脚51和第 二引脚52。上述制作方法在第一绝缘层1上形成构成第二电极4的图案化金属结构之后以及在所述去除所述衬底或研磨所述衬底之前，还可以包括在构成第二电极4的图案化金属结构上形成第二绝缘层6并在第二绝缘层6的设定位置上形成第一过孔结构和第二过孔结构，在第二绝缘层6上形成第一引脚51和第二引脚52。第一子电极41通过位于第二绝缘层6中的第一过孔结构61与第一引脚51电连接，第二子电极42通过位于第二绝缘层6中的第二过孔结构62与第二引脚52电连接。示例性地，在第二绝缘层6上形成第一引脚51以及第二引脚52时，构成第一引脚51以及第二引脚52的材料填充第二绝缘层6上的第一过孔结构61和第二过孔结构62，第一子电极41通过位于第二绝缘层6中的第一过孔结构61与第一引脚51电连接，第二子电极42通过位于第二绝缘层6中的第二过孔结构62与第二引脚52电连接。
示例性地，结合图1和图2，第一引脚51包括第一焊盘结构511和位于第一焊盘结构511上的第一图案化金属结构512，第二引脚52包括第二焊盘结构521和位于第二焊盘结构521上的第二图案化金属结构522，可以在第二绝缘层6上先形成第一图案化金属结构512和第二图案化金属结构522，然后在第一图案化金属结构512和第二图案化金属结构522上形成对应的焊盘结构，可以设置第一引脚51以及第二引脚52中的金属结构与对应的焊盘结构形状一致，二者同时实现图案化以简化工艺制程。
在一实施例中，可以在第二绝缘层6上形成第一引脚51和第二引脚52之后，去除衬底或研磨衬底，即剥离位于构成第一电极3的图案化金属结构上方的衬底或研磨位于构成第一电极3的图案化金属结构上方的衬底以形成完整的贴片式电容。在去除衬底或研磨衬底之后，可以对金属层2和绝缘层1切割形成标准的表贴器件尺寸，例如0201、01005或者更小尺寸的表贴器件。
在一实施例中，沿所述层叠方向，所述第一绝缘层1的厚度可以小于所述第一金属层21以及所述第二金属层22的厚度。
在一实施例中，所述第一引脚可以包括第一焊盘结构和位于所述第一焊盘结构上的第一图案化金属结构，所述第一子电极与所述第一图案化金属结构电 连接；
所述第二引脚包括第二焊盘结构和位于所述第二焊盘结构上的第二图案化金属结构，所述第二子电极与所述第二图案化金属结构电连接。
在一实施例中，所述第一电极可以为整面电极，所述第一子电极与所述第二子电极为块状电极。
在一实施例中，构成所述绝缘层的材料可以包括以下至少一种：硅的氮化物、铝的氧化物和钽的氧化物。
本申请实施例提供的贴片式电容包括层叠结构，层叠结构包括沿层叠方向间隔设置的一层绝缘层和两层金属层，位于相邻金属层中的图案化金属结构形成贴片式电容的第一电极和第二电极，设置第二电极包括第一子电极和第二子电极，构成第一子电极的图案化金属结构和构成第二子电极的图案化金属结构位于同一第一金属层或者第二金属层，沿层叠方向，第一电极的垂直投影与第一子电极的垂直投影以及第二子电极的垂直投影均存在部分重叠，即第一电极与第一子电极与第二子电极均存在正对部分，第一电极与第一子电极以及第一电极与第二子电极均形成电容结构，通过将第二电极分为第一子电极以及第二子电极，提高了贴片式电容的耐压性；另一方面采用半导体工艺制成贴片式电容，在有利于实现贴片式电容小型化的同时，有利于精确控制贴片式电容的尺寸，提高贴片式电容的精度，且能够降低电容的等效串联电阻，提高贴片式电容的Q值。

Claims (12)

  1. 一种贴片式电容，包括：
    层叠结构，所述层叠结构包括沿层叠方向依次间隔设置的第一金属层、绝缘层和第二金属层，位于相邻的金属层中的图案化金属结构分别形成所述贴片式电容的第一电极和第二电极；
    所述第二电极包括第一子电极和第二子电极，构成所述第一子电极的图案化金属结构和构成所述第二子电极的图案化金属结构位于同一所述第一金属层或第二金属层；沿所述层叠方向，所述第一电极的垂直投影与所述第一子电极的垂直投影部分重叠、所述第一电极的垂直投影与所述第二子电极的垂直投影部分重叠、以及所述第一子电极的垂直投影与所述第二子电极的垂直投影不重叠。
  2. 根据权利要求1所述的贴片式电容，其中，沿所述层叠方向，所述绝缘层的厚度小于所述第一金属层以及所述第二金属层的厚度。
  3. 根据权利要求1所述的贴片式电容，其中，沿所述层叠方向，所述贴片式电容还包括位于所述第二电极远离所述第一电极的一侧的引脚层，所述引脚层包括第一引脚和第二引脚，所述第一子电极与所述第一引脚电连接，所述第二子电极与所述第二引脚电连接。
  4. 根据权利要求3所述的贴片式电容，其中，所述引脚层与所述第二电极之间包括至少一层绝缘层，所述第一子电极通过所述引脚层与所述第二电极之间绝缘层中的第一过孔结构与所述第一引脚电连接，所述第二子电极通过所述引脚层与所述第二电极之间绝缘层中的第二过孔结构与所述第二引脚电连接。
  5. 根据权利要求3或4所述的贴片式电容，其中，所述第一引脚包括第一焊盘结构和位于所述第一焊盘结构上的第一图案化金属结构，所述第一子电极与所述第一图案化金属结构电连接；
    所述第二引脚包括第二焊盘结构和位于所述第二焊盘结构上的第二图案化金属结构，所述第二子电极与所述第二图案化金属结构电连接。
  6. 根据权利要求1所述的贴片式电容，其中，所述第一电极为整面电极，所述第一子电极与所述第二子电极为块状电极。
  7. 根据权利要求1所述的贴片式电容，其中，构成所述绝缘层的材料包括以下至少一种：硅的氮化物、铝的氧化物和钽的氧化物。
  8. 一种贴片式电容的制作方法，用于制作权利要求1所述的贴片式电容，所述制作方法包括：
    形成衬底；
    在所述衬底上形成构成所述第一电极的图案化金属结构；
    在构成所述第一电极的图案化金属结构上形成第一绝缘层；
    在所述第一绝缘层上形成构成所述第二电极的图案化金属结构；
    去除所述衬底或研磨所述衬底。
  9. 根据权利要求8所述的贴片式电容的制作方法，其中，沿层叠方向，所述贴片式电容还包括位于所述第二电极远离所述第一电极一侧的引脚层，所述引脚层设置有第一引脚和第二引脚；
    所述制作方法还包括：在所述第一绝缘层上形成构成所述第二电极的图案化金属结构之后以及在所述去除所述衬底或研磨所述衬底之前，
    在构成所述第二电极的图案化金属结构上形成第二绝缘层并在所述第二绝缘层的设定位置上形成所述第一过孔结构和第二过孔结构；
    在所述第二绝缘层上形成所述第一引脚和所述第二引脚，其中，所述第一子电极通过位于所述第二绝缘层中的第一过孔结构与所述第一引脚电连接，所述第二子电极通过位于所述第二绝缘层中的第二过孔结构与所述第二引脚电连接。
  10. 根据权利要求9所述的制作方法，其中，所述第一引脚包括第一焊盘结构和位于所述第一焊盘结构上的第一图案化金属结构，所述第一子电极与所述第一图案化金属结构电连接；
    所述第二引脚包括第二焊盘结构和位于所述第二焊盘结构上的第二图案化金属结构，所述第二子电极与所述第二图案化金属结构电连接。
  11. 根据权利要求8所述的制作方法，其中，所述第一电极为整面电极，所述第一子电极与所述第二子电极为块状电极。
  12. 根据权利要求8所述的制作方法，其中，构成所述绝缘层的材料包括以下至少一种：硅的氮化物、铝的氧化物和钽的氧化物。
PCT/CN2019/094160 2018-12-27 2019-07-01 贴片式电容及其制作方法 WO2020133998A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN101677100A (zh) * 2008-09-17 2010-03-24 财团法人工业技术研究院 电容元件及其制造方法
CN102222702A (zh) * 2010-04-14 2011-10-19 中芯国际集成电路制造(上海)有限公司 电容器及其形成方法
CN109473282A (zh) * 2018-12-27 2019-03-15 安徽安努奇科技有限公司 一种贴片式电容及其制作方法

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Publication number Priority date Publication date Assignee Title
CN101677100A (zh) * 2008-09-17 2010-03-24 财团法人工业技术研究院 电容元件及其制造方法
CN102222702A (zh) * 2010-04-14 2011-10-19 中芯国际集成电路制造(上海)有限公司 电容器及其形成方法
CN109473282A (zh) * 2018-12-27 2019-03-15 安徽安努奇科技有限公司 一种贴片式电容及其制作方法

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