Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
  • H10F39/024—Manufacture or treatment of image sensors covered by group H10F39/12 of coatings or optical elements
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
  • H10F39/026—Wafer-level processing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/199—Back-illuminated image sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/805—Coatings

Definitions

• the present application relates to image sensors suitable for sensing radiation in deep UV (DUV) and vacuum UV (VUV) wavelengths, and to methods for making such image sensors. These sensors are suitable for use in photomask, reticle, or wafer inspection systems and for other applications.
• DUV deep UV
• VUV vacuum UV
• inspection systems operating over a relatively broad range of wavelengths, such as a wavelength range that includes wavelengths in the near UV, DUV, and/or VUV ranges, can be advantageous because a broad range of wavelengths can reduce the sensitivity to small changes in layer thicknesses or pattern dimensions that can cause large changes in reflectivity at an individual
• a photon with a vacuum wavelength of 250 nm has energy of approximately 5 eV.
• the bandgap of silicon dioxide is about 10 eV. Although it may appear such wavelength photons cannot be absorbed by silicon dioxide, silicon dioxide as grown on a
• silicon surface must have some dangling bonds at the interface with the silicon because the silicon dioxide structure cannot perfectly match that of the silicon crystal.
• two high-energy photons may arrive near the same location within a very short time interval (nanoseconds or picoseconds) , which can lead to electrons being excited to the conduction band of the silicon dioxide by two absorption events in rapid succession or by two-photon absorption.
• a further requirement for sensors used for inspection, metrology and related applications is high sensitivity.
• Silicon reflects a high percentage of DUV and VUV light incident on it. For example, near 193 nm in wavelength, silicon with a 2 nm oxide layer on its surface (such as a native oxide layer) reflects approximately 65% of the light incident on it. Growing an oxide layer of about 21nm on the silicon surface reduces the reflectivity to close to 40% for wavelengths near 193 nm.
• a detector with 40% reflectivity is significantly more efficient than one with 65% reflectivity, but lower reflectivity, and hence higher efficiency, is desirable.
• Anti-reflection coatings are commonly used on optical elements such as lenses and mirrors.
• many coating materials and processes commonly used for optical elements are often not compatible with silicon-based sensors.
• electron and ion-assisted deposition techniques are commonly used for optical coatings.
• Such coating processes cannot generally be used to coat semiconductor devices because the electrons or ions can deposit sufficient charge on the surface of the semiconductor device to cause electrical breakdown resulting in damage to the circuits fabricated on the semiconductor.
• DUV and VUV wavelengths are strongly absorbed by silicon. Such wavelengths may be mostly absorbed within about 10 nm or a few tens of nm of the surface of the silicon.
• the efficiency of a sensor operating at DUV or VUV wavelengths depends on how large a fraction of the electrons created by the absorbed photons can be collected before the electrons recombine.
• Silicon dioxide can form a high-quality interface with silicon with a low density of defects.
• a high density of electrical defects on the surface of silicon may not be an issue for a sensor intended to operate at visible wavelengths, as such wavelengths may typically travel about 100 nm or more into the silicon before being absorbed and may, therefore, be little affected by electrical defects on the silicon surface.
• DUV and VUV wavelengths are absorbed so close to the silicon surface that electrical defects on the surface and/or trapped charged within the layer (s) on the surface can result in a significant fraction of the electrons created recombining at, or near, the silicon surface and being lost, resulting in a low efficiency sensor.
• U.S Patents 9,496,425, 9,818,887 and 10,121,914, all to Chern et al . describe image sensor structures and methods of making image sensors that include a boron layer deposited on, at least, an exposed back surface of the image sensor.
• Different ranges of temperature for deposition of the boron are disclosed, including a range of about 400-450°C and a range of about 700- 800 °C.
• the inventors have discovered that one advantage of a higher deposition temperature for the boron, such as a deposition temperature between about 600°C and about 900°C, is that at such temperatures boron diffuses into the silicon providing a very thin, heavily p-type doped silicon layer on the light-sensitive back surface.
• This p-type doped silicon layer is important for ensuring a high quantum efficiency to DUV and VUV radiation because it creates a static electric field near the surface that accelerates electrons away from the surface into the silicon layer.
• the p-type silicon also increases the conductivity of the back surface of the silicon, which is important for high-speed operation of an image sensor, since a return path is needed for ground currents induced by the switching of signals on electrodes on the front surface of the sensor.
• processing temperatures higher than 450°C cannot be used on semiconductor wafers that include conventional CMOS circuits because 450°C is close to the melting point metals such as aluminum and copper commonly used in fabricating CMOS devices. At high temperatures, such as those greater than 450°C, these metals expand, become soft and can delaminate. Furthermore, at high temperatures copper can easily diffuse through silicon which will modify the electrical properties of the CMOS circuits. Thinning a wafer before any metals are deposited on it allows a boron layer to be deposited on the back surface as described in the aforementioned patents at a temperature between 600 and 900°C enabling boron to diffuse into the surface during, or subsequent to, the deposition of the boron layer. Subsequently metal
• interconnects can be formed on the front surface. After the image sensor regions of the wafer have been thinned, for example to a thickness of about 25 pm or thinner, the thinned region can be significantly warped and may have peak-to-valley non-flatness of many tens of microns or more. So, it is necessary to use relatively wide metal interconnect lines and vias, such as
• polysilicon has much higher resistivity than any metal, so the use of such jumpers can limit the maximum operating speed of a sensor .
• US patent 5,376,810 to Hoenk et al describes a delta doping technique for image sensors that may be performed at a temperature of 450 °C or lower.
• This technique includes a 1.5 nm cap layer of nominally undoped silicon.
• This cap layer may be deliberately oxidized or may oxidize due to water and oxygen in the environment. This oxide layer will degrade under high intensity DUV, VUV, EUV or charged-particle radiation and can cause the sensor to degrade.
• a method of fabricating a back-thinned image sensor with a boron layer and boron doping on its back surface while allowing formation of metal interconnects on a relatively flat wafer would allow the use of finer design rules (such as the design rules
• Such a method would allow narrower metal lines connecting to critical features such as the floating diffusion, enabling smaller floating- diffusion capacitance and higher charge to voltage conversions ratios. Finer design rules also allow more interconnect lines per unit area of the sensor and allow more flexibility in
• Image sensors and methods of fabricating image sensors with high-quantum-efficiency for imaging DUV, VUV, EUV, X-rays and/or charged particles (such as electrons) are described.
• image sensors are capable of long-life operation under high fluxes of radiation. These methods include process steps to form light sensitive active and/or passive circuit elements in a layer on a semiconductor (preferably silicon) wafer, as well as forming metal interconnections between the electrical elements of the sensor. These image sensors can include fine metal interconnects and vias (such as those conforming to about 0.35 pm, or finer, design rules) , while having a backside surface coated with an amorphous boron layer and having a highly doped p-type silicon layer immediately adjacent to the boron layer.
• the metal interconnects and vias such as those conforming to about 0.35 pm, or finer, design rules
• interconnections may comprise tungsten, aluminum, copper or other metals used in fabricating interconnects in known CMOS processes.
• An exemplary method of fabricating an image sensor includes forming a first epitaxial silicon layer on a substrate, forming a gate layer on the first epitaxial silicon layer, the gate layer comprising one or more layers of dielectric materials such as silicon dioxide and silicon nitride, forming circuit elements on the gate layer comprising poly-silicon and dielectric materials, forming metal vias and metal interconnects to connect together at least some of those circuit elements, thinning the substrate to expose at least a portion of the first epitaxial silicon layer (the exposed first epitaxial silicon layer is referred to herein as a semiconductor membrane) , growing a second epitaxial silicon layer directly on the exposed portions of the first epitaxial layer, the second epitaxial silicon layer
• circuit elements refers to light sensitive devices such as charge-coupled devices and photodiodes, other semiconductor devices such as transistors, diodes, resistors and capacitors, and electrical interconnections (often called metal interconnects or interconnects) between them. These circuit elements are formed using standard semiconductor manufacturing processes including, but not limited to, photolithography, deposition, etching, ion implantation and annealing.
• the second epitaxial silicon layer may comprise an epitaxial silicon layer with a low concentration of the p-type dopant adjacent to the surface of the first epitaxial silicon layer and high concentration of the p- type dopant adjacent to the pure boron layer.
• epitaxial silicon layer may be formed by molecular-beam epitaxy (MBE) .
• MBE molecular-beam epitaxy
• Thinning the substrate e.g. a wafer
• This thinning can increase the sensitivity of the image sensor to light impinging the back surface.
• An anti-reflection coating may be formed on the boron layer.
• a thin metal coating may be deposited on the boron layer. The thin metal coating may be particularly useful when the sensor is used to detect charged particles (such as electrons), EUV or X-rays. Such a thin metal coating may reduce to sensitivity of the sensor to stray light, may protect the surface of the sensor, and may facilitate in-situ cleaning of contaminants, such as carbon and organic molecules from the sensor surface.
• Another method of fabricating an image sensor includes forming a first epitaxial silicon layer on a substrate, then forming circuit elements on the first epitaxial silicon layer. This step includes forming metal interconnects.
• the metal interconnects may comprise tungsten, molybdenum, aluminum, copper or another metal.
• a protective layer may be formed on the circuit elements.
• a handle wafer may be bonded to the surface that includes the circuit elements.
• the substrate is then thinned to expose, at least part of, the first epitaxial silicon layer. As indicated above, this thinning can increase the sensitivity of the image sensor to light impinging on the back surface.
• a second epitaxial silicon layer is grown on the exposed surface of the semiconductor membrane. The second epitaxial layer is doped with a p-type dopant such as a boron.
• the second epitaxial silicon layer may be grown at a temperature less than or about 450 °C.
• the p-type dopant may be incorporated into the second epitaxial silicon layer during growth of that layer by including a dopant (such as boron) or a dopant precursor (such as diborane) in a growth chamber during a growth process.
• the partial pressure of the dopant or dopant precursor may be increased over time as the second epitaxial silicon layer grows thereby forming a dopant concentration profile within the second epitaxial silicon layer that is highest at the outer surface of the second epitaxial silicon layer and lowest at surface
• a pure boron layer is formed on the surface of the p-type doped epitaxial silicon layer.
• the pure boron layer may be deposited at a temperature between about 300°C and about 450°C.
• An anti reflection coating may be formed on the boron layer.
• the anti reflection coating may be formed by an atomic-layer deposition (ALD) or other process.
• a thin metal coating may be deposited on the boron layer.
• the thin metal coating may be particularly useful when the sensor is used to detect charged particles (such as electrons), EUV or X-rays. Such a thin metal coating may reduce to sensitivity of the sensor to stray light, may protect the surface of the sensor, and may facilitate in-situ cleaning of contaminants, such as carbon and organic molecules from the sensor surface.
• Image sensors with high-quantum-efficiency and long life operation for DUV, VUV, EUV and/or X-ray radiation are described. These image sensors are thinned from the back-side to expose at least a portion of a first epitaxial silicon layer so that they are highly sensitive to radiation impinging on the back-side of the image sensors (wherein these image sensors are back-illuminated) .
• a second epitaxial silicon layer is grown directly on the exposed back surface of the first epitaxial silicon layer.
• the second epitaxial silicon layer is in-situ doped with a p-type dopant such that the concentration of the p- type dopant increases away from the surface of the first
• a thin (e.g. between about 2 nm and about 20 nm thick) , high-purity, amorphous boron layer is deposited on the second epitaxial silicon layer.
• one or more additional layers of material may be coated on the boron. The thickness and material of each layer may be chosen to increase the transmission of a wavelength of interest into the image sensor, and/or to protect the boron layer from damage.
• the image sensors described herein may be fabricated using CCD (charge coupled device) or CMOS (complementary metal oxide semiconductor) technology.
• the image sensors may be two- dimensional area sensors, or one-dimensional array sensors.
• Figure 1 is a cross-sectional view showing an exemplary image sensor produced in accordance with the present invention.
• Figure 2 illustrates an exemplary technique for
• Figures 3A, 3B and 3C illustrate an exemplary method for fabricating an image sensor.
• Figures 4A, 4B, 4C, 4D, 4E, 4F, 4G and 4H illustrate exemplary cross-sections of a portion of a wafer subjected to the method described in reference to Figure 2.
• Figure 5 illustrates an exemplary detector assembly incorporating an image sensor, a silicon interposer, and other electronics .
• Fig. 1 is a cross-sectional side view depicting a portion of an image sensor 100 configured to sense deep
• Image sensor 100 includes a semiconductor membrane 101 including a circuit element 103 formed on an upper (first) surface 102U of a first epitaxial layer and metal interconnects 110 and 120 formed over circuit element 103, a second epitaxial layer 105 disposed on a lower (second) surface 101L of first epitaxial layer 101, a pure boron layer 106 disposed on a lower surface 105L of second epitaxial layer 105, and an optional anti
• reflection coating 108 disposed on a lower (outward-facing) surface 106L of pure boron layer 106.
• first epitaxial layer 101 comprises a layer of lightly p-doped epitaxial silicon having a thickness Tl in a range of 10 pm to 40 pm and a p-type (e.g., boron) dopant concentration in a range of about 10 13 cm -3 to 10 14 cm -3 .
• a p-type dopant concentration in a range of about 10 13 cm -3 to 10 14 cm -3 .
• Circuit element 103 includes a sensor device (e.g., a light sensitive device such as a photodiode) and associated control transistors that are formed on (i.e., into and over) an upper (first) surface 101U of first epitaxial layer 101 using known techniques.
• circuit element 103 includes spaced-apart n+ doped diffusion regions 103- 11, 103-12 and 103-12 that extend from upper surface 101U into corresponding portions of epitaxial layer 101, and
• First metal interconnects 110 and second metal interconnects 120 are formed over circuit element 113 and are operably electrically connected to associated regions of circuit element 113 using known techniques.
• First metal interconnects 110 are formed in or on one or more dielectric layers 112 deposited over circuit element 113, and first metal vias 115 extend through dielectric layers 112 using known via formation techniques.
• Second metal interconnects 120 are formed in a second dielectric layer 122 that is disposed over first metal interconnects 110, and second metal vias 125 extend through one or both dielectric layers 112 and 122.
• a protection layer (not shown in Fig. 1) is formed between first metal interconnects 110 and second metal
• interconnects 120, and all second metal vias 125 comprise at least one of aluminum and copper and extend through this
• circuit element 103 depicted in Fig. 1 along with the exemplary metal interconnects 110 and 120 and metal vias 115 and 125, are arbitrarily configured for illustrative purposes and provided solely to for purposes of describing exemplary
• circuit element structures and is not intended to represent a functional sensor device or to limit the appended claims.
• Second epitaxial layer 101 is disposed on lower surface 101L of first epitaxial layer 101 and has a thickness T2 in the range of lnm to lOOnm, and more preferably in the range of about 2nm and about 20nm.
• second epitaxial layer 105 is formed using processing techniques described below such that second epitaxial layer 105 has a p-type dopant
• concentration gradient d np that systematically increases from a minimum (lowest) p-type doping concentration n p-min at lower
• a benefit gained by simultaneoulsy forming p-type dopant concentration gradient d np and second epitaxial layer 105 in this manner is the ability to create p- type dopant concentration gradient d np at substantially lower processing temperatures (i.e., about 450°C or lower) than that required to form a similar p-type dopant concentration gradient within first epitaxial layer 101 (i.e., forming a similar
• first epitaxial layer 101 requires a processing temperature of at least 700°C
• concentration gradient d np within second epitaxial layer 105 greatly enhances control over the rate at which the p-type dopant concentration changes within gradient d np , which facilitates different gradient patterns (e.g., linear or parabolic) that may be used to further enhance the ability of image sensor (circuit element) 103 to efficiently detect high-energy photons.
• gradient patterns e.g., linear or parabolic
• FIG. 1 depicts the exemplary embodiment of Fig. 1
• p-type dopant concentration gradient d np systematic increase of p-type dopant concentration gradient d np as a continuous linear increase as a function of the negative-Y-axis direction.
• the gradual increase of p-type dopant concentration gradient d np may be defined by any function of the thickness (negative-Y-axis) direction, such as a
• first-to- be-formed layer portions i.e., incremental layer portions generated during a given time period that occurs relatively early in the second epitaxial layer formation process
• first-to- be-formed layer portions have a lower p- type doping concentration than at least one subsequently formed layer portion.
• a p-type dopant concentration n pi of a (first) intermediate layer portion 105-1 of second epitaxial layer 105 is equal to or lower than a p-type dopant concentration n P 2 of a (second) intermediate layer portion 105-1 of second epitaxial layer 105.
• p-type dopant concentration n pi of intermediate layer portion 105-1 is higher (greater) than minimum p-type
• doping concentration n p-min and p-type dopant concentration n P 2 of intermediate layer portion 105-2 is lower (less) than maximum p- type doping concentration n p-max .
• a particular p-type dopant concentration may remain the same for thickness-wise regions of second epitaxial layer 105 (e.g., p- type dopant concentration n pi of intermediate layer portion 105-1 may be equal to minimum p-type doping concentration n p-min ) .
• maximum p-type doping concentration n p-max is approximately 10 20 cm -3
• minimum p-type doping concentration n p-min is greater than or approximately equal to a dopant
• pure boron layer 106 is formed using techniques described below such that pure boron layer 106 has a thickness T3 in the range of 2 nm and 10 nm.
• pure boron layer 106 comprises a boron concentration of 80% or higher, with inter-diffused silicon atoms and oxygen atoms
• thickness T3 of pure boron layer 106 is in the range of 3 nm to 10 nm
• optional anti- reflection coating 108 comprises a silicon dioxide layer deposited on a lower (outward-facing) surface 106L of pure boron layer 106.
• FIG. 2 illustrates an exemplary technique 200 for fabricating an image sensor.
• the circuit elements can be created in step 201 using standard semiconductor processing steps including lithography, deposition, ion
• CCD and/or CMOS sensor elements and devices may also be created in step 201. These circuit elements are created in a first
• the first epitaxial layer is about 10 pm to 40 pm thick.
• the first epitaxial layer is lightly p (p-) doped.
• the first epitaxial layer resistivity is between about 10 and 100 W cm.
• step 201 using any suitable metal including aluminum, copper, tungsten, molybdenum or cobalt.
• refractory metals such as tungsten or molybdenum to form first metal
• interconnects and associated metal vias may allow high
• temperatures in subsequent steps, in particular in steps 209 and/or 211.
• temperatures in subsequent steps are limited to about 450°C or lower, any convenient metal, including copper and
• step 203 the front-side surface of the wafer can be protected.
• This protection may include depositing one or more protective layers on top of the circuit elements formed during step 201.
• the one or more protective layers may comprise silicon dioxide, silicon nitride or other material.
• This protection may include attaching the wafer to a handling wafer, such as a silicon wafer, a quartz wafer, or a wafer made of other material.
• the handling wafer may include through-wafer vias for connecting to the circuit elements.
• Step 205 involves thinning the wafer from the back-side so as to expose the first epitaxial layer in, at least, the
• This step may involve polishing, etching, or both.
• the entire wafer is back-thinned .
• only the active sensor areas are thinned all the way to the first epitaxial layer.
• Step 207 includes cleaning and preparing the back-side surface prior to deposition of a second epitaxial layer. During this cleaning, the native oxide and any contaminants, including organics and metals, should be removed from the back-side surface. In one embodiment, this cleaning can be performed using a dilute HF solution or using an RCA clean process. After cleaning, the wafer can be dried using the Marangoni drying technique or a similar technique to leave the surface dry and free of water marks .
• the wafer is protected in a controlled environment between steps 207 and 208 (e.g. in a
• step 208 a second epitaxial silicon layer is grown (deposited) on, at least, the exposed portion of the first
• the second epitaxial layer is grown by molecular-beam epitaxy (MBE) or other process at a
• second epitaxial layer 105A may be grown in a reaction chamber using a gas G containing both silicon and a p-type dopant such as boron, so as to create a p-doped epitaxial silicon layer.
• gas G includes a
• the deposition process gas G includes an intermediate amount Pi of p-type dopant that is greater than amount PO used at the point indicated in Fig. 3A, whereby an intermediate layer portion 105A1 is formed with an intermediate p-type dopant concentration n p-int that is greater than minimum p-type dopant concentration n p-min .
• an intermediate layer portion 105A1 is formed with an intermediate p-type dopant concentration n p-int that is greater than minimum p-type dopant concentration n p-min .
• the deposition process gas G includes a final amount P2 of p-type dopant that is greater than intermediate amount Pi, whereby a final layer portion 105A2 is formed with maximum p-type dopant concentration n p-max that is greater than intermediate p-type dopant
• gas G used to grow the second epitaxial layer may include silicon or boron in elemental form, or may include precursors such as silane for silicon or diborane for boron.
• boron is deposited on the surface of the second epitaxial layer. In one preferred embodiment, this
• deposition can be done using diborane, or a diborane-hydrogen mixture, diluted in nitrogen at a temperature between about 300°C and about 450 °C, thereby creating a high-purity amorphous boron layer.
• the deposition may be done at a temperature lower than about 350°C, for example, by using a gas containing elemental boron.
• the thickness of the deposited boron layer depends on the intended application for the sensor. Typically, the boron layer thickness will be between about 2 nm and 20 nm, preferably between about 3 nm and 10 nm.
• the minimum thickness is set by the need for a pinhole-free uniform film, whereas the maximum thickness depends on the absorption of the photons or charged particles of interest by the boron, as well as the maximum length of time that the wafer can be kept at the deposition temperature.
• step 209 other layers may be deposited on top of the boron layer.
• These other layers may include anti-reflection coatings comprised of one or more materials, such as silicon dioxide, silicon nitride, aluminum oxide, hafnium dioxide,
• These other layers may include a thin protective layer comprising a metal such as
• ALD atomic layer deposition
• the protective front-side layer may be removed in step 213.
• holes or vias can be opened or exposed in the handling wafer and/or protective front-side layer, or through-silicon vias around the edges of the device can be exposed, thereby allowing connection to the circuit elements.
• the resulting structure may be packed in a suitable package.
• the packing step may comprise flip-chip bonding or wire bonding of the device to a substrate.
• the package may include a window that transmits wavelengths of interest, or may comprise a flange or seal for interface to a vacuum seal .
• Figures 4A-4G illustrate exemplary cross-sections of a wafer subjected to method 200 ( Figure 2) .
• Figure 4A illustrates a first epitaxial (epi) layer 402 formed on the front side of a substrate 401.
• First epi layer 402 is preferably a p- epi layer.
• the first epi layer resistivity is between about 100 and 1000 W cm.
• Figure 4B illustrates various circuit elements 403 including interconnects that can be formed on the first epi layer 402 as described in step 201 above) . Because the interconnects are formed on the wafer while the substrate is still hundreds of microns thick and hence not severely warped, these interconnects can be formed using normal sub-micron CMOS processing techniques and may include multiple layers of high-density metal interconnects.
• the metal interconnects comprise a metal such as copper, aluminum, tungsten, molybdenum or cobalt. In one
• the metal interconnects consist entirely of
• TSV through-silicon vias
• Figure 4C illustrates a handling wafer 404 attached to the top surface of first epi layer 402 over circuit elements 403 (step 203) . Note that the through-silicon vias are shown but not labeled so as not to overly complicate the drawings. In an
• a protective layer can be used instead of, or in addition to, handling wafer 404.
• vias are formed in handling wafer 404 to allow connection to the circuit elements 403.
• Figure 4D illustrates the wafer after the substrate
• first epi layer 402 i.e., opposite to the surface on which circuit elements 403 are formed and to which handling wafer 404 is attached.
• a native oxide may form on back-side surface 402L, which is exposed by the back-thinning process.
• Figure 4E illustrates the wafer after a cleaning and preparation of the back-side surface 402L is completed (step 207) to prepare first epi layer 402 for the formation of a second epitaxial (epi) layer.
• Figure 4F illustrates the wafer after a second epi layer 405 is formed on back-side surface 402L of first epi layer 402, and a pure boron layer 406 is formed on a lower surface 405L of second epi layer 405are respectively (steps 208 and 209) .
• In- situ p-type doping of the second epi layer 405 during growth creates a dopant concentration profile that increases from the bottom (back-side) surface 402L of first epi layer 402 to lower surface 405L of pure boron layer 406.
• Figure 4G illustrates one or more optional anti
• reflection or protection layers 408 deposited bottom/lower surface 406L of pure boron layer 406. At least one of the layers may be deposited using an ALD process.
• Figure 4H illustrates the wafer after etching and deposition steps create metal pads 407 so as to allow electrical connection to the TSVs 403A (step 213) . Note that if vias are formed in handling wafer 404, then metal pad 407 should be formed on the top surface of handling wafer 404.
• a p-type doped second epitaxial layer may be deposited on a back-side surface of a first epitaxial layer.
• the second epitaxial layer is subsequently coated with a boron layer on its photo-sensitive surface. Because the second epitaxial layer includes a concentration gradient of the p-type dopant which has its maximum value adjacent to the boron, the image sensor has high efficiency even for short-wavelength light, or low-energy charged particles, which may penetrate only a few nm, or a few tens of nm into the epitaxial layers.
• Figure 5 illustrates an exemplary detector assembly 500 incorporating an image sensor 504, a silicon interposer 502 and other electronics in accordance with certain embodiments of the present invention.
• the detector assembly 500 may include one or more light sensitive sensors 504 disposed on the surface of an interposer 502.
• the one or more interposers 502 of the assembly 500 may include, but are not limited to, a silicon interposer.
• the one or more light sensitive sensors 504 of the assembly 500 are back-thinned and further configured for back-illumination including a boron layer and a p- type doped second epitaxial layer adjacent to the boron layer as described above.
• various circuit elements of the assembly 500 may be disposed on or built into the interposer 502.
• one or more circuit elements of the assembly 500 may be disposed on or built into the interposer 502.
• amplification circuits e.g., charge conversion amplifier (not shown) may be disposed on or built into the interposer 502.
• one or more conversion circuits 508 e.g., analog-to-digital conversion circuits, i.e. digitizers 508
• one or more driver circuits 506 may be disposed on or built into the interposer 502.
• the one or more driver circuits 506 may include a timing/serial drive circuit.
• the one or more driver circuits 506 may include, but are not limited to, clock driver circuitry or reset driver circuitry.
• one or more decoupling may be included in another embodiment.
• capacitors may be disposed on or built into the interposer 502.
• one or more serial transmitters maybe disposed on or built into the interposer 502.
• one or more of amplification circuits, analog-to-digital converter circuits and driver circuits may be included in light sensitive sensor 504, reducing the number of (or eliminating the need for) circuits such as 506 and 508.
• one or more support structures may be disposed between the bottom surface of the light sensitive array sensor 504 and the top surface of the interposer 502 in order to provide physical support to the sensor 504.
• a plurality of solder balls 516 may be disposed between the bottom surface of the light sensitive array sensor 504 and the top surface of the interposer 502 in order to provide physical support to the sensor 504. It is recognized herein that while the imaging region of the sensor 504 might not include external electrical connections, the back-thinning of the sensor 504 causes the sensor 504 to become increasingly flexible. As such, solder balls 516 may be utilized to connect the sensor 504 to the interposer 502 in a manner that reinforces the imaging portion of the sensor 504.
• an underfill material may be disposed between the bottom surface of the light sensitive array sensor 504 and the top surface of the interposer 502 in order to provide physical support to the sensor 504.
• an epoxy resin may be disposed between the bottom surface of the light sensitive array sensor 504 and the top surface of the interposer 502.
• the interposer 502 and the various additional circuitry are disposed on a surface of a substrate 510.
• the substrate 510 includes a substrate having high thermal conductivity (e.g., ceramic substrate).
• the substrate 510 is configured to provide physical support to the sensor 504/interposer 502 assembly, while also providing a means for the assembly 500 to efficiently conduct heat away from the imaging sensor 504 and the various other circuitry (e.g., digitizer 506, driver circuitry 508, amplifier, and the like) .
• the substrate may include any rigid highly heat conductive substrate material known in the art.
• the substrate 510 may include, but is not limited to, a ceramic substrate.
• the substrate 510 may include, but is not limited to, aluminum nitride.
• the substrate 510 may be any suitable material.
• the substrate 510 may provide interconnection between the
• interposer 502 and a socket or a PCB via interconnects 512.
• the substrate 510 may be operatively coupled to an underlying PCB and further electrically coupled to a socket or PCB in a variety of ways, all of which are interpreted to be within the scope of the present invention .

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• Solid State Image Pick-Up Elements (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Photometry And Measurement Of Optical Pulse Characteristics (AREA)
• Light Receiving Elements (AREA)

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• 2019
  • 2019-09-05 US US16/562,396 patent/US11114491B2/en active Active
  • 2019-12-11 WO PCT/US2019/065575 patent/WO2020123571A1/en not_active Ceased
  • 2019-12-11 KR KR1020217021571A patent/KR102727771B1/ko active Active
  • 2019-12-11 EP EP19895404.2A patent/EP3895215B1/en active Active
  • 2019-12-11 IL IL283238A patent/IL283238B2/en unknown
  • 2019-12-11 CN CN201980079474.0A patent/CN113169201B/zh active Active
  • 2019-12-11 JP JP2021532242A patent/JP7616998B2/ja active Active
  • 2019-12-12 TW TW108145610A patent/TWI814961B/zh active

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