WO2022133642A1 - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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WO2022133642A1
WO2022133642A1 PCT/CN2020/137949 CN2020137949W WO2022133642A1 WO 2022133642 A1 WO2022133642 A1 WO 2022133642A1 CN 2020137949 W CN2020137949 W CN 2020137949W WO 2022133642 A1 WO2022133642 A1 WO 2022133642A1
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Prior art keywords
epitaxial layer
ions
forming
substrate
concentration
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PCT/CN2020/137949
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English (en)
French (fr)
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张斯日古楞
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中芯国际集成电路制造(北京)有限公司
中芯国际集成电路制造(上海)有限公司
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Priority to CN202080103661.0A priority Critical patent/CN116583953A/zh
Priority to PCT/CN2020/137949 priority patent/WO2022133642A1/zh
Priority to US18/038,129 priority patent/US20240063325A1/en
Publication of WO2022133642A1 publication Critical patent/WO2022133642A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
    • H01L31/1896—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates for thin-film semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures

Definitions

  • the present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure.
  • Image sensors may be used to sense radiation (eg, optical radiation, including but not limited to visible light, infrared light, ultraviolet light, etc.). Image sensors can be classified into backside illuminated (BSI) image sensors and front illuminated (FSI) image sensors according to the way they receive radiation.
  • radiation e.g, optical radiation, including but not limited to visible light, infrared light, ultraviolet light, etc.
  • Image sensors can be classified into backside illuminated (BSI) image sensors and front illuminated (FSI) image sensors according to the way they receive radiation.
  • BSI backside illuminated
  • FSI front illuminated
  • a BSI image sensor is capable of receiving radiation from its backside. Unlike the FSI image sensor, in the BSI image sensor, components such as wiring that may affect radiation reception are substantially located on the front side of the substrate, while light is incident from the back side of the substrate.
  • the following steps are currently used: growing an epitaxial layer on the substrate, fabricating a photo-sensing device (eg, photodiode) on the epitaxial layer, and then removing the substrate from the backside, where the epitaxial layer serves as a removal liner Bottom stop layer.
  • a photo-sensing device eg, photodiode
  • the epitaxial layer serves as a removal liner Bottom stop layer.
  • the technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improve the performance of the finally formed semiconductor structure.
  • an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a first substrate, the first substrate includes an opposite first surface and a second surface, and the first substrate There are first ions in the bottom, and the first ions have a first concentration; a first epitaxial layer is formed on the first surface of the first substrate, and the first epitaxial layer has second ions in it, and the first epitaxial layer is formed on the first surface of the first substrate. Two ions have a second concentration, and the second concentration is smaller than the first concentration; a second epitaxial layer and a third epitaxial layer on the second epitaxial layer are formed on the first epitaxial layer, and the first epitaxial layer is formed on the second epitaxial layer.
  • the second epitaxial layer has a third ion, the third ion has a third concentration, the third epitaxial layer has a fourth ion, and the fourth ion has a fourth concentration, and the fourth concentration is smaller than the first concentration Three concentrations: thinning the first substrate from the second surface of the first substrate until the surface of the second epitaxial layer is exposed.
  • the step of the thinning treatment includes: etching the first substrate from the second surface of the first substrate until the surface of the first epitaxial layer is exposed; The first epitaxial layer is planarized until the surface of the second epitaxial layer is exposed.
  • the etching process is wet etching; the process parameters of the wet etching process include: the etching solution includes an HNA solution, and the HNA solution is formed from hydrofluoric acid, nitric acid and acetic acid mixed solution.
  • the planarization treatment is chemical mechanical polishing; the process parameters of the chemical mechanical polishing include: SiO 2 polishing liquid is selected, and the polishing time is 50-100 seconds.
  • the first ions and the second ions have opposite conductivity types.
  • the conductivity types of the third ion and the fourth ion are the same.
  • the first ions are P-type ions; the P-type ions include one or more of boron ions, indium ions, and gallium ions.
  • the second ions are N-type ions; the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.
  • the third ions are P-type ions; the fourth ions are P-type ions; and the P-type ions include one or more of boron ions, indium ions, and gallium ions.
  • the first concentration ranges from 2E18 to 5E18 atoms/cm 3 .
  • the second concentration ranges from 5E12 to 1E15 atoms/cm 3 .
  • the third concentration ranges from 6E17 to 5E18 atoms/cm 3 .
  • the fourth concentration ranges from 1E13 to 2E14 atoms/cm 3 .
  • the thickness of the first epitaxial layer ranges from 1 to 3 microns.
  • the thickness of the second epitaxial layer ranges from 1 to 5 microns.
  • the thickness of the third epitaxial layer ranges from 4 to 10 microns.
  • the third epitaxial layer includes a third surface, the third surface is away from the second epitaxial layer, and before the thinning process is performed on the first substrate, the method further includes: on the third A number of photoelectric doping regions are formed in the epitaxial layer; a first dielectric layer covering the third surface of the third epitaxial layer and the photoelectric doping region is formed; and an electrical interconnection structure is formed in the first dielectric layer.
  • the method further includes: providing a second substrate; and bonding the first surface of the first substrate with the second substrate.
  • the second epitaxial layer includes a fourth surface, and the fourth surface is in contact with the first epitaxial layer, and after thinning the first substrate, the method further includes: A second dielectric layer is formed on the fourth surface of the second epitaxial layer; through holes are formed in the second dielectric layer, the second epitaxial layer and the third epitaxial layer, and the through holes expose the first dielectric forming a contact hole in the bottom of the through hole and in the first dielectric layer to expose the electrical interconnection structure; forming a conductive layer in the through hole and the contact hole.
  • the method further includes: forming a plurality of filters and lenses on the filters on the second medium layer.
  • a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer are formed on the first surface of the first substrate.
  • the concentration is smaller than the first concentration of the first ions in the first substrate, and the third concentration of the third ions in the second epitaxial layer is greater than the fourth concentration of the fourth ions in the third epitaxial layer, from the second surface of the first substrate
  • the thinning process is performed on the first substrate. Since the first epitaxial layer and the first substrate have a difference in ion concentration, the thinning process will first stop at the first epitaxial layer, and the thickness uniformity of the thinning process can be controlled, and the subsequent thinning process can be continued.
  • the thinning process removes the first substrate and the first epitaxial layer, leaving the second epitaxial layer and the third epitaxial layer, And the third concentration is greater than the fourth concentration, after the pixel unit is subsequently formed in the third epitaxial layer, when the reverse bias voltage is applied during the operation of the pixel unit, due to the existence of the second epitaxial layer, the formation of the depletion region can be prevented. Diffusion to the interface of the thinning process not only improves the thickness uniformity of the thinning process, but also satisfies the substrate requirements for fabricating the image sensor, which is beneficial to the performance of the finally formed semiconductor structure.
  • the conductivity types of the first ions and the second ions are opposite.
  • the boundary between the first substrate and the first epitaxial layer can be made clearer, so as to avoid the boundary becoming blurred due to ion diffusion in some heat treatment processes, making the first epitaxial layer clearer.
  • the epitaxial layer better acts as an etch stop layer.
  • 1 to 8 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present invention.
  • the current specific methods for forming a BSI image sensor include:
  • a first substrate is provided, the first substrate includes opposing first and second surfaces, and the first substrate has a first ion therein, the ion has a first concentration; on the first surface an epitaxial layer is formed thereon, the epitaxial layer includes an opposite third surface and a fourth surface, the fourth surface of the epitaxial layer is in contact with the first surface of the first substrate, and the epitaxial layer has a second surface ions, the second ions have a second concentration, and the second concentration is smaller than the first concentration; a plurality of pixel units isolated from each other are formed on the third surface of the epitaxial layer, and a third surface covering the epitaxial layer is formed.
  • each pixel unit includes a light emitting diode and a plurality of MOS transistors; a second substrate is provided, and the second substrate is connected with all the the first substrate is bonded in the direction of the first surface, and then the second substrate is turned over so that the second surface of the first substrate faces upward; The first substrate is subjected to a thinning process.
  • the thinning process of the first substrate usually uses an epitaxial layer as a thinning stop layer. Since the thinning rate is very sensitive to the ion concentration, when the thinning reaches the concentration gradient layer, the thinning rate will suddenly decrease. drop so that the thinning stops at the interface of the first substrate and the epitaxial layer. Using the epitaxial layer-stop thinning process, the first substrate will eventually be completely removed, and there will be many lattice defects at the interface where the thinning-stop is stopped, that is, the fourth surface of the epitaxial layer. During the process, a reverse bias voltage will be applied to the light-emitting diode, so a depletion region will be formed in the epitaxial layer. When the applied reverse bias voltage is large, the depletion region will extend to the crystal on the fourth surface of the epitaxial layer. At the lattice defects, dark current is generated, which is detrimental to the performance of the image sensor.
  • embodiments of the present invention provide a method for forming a semiconductor structure, which comprises forming a first epitaxial layer on a first substrate, a second epitaxial layer on the first epitaxial layer, and a In the third epitaxial layer, the second concentration of the second ions in the first epitaxial layer is smaller than the first concentration of the first ions in the first substrate, and the third concentration of the third ions in the second epitaxial layer is greater than that in the third epitaxial layer.
  • the fourth concentration of four ions when thinning the first substrate, on the one hand, due to the difference in ion concentration between the first epitaxial layer and the first substrate, the thinning process will first stop at the first epitaxial layer and the first substrate.
  • the subsequent thinning process is continued until the surface of the second epitaxial layer is exposed, which is beneficial to control the uniformity of the thinned thickness; on the other hand, after the thinning process, the second epitaxial layer and The third epitaxial layer, and the third concentration is greater than the fourth concentration.
  • a reverse bias voltage is applied during the operation of the pixel unit. Due to the existence of the second epitaxial layer with a larger ion concentration, the The formed depletion region is prevented from extending to the lattice defects at the thinning process interface, and the generation of dark current is reduced, thereby contributing to the improvement of the performance of the semiconductor structure.
  • a first substrate 100 is provided, the first substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, and the first substrate 100 has first ions therein, the first ions has a first concentration.
  • the first substrate 100 may be a silicon substrate, and may also be a germanium, silicon germanium, gallium arsenide substrate or a silicon-on-insulator substrate. Those skilled in the art can select the type of substrate as required, so the type of the first substrate should not be a feature that limits the scope of protection of the present invention.
  • the first substrate 10 is a silicon substrate.
  • the first substrate 100 is P-type doped, that is, the first ions are P-type ions; the P-type ions include one or more of boron ions, indium ions, and gallium ions.
  • the range of the first concentration of the first ions is 2E18 ⁇ 5E18 atoms/cm 3 .
  • the thickness of the first substrate 100 ranges from 725 to 775 microns; the thickness of the first substrate 100 is a general thickness of a substrate in a conventional semiconductor process.
  • a first epitaxial layer 110 is formed on the first surface 101 of the first substrate 100 , the first epitaxial layer 110 has second ions in it, the second ions have a second concentration, and the The second concentration is smaller than the first concentration.
  • the range of the second concentration of the second ions is 5E12 ⁇ 1E15 atoms/cm 3 .
  • the second concentration is smaller than the first concentration, and there is a concentration difference at the interface between the first epitaxial layer 110 and the first substrate 100 .
  • the first substrate 100 is etched first. Since the etching rate is more sensitive to the ion concentration, the etching rate will drop sharply in the ion concentration gradient layer, so that the thinning first stays at the ion concentration gradient layer. The junction of the first epitaxial layer 110 and the first substrate 100, thereby controlling the uniformity of the thinned thickness.
  • the conductivity types of the second ions and the first ions are opposite; the reason why the second ions and the first ions adopt opposite conductivity types is that the first epitaxial layer 110 and all the The boundary of the first substrate 100 is clearer to avoid blurring of the boundary due to ion diffusion in some heat treatment processes.
  • the first epitaxial layer 110 can be better The ground acts as an etch stop layer.
  • the first ions are P-type ions
  • the second ions are N-type ions
  • the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.
  • the conductivity types of the second ions and the first ions may also be the same.
  • the first epitaxial layer 110 is formed by an epitaxial growth process.
  • the thickness of the first epitaxial layer 110 ranges from 1 to 3 microns; if the thickness of the first epitaxial layer 110 is greater than 3 microns, the second ions may form a concentration gradient layer in the first epitaxial layer 110, which is unfavorable for subsequent Stop the etching process in the thinning process; if the thickness of the first epitaxial layer 110 is less than 1 ⁇ m, over-grinding is likely to occur during the planarization process in the subsequent thinning process, which damages the second epitaxial layer 120 .
  • a second epitaxial layer 120 and a third epitaxial layer 130 located on the second epitaxial layer 120 are formed on the first epitaxial layer 110 , and the second epitaxial layer 120 has third ions, so The third ion has a third concentration, the third epitaxial layer 130 has a fourth ion, and the fourth ion has a fourth concentration, and the fourth concentration is smaller than the third concentration.
  • the range of the third concentration is 6E17-5E18 atoms/cm 3 ; the range of the fourth concentration is 1E13-2E14 atoms/cm 3 .
  • the third ion and the fourth ion have the same conductivity type, and the third ion and the fourth ion have the same conductivity type as the first ion.
  • the third ions are P-type ions; the fourth ions are P-type ions; and the P-type ions include one or more of boron ions, indium ions, and gallium ions.
  • the reason for continuing to form the second epitaxial layer 120 and the third epitaxial layer 130 on the first epitaxial layer 110 is that the first substrate will be removed after the subsequent thinning process on the first substrate 100 100 and the first epitaxial layer 110 until the surface of the second epitaxial layer 120 is exposed, the remaining second epitaxial layer 120 and the third epitaxial layer 130 serve as the substrate for forming the semiconductor structure, and the third concentration is greater than the fourth concentration, The substrate requirements for fabricating image sensors are met, and the performance of the formed semiconductor structure is improved.
  • the second epitaxial layer 120 and the third epitaxial layer 130 are formed by an epitaxial growth process.
  • the thickness of the second epitaxial layer 120 is in the range of 1-5 microns; the thickness of the third epitaxial layer 130 is in the range of 4-10 microns; the thicknesses of the second epitaxial layer 120 and the third epitaxial layer 130 may be Choose according to the actual situation.
  • the third epitaxial layer 130 includes a third surface 131, and the third surface 131 faces away from the second epitaxial layer 120; the second epitaxial layer 120 includes a fourth surface 121, the fourth surface 121 and the The first epitaxial layers 110 are in contact.
  • a plurality of photoelectric doped regions 210 are formed in the third epitaxial layer 130 . Adjacent said photoelectrically doped regions 210 are isolated by shallow trench isolation results 240 .
  • the method further includes: forming a first dielectric layer 220 covering the third surface 131 of the third epitaxial layer 130 and the photoelectric doped region.
  • it also includes: forming a logic circuit (not shown) in the first dielectric layer 220, the logic circuit including a MOS transistor and an electrical interconnection structure 230 electrically connected to the MOS transistor, the MOS transistor The electrical signals in are transmitted through the electrical interconnect structure 230 .
  • the method for forming the photoelectric doped region 210 includes:
  • a patterned layer (not shown) is formed on the third surface 131 of the third epitaxial layer 130, and the patterned layer exposes part of the third surface 131 of the third epitaxial layer 130;
  • the photoelectric doped region 210 is formed in the third epitaxial layer 130 for ion implantation as a mask.
  • the doping type of the photoelectric doping region 210 is opposite to the doping type of the third epitaxial layer 130 , for example, the third epitaxial layer 130 is P-type doping, the first doping region is N-type doping, or vice versa. In this way, in a direction perpendicular to the third surface 131 of the third epitaxial layer 130, a PN junction is formed between the first doped region and the third epitaxial layer 130 to form a photodiode.
  • the electrical interconnect structure 230 includes multiple interconnect metal layers stacked together and a plug layer (not shown in the figure) connecting two adjacent interconnect metal layers, wherein the interconnect metal layers The layer is over the shallow trench isolation structure 240 .
  • the formation method of the electrical interconnection structure 230 is well known to those skilled in the art, and will not be repeated here.
  • a second substrate 300 is provided, the second substrate 300 is bonded to the first substrate 100 in the direction of the first surface 101 , and the first substrate 100 is turned over to the second surface 102 up.
  • the bonding method can be eutectic bonding or any other welding process feasible in semiconductor technology.
  • a thinning process is performed on the first substrate 100 from the second surface 102.
  • the steps of the thinning process include:
  • the first substrate 100 is etched from the second surface 102 of the first substrate 100 until the surface of the first epitaxial layer 110 is exposed.
  • the etching process is a wet etching process; the process parameters of the wet etching process include: the etching solution includes an HNA solution, and the HNA solution is composed of hydrofluoric acid, nitric acid and A mixed solution of acetic acid.
  • the first epitaxial layer 110 and the first substrate 100 have an ion concentration difference, and the wet etching is very sensitive to the ion concentration, the etching rate will drop sharply when the concentration changes.
  • the first epitaxial layer 110 is used as an etching stop layer, so that the wet etching can be stopped at the junction of the first substrate 100 and the first epitaxial layer 110 to improve the uniformity of the thinned thickness.
  • the planarization process for the first epitaxial layer 110 is continued until the surface of the second epitaxial layer 120 is exposed.
  • the planarization treatment is chemical mechanical polishing; the process parameters of the chemical mechanical polishing include: SiO 2 polishing liquid is selected, and the polishing time is 50-100 seconds.
  • the chemical mechanical polishing is beneficial to further improve the thickness uniformity of the thinning process.
  • the thickness of the chemical mechanical polishing is the thickness of the first epitaxial layer 110 , and the thickness of the first epitaxial layer 110 ranges from 1 to 3 microns; if the thickness of the first epitaxial layer 110 is greater than 3 microns, the second ions may form a concentration gradient layer in the first epitaxial layer 110, which is not conducive to the stop of the etching process; if the thickness of the first epitaxial layer 110 is less than 1 micron, it cannot meet the uniformity of chemical mechanical polishing. Therefore, it is easy to cause over-grinding and damage to the second epitaxial layer 120 .
  • the surface of the exposed second epitaxial layer 120 is guaranteed to be flat, which is beneficial to the performance of the final semiconductor structure.
  • the method further includes: treating the exposed surface of the second epitaxial layer 120 with a TMAH solution, so that the surface of the second epitaxial layer 120 can be The crystal orientation of silicon is consistent, which is beneficial to further improve the flatness of the surface of the second epitaxial layer 120 after the thinning process.
  • the first substrate 100 and the first epitaxial layer 110 are removed, and the second epitaxial layer 120 and the third epitaxial layer are retained layer 130, the pixel unit is formed on the third surface 131 of the third epitaxial layer 130, and the semiconductor structure finally formed is formed in the third epitaxial layer 130 by applying a reverse bias voltage to the photodiode during operation
  • the depletion region if the applied reverse bias voltage is larger, the depletion region is easy to expand.
  • the second epitaxial layer 120 with a larger ion concentration the expansion of the depletion region can be suppressed and the extension of the depletion region to the treated area can be suppressed.
  • dark currents are generated at the thinned interface defects, thereby benefiting the performance of the final semiconductor structure.
  • a second dielectric layer 250 is formed on the fourth surface 121 of the second epitaxial layer 120 , and the second dielectric layer covers the fourth surface 121 of the second epitaxial layer 120 , to protect the fourth surface 121 of the second epitaxial layer 120 .
  • the second dielectric layer 250 is a single-layer structure, including a silicon oxide layer or a silicon nitride layer or other feasible dielectric materials.
  • the second dielectric layer 250 is a stacked structure including a silicon oxide layer and a silicon nitride layer on the silicon oxide layer.
  • conductive plugs 251 are formed in the second dielectric layer 250 , the second epitaxial layer 120 and the third epitaxial layer 130 , and the conductive plugs 251 are connected to the electrical interconnection structure 230 The interconnect metal layer in the electrical connection.
  • the step of forming the conductive plug 251 includes: forming through holes (not shown in the figure) in the second dielectric layer 250 , the second epitaxial layer 120 and the third epitaxial layer 130 ), the through hole is located above the interconnection metal layer in the electrical interconnection structure 230 in the first dielectric layer 220, and the first dielectric layer 220 is exposed; at the bottom of the through hole and the first dielectric A contact hole (not shown in the figure) is formed in the layer 220 to expose the interconnection metal layer in the electrical interconnection structure 230; a conductive layer is formed in the through hole and the contact hole.
  • the step of forming a conductive layer includes: forming a conductive material (not shown) on the second dielectric layer 250 and in the through holes and contact holes, and the conductive material fills the through holes, Contact holes and cover the second dielectric layer 250, and the conductive material is used to form a conductive layer later; using photolithography and dry etching processes, remove the conductive material outside the through hole, and the remaining in the through hole and the contact hole
  • the conductive material serves as the conductive layer.
  • the conductive plugs 251 play an electrical connection function, and transmit the electrical signals in the electrical interconnection structure 230 on the third surface 131 of the third epitaxial layer 130 to the peripheral circuit.
  • a plurality of filters 410 and a lens 420 located on the filters 410 are formed on the second dielectric layer 250 , and the filters 410 and the pixel units 210 are perpendicular to the third epitaxial layer.
  • the directions of the third surfaces 131 of the 130 are aligned one by one to ensure that the incident light can be accurately captured.

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Abstract

一种半导体结构的形成方法，包括：提供第一衬底，第一衬底包括相对的第一表面和第二表面，且第一衬底内具有第一离子，第一离子具有第一浓度；在第一衬底的第一表面上形成第一外延层，第一外延层内具有第二离子，第二离子具有第二浓度，第二浓度小于所述第一浓度；在第一外延层上形成第二外延层以及位于第二外延层上的第三外延层，第二外延层内具有第三离子，第三离子具有第三浓度，第三外延层内具有第四离子，第四离子具有第四浓度，第四浓度小于所述第三浓度；从第一衬底的第二表面对第一衬底进行减薄处理，直至暴露出第二外延层的表面。本发明在保证减薄厚度均一性的同时，能够满足制作半导体结构衬底需求，有利于提高半导体结构的性能。

Description

半导体结构的形成方法 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构的形成方法。
背景技术
图像传感器可用于感测辐射(例如，光辐射，包括但不限于可见光、红外线、紫外线等)。图像传感器按照其接收辐射的方式可以分为背照式(BSI)图像传感器和前照式(FSI)图像传感器。
BSI图像传感器能够从其背面接收辐射。不同于FSI图像传感器，在BSI图像传感器中，布线等可能影响辐射接收的部件基本位于衬底的正面，而光线从衬底的背面入射进入。
对于BSI图像传感器，目前通常采用以下步骤形成：在衬底上生长外延层，在外延层上制作光电感测器件(例如，光电二极管)，然后从背面去除衬底，其中外延层用作去除衬底的停止层。然而，在使用衬底和衬底上的外延层制作BSI图像传感器的情况下，最终只会保留部分低掺杂的外延层，影响最终形成的图像传感器的性能。
因此，需要提供一种半导体结构的形成方法，能实现具有低掺杂外延层和高掺杂衬底的结构。
发明内容
本发明解决的技术问题是提供一种半导体结构的形成方法，有利于提高最终形成的半导体结构的性能。
为解决上述技术问题，本发明实施例提供一种半导体结构的形成方法，包括：提供第一衬底，所述第一衬底包括相对的第一表面和第二表面，且所述第一衬底内具有第一离子，所述第一离子具有第一浓 度；在所述第一衬底的第一表面上形成第一外延层，所述第一外延层内具有第二离子，所述第二离子具有第二浓度，所述第二浓度小于所述第一浓度；在所述第一外延层上形成第二外延层以及位于所述第二外延层上的第三外延层，所述第二外延层内具有第三离子，所述第三离子具有第三浓度，所述第三外延层内具有第四离子，所述第四离子具有第四浓度，所述第四浓度小于所述第三浓度；从所述第一衬底的第二表面对所述第一衬底进行减薄处理，直至暴露出所述第二外延层的表面。
可选的，所述减薄处理的步骤包括：从所述第一衬底的第二表面对所述第一衬底进行刻蚀处理，直至暴露出所述第一外延层的表面；对所述第一外延层进行平坦化处理，直至暴露出所述第二外延层的表面。
可选的，所述刻蚀处理为湿法刻蚀；所述湿法刻蚀处理的工艺参数包括：所述刻蚀溶液包括HNA溶液，所述HNA溶液为由氢氟酸、硝酸及醋酸形成的混合溶液。
可选的，所述平坦化处理为化学机械抛光；所述化学机械抛光的工艺参数包括：选用SiO 2抛光液，抛光时间50～100秒。
可选的，所述第一离子和所述第二离子的导电类型相反。
可选的，所述第三离子和所述第四离子的导电类型相同。
可选的，所述第一离子为P型离子；所述P型离子包括硼离子、铟离子、镓离子中的一种或几种。
可选的，所述第二离子为N型离子；所述N型离子包括磷离子、砷离子、锑离子中的一种或几种。
可选的，所述第三离子为P型离子；所述第四离子为P型离子；所述P型离子包括硼离子、铟离子、镓离子中的一种或几种。
可选的，所述第一浓度的范围为2E18～5E18atoms/cm 3。
可选的，所述第二浓度的范围为5E12～1E15atoms/cm 3。
可选的，所述第三浓度的范围为6E17～5E18atoms/cm 3。
可选的，所述第四浓度的范围为1E13～2E14atoms/cm 3。
可选的，所述第一外延层的厚度范围为1～3微米。
可选的，所述第二外延层的厚度范围为1～5微米。
可选的，所述第三外延层的厚度范围为4～10微米。
可选的，所述第三外延层包括第三表面，所述第三表面背离所述第二外延层，在对所述第一衬底进行减薄处理之前，还包括：在所述第三外延层内形成若干光电掺杂区；形成覆盖所述第三外延层的第三表面和所述光电掺杂区的第一介质层；在所述第一介质层内形成电互连结构。
可选的，在形成互连层之后，还包括：提供第二衬底；将所述第一衬底的第一表面与所述第二衬底相键合。
可选的，所述第二外延层包括第四表面，所述第四表面与所述第一外延层相接触，在对所述第一衬底进行减薄处理之后，还包括：在所述第二外延层的第四表面形成第二介质层；在所述第二介质层、所述第二外延层以及所述第三外延层内形成通孔，所述通孔露出所述第一介质层；在所述通孔底部和所述第一介质层内形成接触孔，露出所述电互连结构；在所述通孔和所述接触孔内形成导电层。
可选的，还包括：在所述第二介质层上形成若干滤光片以及位于所述滤光片上的透镜。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
在第一衬底的第一表面形成第一外延层、位于第一外延层上的第二外延层以及位于第二外延层上的第三外延层，第一外延层内第二离子的第二浓度小于第一衬底内第一离子的第一浓度，第二外延层内第 三离子的第三浓度大于第三外延层内第四离子的第四浓度，从第一衬底的第二表面对第一衬底进行减薄处理，由于第一外延层和第一衬底具有离子浓度差，减薄处理首先会停止于第一外延层，可以控制减薄工艺的厚度均一性，后续继续减薄直至暴露出第二外延层的表面，使第二外延层是一个平坦的表面；并且减薄处理去除了第一衬底和第一外延层，保留了第二外延层和第三外延层，且第三浓度大于第四浓度，后续在第三外延层内形成像素单元后，在像素单元工作过程中加反向偏置电压时，由于第二外延层的存在，可以阻止形成的耗尽区扩散到减薄工艺的界面处，在提高减薄工艺厚度均一性的同时，又满足了制作图像传感器的衬底要求，有利于最终形成的半导体结构的性能。
进一步，所述第一离子和所述第二离子的导电类型相反。通过形成和第一衬底具有相反导电类型的第一外延层，可以使第一衬底和第一外延层的边界更加清晰，避免边界在一些热处理过程中由于离子扩散变得模糊，使得第一外延层更好地起到刻蚀停止层的作用。
附图说明
图1至图8为本发明一实施例中半导体结构形成方法各步骤对应的结构示意图。
具体实施方式
由背景技术可知，目前形成BSI图像传感器的具体方法包括：
提供第一衬底，所述第一衬底包括相对的第一表面和第二表面，且所述第一衬底内具有第一离子，所述离子具有第一浓度；在所述第一表面上形成外延层，所述外延层包括相对的第三表面和第四表面，所述外延层的第四表面与所述第一衬底的第一表面相接触，所述外延层内具有第二离子，所述第二离子具有第二浓度，所述第二浓度小于所述第一浓度；在所述外延层的第三表面形成相互隔离的多个像素单元、覆盖所述外延层的第三表面和所述像素单元的介质层以及位于介质层内的互连层，其中，每个像素单元包括一个发光二极管和多个 MOS晶体管；提供第二衬底，将所述第二衬底与所述第一衬底在第一表面方向键合，接着将所述第二衬底翻转以使所述第一衬底的第二表面朝上；从所述第一衬底的第二表面对所述第一衬底进行减薄处理。
目前，对所述第一衬底的减薄处理通常采用以外延层作为减薄停止层的方法，由于减薄速率对离子浓度非常敏感，在减薄到浓度渐变层时，减薄速率会骤降，使得减薄停止于第一衬底和外延层的交界处。采用外延层停止的减薄工艺，最终会完全去除所述第一衬底，并且减薄停止的界面处，即外延层的第四表面会存在许多晶格缺陷，当最终形成的图像传感器在工作过程中，发光二极管上会施加反向偏置电压，因此会在外延层内形成耗尽区，当施加的反向偏置电压较大时，耗尽区会扩展到外延层第四表面的晶格缺陷处，导致生成暗电流，不利于图像传感器的性能。
如果为了避免耗尽区扩展到减薄工艺停止的界面处，希望保留离子浓度比较高的部分第一衬底而不采用外延层停止的减薄工艺，在对第一衬底进行减薄时，需要自行控制减薄停止的界面，容易造成减薄后剩余的第一衬底的厚度均匀性差的问题，同样会影响传感器的性能。
为了解决上述问题，本发明实施例提供了一种半导体结构的形成方法，在第一衬底上形成第一外延层、位于第一外延层上的第二外延层以及位于第二外延层上的第三外延层，第一外延层内第二离子的第二浓度小于第一衬底内第一离子的第一浓度，第二外延层内第三离子的第三浓度大于第三外延层内第四离子的第四浓度，对第一衬底进行减薄处理时，一方面，由于第一外延层和第一衬底具有离子浓度差，减薄工艺会先停止于第一外延层与第一衬底的交界处，后续再继续减薄处理直至暴露出所述第二外延层的表面，有利于控制减薄的厚度的均一性；另一方面，减薄处理后还保留第二外延层和第三外延层，且第三浓度大于第四浓度，后续在第三外延层形成像素单元后，在像素 单元工作时施加反向偏置电压，由于存在离子浓度较大的第二外延层，可以阻止形成的耗尽区扩展到减薄工艺界面处晶格缺陷，减少暗电流的生成，从而有利于提高半导体结构的性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
参考图1，提供第一衬底100，所述第一衬底100包括相对的第一表面101和第二表面102，且所述第一衬底100内具有第一离子，所述第一离子具有第一浓度。
所述第一衬底100可以为硅衬底，也可以是锗、锗硅、砷化镓衬底或绝缘体上硅衬底。本领域技术人员可以根据需要选择衬底类型，因此第一衬底的类型不应成为限制本发明的保护范围的特征。本实施例中，所述第一衬底10为硅衬底。
本实施例中，所述第一衬底100为P型掺杂，即第一离子为P型离子；所述P型离子包括硼离子、铟离子、镓离子中的一种或几种。
所述第一离子的第一浓度的范围为2E18～5E18atoms/cm 3。
所述第一衬底100的厚度范围为725～775微米；所述第一衬底100的厚度为常规半导体工艺中衬底的一般厚度。
参考图2，在所述第一衬底100的第一表面101上形成第一外延层110，所述第一外延层110内具有第二离子，所述第二离子具有第二浓度，且所述第二浓度小于所述第一浓度。
所述第二离子的第二浓度的范围为5E12～1E15atoms/cm 3。
本实施例中，所述第二浓度小于所述第一浓度，所述第一外延层110与所述第一衬底100的交界处具有浓度差，后续从第二表面102对所述第一衬底100进行减薄处理时，先对第一衬底100进行刻蚀处理，由于刻蚀速率对离子浓度比较敏感，刻蚀速率在离子浓度渐变层会骤降，从而使减薄首先停留在第一外延层110和第一衬底100的交界处，从而控制减薄厚度的均一性。
本实施例中，所述第二离子与所述第一离子的导电类型相反；所述第二离子和所述第一离子采用相反的导电类型的原因在于，可以使第一外延层110和所述第一衬底100的边界更加清晰，避免边界在一些热处理过程中由于离子扩散变得模糊，后续对所述第一衬底100进行减薄处理时，所述第一外延层110能够更好地起到刻蚀停止层的作用。
本实施例中，所述第一离子为P型离子，则所述第二离子为N型离子；所述N型离子包括磷离子、砷离子、锑离子中的一种或几种。
在其他实施例中，所述第二离子与所述第一离子的导电类型也可以相同。
本实施例中，采用外延生长工艺形成所述第一外延层110。
所述第一外延层110的厚度范围为1～3微米；如果所述第一外延层110的厚度大于3微米，第二离子可能会在第一外延层110内形成浓度渐变层，不利于后续减薄处理中刻蚀工艺的停止；如果所述第一外延层110的厚度小于1微米，后续减薄处理中平坦化处理时容易造成过研磨，损伤到第二外延层120。
参考图3，在所述第一外延层110上形成第二外延层120以及位于所述第二外延层120上的第三外延层130，所述第二外延层120内具有第三离子，所述第三离子具有第三浓度，所述第三外延层130具有第四离子，所述第四离子具有第四浓度，所述第四浓度小于所述第三浓度。
所述第三浓度的范围为6E17～5E18atoms/cm 3；所述第四浓度的范围为1E13～2E14atoms/cm 3。
本实施例中，所述第三离子和所述第四离子的导电类型相同，且所述第三离子、第四离子与所述第一离子的导电类型相同。
本实施例中，所述第三离子为P型离子；所述第四离子为P型离 子；所述P型离子包括硼离子、铟离子、镓离子中的一种或几种。
本实施例中，在所述第一外延层110上继续形成第二外延层120和第三外延层130的原因在于，后续对第一衬底100进行减薄处理后，会去除第一衬底100和第一外延层110，直至暴露出第二外延层120的表面，剩余的第二外延层120和所述第三外延层130作为形成半导体结构的基底，且第三浓度大于第四浓度，满足了制作图像传感器的基底需求，有利于提高形成的半导体结构的性能。
本实施例中，采用外延生长工艺形成所述第二外延层120以及所述第三外延层130。
所述第二外延层120的厚度范围为1～5微米；所述第三外延层130的厚度范围为4～10微米；所述第二外延层120和所述第三外延层130的厚度可以根据具体实际情况进行选择。
所述第三外延层130包括第三表面131，所述第三表面131背离所述第二外延层120；所述第二外延层120包括第四表面121，所述第四表面121与所述第一外延层110相接触。
参考图4，形成第三外延层130后，在所述第三外延层130内形成若干光电掺杂区210。相邻所述光电掺杂区210通过浅沟槽隔离结果240隔离。
本实施例中，还包括：形成覆盖所述第三外延层130的第三表面131和所述光电掺杂区的第一介质层220。
本实施例中，还包括：在所述第一介质层220内形成逻辑电路(未图示)，所述逻辑电路包括MOS晶体管以及与MOS晶体管电连接的电互连结构230，所述MOS晶体管中的电信号通过所述电互连结构230传输。
本实施例中，形成光电掺杂区210的方法包括：
在所述第三外延层130的第三表面131形成图形化层(未图示)，所述图形化层暴露出部分所述第三外延层130的第三表面131；以所 述图形化层为掩膜进行离子注入，在所述第三外延层130内形成光电掺杂区210。
所述光电掺杂区210的掺杂类型与第三外延层130的掺杂类型相反，如第三外延层130为P型掺杂，第一掺杂区为N型掺杂，或相反。这样，在垂直于第三外延层130的第三表面131的方向上，第一掺杂区和第三外延层130之间形成PN结，形成一个光电二极管。
本实施例中，所述电互连结构230包括叠置在一起的多层互连金属层和连接相邻两层互连金属层的插塞层(图中未示出)，其中互连金属层位于浅沟槽隔离结构240上方。电互连结构230的形成方法为本领域技术人员所熟知，在此不再赘述。
参考图5，提供第二衬底300，将所述第二衬底300与所述第一衬底100在第一表面101方向键合，将所述第一衬底100翻转至第二表面102朝上。键合的方式可以是共熔键合，也可以是其他任何在半导体工艺中可行的焊接工艺。
翻转所述第一衬底100后，从所述第二表面102对所述第一衬底100进行减薄处理，具体的，所述减薄处理的步骤包括：
参考图6，从所述第一衬底100的第二表面102对所述第一衬底100进行刻蚀处理，直至暴露出所述第一外延层110的表面。
本实施例中，所述刻蚀处理为湿法刻蚀工艺；所述湿法刻蚀工艺的工艺参数包括：所述刻蚀溶液包括HNA溶液，所述HNA溶液为由氢氟酸、硝酸及醋酸形成的混合溶液。
本实施例中，由于第一外延层110与所述第一衬底100具有离子浓度差，且湿法刻蚀对离子浓度非常敏感，刻蚀速率在浓度变化处会骤降，因此在湿法刻蚀过程中所述第一外延层110作为刻蚀停止层，可以使湿法刻蚀停止在第一衬底100与第一外延层110的交界处，提高减薄厚度的均一性。
参考图7，继续对所述第一外延层110进行平坦化处理，直至暴 露出所述第二外延层120的表面。
本实施例中，所述平坦化处理为化学机械抛光；所述化学机械抛光的工艺参数包括：选用SiO 2抛光液，抛光时间50～100秒。
本实施例中，化学机械抛光有利于进一步提高减薄处理的厚度均匀性。
本实施例中，所述化学机械抛光的厚度为所述第一外延层110的厚度，所述第一外延层110的厚度范围为1～3微米；如果所述第一外延层110的厚度大于3微米，第二离子可能会在第一外延层110内形成浓度渐变层，不利于刻蚀工艺的停止；如果所述第一外延层110的厚度小于1微米，在化学机械抛光时无法满足均匀性的需求，且容易造成过研磨，损伤到第二外延层120。
本实施例中，对第一外延层110进行平坦化处理后，保证暴露出的第二外延层120的表面平整，有利于最终形成的半导体结构的性能。
本实施例中，对所述第一外延层110进行平坦化处理后，还包括：采用TMAH溶液对暴露出的所述第二外延层120的表面进行处理，可以使第二外延层120表面的硅的晶向一致，有利于进一步提高减薄处理后的第二外延层120表面的平整度。
本实施例中，对所述第一衬底100进行减薄处理后，去除所述第一衬底100以及所述第一外延层110，保留所述第二外延层120和所述第三外延层130，像素单元形成在所述第三外延层130的第三表面131，最终形成的半导体结构在工作过程中，在光电二极管上施加反向偏置电压，从而在第三外延层130内形成耗尽区，如果施加的反向偏置电压较大，耗尽区容易扩展，通过保留离子浓度较大的第二外延层120，可以抑制耗尽区的扩展，避免耗尽区扩展到处理的界面处，在减薄处理的界面缺陷处生成暗电流，从而有利于最终形成的半导体结构的性能。
参考图8，在进行减薄处理后，在所述第二外延层120的第四表面121形成第二介质层250，所述第二介质层覆盖所述第二外延层120的第四表面121，以保护所述第二外延层120的第四表面121。
本实施例中，所述第二介质层250为单层结构，包括氧化硅层或氮化硅层或其他可行的介质材料。
在其他实施例中，所述第二介质层250为叠层结构，包括氧化硅层和位于氧化硅层上的氮化硅层。
继续参考图8，在所述第二介质层250、所述第二外延层120以及所述第三外延层130内形成导电插塞251，所述导电插塞251与所述电互连结构230中的互连金属层电连接。
本实施例中，形成所述导电插塞251的步骤包括：在所述第二介质层250、所述第二外延层120以及所述第三外延层130内形成通孔(图中未示出)，所述通孔位于第一介质层220中的电互连结构230中的互连金属层的上方，且露出所述第一介质层220；在所述通孔底部和所述第一介质层220中形成接触孔(图中未示出)，露出所述电互连结构230中的互连金属层；在所述通孔和所述接触孔内形成导电层。
本实施例中，形成导电层的步骤包括：在所述第二介质层250上和所述通孔、接触孔中形成导电材料(未图示)，所述导电材料填充满所述通孔、接触孔并覆盖所述第二介质层250，所述导电材料用于后续形成导电层；使用光刻、干法刻蚀工艺，去除通孔外的导电材料，在通孔和接触孔内剩余的导电材料作为导电层。
本实施例中，所述导电插塞251起到电连接作用，将第三外延层130的第三表面131上电互连结构230中的电信号传输至外围电路。
继续参考图8，在所述第二介质层250上形成若干滤光片410以及位于所述滤光片410上的透镜420，所述滤光片410与像素单元210在垂直于第三外延层130的第三表面131的方向上一一对准，以保证 能够准确捕捉入射光。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种半导体结构的形成方法，其特征在于，包括：
    提供第一衬底，所述第一衬底包括相对的第一表面和第二表面，且所述第一衬底内具有第一离子，所述第一离子具有第一浓度；
    在所述第一衬底的第一表面上形成第一外延层，所述第一外延层内具有第二离子，所述第二离子具有第二浓度，所述第二浓度小于所述第一浓度；
    在所述第一外延层上形成第二外延层以及位于所述第二外延层上的第三外延层，所述第二外延层内具有第三离子，所述第三离子具有第三浓度，所述第三外延层内具有第四离子，所述第四离子具有第四浓度，所述第四浓度小于所述第三浓度；
    从所述第一衬底的第二表面对所述第一衬底进行减薄处理，直至暴露出所述第二外延层的表面。
  2. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述减薄处理的步骤包括：从所述第一衬底的第二表面对所述第一衬底进行刻蚀处理，直至暴露出所述第一外延层的表面；对所述第一外延层进行平坦化处理，直至暴露出所述第二外延层的表面。
  3. 如权利要求2所述的半导体结构的形成方法，其特征在于，所述刻蚀处理为湿法刻蚀；所述湿法刻蚀处理的工艺参数包括：所述刻蚀溶液包括HNA溶液，所述HNA溶液为由氢氟酸、硝酸及醋酸形成的混合溶液。
  4. 如权利要求2所述的半导体结构的形成方法，其特征在于，所述平坦化处理为化学机械抛光；所述化学机械抛光的工艺参数包括：选用SiO 2抛光液，抛光时间50～100秒。
  5. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一离子和所述第二离子的导电类型相反。
  6. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第三离子和所述第四离子的导电类型相同。
  7. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述第一离子为P型离子；所述P型离子包括硼离子、铟离子、镓离子中的一种或几种。
  8. 如权利要求5所述的半导体结构的形成方法，其特征在于，所述第二离子为N型离子；所述N型离子包括磷离子、砷离子、锑离子中的一种或几种。
  9. 如权利要求6所述的半导体结构的形成方法，其特征在于，所述第三离子为P型离子；所述第四离子为P型离子；所述P型离子包括硼离子、铟离子、镓离子中的一种或几种。
  10. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一浓度的范围为2E18～5E18atoms/cm 3。
  11. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第二浓度的范围为5E12～1E15atoms/cm 3。
  12. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第三浓度的范围为6E17～5E18atoms/cm 3。
  13. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第四浓度的范围为1E13～2E14atoms/cm 3。
  14. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一外延层的厚度范围为1～3微米。
  15. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第二外延层的厚度范围为1～5微米。
  16. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第三外延层的厚度范围为4～10微米。
  17. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述第三外延层包括第三表面，所述第三表面背离所述第二外延层，在对所述第一衬底进行减薄处理之前，还包括：在所述第三外延层内形成若干光电掺杂区；形成覆盖所述第三外延层的第三表面和所述光电掺杂区的第一介质层；在所述第一介质层内形成电互连结构。
  18. 如权利要求17所述的半导体结构的形成方法，其特征在 于，在形成电互连结构之后，还包括：提供第二衬底；将所述第一衬底的第一表面与所述第二衬底相键合。
  19. 如权利要求18所述的半导体结构的形成方法，其特征在于，所述第二外延层包括第四表面，所述第四表面与所述第一外延层相接触，在对所述第一衬底进行减薄处理之后，还包括：在所述第二外延层的第四表面形成第二介质层；在所述第二介质层、所述第二外延层以及所述第三外延层内形成通孔，所述通孔露出所述第一介质层；在所述通孔底部和所述第一介质层内形成接触孔，露出所述电互连结构；在所述通孔和所述接触孔内形成导电层。
  20. 如权利要求19所述的半导体结构的形成方法，其特征在于，还包括：在所述第二介质层上形成若干滤光片以及位于所述滤光片上的透镜。
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