WO2020113613A1 - 薄膜晶体管结构及其制作方法、显示装置 - Google Patents

薄膜晶体管结构及其制作方法、显示装置 Download PDF

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WO2020113613A1
WO2020113613A1 PCT/CN2018/120171 CN2018120171W WO2020113613A1 WO 2020113613 A1 WO2020113613 A1 WO 2020113613A1 CN 2018120171 W CN2018120171 W CN 2018120171W WO 2020113613 A1 WO2020113613 A1 WO 2020113613A1
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layer
thin film
film transistor
preset time
transistor structure
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French (fr)
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莫琼花
卓恩宗
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HKC Co Ltd
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HKC Co Ltd
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    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators

Definitions

  • the present application relates to the field of display technology, and in particular to a thin film transistor structure, a manufacturing method thereof, and a display device.
  • GOA Gate Driven Array, grid drive integration on array substrate
  • the gate drive circuit is integrated on the display panel array substrate by using the GOA technology, so that the gate can be omitted Drive the integrated circuit part to reduce product cost from both material cost and manufacturing process.
  • the use of GOA drive technology has certain quality and reliability risks, mainly due to the switching elements used to control the progressive scan switch, such as TFT (Thin Film Transistor, thin film transistor) hydrogen-doped amorphous silicon semiconductor Threshold voltage shift caused by shift characteristics.
  • TFT Thin Film Transistor, thin film transistor
  • a method for manufacturing a thin film transistor structure that can reduce a threshold voltage shift in a TFT device is provided.
  • a thin film transistor structure and a display device are also provided.
  • a method for manufacturing a thin film transistor structure includes:
  • the source electrode and the drain electrode are used as etching barrier layers, and the active layer and the doped layer are dry-etched to obtain a second groove corresponding to the first groove, and the second groove A groove penetrates the doped layer and partially penetrates the active layer, and the first groove and the second groove form a channel region;
  • the channel region Placing the channel region in a preset gas atmosphere for heating; wherein, the channel region is first heated for a first preset time, then placed in a nitrogen atmosphere for a second preset time, and finally set Heating for a third preset time in an ammonia atmosphere; or
  • the channel region is heated for a fourth preset time, and finally placed in an ammonia gas atmosphere for a fifth preset time.
  • a method of increasing the total volume of the deposition gas is used for deposition, wherein the reference range of the total volume is 41200 sccm-43200 sccm; when the total volume increases by 100%, PH3 in the deposition gas
  • the gas flow ratio with SiH4 is 1.8-4.5.
  • the gas flow ratio of PH3 and SiH4 in the deposition gas is 2-6.
  • the first preset time is 0s-50s
  • the second preset time is 0s-20s
  • the third preset time is 0s-20s
  • the fourth preset time Is 0s-50s
  • the fifth preset time is 0s-20s.
  • the first preset time is 25s
  • the second preset time is 15s
  • the third preset time is 7s
  • the fourth preset time is 25s
  • the first Five preset time is 10s.
  • the deposited gate insulating layer is divided into a first rate deposition, a second rate deposition, and a third rate deposition; wherein, the values of the first rate, second rate, and third rate decrease sequentially .
  • the thickness of the gate insulating layer formed by the first rate deposition is 500 angstroms to 1000 angstroms
  • the thickness of the gate insulating layer formed by the second rate deposition is 1000 angstroms
  • the third rate deposition The thickness of the gate insulating layer formed is 2000 angstroms.
  • the deposition process of the first metal layer includes one of radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process.
  • a thin film transistor structure wherein the manufacturing method of the thin film transistor structure is used, the method includes:
  • the source electrode and the drain electrode are used as etching barrier layers, and the active layer and the doped layer are dry-etched to obtain a second groove corresponding to the first groove, and the second groove A groove penetrates the doped layer and partially penetrates the active layer, and the first groove and the second groove form a channel region;
  • the channel region Placing the channel region in a preset gas atmosphere for heating; wherein, the channel region is first heated for a first preset time, then placed in a nitrogen atmosphere for a second preset time, and finally set Heating for a third preset time in an ammonia atmosphere; or
  • the thin film transistor structure includes:
  • a channel region is located in the middle of the doped layer, the channel region penetrates the doped layer and partially penetrates to the active layer, and the source and drain are located in the channel region On both sides.
  • the thickness of the gate ranges from 3000 angstroms to 5000 angstroms.
  • the gate includes at least one of molybdenum, titanium, aluminum, and copper.
  • the thickness of the active layer ranges from 550 angstroms to 700 angstroms.
  • the active layer includes amorphous silicon.
  • the thickness of the source electrode ranges from 3500 angstroms to 5000 angstroms; the thickness of the drain electrode ranges from 3500 angstroms to 5000 angstroms.
  • the source electrode includes at least one of molybdenum, titanium, aluminum, and copper; the drain electrode includes at least one of molybdenum, titanium, aluminum, and copper.
  • the thickness of the gate insulating layer ranges from 3500 angstroms to 4000 angstroms.
  • the gate insulating layer includes at least one of silicon oxide and silicon nitride.
  • the thin film transistor structure further includes:
  • a protective layer is formed on the source electrode and the drain electrode.
  • the protective layer includes at least one of silicon oxide and silicon nitride.
  • a display device including a thin film transistor structure, the thin film transistor structure including:
  • a channel region is located in the middle of the doped layer, the channel region penetrates the doped layer and partially penetrates to the active layer, and the source and drain are located in the channel region On both sides.
  • the above thin film transistor structure, its manufacturing method and display device by heating the channel region for a first preset time, then placed in a nitrogen atmosphere for a second preset time, and finally placed in an ammonia atmosphere for a third preset Set time. Or the channel region is heated for a fourth preset time, and finally placed in an atmosphere of ammonia for a fifth preset time to repair the damage to the channel region, reduce the weak bonds in the amorphous silicon, and enhance the illumination and illumination of the thin film transistor
  • the stability reduces the drift of the threshold voltage, which in turn can improve the final display effect of the display device.
  • FIG. 1 is a flowchart of a method for manufacturing a thin film transistor structure in an embodiment
  • FIG. 2 is a schematic structural view of step S100 in FIG. 1;
  • FIG. 3 is a schematic diagram of the structure formed in FIG. 1 according to step S200;
  • FIG. 4 is a schematic diagram of the structure formed in FIG. 1 according to steps S300 and S400;
  • FIG. 5 is a schematic structural view of FIG. 1 formed according to step S500;
  • FIG. 6 is a schematic structural view of FIG. 1 formed according to step S600;
  • FIG. 7 is a schematic structural diagram of a thin film transistor structure in an embodiment
  • FIG. 8 is a schematic structural diagram of a thin film transistor structure in another embodiment.
  • FIG. 1 is a schematic flowchart of a method for manufacturing a thin film transistor in an embodiment.
  • the manufacturing method of the thin film transistor may include steps: S100-S700.
  • Step S100 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate.
  • the substrate 10 may be a glass substrate or a plastic substrate.
  • the glass substrate may be alkali-free borosilicate ultra-thin glass.
  • the alkali-free borosilicate glass has higher physical characteristics Good corrosion resistance, higher thermal stability and lower density and higher elastic modulus.
  • the deposition of the first metal layer (not shown in FIG. 2) on the substrate 10 may be a radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process.
  • the first metal layer (not shown in FIG. 2) may be a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the patterning process may be to form a desired pattern, that is, the gate electrode 20, by a photolithography process.
  • the thickness of the gate electrode 20 may range from 3000 angstroms to 5000 angstroms. Alternatively, the thickness of the gate electrode 20 may be 3000 angstroms to 4000 angstroms. Further, the thickness of the gate electrode 20 may be 4000 angstroms to 5000 angstroms. It can be understood that the thickness of the gate electrode 20 can be selected and adjusted according to actual application conditions and product performance, which is not further limited herein.
  • Step S200 a gate insulating layer is deposited on the substrate, and the gate insulating layer covers the gate.
  • a gate insulating layer 30 is deposited on the substrate 10, and at the same time, the gate insulating layer 30 covers the gate 20.
  • the deposition process may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process.
  • the thickness of the gate insulating layer 30 may be 3500 angstroms-4000 angstroms. Alternatively, the thickness of the gate insulating layer 30 may be 3500 angstroms-3700 angstroms. Further, the thickness of the gate insulating layer 30 may be 3700 angstroms-4000 angstroms. Egypt.
  • the thickness of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the gate insulating layer 30 may be one or a combination of silicon oxide and silicon nitride, that is, the gate insulating layer 30 may be silicon oxide, silicon nitride, or silicon oxide and nitrogen Silicone mixture.
  • the plasma enhanced chemical vapor deposition gate insulating layer 30 can be divided into a first rate deposition, a second rate deposition, and a third rate deposition; wherein, the first rate, the first rate The values of the second rate and the third rate decrease sequentially.
  • the value of the first rate is greater than the value of the second rate
  • the value of the second rate is greater than the value of the third rate.
  • the first rate is the high speed
  • the second rate corresponds to medium speed
  • the third rate corresponds to low speed.
  • the thickness of the gate insulating layer formed by the first rate deposition is 500 angstroms to 1000 angstroms
  • the thickness of the gate insulating layer formed by the second rate deposition is 1000 angstroms
  • the thickness of the gate insulating layer formed by the third rate deposition It is 2000 Angstroms.
  • the deposition formation of the gate insulating layer 30 is divided into three deposition stages, first using the first rate deposition can increase the deposition rate and increase the productivity, then using the second rate deposition to perform the rate transition, and transitioning to the third deposition rate for the deposition
  • the channel region to be formed subsequently has good interface characteristics, and at the same time, the unevenness of the interface between the amorphous silicon and the gate insulating layer can be reduced, and the electron mobility can be improved.
  • Step S300 an active layer and a doped layer are sequentially deposited on the gate insulating layer.
  • the active layer 40 and the doped layer 50 may be deposited by radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition processes.
  • the active layer 40 may be deposited using SiH4 gas
  • the doped layer 50 may be deposited using PH3 and SiH4 gas.
  • the temperature for depositing the doped layer 50 may be 300°C-400°C.
  • the temperature for depositing the doped layer 50 may be 300°C-360°C
  • the temperature for depositing the doped layer 50 may be 340°C-360°C. .
  • deposition is performed by increasing the total volume of the deposition gas, wherein the reference range of the total volume is 41200sccm-43200sccm; sccm means standard milliliters/minute.
  • the total volume increases by 100% the gas flow ratio of PH 3 and SiH 4 in the deposition gas is 1.8-4.5; the total volume increase here by 100% is an increase over the reference range of the total volume of deposition gas familiar to those skilled in the art 100%.
  • the total volume can be increased by 100% on the basis of 41200sccm.
  • the gas flow ratio of PH 3 and SiH 4 in the deposition gas can be 1.8-4.5, optionally, PH 3 and SiH 4
  • the gas flow ratio can also be 1.8-3; alternatively, the gas flow ratio of PH 3 and SiH 4 can also be 3-4.5.
  • the deposition gas may further include H2, NH3, N2, and Ar.
  • the flow ratio of these gases is not further limited, and those skilled in the art can select and adjust according to the performance and actual conditions of the product.
  • the gas flow ratio of PH 3 and SiH 4 in the deposition gas is 2-6; the total volume increase here by 150% is a benchmark for the total volume of deposition gas familiar to those skilled in the art 150% increase in range.
  • the total volume can be increased by 150% on the basis of 43200sccm.
  • the gas flow ratio of PH 3 and SiH 4 can be 2-6.
  • the gas flow of PH 3 and SiH 4 The ratio can also be 2-4; alternatively, the gas flow ratio of PH 3 and SiH 4 can also be 4-6.
  • Step S400 performing photolithography on the active layer and the doped layer.
  • Photolithography refers to the use of a reticle with a certain layer of design graphics. After exposure and development, a photosensitive photoresist is used to form a three-dimensional relief pattern on the substrate.
  • Step S500 a second metal layer is deposited on the doped layer, and the second metal layer is subjected to photolithography and wet etching to obtain a central portion of the second metal layer that penetrates the second metal layer A first groove of the metal layer, and the second metal layer are separated into a source electrode and a drain electrode by the first groove.
  • FIG. 5 deposit a second metal layer (not shown in FIG. 5) on the doped layer 50, and perform photolithography and wet etching on the second metal layer to obtain a layer located in the middle of the second metal layer And penetrate the first groove 72 of the second metal layer.
  • the second metal layer is separated into the source electrode 610 and the drain electrode 620 by the first groove 72.
  • a photoresist layer can be coated on the second metal layer, and then a photomask can be used to expose and develop the photoresist layer.
  • the second metal layer is wet etched to obtain a first groove 72 located in the middle of the second metal layer and penetrating the first metal layer, as shown in FIG. 5 The three-dimensional pattern shown.
  • On the left and right sides of the first groove 72 are a source electrode 610 and a drain electrode 620, respectively.
  • Step S600 using the source electrode and the drain electrode as an etching barrier layer, dry etching the active layer and the doped layer to obtain a second groove corresponding to the first groove, A second groove penetrates the doped layer and partially penetrates the active layer, and the first groove and the second groove form a channel region.
  • the source electrode 610 and the drain electrode 620 are used as etching barrier layers, and the active layer 40 and the doped layer 50 are dry etched To obtain a second groove corresponding to the first groove 72 (not shown in FIG. 6).
  • the second groove penetrates the doped layer 50 and partially penetrates the active layer 40.
  • "Partial penetration” means that the active layer part located in the second groove is not completely etched. Because the active layer serves as a conductive medium, it cannot be completely etched. It can be understood that the specific thickness of the "part" can be selected and adjusted according to the actual production situation and product performance.
  • the first groove 72 and the second groove form a channel region 70.
  • Step S700 the channel region is placed in a preset gas atmosphere for heating treatment; wherein, the channel region is placed in a nitrogen atmosphere and heated for a first preset time in a mixed atmosphere of nitrogen and ammonia The second preset time is heated in the middle, and the third preset time is heated in the atmosphere of ammonia. Or, the channel region is first heated for a fourth preset time, and finally placed in an ammonia gas atmosphere for a fifth preset time.
  • the channel region 70 may be damaged. Therefore, in order to repair the damage of the channel region, the channel region 70 may be Gas heat treatment.
  • the specific heating environment and heating time can be: under the heating temperature of 275 °C-285 °C, the channel area is first heated for 0s-50s, optionally, first heated for 25s; then placed in a nitrogen atmosphere and heated for 0s-20s Alternatively, the channel region may be heated in an atmosphere of nitrogen for 15 s; finally placed in an atmosphere of ammonia for 0 s-20 s, and optionally, heated in an atmosphere of ammonia for 7 s.
  • the manufacturing method of the above thin film transistor structure is that the channel region is heated for a first preset time, then placed in an atmosphere of nitrogen for a second preset time, and finally placed in an atmosphere of ammonia for a third preset time. Or the channel region is heated for a fourth preset time, and finally placed in an atmosphere of ammonia for a fifth preset time to repair the damage to the channel region, reduce the weak bonds in the amorphous silicon, and enhance the illumination and illumination of the thin film transistor
  • the stability reduces the drift of the threshold voltage, which in turn can improve the final display effect of the display device.
  • SiH 4 gas flow rate ratio of the threshold voltage shift may be Improve the final display effect of the display device.
  • FIG. 7 is a schematic structural diagram of a thin film transistor structure in an embodiment.
  • the thin film transistor structure is manufactured using the foregoing method for manufacturing a thin film transistor structure.
  • the thin film transistor structure may include: a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, a doped layer 50, a source 610, and a drain 620.
  • the gate 20 is formed on the substrate 10; the gate insulating layer 30 is formed on the substrate 10, and the gate insulating layer 30 covers the gate 20; the active layer 40 is formed on the gate insulating layer 30; the doped layer 50 It is formed on the active layer 40; the source electrode 610 and the drain electrode 620 are formed on the doped layer 50.
  • a channel region 70 is located in the middle of the doped layer 50. The channel region 70 penetrates the doped layer 50 and partially penetrates the active layer 40.
  • the source electrode 610 and the drain electrode 620 are located on both sides of the channel region 70.
  • the above thin film transistor structure is manufactured by using the foregoing thin film transistor structure manufacturing method embodiment, and the foregoing thin film transistor structure manufacturing method embodiment is to heat the channel region for a first preset time, and then heat the second in a nitrogen atmosphere The preset time, and finally placed in an atmosphere of ammonia gas for heating for a third preset time. Or the channel region is heated for a fourth preset time, and finally placed in an atmosphere of ammonia for a fifth preset time to repair the damage to the channel region, reduce the weak bonds in the amorphous silicon, and enhance the illumination and illumination of the thin film transistor
  • the stability reduces the drift of the threshold voltage, which in turn enables the manufactured thin film transistor to improve the final display effect of the display device.
  • SiH 4 gas flow rate ratio of the threshold voltage shift can be reduced, while obtaining better IS (Image Sticking, blur) effect, may be The thin film transistor manufactured thereby improves the final display effect of the display device.
  • the substrate 10 may be a glass substrate or a plastic substrate, wherein the glass substrate may be alkali-free borosilicate ultra-thin glass, and the alkali-free borosilicate glass has higher physical characteristics, better corrosion resistance, and higher Thermal stability and lower density and higher modulus of elasticity.
  • the grid 20 is formed on the substrate 10, wherein the formation process of the grid 20 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the gate electrode 20 can be selected and adjusted according to actual application conditions and product performance, which is not further limited herein.
  • the material of the gate 20 can be one or more of a stack combination of molybdenum, titanium, aluminum, and copper; selecting molybdenum, titanium, aluminum, and copper as the material of the gate 20 can ensure good conductivity. It can be understood that the material of the gate 20 can be selected and adjusted according to the actual application situation and product performance, and is not further limited herein.
  • the thickness of the gate electrode 20 may range from 3000 angstroms to 5000 angstroms. Alternatively, the thickness of the gate electrode 20 may be 3000 angstroms to 4000 angstroms. Further, the thickness of the gate electrode 20 may be 4000 angstroms to 5000 angstroms. It can be understood that the thickness of the gate electrode 20 can be selected and adjusted according to actual application conditions and product performance, which is not further limited herein.
  • the gate insulating layer 30 is formed on the substrate 10, and the forming process of the gate insulating layer 30 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the gate insulating layer 30 may be one or a combination of silicon oxide and silicon nitride, that is, the gate insulating layer 30 may be silicon oxide, silicon nitride, or silicon oxide and nitrogen Silicone mixture.
  • the material of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the thickness of the gate insulating layer 30 may be 3500 angstroms-4000 angstroms. Alternatively, the thickness of the gate insulating layer 30 may be 3500 angstroms-3700 angstroms. Alternatively, the thickness of the gate insulating layer 30 may be 3700 angstroms- 4000 Angstroms. It can be understood that the thickness of the gate insulating layer 30 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the active layer 40 is formed on the gate insulating layer 30.
  • the formation process of the active layer 40 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the forming process of the active layer 40 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the active layer 40 may be amorphous silicon, and the active layer 40 is generally used as a conductive medium.
  • the thickness of the active layer 40 may be 550 angstroms to 700 angstroms. Alternatively, the thickness of the active layer 40 may be 550 angstroms to 600 angstroms. Further, the thickness of the active layer 40 may be 600 angstroms to 700 angstroms. It can be understood that the thickness of the active layer 40 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the doped layer 50 is formed on the active layer 40.
  • the formation process of the doped layer 50 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the doped layer 50 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the thickness of the doped layer 50 may be 400 angstroms. It can be understood that the thickness of the doped layer 50 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the doped layer 50 may be N-type doped in the amorphous silicon layer or P-type doped in the amorphous silicon layer.
  • the doped layer 50 is N-type doped in the amorphous silicon layer At the same time, it is N-type heavily doped, wherein the doping method may include high temperature diffusion and ion implantation.
  • High temperature diffusion is the diffusion or deposition of impurity atoms onto the surface of a silicon wafer through a gas phase source or doped oxide. The concentration of these impurities will monotonically decrease from the surface to the body. In high temperature diffusion, the distribution of impurities is mainly caused by high temperature and Diffusion time to decide.
  • Ion implantation is to implant doped ions into the semiconductor in the form of an ion beam, and the impurity concentration has a peak distribution in the semiconductor.
  • the impurity distribution is mainly determined by the ion mass and the implantation energy.
  • N-type doping is mainly doped with pentavalent impurity elements such as phosphorus and arsenic in semiconductors.
  • the advantages of ion implantation over high temperature diffusion are: 1.
  • the implanted ions are selected by a mass analyzer.
  • the selected particles have high purity and single energy, thus ensuring that the doping concentration is not affected by the purity of the impurity source.
  • the implantation process is carried out under clean, dry vacuum conditions, and all kinds of pollution are reduced to the lowest level; 2.
  • the number of doped atoms implanted into the wafer can be accurately controlled, and the implantation dose is from 10 11 /cm for adjusting the threshold voltage 2 to 10 17 /cm 2 where the buried insulating layer is formed, with a wide range. 3.
  • the substrate is generally maintained at room temperature or below 400°C. Therefore, silicon dioxide, silicon nitride, aluminum, and photoresist can be used as masking films for selective doping, making the self-aligned masking technology in device manufacturing more flexible.
  • the source electrode 610 and the drain electrode 620 are formed on the doped layer 50.
  • the formation process of the source electrode 610 and the drain electrode 620 may include radio frequency magnetron sputtering, thermal evaporation, vacuum electron beam evaporation, and plasma enhanced chemical vapor deposition process. It can be understood that the formation process of the source electrode 610 and the drain electrode 620 can be selected and adjusted according to actual application conditions and product performance, and is not further limited herein.
  • the material of the source electrode 610 and the drain electrode 620 can be one or more of a stack combination of molybdenum, titanium, aluminum and copper; the selection of molybdenum, titanium, aluminum and copper as the source electrode 610 and the drain electrode 620 can ensure good Conductive properties.
  • the materials of the source electrode 610 and the drain electrode 620 can be selected and adjusted according to actual application conditions and product performance, and are not further limited herein.
  • the thickness of the source electrode 610 and the drain electrode 620 may be from 3500 angstroms to 5000 angstroms. Alternatively, the thickness of the source electrode 610 and the drain electrode 620 may be from 3500 angstroms to 4000 angstroms. Further, the thickness of the source electrode 610 and the drain electrode 620 The thickness may be 4000 to 5000 Angstroms.
  • the material and thickness of the source electrode 610 and the drain electrode 620 may be the same or different, and the material and thickness of the source electrode 610 and the drain electrode 620 may be selected and adjusted according to the actual application situation and product performance, and no further details will be made here. limited.
  • the channel region 70 is located in the middle of the doped layer 50.
  • the channel region 70 penetrates the doped layer 50 and partially penetrates the active layer 40.
  • the source electrode 610 and the drain electrode 620 are located on both sides of the channel region 70.
  • "Through" can be achieved by photolithography or etching methods. Specifically, photolithography refers to the use of a reticle with a certain layer of design graphics. After exposure and development, the photosensitive photoresist forms a three-dimensional relief on the substrate Graphics. Etching means that under the masking of photoresist, different microlayer patterns are formed as required, and different etching substances and methods are used to selectively etch the film layers. In this way, after removing the photoresist, the three-dimensional design pattern is transferred to the relevant film layer of the substrate.
  • FIG. 8 is a structural schematic diagram of a thin film transistor structure in another embodiment.
  • the thin film transistor structure may include a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, a doped layer 50, a source 610, a drain 620, and a protective layer 80.
  • the gate 20 is formed on the substrate 10; the gate insulating layer 30 is formed on the substrate 10, and the gate insulating layer 30 covers the gate 20; the active layer 40 is formed on the gate insulating layer 30; the doped layer 50 Formed on the active layer 40; the source electrode 610 and the drain electrode 620 are formed on the doped layer 50, the protective layer 80 is formed on the source electrode 610 and the drain electrode 620; a channel region 70 is located in the middle of the doped layer 50, The channel region 70 penetrates the doped layer 50 and partially penetrates the active layer 40.
  • the source electrode 610 and the drain electrode 620 are located on both sides of the channel region 70, and the protective layer 80 covers the channel region 70.
  • the protective layer 80 is mainly used to protect the thin film transistor device from pollution and damage. Specifically, the protective layer 80 is also called a PV (Passivation, passivation) layer.
  • the material of the protective layer 80 may be silicon nitride, silicon oxide, or both. Combination. It can be understood that there is no special limit to the thickness of the protective layer 80, and those skilled in the art can select and adjust according to actual production conditions and product performance.
  • the above thin film transistor structure is manufactured by using the foregoing thin film transistor structure manufacturing method embodiment, and the foregoing thin film transistor structure manufacturing method embodiment is to heat the channel region for a first preset time, and then heat the second in a nitrogen atmosphere The preset time, and finally placed in an atmosphere of ammonia gas for heating for a third preset time. Or the channel region is heated for a fourth preset time, and finally placed in an atmosphere of ammonia for a fifth preset time to repair the damage to the channel region, reduce the weak bonds in the amorphous silicon, and enhance the illumination and illumination of the thin film transistor
  • the stability reduces the drift of the threshold voltage, which in turn enables the manufactured thin film transistor to improve the final display effect of the display device.
  • the thin film transistor manufactured thereby improves the final display effect of the display device. Further, by providing a protective layer, the thin film transistor can be protected from damage.
  • a display device may include the aforementioned thin film transistor structure embodiment.
  • the aforementioned display device is manufactured using the aforementioned thin film transistor structure manufacturing method embodiment, and the aforementioned thin film transistor structure manufacturing method embodiment is adopted by The channel region is heated for a first preset time, then placed in an atmosphere of nitrogen for a second preset time, and finally placed in an atmosphere of ammonia for a third preset time.
  • the channel region is heated for a fourth preset time, and finally placed in an atmosphere of ammonia for a fifth preset time to repair the damage to the channel region, reduce the weak bonds in the amorphous silicon, and enhance the illumination and illumination of the thin film transistor
  • the stability reduces the drift of the threshold voltage, which can further improve the final display effect of the thin film transistor display device manufactured by the above manufacturing method. Further, by increasing the total volume of SiH 4, PH 3 and PH 3, and thereby increasing manner SiH 4 gas flow rate ratio of the threshold voltage shift can be reduced, while obtaining better IS (Image Sticking, blur) effect, may be Therefore, the final display effect of the thin film transistor display device manufactured by the above manufacturing method is improved.

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Abstract

一种薄膜晶体管结构及其制作方法、显示装置。该方法包括：提供一基板（10），并在基板（10）上依次形成栅极（20）、栅极绝缘层（30）、有源层（40）、掺杂层（50）、源极（610）、漏极（620）及沟道区（70）；将沟道区（70）置于预设的气体氛围中进行加热处理；其中，将沟道区（70）置于氮气的气氛中加热第一预设时间，在氮气和氨气的混合气氛中加热第二预设时间，在氨气的气氛中加热第三预设时间；或先对沟道区（70）加热第四预设时间，最后置于氨气的气氛中加热第五预设时间。

Description

薄膜晶体管结构及其制作方法、显示装置
相关申请的交叉引用
本申请要求于2018年12月03日提交中国专利局、申请号为201811466314.5、申请名称为“薄膜晶体管结构及其制作方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及一种薄膜晶体管结构及其制作方法、显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
GOA(Gate Driven on Array，阵列基板上栅驱动集成)技术，能实现显示面板的逐行扫描驱动功能，利用GOA技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
相比集成电路驱动，采用GOA驱动技术存在一定的品质和可靠性风险，主要是由于用于控制逐行扫描开关的开关元件，例如TFT(Thin Film Transistor，薄膜晶体管)中掺氢非晶硅半导体偏移特性所引起的阈值电压偏移。如何减小TFT器件中的阈值电压偏移，进而提高显示器的显示效果是本领域技术人员亟待解决的问题。
申请内容
根据本申请的各种实施例，提供一种可以减小TFT器件中的阈值电压偏移的薄膜晶体管结构的制作方法。
此外，还提供一种薄膜晶体管结构及显示装置。
一种薄膜晶体管结构的制作方法，包括：
提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进 行图案化处理，形成栅极；
在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
在所述栅极绝缘层上依次沉积有源层、掺杂层；
对所述有源层、掺杂层进行光刻处理；
在所述掺杂层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层被所述第一凹槽间隔成源极、漏极；
以所述源极、漏极为刻蚀阻挡层，对所述有源层、掺杂层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述掺杂层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区；
将所述沟道区置于预设的气体氛围中进行加热处理；其中，先对所述沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间；或
先对所述沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间。
在其中一个实施例中，沉积所述掺杂层时，采用增加沉积气体总体积的方式进行沉积，其中，总体积的基准范围为41200sccm-43200sccm；当总体积增加100％时，沉积气体中PH3和SiH4的气体流量比为1.8-4.5。
在其中一个实施例中，当总体积增加150％时，沉积气体中PH3和SiH4的气体流量比为2-6。
在其中一个实施例中，所述第一预设时间为0s-50s，所述第二预设时间为0s-20s，所述第三预设时间为0s-20s，所述第四预设时间为0s-50s，所述第五预设时间为0s-20s。
在其中一个实施例中，所述第一预设时间为25s，所述第二预设时间为15s，所述第三预设时间为7s，所述第四预设时间为25s，所述第五预设时间为10s。
在其中一个实施例中，所述沉积栅极绝缘层分为第一速率沉积、第二速率沉积和第三速率沉积；其中，所述第一速率、第二速率及第三速率的数值依次递减。
在其中一个实施例中，第一速率沉积形成的所述栅极绝缘层的厚度为500埃-1000埃，第二速率沉积形成的所述栅极绝缘层的厚度为1000埃，第三速率沉积形成的所述栅极绝缘层的厚度为2000埃。
在其中一个实施例中，所述第一金属层的沉积工艺包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺中的一种。
一种薄膜晶体管结构，其中，使用薄膜晶体管结构的制作方法进行制造，所述方法包括：
提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
在所述栅极绝缘层上依次沉积有源层、掺杂层；
对所述有源层、掺杂层进行光刻处理；
在所述掺杂层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层被所述第一凹槽间隔成源极、漏极；
以所述源极、漏极为刻蚀阻挡层，对所述有源层、掺杂层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述掺杂层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区；
将所述沟道区置于预设的气体氛围中进行加热处理；其中，先对所述沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间；或
先对所述沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间；
所述薄膜晶体管结构包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
有源层，形成于所述栅极绝缘层上；
掺杂层，形成于所述有源层上；及
形成于所述掺杂层上的源极与漏极；
其中，一沟道区位于所述掺杂层的中部，所述沟道区贯穿所述掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
在其中一个实施例中，所述栅极的厚度范围为3000埃-5000埃。
在其中一个实施例中，所述栅极包括钼、钛、铝和铜中的至少一种。
在其中一个实施例中，所述有源层的厚度范围为550埃-700埃。
在其中一个实施例中，所述有源层包括非晶硅。
在其中一个实施例中，所述源极的厚度范围为3500埃-5000埃；所述漏极的厚度范围为3500埃-5000埃。
在其中一个实施例中，所述源极包括钼、钛、铝和铜中的至少一种；所述漏极包括钼、钛、铝和铜中的至少一种。
在其中一个实施例中，所述栅极绝缘层的厚度范围为3500埃-4000埃。
在其中一个实施例中，所述栅极绝缘层包括氧化硅和氮化硅中的至少一种。
在其中一个实施例中，所述薄膜晶体管结构还包括：
保护层，形成于所述源极、漏极上。
在其中一个实施例中，所述保护层包括氧化硅和氮化硅中的至少一种。
一种显示装置，其中，包括薄膜晶体管结构，所述薄膜晶体管结构包括：
基板；
栅极，形成于所述基板上；
栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
有源层，形成于所述栅极绝缘层上；
掺杂层，形成于所述有源层上；及
形成于所述掺杂层上的源极与漏极；
其中，一沟道区位于所述掺杂层的中部，所述沟道区贯穿所述掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
上述薄膜晶体管结构及其制作方法、显示装置，通过将沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间。或者将沟道区加热第四预设时间，最后置于氨气的气 氛中加热第五预设时间可修复沟道区的损伤，减少非晶硅中的弱键，增强薄膜晶体管的照光以及照光稳定性，减少阈值电压的漂移，进而可提高显示装置的最终显示效果。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的薄膜晶体管结构的制作方法流程图；
图2为图1中步骤S100形成的结构示意图；
图3为图1中根据步骤S200形成的结构示意图；
图4为图1中根据步骤S300和S400形成的结构示意图；
图5为图1中根据步骤S500形成的结构示意图；
图6为图1中根据步骤S600形成的结构示意图；
图7为一实施例中的薄膜晶体管结构的结构示意图；
图8为另一实施例中的薄膜晶体管结构的结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的可选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
请参阅图1，为一实施例中的薄膜晶体管的制作方法流程示意图。该薄膜 晶体管的制作方法可以包括步骤：S100-S700。
步骤S100，提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极。
具体地，请辅助参阅图2，基板10可以是玻璃基板或塑料基板，其中，玻璃基板可以为无碱硼硅酸盐超薄玻璃，无碱硼硅酸盐玻璃具有较高的物理特性、较好的耐腐蚀性能、较高的热稳定性以及较低的密度和较高的弹性模量。在基板10上沉积第一金属层(图2未标示)可以是射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。第一金属层(图2未标示)可以是钼、钛、铝和铜中的一种或者多种的堆栈组合。图案化处理可以是通过光刻处理形成所需的图案，也就是栅极20。栅极20的厚度范围可以为3000埃-5000埃，可选地，栅极20的厚度可以为3000埃-4000埃，进一步地，栅极20的厚度可以为4000埃-5000埃。可以理解，栅极20的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
步骤S200，在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极。
具体地，请辅助参阅图3，在基板10上沉积栅极绝缘层30，同时，栅极绝缘层30将栅极20覆盖住。沉积工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。栅极绝缘层30的厚度可以为3500埃-4000埃，可选地，栅极绝缘层30的厚度可以为3500埃-3700埃，进一步地，栅极绝缘层30的厚度可以为3700埃-4000埃。可以理解，栅极绝缘层30的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极绝缘层30的材料可以是氧化硅、氮化硅中的一种或者二者的组合，即栅极绝缘层30可以是氧化硅，也可以是氮化硅，还可以是氧化硅和氮化硅的混合物。
可选地，以等离子增强化学气相沉积工艺为例，采用等离子增强化学气相沉积栅极绝缘层30可以分为第一速率沉积、第二速率沉积和第三速率沉积；其中，第一速率、第二速率及第三速率的数值依次递减，换句话说，第一速率的数值大于第二速率的数值，第二速率的数值大于第三速率的数值，可以这样理解，以第一速率为高速为例，第二速率相应为中速，第三速率相应 为低速。当然，对于具体的数值本申请没有特殊限制，本领域人员可以实际生产情况和产品性能进行调整和选择。进一步地，第一速率沉积形成的栅极绝缘层的厚度为500埃-1000埃，第二速率沉积形成的栅极绝缘层的厚度为1000埃，第三速率沉积形成的栅极绝缘层的厚度为2000埃。将栅极绝缘层30的沉积形成分为三个沉积阶段，先使用第一速率沉积可以增加沉积速率，提高产能，然后使用第二速率沉积进行速率的过渡，过渡到第三沉积速率进行沉积可以使得后续形成的沟道区有良好的界面特性，同时还可减少非晶硅和栅极绝缘层界面的凹凸特性，提高电子迁移率。
步骤S300，在所述栅极绝缘层上依次沉积有源层、掺杂层。
具体地，可以通过射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺来沉积有源层40、掺杂层50。示例性地，以等离子增强化学气相沉积为例。可采用SiH4气体来沉积有源层40，采用PH3和SiH4气体来沉积掺杂层50。同时，沉积掺杂层50的温度可以为300℃-400℃，可选地，沉积掺杂层50的温度可以为300℃-360℃，沉积掺杂层50的温度可以为340℃-360℃。可选地，沉积掺杂层50时，采用增加沉积气体总体积的方式进行沉积，其中，总体积的基准范围为41200sccm-43200sccm；sccm的含义为标准毫升/分钟。当总体积增加100％时，沉积气体中PH 3和SiH 4的气体流量比为1.8-4.5；此处的总体积增加100％是在本领域技术人员熟悉的沉积气体总体积的基准范围上增加的100％。例如，可在总体积为41200sccm的基础上增加100％，在总体积增加100％后，沉积气体中PH 3和SiH 4的气体流量比可以为1.8-4.5，可选地，PH 3和SiH 4的气体流量比还可以为1.8-3；可选地，PH 3和SiH 4的气体流量比还可以为3-4.5。可以理解，沉积气体中还可包括H2、NH3、N2和Ar，对于这几种气体的流量比不作进一步限定，本领域技术人员可根据产品的性能和实际情况进行选择和调整。进一步地，当总体积增加150％时，沉积气体中PH 3和SiH 4的气体流量比为2-6；此处的总体积增加150％是在本领域技术人员熟悉的沉积气体总体积的基准范围上增加的150％。例如，可在总体积为43200sccm的基础上增加150％，在总体积增加150％后，PH 3和SiH 4的气体流量比可以为2-6，可选地，PH 3和SiH 4的气体流量比还可以为2-4；可选地，PH 3和SiH 4的气体流量比还可以为4-6。采用增加PH 3和SiH 4 的总体积进而增加PH 3和SiH 4的气体流量比的方式可以减小阈值电压漂移，同时获得较好的IS(Image Sticking，残影)效果。
步骤S400，对所述有源层、掺杂层进行光刻处理。
具体地，请辅助参阅图4，对有源层40、掺杂层50进行光刻处理得到如图4所示的立体图案。光刻是指使用带有某一层设计图形的掩模版，经过曝光和显影，使光敏的光刻胶在衬底上形成三维浮雕图形。
步骤S500，在所述掺杂层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层通过所述第一凹槽间隔成源极、漏极。
具体地，请辅助参阅图5，在掺杂层50上沉积第二金属层(图5未标示)，对第二金属层进行光刻、湿法刻蚀处理，得到一位于第二金属层中部、并贯穿所述第二金属层的第一凹槽72，第二金属层被第一凹槽72间隔成源极610、漏极620。进一步地，可以通过在第二金属层上涂布一层光阻层，然后采用一道光罩对光阻层进行曝光、显影。更进一步地，然后以光阻层为遮挡，对第二金属层进行湿法刻蚀，得到一位于第二金属层中部、并贯穿第一金属层的第一凹槽72，得到如图5所示的立体图案。在第一凹槽72的左右两侧分别为源极610和漏极620。
步骤S600，以所述源极、漏极为刻蚀阻挡层，对所述有源层、掺杂层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述掺杂层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区。
具体地，请辅助参阅图6，在形成源极610和漏极620之后，以源极610和漏极620为刻蚀阻挡层，对有源层40、掺杂层50进行干法刻蚀处理，得到与第一凹槽72对应的第二凹槽(图6未标示)。第二凹槽贯穿掺杂层50、并部分贯穿至有源层40。“部分贯穿”即没有全部刻蚀掉位于第二凹槽中的有源层部分，因为有源层作为导电的介质，所以不能被全部刻蚀掉。可以理解，对于“部分”的具体厚度，可以根据实际生产情况和产品性能作出选择和调整。第一凹槽72与第二凹槽形成沟道区70。
步骤S700，将所述沟道区置于预设的气体氛围中进行加热处理；其中， 将所述沟道区置于氮气的气氛中加热第一预设时间，在氮气和氨气的混合气氛中加热第二预设时间，在氨气的气氛中加热第三预设时间。或先对所述沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间。
具体地，在对有源层40、掺杂层50进行蚀刻形成沟道区70的时候，会造成沟道区70的损伤，因此，为了修复沟道区的损伤，可以对沟道区70进行气体加热处理。具体的加热环境和加热时间可以为：在加热温度275℃-285℃之下，先对沟道区加热0s-50s，可选地，先加热25s；然后置于氮气的气氛中加热0s-20s，可选地，可将沟道区置于氮气的气氛中加热15s；最后置于氨气的气氛中加热0s-20s，可选地，在氨气的气氛中加热7s。最后置于氨气的气氛中加热0s-20s，可选地，在氨气的气氛中加热7s。或者，在加热温度275℃-285℃之下，先对沟道区加热0s-50s，可选地，先加热25s；最后置于氨气的气氛中加热0s-20s，可选地，在氨气的气氛中加热10s。
上述薄膜晶体管结构的制作方法，通过将沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间。或者将沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间可修复沟道区的损伤，减少非晶硅中的弱键，增强薄膜晶体管的照光以及照光稳定性，减少阈值电压的漂移，进而可提高显示装置的最终显示效果。进一步地，采用增加PH 3和SiH 4的总体积进而增加PH 3和SiH 4的气体流量比的方式可以减小阈值电压漂移，同时获得较好的IS(Image Sticking，残影)效果，也可以提高显示装置的最终显示效果。
请参阅图7为一实施例中的薄膜晶体管结构的结构示意图，该薄膜晶体管结构使用前述薄膜晶体管结构的制作方法实施例进行制造。该薄膜晶体管结构可以包括：基板10，栅极20，栅极绝缘层30，有源层40，掺杂层50及源极610、漏极620。其中，栅极20形成于基板10上；栅极绝缘层30形成于基板10上，同时栅极绝缘层30覆盖栅极20；有源层40形成于栅极绝缘层30上；掺杂层50形成于有源层40上；源极610、漏极620形成于掺杂层50上。一沟道区70位于掺杂层50的中部，沟道区70贯穿掺杂层50、并部分贯穿至有源层40，源极610与漏极620位于沟道区70的两侧。
上述薄膜晶体管结构通过使用前述薄膜晶体管结构的制作方法实施例进 行制造，而前述薄膜晶体管结构的制作方法实施例通过将沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间。或者将沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间可修复沟道区的损伤，减少非晶硅中的弱键，增强薄膜晶体管的照光以及照光稳定性，减少阈值电压的漂移，进而可使得制造出来的薄膜晶体管可提高显示装置的最终显示效果。进一步地，采用增加PH 3和SiH 4的总体积进而增加PH 3和SiH 4的气体流量比的方式可以减小阈值电压漂移，同时获得较好的IS(Image Sticking，残影)效果，也可以使得制造出来的薄膜晶体管提高显示装置的最终显示效果。
基板10可以是玻璃基板或塑料基板，其中，玻璃基板可以为无碱硼硅酸盐超薄玻璃，无碱硼硅酸盐玻璃具有较高的物理特性、较好的耐腐蚀性能、较高的热稳定性以及较低的密度和较高的弹性模量。
栅极20形成于基板10上，其中，栅极20的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，栅极20的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极20的材料可以为钼、钛、铝和铜中的一种或者多种的堆栈组合；选用钼、钛、铝和铜作为栅极20材料可以保证良好的导电性能。可以理解，栅极20的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极20的厚度范围可以为3000埃-5000埃，可选地，栅极20的厚度可以为3000埃-4000埃，进一步地，栅极20的厚度可以为4000埃-5000埃。可以理解，栅极20的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
栅极绝缘层30，形成于基板10上，栅极绝缘层30的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，栅极绝缘层30的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。栅极绝缘层30的材料可以是氧化硅、氮化硅中的一种或者二者的组合，即栅极绝缘层30可以是氧化硅，也可以是氮化硅，还可以是氧化硅和氮化硅的混合物。可以理解，栅极绝缘层30的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的 限定。栅极绝缘层30的厚度可以为3500埃-4000埃，可选地，栅极绝缘层30的厚度可以为3500埃-3700埃，可选地，栅极绝缘层30的厚度可以为3700埃-4000埃。可以理解，栅极绝缘层30的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
有源层40形成于栅极绝缘层30上，有源层40的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，有源层40的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。有源层40的材料可以为非晶硅，有源层40通常作为导电的介质。有源层40的厚度可以为550埃-700埃，可选地，有源层40的厚度为550埃-600埃，进一步地，有源层40的厚度可以为600埃-700埃。可以理解，有源层40的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
掺杂层50，形成于有源层40上，掺杂层50的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，掺杂层50的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。掺杂层50的厚度可以为400埃，可以理解，掺杂层50的厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。掺杂层50可以是在非晶硅层中进行N型掺杂，也可以是非晶硅层中进行P型掺杂，可选地，掺杂层50为在非晶硅层中进行N型掺杂，同时，为N型重掺杂，其中，掺杂方式可以包括高温扩散和离子注入。高温扩散是将杂质原子通过气相源或掺杂过的氧化物扩散或淀积到硅晶片的表面，这些杂质浓度将从表面到体内单调下降，在高温扩散中，杂质的分布主要是由高温与扩散时间来决定。离子注入即将掺杂离子以离子束的形式注入半导体内，杂质浓度在半导体内有峰值分布，在离子注入中，杂质分布主要由离子质量和注入能量决定。N型掺杂主要是在半导体内掺入五价杂质元素，例如：磷、砷。离子注入相对于高温扩散的优点是：1、注入的离子是通过质量分析器选取出来的，被选取的粒子纯度高，能量单一，从而保证了掺杂浓度不受杂质源纯度的影响。另外，注入过程在清洁、干燥的真空条件下进行，各种污染降到最低水平；2、可以精确控制注入到晶片中的掺杂原子数 目，注入剂量从用于调整阈值电压的10 11/cm 2到形成绝缘埋层的10 17/cm 2，范围较宽。3、离子注入时，衬底一般保持在室温或低于400℃的温度环境下。因此，像二氧化硅、氮化硅、铝和光刻胶等都可以用来作为选择掺杂的掩蔽膜，使器件制造中的自对准掩蔽技术更加灵活。
源极610、漏极620形成于掺杂层50上，源极610、漏极620的形成工艺可以包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺。可以理解，源极610、漏极620的形成工艺可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。源极610、漏极620的材料可以为钼、钛、铝和铜中的一种或者多种的堆栈组合；选用钼、钛、铝和铜作为源极610、漏极620材料可以保证良好的导电性能。可以理解，源极610、漏极620的材料可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。源极610、漏极620的厚度可以为3500埃-5000埃，可选地，源极610、漏极620的厚度可以为3500埃-4000埃，更进一步地，源极610、漏极620的厚度可以为4000埃-5000埃。可以理解，源极610、漏极620的材料和厚度可以相同也可以不相同，源极610、漏极620的材料和厚度可以根据实际应用情况以及产品性能进行选择和调整，在此不作进一步的限定。
沟道区70位于掺杂层50的中部，沟道区70贯穿掺杂层50、并部分贯穿有源层40。源极610与漏极620就位于沟道区70的两侧。“贯穿”可以通过光刻或者刻蚀方法实现，具体的，光刻是指使用带有某一层设计图形的掩模版，经过曝光和显影，使光敏的光刻胶在衬底上形成三维浮雕图形。刻蚀是指在光刻胶掩蔽下，根据需要形成微图形的膜层不同，采用不同的刻蚀物质和方法在膜层上进行选择性刻蚀。这样，去掉光刻胶以后，三维设计图形就转移到了衬底的相关膜层上。
请参阅图8，为另一实施例中薄膜晶体管结构的结构示意图。该薄膜晶体管结构可以包括基板10，栅极20，栅极绝缘层30，有源层40，掺杂层50，源极610、漏极620及保护层80。其中，栅极20形成于基板10上；栅极绝缘层30形成于基板10上，同时栅极绝缘层30覆盖栅极20；有源层40形成于栅极绝缘层30上；掺杂层50形成于有源层40上；源极610、漏极620形 成于掺杂层50上，保护层80形成于源极610、漏极620上；一沟道区70位于掺杂层50的中部，沟道区70贯穿掺杂层50、并部分贯穿至有源层40，源极610与漏极620位于沟道区70的两侧，同时保护层80覆盖沟道区70。
可以理解，对于基板10、栅极20、栅极绝缘层30、有源层40、掺杂层50、源极610、漏极620的材料、形成工艺、组成、厚度等，可以参照前述薄膜晶体管结构实施例的描述，在此不再进一步进行赘述。
保护层80主要用于保护薄膜晶体管器件免受污染和损伤，具体的，保护层80也称为PV(Passivation,钝化)层，保护层80的材料可以是氮化硅、氧化硅或者二者的结合。可以理解，对于保护层80的厚度没有特殊限制，本领域技术人员可根据实际生产情况和产品性能进行选择和调整。
上述薄膜晶体管结构通过使用前述薄膜晶体管结构的制作方法实施例进行制造，而前述薄膜晶体管结构的制作方法实施例通过将沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间。或者将沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间可修复沟道区的损伤，减少非晶硅中的弱键，增强薄膜晶体管的照光以及照光稳定性，减少阈值电压的漂移，进而可使得制造出来的薄膜晶体管可提高显示装置的最终显示效果。进一步地，采用增加PH 3和SiH 4的总体积进而增加PH 3和SiH 4的气体流量比的方式可以减小阈值电压漂移，同时获得较好的IS(Image Sticking，残影)效果，也可以使得制造出来的薄膜晶体管提高显示装置的最终显示效果。进一步地，通过设置保护层，可保护薄膜晶体管免受损伤。
一种显示装置，可以包括前述所述的薄膜晶体管结构实施例，上述显示装置，由于薄膜晶体管结构采用使用前述薄膜晶体管结构的制作方法实施例进行制造，而前述薄膜晶体管结构的制作方法实施例通过将沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间。或者将沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间可修复沟道区的损伤，减少非晶硅中的弱键，增强薄膜晶体管的照光以及照光稳定性，减少阈值电压的漂移，进而可使得采用上述制作方法制造出来的薄膜晶体管的显示装置的最终显示效果得以提高。进 一步地，采用增加PH 3和SiH 4的总体积进而增加PH 3和SiH 4的气体流量比的方式可以减小阈值电压漂移，同时获得较好的IS(Image Sticking，残影)效果，也可以使得采用上述制作方法制造出来的薄膜晶体管的显示装置的最终显示效果得以提高。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种薄膜晶体管结构的制作方法，其中，包括：
    提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
    在所述栅极绝缘层上依次沉积有源层、掺杂层；
    对所述有源层、掺杂层进行光刻处理；
    在所述掺杂层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层被所述第一凹槽间隔成源极、漏极；
    以所述源极、漏极为刻蚀阻挡层，对所述有源层、掺杂层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述掺杂层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区；
    将所述沟道区置于预设的气体氛围中进行加热处理；其中，先对所述沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间；或
    先对所述沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间。
  2. 根据权利要求1所述的薄膜晶体管结构的制作方法，其中，沉积所述掺杂层时，采用增加沉积气体总体积的方式进行沉积，其中，总体积的基准范围为41200sccm-43200sccm；当总体积增加100％时，沉积气体中PH3和SiH4的气体流量比为1.8-4.5。
  3. 根据权利要求2所述的薄膜晶体管结构的制作方法，其中，当总体积增加150％时，沉积气体中PH3和SiH4的气体流量比为2-6。
  4. 根据权利要求1所述的薄膜晶体管结构的制作方法，其中，所述第一预设时间为0s-50s，所述第二预设时间为0s-20s，所述第三预设时间为0s-20s，所述第四预设时间为0s-50s，所述第五预设时间为0s-20s。
  5. 根据权利要求4所述的薄膜晶体管结构的制作方法，其中，所述第一预设时间为25s，所述第二预设时间为15s，所述第三预设时间为7s，所述第 四预设时间为25s，所述第五预设时间为10s。
  6. 根据权利要求1所述的薄膜晶体管结构的制作方法，其中，所述沉积栅极绝缘层分为第一速率沉积、第二速率沉积和第三速率沉积；其中，所述第一速率、第二速率及第三速率的数值依次递减。
  7. 根据权利要求6所述的薄膜晶体管结构的制作方法，其中，第一速率沉积形成的所述栅极绝缘层的厚度为500埃-1000埃，第二速率沉积形成的所述栅极绝缘层的厚度为1000埃，第三速率沉积形成的所述栅极绝缘层的厚度为2000埃。
  8. 根据权利要求1所述的薄膜晶体管结构的制作方法，所述第一金属层的沉积工艺包括射频磁控溅射、热蒸发、真空电子束蒸发以及等离子增强化学气相沉积工艺中的一种。
  9. 一种薄膜晶体管结构，其中，使用薄膜晶体管结构的制作方法进行制造，所述方法包括：
    提供一基板，并在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
    在所述基板上沉积栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
    在所述栅极绝缘层上依次沉积有源层、掺杂层；
    对所述有源层、掺杂层进行光刻处理；
    在所述掺杂层上沉积第二金属层，对所述第二金属层进行光刻、湿法刻蚀处理，得到一位于所述第二金属层中部、并贯穿所述第二金属层的第一凹槽，所述第二金属层被所述第一凹槽间隔成源极、漏极；
    以所述源极、漏极为刻蚀阻挡层，对所述有源层、掺杂层进行干法刻蚀处理，得到与所述第一凹槽对应的第二凹槽，所述第二凹槽贯穿所述掺杂层、并部分贯穿至所述有源层，所述第一凹槽与所述第二凹槽形成沟道区；
    将所述沟道区置于预设的气体氛围中进行加热处理；其中，先对所述沟道区加热第一预设时间，然后置于氮气的气氛中加热第二预设时间，最后置于氨气的气氛中加热第三预设时间；或
    先对所述沟道区加热第四预设时间，最后置于氨气的气氛中加热第五预设时间；
    所述薄膜晶体管结构包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
    有源层，形成于所述栅极绝缘层上；
    掺杂层，形成于所述有源层上；及
    形成于所述掺杂层上的源极与漏极；
    其中，一沟道区位于所述掺杂层的中部，所述沟道区贯穿所述掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
  10. 根据权利要求9所述的薄膜晶体管结构，其中，所述栅极的厚度范围为3000埃-5000埃。
  11. 根据权利要求10所述的薄膜晶体管结构，其中，所述栅极包括钼、钛、铝和铜中的至少一种。
  12. 根据权利要求9所述的薄膜晶体管结构，其中，所述有源层的厚度范围为550埃-700埃。
  13. 根据权利要求12所述的薄膜晶体管结构，其中，所述有源层包括非晶硅。
  14. 根据权利要求9所述的薄膜晶体管结构，其中，所述源极的厚度范围为3500埃-5000埃；所述漏极的厚度范围为3500埃-5000埃。
  15. 根据权利要求14所述的薄膜晶体管结构，其中，所述源极包括钼、钛、铝和铜中的至少一种；所述漏极包括钼、钛、铝和铜中的至少一种。
  16. 根据权利要求9所述的薄膜晶体管结构，其中，所述栅极绝缘层的厚度范围为3500埃-4000埃。
  17. 根据权利要求16所述的薄膜晶体管结构，其中，所述栅极绝缘层包括氧化硅和氮化硅中的至少一种。
  18. 根据权利要求9所述的薄膜晶体管结构，其中，还包括：
    保护层，形成于所述源极、漏极上。
  19. 根据权利要求18所述的薄膜晶体管结构，其中，所述保护层包括氧化硅和氮化硅中的至少一种。
  20. 一种显示装置，其中，包括薄膜晶体管结构，所述薄膜晶体管结构包括：
    基板；
    栅极，形成于所述基板上；
    栅极绝缘层，形成所述基板上，其中，所述栅极绝缘层覆盖所述栅极；
    有源层，形成于所述栅极绝缘层上；
    掺杂层，形成于所述有源层上；及
    形成于所述掺杂层上的源极与漏极；
    其中，一沟道区位于所述掺杂层的中部，所述沟道区贯穿所述掺杂层、并部分贯穿至所述有源层，所述源极与漏极位于所述沟道区的两侧。
PCT/CN2018/120171 2018-12-03 2018-12-11 薄膜晶体管结构及其制作方法、显示装置 Ceased WO2020113613A1 (zh)

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