WO2020107953A1 - Goa 电路及显示面板 - Google Patents

Goa 电路及显示面板 Download PDF

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Publication number
WO2020107953A1
WO2020107953A1 PCT/CN2019/101404 CN2019101404W WO2020107953A1 WO 2020107953 A1 WO2020107953 A1 WO 2020107953A1 CN 2019101404 W CN2019101404 W CN 2019101404W WO 2020107953 A1 WO2020107953 A1 WO 2020107953A1
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WIPO (PCT)
Prior art keywords
transistor
signal
clock signal
electrically connected
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/101404
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English (en)
French (fr)
Inventor
赵莽
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US16/611,237 priority Critical patent/US10930192B2/en
Publication of WO2020107953A1 publication Critical patent/WO2020107953A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA Gate Driver on Array
  • Chinese full name: integrated gate drive circuit integrates the gate drive circuit on the array substrate of the display panel, so that the gate drive integrated circuit part can be omitted, from the material cost and The production process reduces the product cost in two aspects.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem that the existing GOA circuit has a leakage risk and poor reliability.
  • An embodiment of the present application provides a GOA circuit, including: a multi-level cascaded GOA unit, each level of GOA unit includes: a positive and negative scanning module, an output module and a pull-down module;
  • the forward and reverse scanning modules are connected to the upper-level scanning drive signal, forward scanning signal, lower-level scanning drive signal, reverse scanning signal and constant voltage low-level signal, and are electrically connected to the first control clock terminal , A third control clock terminal, a first node and a second node, for outputting the forward scan signal to the first node, or for outputting the reverse scan signal to the first node, And output the constant voltage low-level signal to the second node under the potential control of the first node;
  • the output module is connected to the constant-voltage low-level signal and the constant-voltage high-level signal, and is electrically connected to the first node and the second control clock terminal, and is used to output a scan driving signal at the current level;
  • the pull-down module is connected to the constant voltage low level signal, the forward scan signal, the reverse scan signal and the constant voltage high level signal, and is electrically connected to the first control clock Terminal, the third control clock terminal, the first node and the current-level scan drive signal, used to pull down the potential of the first node and the potential of the current level scan drive signal to the constant voltage low power The potential of the flat signal;
  • the forward scan signal and the reverse scan signal are both DC power sources, and the potential of the forward scan signal is opposite to the potential of the reverse scan signal;
  • the forward and reverse scanning module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the gate of the first transistor is electrically connected to the first control clock terminal, the source of the first transistor is connected to the forward scan signal, and the drain of the first transistor is electrically connected to the The source of the second transistor, the gate of the second transistor is connected to the scan drive signal of the previous stage, the drain of the second transistor is electrically connected to the first node, and the third transistor Is electrically connected to the third control clock terminal, the source of the third transistor is connected to the reverse scan signal, and the drain of the third transistor is electrically connected to the fourth transistor The source, the gate of the fourth transistor is connected to the next-level scan driving signal, the drain of the fourth transistor is electrically connected to the first node, and the gate of the fifth transistor is electrically Connected to the first node, the source of the fifth transistor is connected to the constant voltage low-level signal, and the drain of the fifth transistor is electrically connected to the second node;
  • the output module includes: a sixth transistor, a seventh transistor, and a first capacitor;
  • the gate of the sixth transistor is connected to the constant voltage high-level signal, the source of the sixth transistor is electrically connected to the first node, and the drain of the sixth transistor is electrically connected to the A gate of the seventh transistor, a source of the seventh transistor is electrically connected to the first control clock terminal, and a drain of the seventh transistor is electrically connected to the current scan driving signal, the One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the constant voltage low-level signal.
  • the pull-down module includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor;
  • the gate of the eighth transistor is connected to the forward scan signal, the source of the eighth transistor is electrically connected to the third control clock terminal, and the gate of the ninth transistor is connected to the reverse To the scan signal, the source of the ninth transistor is electrically connected to the first control clock terminal, and the drain of the eighth transistor and the drain of the ninth transistor are electrically connected to the tenth transistor Gate, the source of the tenth transistor is connected to the constant voltage high-level signal, the drain of the tenth transistor, the gate of the eleventh transistor, and the gate of the twelfth transistor
  • the electrode is electrically connected to the second node, the source of the eleventh transistor and the source of the twelfth transistor are connected to the constant voltage low-level signal, and the drain of the eleventh transistor Is electrically connected to the first node, the drain of the twelfth transistor is electrically connected to the current-level scan driving signal, and one end of the second capacitor is electrically connected to the second node, the The other end of the second capacitor is electrically connected to the
  • the GOA circuit receives a first master clock signal, a second master clock signal, a third master clock signal, and a fourth master clock signal, the first master clock signal, the first The second master clock signal, the third master clock signal, and the fourth master clock signal are sequentially time-sharing effective in the action period of the GOA circuit;
  • the second control clock terminal is connected to the first master clock signal, and the third control clock terminal is connected to the second A main clock signal, the first control clock terminal is connected to the fourth main clock signal;
  • the second control clock terminal is connected to the second master clock signal, and the third control clock terminal is connected to the third master clock Signal, the first control clock terminal is connected to the first master clock signal;
  • the second control clock terminal is connected to the third master clock signal, and the third control clock terminal is connected to the fourth master clock Signal, the first control clock terminal is connected to the second master clock signal;
  • the second control clock terminal is connected to the fourth master clock signal, and the third control clock terminal is connected to the first master clock Signal, the first control clock terminal is connected to the third master clock signal; k is a positive integer.
  • the GOA circuit receives the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal ,
  • the clock signal, the sixth clock signal, the seventh clock signal, and the eighth clock signal are sequentially time-sharing effective in the action period of the GOA circuit;
  • the second control clock terminal is connected to the first clock signal
  • the third control clock terminal is connected to the third clock signal, the first Controlling the clock terminal to access the seventh clock signal
  • the second control clock terminal is connected to the second clock signal
  • the third control clock terminal is connected to the fourth clock signal
  • the first control clock The terminal accesses the eighth clock signal
  • the second control clock terminal is connected to the third master clock signal, the third control clock terminal is connected to the fifth clock signal, and the first control The clock terminal accesses the first clock signal;
  • the second control clock terminal is connected to the fourth master clock signal
  • the third control clock terminal is connected to the sixth clock signal
  • the first control The clock terminal accesses the second clock signal
  • the second control clock terminal accesses the fifth clock signal
  • the third control clock terminal accesses the seventh clock signal
  • the first control clock The terminal accesses the third clock signal
  • the second control clock terminal accesses the sixth clock signal
  • the third control clock terminal accesses the eighth clock signal
  • the first control clock The terminal accesses the fourth clock signal
  • the second control clock terminal accesses the seventh clock signal
  • the third control clock terminal accesses the first clock signal
  • the first control clock The terminal accesses the fifth clock signal
  • the second control clock terminal accesses the eighth clock signal
  • the third control clock terminal accesses the second clock signal
  • the first control clock The terminal accesses the sixth clock signal; k is a positive integer.
  • the GOA unit further includes a function control module, the function control module accesses the first function control signal and the second function control signal, and is electrically connected to the first node, The second node and the scan drive signal at the current level are used to realize an open function and a close function of all scan drive signals of the GOA circuit.
  • the function control module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
  • the gate of the thirteenth transistor, the gate of the fourteenth transistor, and the source and gate of the fifteenth transistor are connected to the first function control signal, and the gate of the sixteenth transistor A pole is connected to the second function control signal, a source of the thirteenth transistor, a source of the fourteenth transistor, and a source of the sixteenth transistor are connected to the constant voltage low-level signal ,
  • the drain of the thirteenth transistor is electrically connected to the first node, the drain of the fourteenth transistor is electrically connected to the second node, the drain of the fifteenth transistor and all The drain of the sixteenth transistor is electrically connected to the current scan driving signal.
  • the GOA circuit includes a function opening phase and a function closing phase; wherein, in the function opening phase, the first function control signal is at a high level, and the second function control The signal is at a low level; during the shutdown function stage, the first function control signal is at a low level and the second function control signal is at a high level.
  • An embodiment of the present application further provides a GOA circuit, including: a multi-level cascaded GOA unit, each level of GOA unit includes: a positive and negative scanning module, an output module and a pull-down module;
  • the forward and reverse scanning modules are connected to the upper-level scanning drive signal, forward scanning signal, lower-level scanning drive signal, reverse scanning signal and constant voltage low-level signal, and are electrically connected to the first control clock terminal , A third control clock terminal, a first node and a second node, for outputting the forward scan signal to the first node, or for outputting the reverse scan signal to the first node, And output the constant voltage low-level signal to the second node under the potential control of the first node;
  • the output module is connected to the constant-voltage low-level signal and the constant-voltage high-level signal, and is electrically connected to the first node and the second control clock terminal, and is used to output a scan driving signal at the current level;
  • the pull-down module is connected to the constant voltage low level signal, the forward scan signal, the reverse scan signal and the constant voltage high level signal, and is electrically connected to the first control clock Terminal, the third control clock terminal, the first node and the current-level scan drive signal, used to pull down the potential of the first node and the potential of the current level scan drive signal to the constant voltage low power The potential of the flat signal;
  • the forward scan signal and the reverse scan signal are both DC power sources, and the potential of the forward scan signal is opposite to the potential of the reverse scan signal.
  • the forward and reverse scanning modules include: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the gate of the first transistor is electrically connected to the first control clock terminal, the source of the first transistor is connected to the forward scan signal, and the drain of the first transistor is electrically connected to the The source of the second transistor, the gate of the second transistor is connected to the scan drive signal of the previous stage, the drain of the second transistor is electrically connected to the first node, and the third transistor Is electrically connected to the third control clock terminal, the source of the third transistor is connected to the reverse scan signal, and the drain of the third transistor is electrically connected to the fourth transistor The source, the gate of the fourth transistor is connected to the next-level scan driving signal, the drain of the fourth transistor is electrically connected to the first node, and the gate of the fifth transistor is electrically Connected to the first node, the source of the fifth transistor is connected to the constant voltage low-level signal, and the drain of the fifth transistor is electrically connected to the second node.
  • the output module includes: a sixth transistor, a seventh transistor, and a first capacitor;
  • the gate of the sixth transistor is connected to the constant voltage high-level signal, the source of the sixth transistor is electrically connected to the first node, and the drain of the sixth transistor is electrically connected to the A gate of the seventh transistor, a source of the seventh transistor is electrically connected to the first control clock terminal, and a drain of the seventh transistor is electrically connected to the current scan driving signal, the One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the constant voltage low-level signal.
  • the pull-down module includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor;
  • the gate of the eighth transistor is connected to the forward scan signal, the source of the eighth transistor is electrically connected to the third control clock terminal, and the gate of the ninth transistor is connected to the reverse To the scan signal, the source of the ninth transistor is electrically connected to the first control clock terminal, and the drain of the eighth transistor and the drain of the ninth transistor are electrically connected to the tenth transistor Gate, the source of the tenth transistor is connected to the constant voltage high-level signal, the drain of the tenth transistor, the gate of the eleventh transistor, and the gate of the twelfth transistor
  • the electrode is electrically connected to the second node, the source of the eleventh transistor and the source of the twelfth transistor are connected to the constant voltage low-level signal, and the drain of the eleventh transistor Is electrically connected to the first node, the drain of the twelfth transistor is electrically connected to the current-level scan driving signal, and one end of the second capacitor is electrically connected to the second node, the The other end of the second capacitor is electrically connected to the
  • the GOA circuit receives a first master clock signal, a second master clock signal, a third master clock signal, and a fourth master clock signal, the first master clock signal, the first The second master clock signal, the third master clock signal, and the fourth master clock signal are sequentially time-sharing effective in the action period of the GOA circuit;
  • the second control clock terminal is connected to the first master clock signal, and the third control clock terminal is connected to the second A main clock signal, the first control clock terminal is connected to the fourth main clock signal;
  • the second control clock terminal is connected to the second master clock signal, and the third control clock terminal is connected to the third master clock Signal, the first control clock terminal is connected to the first master clock signal;
  • the second control clock terminal is connected to the third master clock signal, and the third control clock terminal is connected to the fourth master clock Signal, the first control clock terminal is connected to the second master clock signal;
  • the second control clock terminal is connected to the fourth master clock signal, and the third control clock terminal is connected to the first master clock Signal, the first control clock terminal is connected to the third master clock signal; k is a positive integer.
  • the GOA circuit receives the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal ,
  • the clock signal, the sixth clock signal, the seventh clock signal, and the eighth clock signal are sequentially time-sharing effective in the action period of the GOA circuit;
  • the second control clock terminal is connected to the first clock signal
  • the third control clock terminal is connected to the third clock signal, the first Controlling the clock terminal to access the seventh clock signal
  • the second control clock terminal is connected to the second clock signal
  • the third control clock terminal is connected to the fourth clock signal
  • the first control clock The terminal accesses the eighth clock signal
  • the second control clock terminal is connected to the third master clock signal, the third control clock terminal is connected to the fifth clock signal, and the first control The clock terminal accesses the first clock signal;
  • the second control clock terminal is connected to the fourth master clock signal
  • the third control clock terminal is connected to the sixth clock signal
  • the first control The clock terminal accesses the second clock signal
  • the second control clock terminal accesses the fifth clock signal
  • the third control clock terminal accesses the seventh clock signal
  • the first control clock The terminal accesses the third clock signal
  • the second control clock terminal accesses the sixth clock signal
  • the third control clock terminal accesses the eighth clock signal
  • the first control clock The terminal accesses the fourth clock signal
  • the second control clock terminal accesses the seventh clock signal
  • the third control clock terminal accesses the first clock signal
  • the first control clock The terminal accesses the fifth clock signal
  • the second control clock terminal accesses the eighth clock signal
  • the third control clock terminal accesses the second clock signal
  • the first control clock The terminal accesses the sixth clock signal; k is a positive integer.
  • the GOA unit further includes a function control module, the function control module accesses the first function control signal and the second function control signal, and is electrically connected to the first node, The second node and the scan drive signal at the current level are used to realize an open function and a close function of all scan drive signals of the GOA circuit.
  • the function control module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
  • the gate of the thirteenth transistor, the gate of the fourteenth transistor, and the source and gate of the fifteenth transistor are connected to the first function control signal, and the gate of the sixteenth transistor A pole is connected to the second function control signal, a source of the thirteenth transistor, a source of the fourteenth transistor, and a source of the sixteenth transistor are connected to the constant voltage low-level signal ,
  • the drain of the thirteenth transistor is electrically connected to the first node, the drain of the fourteenth transistor is electrically connected to the second node, the drain of the fifteenth transistor and all The drain of the sixteenth transistor is electrically connected to the current scan driving signal.
  • the GOA circuit includes a function opening phase and a function closing phase; wherein, in the function opening phase, the first function control signal is at a high level, and the second function control The signal is at a low level; during the shutdown function stage, the first function control signal is at a low level and the second function control signal is at a high level.
  • An embodiment of the present application further provides a display panel, which includes a GOA circuit.
  • the GOA circuit includes: a multi-stage cascaded GOA unit, and each stage of the GOA unit includes a forward and reverse scanning module, an output module, and a pull-down module;
  • the forward and reverse scanning modules are connected to the upper-level scanning drive signal, forward scanning signal, lower-level scanning drive signal, reverse scanning signal and constant voltage low-level signal, and are electrically connected to the first control clock terminal , A third control clock terminal, a first node and a second node, for outputting the forward scan signal to the first node, or for outputting the reverse scan signal to the first node, And output the constant voltage low-level signal to the second node under the potential control of the first node;
  • the output module is connected to the constant-voltage low-level signal and the constant-voltage high-level signal, and is electrically connected to the first node and the second control clock terminal, and is used to output a scan driving signal at the current level;
  • the pull-down module is connected to the constant voltage low level signal, the forward scan signal, the reverse scan signal and the constant voltage high level signal, and is electrically connected to the first control clock Terminal, the third control clock terminal, the first node and the current-level scan drive signal, used to pull down the potential of the first node and the potential of the current level scan drive signal to the constant voltage low power Flat signal potential.
  • the forward and reverse scanning modules include: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;
  • the gate of the first transistor is electrically connected to the first control clock terminal, the source of the first transistor is connected to the forward scan signal, and the drain of the first transistor is electrically connected to the The source of the second transistor, the gate of the second transistor is connected to the scan drive signal of the previous stage, the drain of the second transistor is electrically connected to the first node, and the third transistor Is electrically connected to the third control clock terminal, the source of the third transistor is connected to the reverse scan signal, and the drain of the third transistor is electrically connected to the fourth transistor The source, the gate of the fourth transistor is connected to the next-level scan driving signal, the drain of the fourth transistor is electrically connected to the first node, and the gate of the fifth transistor is electrically Connected to the first node, the source of the fifth transistor is connected to the constant voltage low-level signal, and the drain of the fifth transistor is electrically connected to the second node.
  • the output module includes: a sixth transistor, a seventh transistor, and a first capacitor;
  • the gate of the sixth transistor is connected to the constant voltage high-level signal, the source of the sixth transistor is electrically connected to the first node, and the drain of the sixth transistor is electrically connected to the A gate of the seventh transistor, a source of the seventh transistor is electrically connected to the first control clock terminal, and a drain of the seventh transistor is electrically connected to the current scan driving signal, the One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the constant voltage low-level signal.
  • the pull-down module includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor;
  • the gate of the eighth transistor is connected to the forward scan signal, the source of the eighth transistor is electrically connected to the third control clock terminal, and the gate of the ninth transistor is connected to the reverse To the scan signal, the source of the ninth transistor is electrically connected to the first control clock terminal, and the drain of the eighth transistor and the drain of the ninth transistor are electrically connected to the tenth transistor Gate, the source of the tenth transistor is connected to the constant voltage high-level signal, the drain of the tenth transistor, the gate of the eleventh transistor, and the gate of the twelfth transistor
  • the electrode is electrically connected to the second node, the source of the eleventh transistor and the source of the twelfth transistor are connected to the constant voltage low-level signal, and the drain of the eleventh transistor Is electrically connected to the first node, the drain of the twelfth transistor is electrically connected to the current-level scan driving signal, and one end of the second capacitor is electrically connected to the second node, the The other end of the second capacitor is electrically connected to the
  • the GOA circuit and the display panel provided by the embodiments of the present application can control the first node by adding the first control clock terminal and the third control clock terminal to the forward and reverse scanning modules, thereby reducing the leakage of the first node during operation Improve the reliability of the GOA circuit; in addition, in the embodiment of the present application, during the function opening phase, the first control clock terminal and the third control clock terminal are used to isolate the path between the forward scan signal/reverse scan signal and the first node, and high power The flat forward scan signal/reverse scan signal is driven, and at the same time, the first function control signal is used to control the path of the first node, which can connect the signal of the second control clock terminal to the uncontrollable node of the GOA circuit to avoid competition in the GOA circuit. path.
  • FIG. 1 is a schematic diagram of a first structure of a GOA circuit provided by an embodiment of this application;
  • FIG. 2 is a schematic diagram of a first type of circuit of a GOA unit in the GOA circuit shown in FIG. 1;
  • FIG. 3 is a timing diagram of the third-level GOA unit corresponding to the GOA circuit shown in FIG. 1;
  • Figure 4 is a schematic diagram of a second circuit of a GOA unit in the GOA circuit shown in Figure 1;
  • Figure 5 is a schematic diagram of a third circuit of a GOA unit in the GOA circuit shown in Figure 1;
  • Figure 6 is a schematic diagram of a second structure of a GOA circuit provided by an embodiment of the present application.
  • FIG. 7 is a timing diagram of the GOA unit corresponding to the GOA circuit shown in FIG. 6;
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the transistors used in all the embodiments of this application may be thin film transistors, field effect transistors or other devices with the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged of. In the embodiment of the present application, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called a source electrode, and the other electrode is called a drain electrode. According to the form in the drawing, the middle end of the switching transistor is a gate, the signal input end is a source, and the output end is a drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors, where the P-type transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type transistor is at The gate turns on when the gate is high, and turns off when the gate is low.
  • FIG. 1 is a schematic diagram of a first structure of a GOA circuit provided by an embodiment of the present application.
  • the GOA circuit 10 of the embodiment of the present application includes multi-level cascaded GOA units.
  • the nth stage GOA unit is used to output the nth stage scan driving signal to charge the corresponding nth scan line in the display area, so as to realize the normal display of the display panel.
  • the GOA circuit 10 of the embodiment of the present application includes a first GOA sub-circuit 11 formed by a cascade of odd-numbered GOA units and a second GOA sub-circuit 12 formed by a cascade of even-numbered GOA units.
  • the GOA circuit of the embodiment of the present application adopts the interlaced scanning driving mode, and the first GOA sub-circuit 11 and the second GOA sub-circuit 12 simultaneously output scan driving signals.
  • the GOA circuit 10 of the embodiment of the present application receives the first main clock signal CK1, the second main clock signal CK2, the third main clock signal CK3, and the fourth main clock signal CK4.
  • the first main clock signal CK1, the second main clock signal CK2, the third main clock signal CK3, and the fourth main clock signal CK4 are sequentially time-sharing effective in the action period of the GOA circuit 10.
  • the second control clock terminal CKb is connected to the first master clock signal CK1
  • the third control clock terminal CKc is connected to the second master clock signal CKc
  • the clock signal CK2 and the first control clock terminal CKa are connected to the fourth main clock signal CK4, where k is a positive integer.
  • the second control clock terminal CKb is connected to the first main clock signal CK1
  • the third control clock terminal CKc is The second main clock signal CK2 is input
  • the first control clock terminal CKa is connected to the fourth main clock signal CK4.
  • the second control clock terminal CKb is connected to the second master clock signal CK2, and the third control clock terminal CKc is connected to the third master clock signal CKc
  • the first control clock terminal CKa is connected to the first main clock signal CK1, where k is a positive integer.
  • the second control clock terminal CKb is connected to the second main clock signal CK2
  • the third control clock terminal CKc is connected to the third main clock signal CK3, and the first control clock
  • the terminal CKa is connected to the first main clock signal CK1.
  • the second control clock terminal CKb is connected to the third master clock signal CK3, and the third control clock terminal CKc is connected to the fourth master clock signal CKc
  • the first control clock terminal CKa is connected to the second main clock signal CK2, where k is a positive integer.
  • the second control clock terminal CKb is connected to the third main clock signal CK3
  • the third control clock terminal CKc is connected to the fourth main clock signal CK4, and the first control clock
  • the terminal CKa is connected to the second main clock signal CK2.
  • the second control clock terminal CKb is connected to the fourth master clock signal CK4, and the third control clock terminal CKc is connected to the first master
  • the clock signal CK1 and the first control clock terminal CKa are connected to the third main clock signal CK3, where k is a positive integer.
  • the second control clock terminal CKb is connected to the fourth main clock signal CK4
  • the third control clock terminal CKc is connected to the first main clock signal CK1
  • the first control clock The terminal CKa is connected to the third main clock signal CK3.
  • FIG. 2 is a first schematic circuit diagram of a GOA unit in the GOA circuit shown in FIG. 1.
  • the GOA unit includes a forward and reverse scanning module 101, an output module 102, and a pull-down module 103.
  • the forward and reverse scanning module 101 is connected to the upper level scanning drive signal G (n-2), the forward scanning signal U2D, the next level scanning drive signal G (n+2), the reverse scanning signal D2U, and the constant voltage is low
  • the level signal VGL is electrically connected to the first control clock terminal CKa, the third control clock terminal CKc, the first node Q(n) and the second node P(n), and is used to output the forward scan signal U2D to The first node Q(n), or for outputting the reverse scan signal D2U to the first node Q(n), and under the potential control of the first node Q(n), output the constant voltage low-level signal VGL to The second node P(n).
  • the output module 102 is connected to the constant voltage low-level signal VGL and the constant voltage high-level signal VGH, and is electrically connected to the first node Q(n) and the second control clock terminal CKb, and is used to output the current-level scan driver Signal G(n).
  • the pull-down module 103 is connected to a constant voltage low-level signal VGL, a forward scan signal U2D, a reverse scan signal D2U, and a constant-voltage high level signal VGH, and is electrically connected to the first control clock terminal CKa and the third control
  • the clock terminal CKc, the first node Q(n) and the current-level scan driving signal G(n) are used to pull down the potential of the first node Q(n) and the current-level scan driving signal G(n) to a constant voltage The potential of the low-level signal VGL.
  • the forward and reverse scanning module 101 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the gate of the first transistor T1 is electrically connected to the first control clock terminal CKa, the source of the first transistor T1 is connected to the forward scan signal U2D, and the drain of the first transistor T1 is electrically connected to the second transistor T2 Source, the gate of the second transistor T2 is connected to the previous scan drive signal G(n-2), the drain of the second transistor T2 is electrically connected to the first node Q(n), the third transistor T3 The gate is electrically connected to the third control clock terminal CKc, the source of the third transistor T3 is connected to the reverse scan signal D2U, the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4, the fourth transistor The gate of T4 is connected to the next-stage scan driving signal G(n+2), the drain of the fourth transistor T4 is electrically connected to the first node Q(n), and the gate of the fifth transistor T5 is electrically connected to the first At a node Q(n), the source of the fifth transistor T5 is connected to the constant voltage low-level signal V
  • the output module 102 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.
  • the gate of the sixth transistor T6 is connected to the constant voltage high-level signal VGH, the source of the sixth transistor T6 is electrically connected to the first node Q(n), and the drain of the sixth transistor T6 is electrically connected to the first
  • the gate of the seven transistors T7, the source of the seventh transistor T7 is electrically connected to the first control clock terminal CKa, the drain of the seventh transistor T7 is electrically connected to the current scan driving signal G(n), and the first capacitor C1
  • One end of is electrically connected to the first node Q(n), and the other end of the first capacitor C1 is electrically connected to the constant voltage low-level signal VGL.
  • the pull-down module 103 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a second capacitor C2.
  • the gate of the eighth transistor T8 is connected to the forward scan signal U2D, the source of the eighth transistor T8 is electrically connected to the third control clock terminal CKc, and the gate of the ninth transistor T9 is connected to the reverse scan signal D2U,
  • the source of the ninth transistor T9 is electrically connected to the first control clock terminal CKa, the drain of the eighth transistor T8 and the drain of the ninth transistor T9 are electrically connected to the gate of the tenth transistor T10, and the tenth transistor T10
  • the source is connected to the constant voltage high-level signal VGH, the drain of the tenth transistor T10, the gate of the eleventh transistor T11, and the gate of the twelfth transistor T12 are electrically connected to the second node P(n),
  • the source of the eleventh transistor T11 and the source of the twelfth transistor T12 are connected to the constant voltage low-level signal VGL, the drain of the eleventh transistor T11 is electrically connected to the first node Q(n), the twelf
  • FIG. 3 is a timing diagram of the third-level GOA unit corresponding to the GOA circuit shown in FIG.
  • the first main clock signal CK1, the second main clock signal CK2, the third main clock signal CK3 and the fourth main clock signal CK4 are clock signals with the same period and having a phase difference.
  • the second control clock terminal CKb is connected to the second main clock signal CK2
  • the third control clock terminal CKc is connected to the third main clock signal CK3
  • the first control clock terminal CKa is connected to Enter the first master clock signal CK1.
  • the forward scanning signal U2D is at a high level
  • the reverse scanning signal D2U is at a low level.
  • the first main clock signal CK1 is at a high level
  • the upper-level scan driving signal G1 is at a high level.
  • the first transistor T1 and the second transistor T2 are turned on, and the forward scan signal U2D
  • the first transistor T1 and the second transistor T2 are output to the first node Q(3), and the potential of the first node Q(3) is raised.
  • the fifth transistor T5 Since the potential of the first node Q(3) is raised, the fifth transistor T5 is turned on, and the constant voltage low level signal is output to the second node P(3), so that the eleventh transistor T11 and the twelfth transistor T12 are turned off .
  • the seventh transistor T7 since the potential of the first node Q(3) is raised, the seventh transistor T7 is turned on, the second master clock signal CK2 is at a low potential, and the second master clock signal CK2 is output through the seventh transistor T7.
  • the level scan drive signal G(3) is at a low potential.
  • the second main clock signal CK2 is at a high potential, and the second main clock signal CK2 is output via the seventh transistor T7, so the scan drive signal G(3) at this stage is at a high potential.
  • the third main clock signal CK3 is at a high potential, so that the tenth transistor T10 is turned on, the constant voltage high-level signal VGH is output to the second node P(3) through the tenth transistor T10, and the eleventh transistor T11 and the twelfth transistor T12 are turned on, the constant voltage low-level signal VGL is output to the first node Q(3) via the eleventh transistor T11, and the constant voltage low-level signal VGL is output to the current stage via the twelfth transistor T12
  • the drive signal G(3) at this time, the potential of the first node Q(3) and the potential of the scan drive signal G(3) of the current stage are pulled down to the potential of the constant voltage low-level signal VGL.
  • the forward scan signal U2D is low and the reverse scan signal D2U is high.
  • the third main clock signal CK3 is at a high level, and the next-stage scan driving signal G5 is at a high level.
  • the third transistor T3 and the fourth transistor T4 are turned on, and the reverse scan signal D2U passes
  • the third transistor T3 and the fourth transistor T4 are output to the first node Q(3), and the potential of the first node Q(3) is raised.
  • the fifth transistor T5 Since the potential of the first node Q(3) is raised, the fifth transistor T5 is turned on, and the constant voltage low level signal is output to the second node P(3), so that the eleventh transistor T11 and the twelfth transistor T12 are turned off .
  • the seventh transistor T7 since the potential of the first node Q(3) is raised, the seventh transistor T7 is turned on, the second master clock signal CK2 is at a low potential, and the second master clock signal CK2 is output through the seventh transistor T7.
  • the level scan drive signal G(3) is at a low potential.
  • the second main clock signal CK2 is at a high potential, and the second main clock signal CK2 is output via the seventh transistor T7, so the scan drive signal G(3) at this stage is at a high potential.
  • the first master clock signal CK1 is at a high potential, so that the tenth transistor T10 is turned on, the constant voltage high-level signal VGH is output to the second node P(3) via the tenth transistor T10, and the eleventh transistor T11 and the twelfth transistor T12 are turned on, the constant voltage low-level signal VGL is output to the first node Q(3) via the eleventh transistor T11, and the constant voltage low-level signal VGL is output to the current stage via the twelfth transistor T12
  • the drive signal G(3) at this time, the potential of the first node Q(3) and the potential of the scan drive signal G(3) of the current stage are pulled down to the potential of the constant voltage low-level signal VGL.
  • the GOA circuit 10 of the embodiment of the present application controls the first node Q(n) by adding the first control clock terminal CKa and the third control clock terminal CKc to the forward and reverse scanning modules 101, thereby reducing the number of A node Q(n) leaks during operation, thereby improving the reliability of the GOA circuit 10.
  • FIG. 4 is a schematic diagram of a second circuit of a GOA unit in the GOA circuit shown in FIG. 1.
  • the GOA unit shown in FIG. 4 further includes a function control module 104, which is connected to the first function control signal Gas1 and The second function control signal Gas2 is electrically connected to the first node Q(n), the second node P(n), and the current scan drive signal G(n), which is used to enable all scan drive signals of the GOA circuit 10 to turn on Function and shutdown function.
  • the function control module 104 includes: a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixteenth transistor T16.
  • the gate of the thirteenth transistor T13, the gate of the fourteenth transistor T14, and the source and gate of the fifteenth transistor T15 are connected to the first function control signal Gas1, and the gate of the sixteenth transistor T16 is connected to the second The function control signal Gas2, the source of the thirteenth transistor T13, the source of the fourteenth transistor T14, and the source of the sixteenth transistor T16 are connected to the constant voltage low-level signal VGL, and the drain of the thirteenth transistor T13 Is connected to the first node Q(n), the drain of the fourteenth transistor T14 is electrically connected to the second node P(n), the drain of the fifteenth transistor T15 and the drain of the sixteenth transistor T16 Connected to the scan drive signal G(n) of this stage.
  • the GOA circuit 10 includes a function opening phase and a function closing phase.
  • the function opening phase the first function control signal Gas1 is high level and the second function control signal Gas2 is low level; in the function closing phase, the first function control signal Gas1 is low level and the second function control signal Gas2 is High level.
  • the GOA circuit 10 of the embodiment of the present application isolates the forward scan signal U2D/reverse scan signal D2U from the first node Q (through the first control clock terminal CKa and the third control clock terminal CKc during the function opening phase n)
  • the path is driven by the high-level forward scan signal U2D/reverse scan signal D2U, and at the same time, the first function control signal Gas1 controls the path of the first node Q(n), and the second control clock terminal
  • the signal of CKb is connected to the uncontrollable node of the GOA circuit 10 to prevent the GOA circuit 10 from competing for the path.
  • FIG. 5 is a schematic diagram of a third circuit of a GOA unit in the GOA circuit shown in FIG. 1.
  • the difference between the GOA unit shown in FIG. 5 and the GOA unit shown in FIG. 4 is that the drain of the thirteenth transistor T13 shown in FIG. 4 is electrically connected to the source of the sixth transistor T6, as shown in FIG. 5
  • the drain of the thirteenth transistor T13 is electrically connected to the drain of the sixth transistor T6. Since the gate of the sixth transistor T6 is connected to a constant voltage high-level signal, the working principle of the GOA unit shown in FIG. 5 and the GOA unit shown in FIG. 4 are the same, and will not be repeated here.
  • FIG. 6 is a second schematic structural diagram of a GOA circuit provided by an embodiment of the present application.
  • the difference between the GOA circuit 20 shown in FIG. 6 and the GOA circuit 10 shown in FIG. 1 is that the clock signals connected to the first control clock terminal CKa, the second control clock terminal CKb, and the third control clock terminal CKc are different.
  • the GOA circuit 20 of the embodiment of the present application receives the first clock signal CK11, the second clock signal CK12, the third clock signal CK13, the fourth clock signal CK14, the fifth clock signal CK15, and the sixth clock Signal CK16, seventh clock signal CK17 and eighth clock signal CK18, first clock signal CK11, second clock signal CK12, third clock signal CK13, fourth clock signal CK14, fifth clock signal CK15, the sixth-time clock signal CK16, the seventh-time clock signal CK17, and the eighth-time clock signal CK18 are sequentially time-sharing effective in the action cycle of the GOA circuit 20.
  • the second control clock terminal CKb accesses the first clock signal CK11
  • the third control clock terminal CKc accesses the third clock signal CK13
  • the first control clock The terminal CKa accesses the seventh clock signal CK17, where k is a positive integer.
  • the second control clock terminal CKb accesses the first clock signal CK11
  • the third control clock terminal CKc accesses the third clock signal CK13
  • the terminal CKa is connected to the seventh clock signal CK17.
  • the second control clock terminal CKb is connected to the second clock signal CK12
  • the third control clock terminal CKc is connected to the fourth clock signal CK14
  • the first control clock The terminal CKa accesses the eighth clock signal CK18, where k is a positive integer.
  • the second control clock terminal CKb accesses the second clock signal CK12
  • the third control clock terminal CKc accesses the fourth clock signal CK14
  • the terminal CKa is connected to the eighth clock signal CK18.
  • the second control clock terminal CKb is connected to the third master clock signal
  • the third control clock terminal CKc is connected to the fifth clock signal CK15
  • the first control clock The terminal CKa is connected to the first clock signal CK11, where k is a positive integer.
  • the second control clock terminal CKb is connected to the third master clock signal
  • the third control clock terminal CKc is connected to the fifth clock signal CK15
  • the first control clock terminal CKa is connected to the first Secondary clock signal CK11.
  • the second control clock terminal CKb is connected to the fourth master clock signal
  • the third control clock terminal CKc is connected to the sixth clock signal CK16
  • the first control clock The terminal CKa is connected to the second clock signal CK12, where k is a positive integer.
  • the second control clock terminal CKb is connected to the fourth main clock signal
  • the third control clock terminal CKc is connected to the sixth clock signal CK16
  • the first control clock terminal CKa is connected to the second Secondary clock signal CK12.
  • the second control clock terminal CKb accesses the fifth clock signal CK15
  • the third control clock terminal CKc accesses the seventh clock signal CK17
  • the terminal CKa is connected to the third clock signal CK13, where k is a positive integer.
  • the second control clock terminal CKb is connected to the fifth clock signal CK15
  • the third control clock terminal CKc is connected to the seventh clock signal CK17
  • the first control clock terminal CKa is connected to the third Secondary clock signal CK13.
  • the second control clock terminal CKb accesses the sixth clock signal CK16
  • the third control clock terminal CKc accesses the eighth clock signal CK18
  • the terminal CKa is connected to the fourth clock signal CK14, where k is a positive integer.
  • the second control clock terminal CKb is connected to the sixth clock signal CK16
  • the third control clock terminal CKc is connected to the eighth clock signal CK18
  • the first control clock terminal CKa is connected to the fourth Secondary clock signal CK14.
  • the second control clock terminal CKb accesses the seventh clock signal CK17
  • the third control clock terminal CKc accesses the first clock signal CK11
  • the first control clock The terminal CKa is connected to the fifth clock signal CK15, where k is a positive integer.
  • the second control clock terminal CKb is connected to the seventh clock signal CK17
  • the third control clock terminal CKc is connected to the first clock signal CK11
  • the first control clock terminal CKa is connected to the fifth Secondary clock signal CK15.
  • the second control clock terminal CKb accesses the eighth clock signal CK18
  • the third control clock terminal CKc accesses the second clock signal CK12
  • the first control clock The terminal CKa accesses the sixth clock signal CK16, where k is a positive integer.
  • the second control clock terminal CKb is connected to the eighth clock signal CK18
  • the third control clock terminal CKc is connected to the second clock signal CK12
  • the first control clock terminal CKa is connected to the sixth Secondary clock signal CK16.
  • circuit schematic diagram of the GOA unit in the GOA circuit 20 shown in FIG. 6 is the same as the circuit schematic diagram of the GOA unit in the GOA circuit 10 shown in FIG. 1.
  • FIGS. 2, 4, and 5. The description will not be repeated here.
  • the following uses the third-level GOA unit as an example to describe the working principle of the third-level GOA unit corresponding to the GOA circuit shown in FIG. 6.
  • FIG. 7 is a timing diagram of the third-level GOA unit corresponding to the GOA circuit shown in FIG. 6.
  • the eighth clock signal CK18 is a clock signal with the same period and a phase difference.
  • the second control clock terminal CKb is connected to the third clock signal CK13
  • the third control clock terminal CKc is connected to the fifth clock signal CK15
  • the first control clock terminal CKa is connected to Enter the first clock signal CK11.
  • the forward scanning signal U2D is at a high level, and the reverse scanning signal D2U is at a low level.
  • the first clock signal CK11 is at a high level
  • the previous-stage scan drive signal G1 is at a high level.
  • the first transistor T1 and the second transistor T2 are turned on, and the forward scan signal U2D is
  • the first transistor T1 and the second transistor T2 are output to the first node Q(3), and the potential of the first node Q(3) is raised.
  • the fifth transistor T5 Since the potential of the first node Q(3) is raised, the fifth transistor T5 is turned on, and the constant voltage low level signal is output to the second node P(3), so that the eleventh transistor T11 and the twelfth transistor T12 are turned off .
  • the seventh transistor T7 since the potential of the first node Q(3) is raised, the seventh transistor T7 is turned on, the third clock signal CK13 is at a low potential, and the third clock signal CK13 is output through the seventh transistor T7.
  • the level scan drive signal G(3) is at a low potential.
  • the potential of the first node Q(3) is still high, and the potential of the second node P(3) is still low.
  • the third-time clock signal CK13 is at a high potential, and the third-time clock signal CK13 is output through the seventh transistor T7, so the scan drive signal G(3) at this stage is at a high potential.
  • the fifth clock signal CK15 is at a high potential, so that the tenth transistor T10 is turned on, the constant voltage high-level signal VGH is output to the second node P(3) via the tenth transistor T10, and the eleventh transistor T11 and the twelfth transistor T12 are turned on, the constant voltage low-level signal VGL is output to the first node Q(3) via the eleventh transistor T11, and the constant voltage low-level signal VGL is output to the current stage via the twelfth transistor T12
  • the drive signal G(3) at this time, the potential of the first node Q(3) and the potential of the scan drive signal G(3) of the current stage are pulled down to the potential of the constant voltage low-level signal VGL.
  • the forward scan signal is low and the reverse scan signal is high.
  • the fifth clock signal CK15 is at a high level, and the next-stage scan driving signal G5 is at a high level.
  • the third transistor T3 and the fourth transistor T4 are turned on, and the reverse scan signal D2U passes The third transistor T3 and the fourth transistor T4 are output to the first node Q(3), and the potential of the first node Q(3) is raised.
  • the fifth transistor T5 Since the potential of the first node Q(3) is raised, the fifth transistor T5 is turned on, and the constant voltage low level signal is output to the second node P(3), so that the eleventh transistor T11 and the twelfth transistor T12 are turned off .
  • the seventh transistor T7 since the potential of the first node Q(3) is raised, the seventh transistor T7 is turned on, the third clock signal CK13 is at a low potential, and the third clock signal CK13 is output through the seventh transistor T7.
  • the level scan drive signal G(3) is at a low potential.
  • the potential of the first node Q(3) is still high, and the potential of the second node P(3) is still low.
  • the third-time clock signal CK13 is at a high potential, and the third-time clock signal CK13 is output through the seventh transistor T7, so the scan drive signal G(3) at this stage is at a high potential.
  • the first clock signal CK11 is at a high potential, so that the tenth transistor T10 is turned on, and the constant voltage high-level signal VGH is output to the second node P(3) via the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 are turned on, the constant voltage low-level signal VGL is output to the first node Q(3) via the eleventh transistor T11, and the constant voltage low-level signal VGL is output to the current stage via the twelfth transistor T12
  • the drive signal G(3) at this time, the potential of the first node Q(3) and the potential of the scan drive signal G(3) of the current stage are pulled down to the potential of the constant voltage low-level signal VGL.
  • FIG. 8 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel includes a display area 100 and a GOA circuit 200 integrated on the edge of the display area 100; wherein, the structure and principle of the GOA circuit 200 is similar to the GOA circuit described above, and will not be repeated here.

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Abstract

一种GOA电路（10）及显示面板，通过在正反扫描模块（101）中增加第一控制时钟端（CKa）和第三控制时钟端（CKc）以控制第一节点（Q(n)），从而可以减小第一节点（Q(n)）在工作期间漏电，进而提高GOA电路（10）的可靠性。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
GOA( 英文全称：Gate Driver on Array ，中文全称：集成栅极驱动电路)技术将栅极驱动电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
现有的GOA电路存在漏电风险，可靠性较差。
 技术问题
本申请实施例的目的在于提供一种GOA电路及显示面板，能够解决现有的GOA电路存在漏电风险，可靠性较差的技术问题。
 技术解决方案
本申请实施例提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：正反扫描模块、输出模块以及下拉模块；
所述正反扫描模块，接入上一级扫描驱动信号、正向扫描信号、下一级扫描驱动信号、反向扫描信号以及恒压低电平信号，并电性连接于第一控制时钟端、第三控制时钟端、第一节点以及第二节点，用于将所述正向扫描信号输出至所述第一节点，或用于将所述反向扫描信号输出至所述第一节点，并在所述第一节点的电位控制下将所述恒压低电平信号输出至所述第二节点；
所述输出模块，接入所述恒压低电平信号以及恒压高电平信号，并电性连接于所述第一节点以及第二控制时钟端，用于输出本级扫描驱动信号；
所述下拉模块，接入所述恒压低电平信号、所述正向扫描信号、所述反向扫描信号以及所述恒压高电平信号，并电性连接于所述第一控制时钟端、第三控制时钟端、所述第一节点以及所述本级扫描驱动信号，用于将所述第一节点的电位以及所述本级扫描驱动信号的电位下拉至所述恒压低电平信号的电位；
其中，所述正向扫描信号以及所述反向扫描信号均为直流电源，且所述正向扫描信号的电位与所述反向扫描信号的电位相反；
所述正反扫描模块包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
所述第一晶体管的栅极电性连接于所述第一控制时钟端，所述第一晶体管的源极接入所述正向扫描信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极，所述第二晶体管的栅极接入所述上一级扫描驱动信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的栅极电性连接于所述第三控制时钟端，所述第三晶体管的源极接入所述反向扫描信号，所述第三晶体管的漏极电性连接于所述第四晶体管的源极，所述第四晶体管的栅极接入所述下一级扫描驱动信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极接入所述恒压低电平信号，所述第五晶体管的漏极电性连接于所述第二节点；
所述输出模块包括：第六晶体管、第七晶体管以及第一电容；
所述第六晶体管的栅极接入所述恒压高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第七晶体管的栅极，所述第七晶体管的源极电性连接于所述第一控制时钟端，所述第七晶体管的漏极电性连接于所述本级扫描驱动信号，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
在本申请所述的GOA电路中，所述下拉模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第二电容；
所述第八晶体管的栅极接入所述正向扫描信号，所述第八晶体管的源极电性连接于所述第三控制时钟端，所述第九晶体管的栅极接入所述反向扫描信号，所述第九晶体管的源极电性连接于所述第一控制时钟端，所述第八晶体管的漏极、所述第九晶体管的漏极电性连接于所述第十晶体管的栅极，所述第十晶体管的源极接入所述恒压高电平信号，所述第十晶体管的漏极、所述第十一晶体管的栅极、所述第十二晶体管的栅极电性连接于所述第二节点，所述第十一晶体管的源极以及所述第十二晶体管的源极接入所述恒压低电平信号，所述第十一晶体管的漏极电性连接于所述第一节点，所述第十二晶体管的漏极电性连接于所述本级扫描驱动信号，所述第二电容的一端电性连接于所述第二节点，所述第二电容的另一端电性连接于所述恒压低电平信号。
在本申请所述的GOA电路中，所述GOA电路接收第一主时钟信号、第二主时钟信号、第三主时钟信号以及第四主时钟信号，所述第一主时钟信号、所述第二主时钟信号、所述第三主时钟信号以及所述第四主时钟信号在所述GOA电路的作用周期依次分时有效；
其中，在第1+8k级GOA单元和第2+8k级GOA单元中，所述第二控制时钟端接入所述第一主时钟信号，所述第三控制时钟端接入所述第二主时钟信号，所述第一控制时钟端接入所述第四主时钟信号；
在第3+8k级GOA单元和第4+8k级GOA单元中，所述第二控制时钟端接入所述第二主时钟信号，所述第三控制时钟端接入所述第三主时钟信号，所述第一控制时钟端接入所述第一主时钟信号；
在第5+8k级GOA单元和第6+8k级GOA单元中，所述第二控制时钟端接入所述第三主时钟信号，所述第三控制时钟端接入所述第四主时钟信号，所述第一控制时钟端接入所述第二主时钟信号；
在第7+8k级GOA单元和第8+8k级GOA单元中，所述第二控制时钟端接入所述第四主时钟信号，所述第三控制时钟端接入所述第一主时钟信号，所述第一控制时钟端接入所述第三主时钟信号；k为正整数。
在本申请所述的GOA电路中，所述GOA电路接收第一次时钟信号、第二次时钟信号、第三次时钟信号、第四次时钟信号、第五次时钟信号、第六次时钟信号、第七次时钟信号以及第八次时钟信号，所述第一次时钟信号、所述第二次时钟信号、所述第三次时钟信号、所述第四次时钟信号、所述第五次时钟信号、所述第六次时钟信号、所述第七次时钟信号以及所述第八次时钟信号在所述GOA电路的作用周期依次分时有效；
其中，在第1+8k级GOA单元中，所述第二控制时钟端接入所述第一次时钟信号，所述第三控制时钟端接入所述第三次时钟信号，所述第一控制时钟端接入所述第七次时钟信号；
在第2+8k级GOA单元中，所述第二控制时钟端接入所述第二次时钟信号，所述第三控制时钟端接入所述第四次时钟信号，所述第一控制时钟端接入所述第八次时钟信号；
在第3+8k级GOA单元中，所述第二控制时钟端接入所述第三次主时钟信号，所述第三控制时钟端接入所述第五次时钟信号，所述第一控制时钟端接入所述第一次时钟信号；
在第4+8k级GOA单元中，所述第二控制时钟端接入所述第四次主时钟信号，所述第三控制时钟端接入所述第六次时钟信号，所述第一控制时钟端接入所述第二次时钟信号；
在第5+8k级GOA单元中，所述第二控制时钟端接入所述第五次时钟信号，所述第三控制时钟端接入所述第七次时钟信号，所述第一控制时钟端接入所述第三次时钟信号；
在第6+8k级GOA单元中，所述第二控制时钟端接入所述第六次时钟信号，所述第三控制时钟端接入所述第八次时钟信号，所述第一控制时钟端接入所述第四次时钟信号；
在第7+8k级GOA单元中，所述第二控制时钟端接入所述第七次时钟信号，所述第三控制时钟端接入所述第一次时钟信号，所述第一控制时钟端接入所述第五次时钟信号；
在第8+8k级GOA单元中，所述第二控制时钟端接入所述第八次时钟信号，所述第三控制时钟端接入所述第二次时钟信号，所述第一控制时钟端接入所述第六次时钟信号；k为正整数。
在本申请所述的GOA电路中，所述GOA单元还包括功能控制模块，所述功能控制模块接入第一功能控制信号和第二功能控制信号，并电性连接于所述第一节点、所述第二节点以及所述本级扫描驱动信号，用于实现所述GOA电路的所有扫描驱动信号打开功能以及关闭功能。
在本申请所述的GOA电路中，所述功能控制模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
所述第十三晶体管的栅极、所述第十四晶体管的栅极以及所述第十五晶体管的源极、栅极接入所述第一功能控制信号，所述第十六晶体管的栅极接入所述第二功能控制信号，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十六晶体管的源极接入所述恒压低电平信号，所述第十三晶体管的漏极电性连接于所述第一节点，所述第十四晶体管的漏极电性连接于所述第二节点，所述第十五晶体管的漏极以及所述第十六晶体管的漏极电性连接于所述本级扫描驱动信号。
在本申请所述的GOA电路中，所述GOA电路包括打开功能阶段以及关闭功能阶段；其中，在所述打开功能阶段，所述第一功能控制信号为高电平，所述第二功能控制信号为低电平；在所述关闭功能阶段，所述第一功能控制信号为低电平，所述第二功能控制信号为高电平。
本申请实施例还提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括：正反扫描模块、输出模块以及下拉模块；
所述正反扫描模块，接入上一级扫描驱动信号、正向扫描信号、下一级扫描驱动信号、反向扫描信号以及恒压低电平信号，并电性连接于第一控制时钟端、第三控制时钟端、第一节点以及第二节点，用于将所述正向扫描信号输出至所述第一节点，或用于将所述反向扫描信号输出至所述第一节点，并在所述第一节点的电位控制下将所述恒压低电平信号输出至所述第二节点；
所述输出模块，接入所述恒压低电平信号以及恒压高电平信号，并电性连接于所述第一节点以及第二控制时钟端，用于输出本级扫描驱动信号；
所述下拉模块，接入所述恒压低电平信号、所述正向扫描信号、所述反向扫描信号以及所述恒压高电平信号，并电性连接于所述第一控制时钟端、第三控制时钟端、所述第一节点以及所述本级扫描驱动信号，用于将所述第一节点的电位以及所述本级扫描驱动信号的电位下拉至所述恒压低电平信号的电位；
其中，所述正向扫描信号以及所述反向扫描信号均为直流电源，且所述正向扫描信号的电位与所述反向扫描信号的电位相反。
在本申请所述的GOA电路中，所述正反扫描模块包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
所述第一晶体管的栅极电性连接于所述第一控制时钟端，所述第一晶体管的源极接入所述正向扫描信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极，所述第二晶体管的栅极接入所述上一级扫描驱动信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的栅极电性连接于所述第三控制时钟端，所述第三晶体管的源极接入所述反向扫描信号，所述第三晶体管的漏极电性连接于所述第四晶体管的源极，所述第四晶体管的栅极接入所述下一级扫描驱动信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极接入所述恒压低电平信号，所述第五晶体管的漏极电性连接于所述第二节点。
在本申请所述的GOA电路中，所述输出模块包括：第六晶体管、第七晶体管以及第一电容；
所述第六晶体管的栅极接入所述恒压高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第七晶体管的栅极，所述第七晶体管的源极电性连接于所述第一控制时钟端，所述第七晶体管的漏极电性连接于所述本级扫描驱动信号，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
在本申请所述的GOA电路中，所述下拉模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第二电容；
所述第八晶体管的栅极接入所述正向扫描信号，所述第八晶体管的源极电性连接于所述第三控制时钟端，所述第九晶体管的栅极接入所述反向扫描信号，所述第九晶体管的源极电性连接于所述第一控制时钟端，所述第八晶体管的漏极、所述第九晶体管的漏极电性连接于所述第十晶体管的栅极，所述第十晶体管的源极接入所述恒压高电平信号，所述第十晶体管的漏极、所述第十一晶体管的栅极、所述第十二晶体管的栅极电性连接于所述第二节点，所述第十一晶体管的源极以及所述第十二晶体管的源极接入所述恒压低电平信号，所述第十一晶体管的漏极电性连接于所述第一节点，所述第十二晶体管的漏极电性连接于所述本级扫描驱动信号，所述第二电容的一端电性连接于所述第二节点，所述第二电容的另一端电性连接于所述恒压低电平信号。
在本申请所述的GOA电路中，所述GOA电路接收第一主时钟信号、第二主时钟信号、第三主时钟信号以及第四主时钟信号，所述第一主时钟信号、所述第二主时钟信号、所述第三主时钟信号以及所述第四主时钟信号在所述GOA电路的作用周期依次分时有效；
其中，在第1+8k级GOA单元和第2+8k级GOA单元中，所述第二控制时钟端接入所述第一主时钟信号，所述第三控制时钟端接入所述第二主时钟信号，所述第一控制时钟端接入所述第四主时钟信号；
在第3+8k级GOA单元和第4+8k级GOA单元中，所述第二控制时钟端接入所述第二主时钟信号，所述第三控制时钟端接入所述第三主时钟信号，所述第一控制时钟端接入所述第一主时钟信号；
在第5+8k级GOA单元和第6+8k级GOA单元中，所述第二控制时钟端接入所述第三主时钟信号，所述第三控制时钟端接入所述第四主时钟信号，所述第一控制时钟端接入所述第二主时钟信号；
在第7+8k级GOA单元和第8+8k级GOA单元中，所述第二控制时钟端接入所述第四主时钟信号，所述第三控制时钟端接入所述第一主时钟信号，所述第一控制时钟端接入所述第三主时钟信号；k为正整数。
在本申请所述的GOA电路中，所述GOA电路接收第一次时钟信号、第二次时钟信号、第三次时钟信号、第四次时钟信号、第五次时钟信号、第六次时钟信号、第七次时钟信号以及第八次时钟信号，所述第一次时钟信号、所述第二次时钟信号、所述第三次时钟信号、所述第四次时钟信号、所述第五次时钟信号、所述第六次时钟信号、所述第七次时钟信号以及所述第八次时钟信号在所述GOA电路的作用周期依次分时有效；
其中，在第1+8k级GOA单元中，所述第二控制时钟端接入所述第一次时钟信号，所述第三控制时钟端接入所述第三次时钟信号，所述第一控制时钟端接入所述第七次时钟信号；
在第2+8k级GOA单元中，所述第二控制时钟端接入所述第二次时钟信号，所述第三控制时钟端接入所述第四次时钟信号，所述第一控制时钟端接入所述第八次时钟信号；
在第3+8k级GOA单元中，所述第二控制时钟端接入所述第三次主时钟信号，所述第三控制时钟端接入所述第五次时钟信号，所述第一控制时钟端接入所述第一次时钟信号；
在第4+8k级GOA单元中，所述第二控制时钟端接入所述第四次主时钟信号，所述第三控制时钟端接入所述第六次时钟信号，所述第一控制时钟端接入所述第二次时钟信号；
在第5+8k级GOA单元中，所述第二控制时钟端接入所述第五次时钟信号，所述第三控制时钟端接入所述第七次时钟信号，所述第一控制时钟端接入所述第三次时钟信号；
在第6+8k级GOA单元中，所述第二控制时钟端接入所述第六次时钟信号，所述第三控制时钟端接入所述第八次时钟信号，所述第一控制时钟端接入所述第四次时钟信号；
在第7+8k级GOA单元中，所述第二控制时钟端接入所述第七次时钟信号，所述第三控制时钟端接入所述第一次时钟信号，所述第一控制时钟端接入所述第五次时钟信号；
在第8+8k级GOA单元中，所述第二控制时钟端接入所述第八次时钟信号，所述第三控制时钟端接入所述第二次时钟信号，所述第一控制时钟端接入所述第六次时钟信号；k为正整数。
在本申请所述的GOA电路中，所述GOA单元还包括功能控制模块，所述功能控制模块接入第一功能控制信号和第二功能控制信号，并电性连接于所述第一节点、所述第二节点以及所述本级扫描驱动信号，用于实现所述GOA电路的所有扫描驱动信号打开功能以及关闭功能。
在本申请所述的GOA电路中，所述功能控制模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
所述第十三晶体管的栅极、所述第十四晶体管的栅极以及所述第十五晶体管的源极、栅极接入所述第一功能控制信号，所述第十六晶体管的栅极接入所述第二功能控制信号，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十六晶体管的源极接入所述恒压低电平信号，所述第十三晶体管的漏极电性连接于所述第一节点，所述第十四晶体管的漏极电性连接于所述第二节点，所述第十五晶体管的漏极以及所述第十六晶体管的漏极电性连接于所述本级扫描驱动信号。
在本申请所述的GOA电路中，所述GOA电路包括打开功能阶段以及关闭功能阶段；其中，在所述打开功能阶段，所述第一功能控制信号为高电平，所述第二功能控制信号为低电平；在所述关闭功能阶段，所述第一功能控制信号为低电平，所述第二功能控制信号为高电平。
本申请实施例还提供一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：正反扫描模块、输出模块以及下拉模块；
所述正反扫描模块，接入上一级扫描驱动信号、正向扫描信号、下一级扫描驱动信号、反向扫描信号以及恒压低电平信号，并电性连接于第一控制时钟端、第三控制时钟端、第一节点以及第二节点，用于将所述正向扫描信号输出至所述第一节点，或用于将所述反向扫描信号输出至所述第一节点，并在所述第一节点的电位控制下将所述恒压低电平信号输出至所述第二节点；
所述输出模块，接入所述恒压低电平信号以及恒压高电平信号，并电性连接于所述第一节点以及第二控制时钟端，用于输出本级扫描驱动信号；
所述下拉模块，接入所述恒压低电平信号、所述正向扫描信号、所述反向扫描信号以及所述恒压高电平信号，并电性连接于所述第一控制时钟端、第三控制时钟端、所述第一节点以及所述本级扫描驱动信号，用于将所述第一节点的电位以及所述本级扫描驱动信号的电位下拉至所述恒压低电平信号的电位。
在本申请所述的显示面板中，所述正反扫描模块包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
所述第一晶体管的栅极电性连接于所述第一控制时钟端，所述第一晶体管的源极接入所述正向扫描信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极，所述第二晶体管的栅极接入所述上一级扫描驱动信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的栅极电性连接于所述第三控制时钟端，所述第三晶体管的源极接入所述反向扫描信号，所述第三晶体管的漏极电性连接于所述第四晶体管的源极，所述第四晶体管的栅极接入所述下一级扫描驱动信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极接入所述恒压低电平信号，所述第五晶体管的漏极电性连接于所述第二节点。
在本申请所述的显示面板中，所述输出模块包括：第六晶体管、第七晶体管以及第一电容；
所述第六晶体管的栅极接入所述恒压高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第七晶体管的栅极，所述第七晶体管的源极电性连接于所述第一控制时钟端，所述第七晶体管的漏极电性连接于所述本级扫描驱动信号，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
在本申请所述的显示面板中，所述下拉模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第二电容；
所述第八晶体管的栅极接入所述正向扫描信号，所述第八晶体管的源极电性连接于所述第三控制时钟端，所述第九晶体管的栅极接入所述反向扫描信号，所述第九晶体管的源极电性连接于所述第一控制时钟端，所述第八晶体管的漏极、所述第九晶体管的漏极电性连接于所述第十晶体管的栅极，所述第十晶体管的源极接入所述恒压高电平信号，所述第十晶体管的漏极、所述第十一晶体管的栅极、所述第十二晶体管的栅极电性连接于所述第二节点，所述第十一晶体管的源极以及所述第十二晶体管的源极接入所述恒压低电平信号，所述第十一晶体管的漏极电性连接于所述第一节点，所述第十二晶体管的漏极电性连接于所述本级扫描驱动信号，所述第二电容的一端电性连接于所述第二节点，所述第二电容的另一端电性连接于所述恒压低电平信号。
 有益效果
本申请实施例提供的GOA电路及显示面板，通过在正反扫描模块中增加第一控制时钟端和第三控制时钟端以控制第一节点，从而可以减小第一节点在工作期间漏电，进而提高GOA电路的可靠性；另外，本申请实施例在打开功能阶段，通过第一控制时钟端和第三控制时钟端隔绝正向扫描信号/反向扫描信号与第一节点的通路，采用高电平的正向扫描信号/反向扫描信号进行驱动，同时通过第一功能控制信号控制第一节点的通路，可以将第二控制时钟端的信号连通到GOA电路的不可控节点，避免GOA电路出现竞争通路。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA电路的第一种结构示意图；
图2为图1所示的GOA电路中一GOA单元的第一种电路示意图；
图3为图1所示的GOA电路对应的第3级GOA单元的时序示意图；
图4为图1所示的GOA电路中一GOA单元的第二种电路示意图;
图5为图1所示的GOA电路中一GOA单元的第三种电路示意图;
图6为本申请实施例提供的GOA电路的第二种结构示意图;
图7为图6所示的GOA电路对应的第3级GOA单元的时序示意图;
图8为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参阅图1，图1为本申请实施例提供的GOA电路的第一种结构示意图。如图1所示，本申请实施例的GOA电路10包括多级级联的GOA单元。其中，第n级GOA单元用于输出第n级扫描驱动信号以对显示区域中对应的第n条扫描线进行充电，从而实现显示面板的正常显示。
具体来说，本申请实施例的GOA电路10包括奇数级GOA单元级联形成的第一GOA子电路11和偶数级GOA单元级联形成的第二GOA子电路12。本申请实施例的GOA电路采用隔行扫描的驱动方式，第一GOA子电路11和第二GOA子电路12同时输出扫描驱动信号。
其中，本申请实施例的GOA电路10接收第一主时钟信号CK1、第二主时钟信号CK2、第三主时钟信号CK3以及第四主时钟信号CK4。第一主时钟信号CK1、第二主时钟信号CK2、第三主时钟信号CK3以及第四主时钟信号CK4在GOA电路10的作用周期依次分时有效。
在一些实施例中，在第1+8k级GOA单元和第2+8k级GOA单元中，第二控制时钟端CKb接入第一主时钟信号CK1，第三控制时钟端CKc接入第二主时钟信号CK2，第一控制时钟端CKa接入第四主时钟信号CK4，其中，k为正整数。例如，在第1级GOA单元、第2级GOA单元、第9级GOA单元、第10级GOA单元中，第二控制时钟端CKb接入第一主时钟信号CK1，第三控制时钟端CKc接入第二主时钟信号CK2，第一控制时钟端CKa接入第四主时钟信号CK4。
在一些实施例中，在第3+8k级GOA单元和第4+8k级GOA单元中，第二控制时钟端CKb接入第二主时钟信号CK2，第三控制时钟端CKc接入第三主时钟信号CK3，第一控制时钟端CKa接入第一主时钟信号CK1，其中，k为正整数。例如，在第3级GOA单元、第4级GOA单元中，第二控制时钟端CKb接入第二主时钟信号CK2，第三控制时钟端CKc接入第三主时钟信号CK3，第一控制时钟端CKa接入第一主时钟信号CK1。
在一些实施例中，在第5+8k级GOA单元和第6+8k级GOA单元中，第二控制时钟端CKb接入第三主时钟信号CK3，第三控制时钟端CKc接入第四主时钟信号CK4，第一控制时钟端CKa接入第二主时钟信号CK2，其中，k为正整数。例如，在第5级GOA单元、第6级GOA单元中，第二控制时钟端CKb接入第三主时钟信号CK3，第三控制时钟端CKc接入第四主时钟信号CK4，第一控制时钟端CKa接入第二主时钟信号CK2。
在一些实施例中，在第7+8k级GOA单元和第8+8k级GOA单元中，第二控制时钟端CKb接入第四主时钟信号CK4，第三控制时钟端CKc接入第一主时钟信号CK1，第一控制时钟端CKa接入第三主时钟信号CK3，其中，k为正整数。例如，在第7级GOA单元、第8级GOA单元中，第二控制时钟端CKb接入第四主时钟信号CK4，第三控制时钟端CKc接入第一主时钟信号CK1，第一控制时钟端CKa接入第三主时钟信号CK3。
进一步的，请参阅图2，图2为图1所示的GOA电路中一GOA单元的第一种电路示意图。结合图1、图2所示，该GOA单元包括：正反扫描模块101、输出模块102以及下拉模块103。
其中，正反扫描模块101接入上一级扫描驱动信号G（n-2）、正向扫描信号U2D、下一级扫描驱动信号G（n+2）、反向扫描信号D2U以及恒压低电平信号VGL，并电性连接于第一控制时钟端CKa、第三控制时钟端CKc、第一节点Q（n）以及第二节点P（n），用于将正向扫描信号U2D输出至第一节点Q（n），或用于将反向扫描信号D2U输出至第一节点Q（n），并在第一节点Q（n）的电位控制下将恒压低电平信号VGL输出至第二节点P（n）。
其中，输出模块102接入恒压低电平信号VGL以及恒压高电平信号VGH，并电性连接于第一节点Q（n）以及第二控制时钟端CKb，用于输出本级扫描驱动信号G（n）。
其中，下拉模块103接入恒压低电平信号VGL、正向扫描信号U2D、反向扫描信号D2U以及恒压高电平信号VGH，并电性连接于第一控制时钟端CKa、第三控制时钟端CKc、第一节点Q（n）以及本级扫描驱动信号G（n），用于将第一节点Q（n）的电位以及本级扫描驱动信号G（n）的电位下拉至恒压低电平信号VGL的电位。
具体的，正反扫描模块101包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4以及第五晶体管T5。
其中，第一晶体管T1的栅极电性连接于第一控制时钟端CKa，第一晶体管T1的源极接入正向扫描信号U2D，第一晶体管T1的漏极电性连接于第二晶体管T2的源极，第二晶体管T2的栅极接入上一级扫描驱动信号G（n-2），第二晶体管T2的漏极电性连接于第一节点Q（n），第三晶体管T3的栅极电性连接于第三控制时钟端CKc，第三晶体管T3的源极接入反向扫描信号D2U，第三晶体管T3的漏极电性连接于第四晶体管T4的源极，第四晶体管T4的栅极接入下一级扫描驱动信号G（n+2），第四晶体管T4的漏极电性连接于第一节点Q（n），第五晶体管T5的栅极电性连接于第一节点Q（n），第五晶体管T5的源极接入恒压低电平信号VGL，第五晶体管T5的漏极电性连接于第二节点P（n）。
具体的，输出模块102包括：第六晶体管T6、第七晶体管T7以及第一电容C1。
其中，第六晶体管T6的栅极接入恒压高电平信号VGH，第六晶体管T6的源极电性连接于第一节点Q（n），第六晶体管T6的漏极电性连接于第七晶体管T7的栅极，第七晶体管T7的源极电性连接于第一控制时钟端CKa，第七晶体管T7的漏极电性连接于本级扫描驱动信号G（n），第一电容C1的一端电性连接于第一节点Q（n），第一电容C1的另一端电性连接于恒压低电平信号VGL。
具体的，下拉模块103包括：第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12以及第二电容C2。
其中，第八晶体管T8的栅极接入正向扫描信号U2D，第八晶体管T8的源极电性连接于第三控制时钟端CKc，第九晶体管T9的栅极接入反向扫描信号D2U，第九晶体管T9的源极电性连接于第一控制时钟端CKa，第八晶体管T8的漏极、第九晶体管T9的漏极电性连接于第十晶体管T10的栅极，第十晶体管T10的源极接入恒压高电平信号VGH，第十晶体管T10的漏极、第十一晶体管T11的栅极、第十二晶体管T12的栅极电性连接于第二节点P（n），第十一晶体管T11的源极以及第十二晶体管T12的源极接入恒压低电平信号VGL，第十一晶体管T11的漏极电性连接于第一节点Q（n），第十二晶体管T12的漏极电性连接于本级扫描驱动信号G（n），第二电容C2的一端电性连接于所述第二节点P（n），第二电容C2的另一端电性连接于恒压低电平信号VGL。
下面以第3级GOA单元为例说明图1所示的GOA电路对应的第3级GOA单元的工作原理。请参阅图3，图3为图1所示的GOA电路对应的第3级GOA单元的时序示意图。其中，第一主时钟信号CK1、第二主时钟信号CK2、第三主时钟信号CK3以及第四主时钟信号CK4为周期相同，且具有相位差的时钟信号。需要说明的是，在第3级GOA单元中，第二控制时钟端CKb接入第二主时钟信号CK2，第三控制时钟端CKc接入第三主时钟信号CK3，第一控制时钟端CKa接入第一主时钟信号CK1。
结合图1、图2、图3所示，当GOA电路进行正向扫描时，正向扫描信号U2D为高电平，反向扫描信号D2U为低电平。在第一时间段t1，第一主时钟信号CK1为高电平，上一级扫描驱动信号G1为高电平，此时，第一晶体管T1和第二晶体管T2打开，正向扫描信号U2D经第一晶体管T1和第二晶体管T2输出至第一节点Q（3），第一节点Q（3）的电位被抬高。由于第一节点Q（3）的电位被抬高，使得第五晶体管T5打开，恒压低电平信号输出至第二节点P（3），使得第十一晶体管T11和第十二晶体管T12关闭。与此同时，由于第一节点Q（3）的电位被抬高，使得第七晶体管T7打开，第二主时钟信号CK2为低电位，第二主时钟信号CK2经第七晶体管T7输出，因此本级扫描驱动信号G（3）为低电位。
在第二时间段t2，由于第一电容C1和第二电容C2的作用，使得此时第一节点Q（3）的电位仍为高电位，第二节点P（3）的电位仍为低电位。此时，第二主时钟信号CK2为高电位，第二主时钟信号CK2经第七晶体管T7输出，因此本级扫描驱动信号G（3）为高电位。
在第三时间段t3，第三主时钟信号CK3为高电位，使得第十晶体管T10打开，恒压高电平信号VGH经第十晶体管T10输出至第二节点P（3），第十一晶体管T11和第十二晶体管T12打开，恒压低电平信号VGL经第十一晶体管T11输出至第一节点Q（3），恒压低电平信号VGL经第十二晶体管T12输出至本级扫描驱动信号G（3），此时，第一节点Q（3）的电位和本级扫描驱动信号G（3）的电位被下拉至恒压低电平信号VGL的电位。
同样，当GOA电路进行反向扫描时，正向扫描信号U2D为低电平，反向扫描信号D2U为高电平。在第三时间段t3，第三主时钟信号CK3为高电平，下一级扫描驱动信号G5为高电平，此时，第三晶体管T3和第四晶体管T4打开，反向扫描信号D2U经第三晶体管T3和第四晶体管T4输出至第一节点Q（3），第一节点Q（3）的电位被抬高。由于第一节点Q（3）的电位被抬高，使得第五晶体管T5打开，恒压低电平信号输出至第二节点P（3），使得第十一晶体管T11和第十二晶体管T12关闭。与此同时，由于第一节点Q（3）的电位被抬高，使得第七晶体管T7打开，第二主时钟信号CK2为低电位，第二主时钟信号CK2经第七晶体管T7输出，因此本级扫描驱动信号G（3）为低电位。
在第二时间段t2，由于第一电容C1和第二电容C2的作用，使得此时第一节点Q（3）的电位仍为高电位，第二节点P（3）的电位仍为低电位。此时，第二主时钟信号CK2为高电位，第二主时钟信号CK2经第七晶体管T7输出，因此本级扫描驱动信号G（3）为高电位。
在第一时间段t1，第一主时钟信号CK1为高电位，使得第十晶体管T10打开，恒压高电平信号VGH经第十晶体管T10输出至第二节点P（3），第十一晶体管T11和第十二晶体管T12打开，恒压低电平信号VGL经第十一晶体管T11输出至第一节点Q（3），恒压低电平信号VGL经第十二晶体管T12输出至本级扫描驱动信号G（3），此时，第一节点Q（3）的电位和本级扫描驱动信号G（3）的电位被下拉至恒压低电平信号VGL的电位。
需要说明的是，本申请实施例的GOA电路10通过在正反扫描模块101中增加第一控制时钟端CKa和第三控制时钟端CKc以控制第一节点Q（n），从而可以减小第一节点Q（n）在工作期间漏电，进而提高GOA电路10的可靠性。
请参阅图4，图4为图1所示的GOA电路中一GOA单元的第二种电路示意图。其中，图4所示的GOA单元与图2所示的GOA单元的区别在于：图4所示的GOA单元还包括：功能控制模块104，该功能控制模块104接入第一功能控制信号Gas1和第二功能控制信号Gas2，并电性连接于第一节点Q（n）、第二节点P（n）以及本级扫描驱动信号G（n），用于实现GOA电路10的所有扫描驱动信号打开功能以及关闭功能。
具体的，功能控制模块104包括：第十三晶体管T13、第十四晶体管T14、第十五晶体管T15以及第十六晶体管T16。
第十三晶体管T13的栅极、第十四晶体管T14的栅极以及第十五晶体管T15的源极、栅极接入第一功能控制信号Gas1，第十六晶体管T16的栅极接入第二功能控制信号Gas2，第十三晶体管T13的源极、第十四晶体管T14的源极以及第十六晶体管T16的源极接入恒压低电平信号VGL，第十三晶体管T13的漏极电性连接于第一节点Q（n），第十四晶体管T14的漏极电性连接于第二节点P（n），第十五晶体管T15的漏极以及第十六晶体管T16的漏极电性连接于本级扫描驱动信号G（n）。
其中，GOA电路10包括打开功能阶段以及关闭功能阶段。在打开功能阶段，第一功能控制信号Gas1为高电平，第二功能控制信号Gas2为低电平；在关闭功能阶段，第一功能控制信号Gas1为低电平，第二功能控制信号Gas2为高电平。
需要说明的是，本申请实施例的GOA电路10在打开功能阶段，通过第一控制时钟端CKa和第三控制时钟端CKc隔绝正向扫描信号U2D/反向扫描信号D2U与第一节点Q（n）的通路，采用高电平的正向扫描信号U2D/反向扫描信号D2U进行驱动，同时通过第一功能控制信号Gas1控制第一节点Q（n）的通路，可以将第二控制时钟端CKb的信号连通到GOA电路10的不可控节点，避免GOA电路10出现竞争通路。
请参阅图5，图5为图1所示的GOA电路中一GOA单元的第三种电路示意图。其中，图5所示的GOA单元与图4所示的GOA单元的区别在于：图4所示的第十三晶体管T13的漏极与第六晶体管T6的源极电性连接，图5所示的第十三晶体管T13的漏极与第六晶体管T6的漏极电性连接。由于第六晶体管T6的栅极接入恒压高电平信号，因此，图5所示的GOA单元与图4所示的GOA单元的工作原理一致，在此不做赘述。
请参阅图6，图6为本申请实施例提供的GOA电路的第二种结构示意图。图6所示的的GOA电路20与图1所示的GOA电路10的区别在于：第一控制时钟端CKa、第二控制时钟端CKb和第三控制时钟端CKc接入的时钟信号不同。
其中，本申请实施例的GOA电路20接收第一次时钟信号CK11、第二次时钟信号CK12、第三次时钟信号CK13、第四次时钟信号CK14、第五次时钟信号CK15、第六次时钟信号CK16、第七次时钟信号CK17以及第八次时钟信号CK18，第一次时钟信号CK11、第二次时钟信号CK12、第三次时钟信号CK13、第四次时钟信号CK14、第五次时钟信号CK15、第六次时钟信号CK16、第七次时钟信号CK17以及第八次时钟信号CK18在GOA电路20的作用周期依次分时有效。
在一些实施例中，在第1+8k级GOA单元中，第二控制时钟端CKb接入第一次时钟信号CK11，第三控制时钟端CKc接入第三次时钟信号CK13，第一控制时钟端CKa接入第七次时钟信号CK17，其中，k为正整数。例如，在第1级GOA单元、第9级GOA单元中，第二控制时钟端CKb接入第一次时钟信号CK11，第三控制时钟端CKc接入第三次时钟信号CK13，第一控制时钟端CKa接入第七次时钟信号CK17。
在一些实施例中，在第2+8k级GOA单元中，第二控制时钟端CKb接入第二次时钟信号CK12，第三控制时钟端CKc接入第四次时钟信号CK14，第一控制时钟端CKa接入第八次时钟信号CK18，其中，k为正整数。例如，在第2级GOA单元、第10级GOA单元中，第二控制时钟端CKb接入第二次时钟信号CK12，第三控制时钟端CKc接入第四次时钟信号CK14，第一控制时钟端CKa接入第八次时钟信号CK18。
在一些实施例中，在第3+8k级GOA单元中，第二控制时钟端CKb接入第三次主时钟信号，第三控制时钟端CKc接入第五次时钟信号CK15，第一控制时钟端CKa接入第一次时钟信号CK11，其中，k为正整数。例如，在第3级GOA单元中，第二控制时钟端CKb接入第三次主时钟信号，第三控制时钟端CKc接入第五次时钟信号CK15，第一控制时钟端CKa接入第一次时钟信号CK11。
在一些实施例中，在第4+8k级GOA单元中，第二控制时钟端CKb接入第四次主时钟信号，第三控制时钟端CKc接入第六次时钟信号CK16，第一控制时钟端CKa接入第二次时钟信号CK12，其中，k为正整数。例如，在第4级GOA单元中，第二控制时钟端CKb接入第四次主时钟信号，第三控制时钟端CKc接入第六次时钟信号CK16，第一控制时钟端CKa接入第二次时钟信号CK12。
在一些实施例中，在第5+8k级GOA单元中，第二控制时钟端CKb接入第五次时钟信号CK15，第三控制时钟端CKc接入第七次时钟信号CK17，第一控制时钟端CKa接入第三次时钟信号CK13，其中，k为正整数。例如，在第5级GOA单元中，第二控制时钟端CKb接入第五次时钟信号CK15，第三控制时钟端CKc接入第七次时钟信号CK17，第一控制时钟端CKa接入第三次时钟信号CK13。
在一些实施例中，在第6+8k级GOA单元中，第二控制时钟端CKb接入第六次时钟信号CK16，第三控制时钟端CKc接入第八次时钟信号CK18，第一控制时钟端CKa接入第四次时钟信号CK14，其中，k为正整数。例如，在第6级GOA单元中，第二控制时钟端CKb接入第六次时钟信号CK16，第三控制时钟端CKc接入第八次时钟信号CK18，第一控制时钟端CKa接入第四次时钟信号CK14。
在一些实施例中，在第7+8k级GOA单元中，第二控制时钟端CKb接入第七次时钟信号CK17，第三控制时钟端CKc接入第一次时钟信号CK11，第一控制时钟端CKa接入第五次时钟信号CK15，其中，k为正整数。例如，在第7级GOA单元中，第二控制时钟端CKb接入第七次时钟信号CK17，第三控制时钟端CKc接入第一次时钟信号CK11，第一控制时钟端CKa接入第五次时钟信号CK15。
在一些实施例中，在第8+8k级GOA单元中，第二控制时钟端CKb接入第八次时钟信号CK18，第三控制时钟端CKc接入第二次时钟信号CK12，第一控制时钟端CKa接入第六次时钟信号CK16，其中，k为正整数。例如，在第8级GOA单元中，第二控制时钟端CKb接入第八次时钟信号CK18，第三控制时钟端CKc接入第二次时钟信号CK12，第一控制时钟端CKa接入第六次时钟信号CK16。
需要说明的是，图6所示的GOA电路20中的GOA单元的电路示意图与图1所示的GOA电路10中的GOA单元的电路示意图一致，具体可参照图2、图4、图5中的描述，在此不做赘述。
下面以第3级GOA单元为例说明图6所示的GOA电路对应的第3级GOA单元的工作原理。
请参阅图7，图7为图6所示的GOA电路对应的第3级GOA单元的时序示意图。其中，第一次时钟信号CK11、第二次时钟信号CK12、第三次时钟信号CK13、第四次时钟信号CK14、第五次时钟信号CK15、第六次时钟信号CK16、第七次时钟信号CK17以及第八次时钟信号CK18为周期相同，且具有相位差的时钟信号。需要说明的是，在第3级GOA单元中，第二控制时钟端CKb接入第三次时钟信号CK13，第三控制时钟端CKc接入第五次时钟信号CK15，第一控制时钟端CKa接入第一次时钟信号CK11。
结合图6、图7、图3所示，当GOA电路进行正向扫描时，正向扫描信号U2D为高电平，反向扫描信号D2U为低电平。在第一时间段t11，第一次时钟信号CK11为高电平，上一级扫描驱动信号G1为高电平，此时，第一晶体管T1和第二晶体管T2打开，正向扫描信号U2D经第一晶体管T1和第二晶体管T2输出至第一节点Q（3），第一节点Q（3）的电位被抬高。由于第一节点Q（3）的电位被抬高，使得第五晶体管T5打开，恒压低电平信号输出至第二节点P（3），使得第十一晶体管T11和第十二晶体管T12关闭。与此同时，由于第一节点Q（3）的电位被抬高，使得第七晶体管T7打开，第三次时钟信号CK13为低电位，第三次时钟信号CK13经第七晶体管T7输出，因此本级扫描驱动信号G（3）为低电位。
在第二时间段t12，由于第一电容C1和第二电容C2的作用，使得此时第一节点Q（3）的电位仍为高电位，第二节点P（3）的电位仍为低电位。此时，第三次时钟信号CK13为高电位，第三次时钟信号CK13经第七晶体管T7输出，因此本级扫描驱动信号G（3）为高电位。
在第三时间段t13，第五次时钟信号CK15为高电位，使得第十晶体管T10打开，恒压高电平信号VGH经第十晶体管T10输出至第二节点P（3），第十一晶体管T11和第十二晶体管T12打开，恒压低电平信号VGL经第十一晶体管T11输出至第一节点Q（3），恒压低电平信号VGL经第十二晶体管T12输出至本级扫描驱动信号G（3），此时，第一节点Q（3）的电位和本级扫描驱动信号G（3）的电位被下拉至恒压低电平信号VGL的电位。
同样，当GOA电路进行反向扫描时，正向扫描信号为低电平，反向扫描信号为高电平。在第三时间段t13，第五次时钟信号CK15为高电平，下一级扫描驱动信号G5为高电平，此时，第三晶体管T3和第四晶体管T4打开，反向扫描信号D2U经第三晶体管T3和第四晶体管T4输出至第一节点Q（3），第一节点Q（3）的电位被抬高。由于第一节点Q（3）的电位被抬高，使得第五晶体管T5打开，恒压低电平信号输出至第二节点P（3），使得第十一晶体管T11和第十二晶体管T12关闭。与此同时，由于第一节点Q（3）的电位被抬高，使得第七晶体管T7打开，第三次时钟信号CK13为低电位，第三次时钟信号CK13经第七晶体管T7输出，因此本级扫描驱动信号G（3）为低电位。
在第二时间段t12，由于第一电容C1和第二电容C2的作用，使得此时第一节点Q（3）的电位仍为高电位，第二节点P（3）的电位仍为低电位。此时，第三次时钟信号CK13为高电位，第三次时钟信号CK13经第七晶体管T7输出，因此本级扫描驱动信号G（3）为高电位。
在第一时间段t11，第一次时钟信号CK11为高电位，使得第十晶体管T10打开，恒压高电平信号VGH经第十晶体管T10输出至第二节点P（3），第十一晶体管T11和第十二晶体管T12打开，恒压低电平信号VGL经第十一晶体管T11输出至第一节点Q（3），恒压低电平信号VGL经第十二晶体管T12输出至本级扫描驱动信号G（3），此时，第一节点Q（3）的电位和本级扫描驱动信号G（3）的电位被下拉至恒压低电平信号VGL的电位。
请参阅图8，图8为本申请实施例提供的显示面板的结构示意图。如图8所示，该显示面板包括显示区域100以及集成设置在显示区域100边缘上的GOA电路200；其中，该GOA电路200与上述的GOA电路的结构和原理类似，这里不再赘述。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：正反扫描模块、输出模块以及下拉模块；
    所述正反扫描模块，接入上一级扫描驱动信号、正向扫描信号、下一级扫描驱动信号、反向扫描信号以及恒压低电平信号，并电性连接于第一控制时钟端、第三控制时钟端、第一节点以及第二节点，用于将所述正向扫描信号输出至所述第一节点，或用于将所述反向扫描信号输出至所述第一节点，并在所述第一节点的电位控制下将所述恒压低电平信号输出至所述第二节点；
    所述输出模块，接入所述恒压低电平信号以及恒压高电平信号，并电性连接于所述第一节点以及第二控制时钟端，用于输出本级扫描驱动信号；
    所述下拉模块，接入所述恒压低电平信号、所述正向扫描信号、所述反向扫描信号以及所述恒压高电平信号，并电性连接于所述第一控制时钟端、第三控制时钟端、所述第一节点以及所述本级扫描驱动信号，用于将所述第一节点的电位以及所述本级扫描驱动信号的电位下拉至所述恒压低电平信号的电位；
    其中，所述正向扫描信号以及所述反向扫描信号均为直流电源，且所述正向扫描信号的电位与所述反向扫描信号的电位相反；
    所述正反扫描模块包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
    所述第一晶体管的栅极电性连接于所述第一控制时钟端，所述第一晶体管的源极接入所述正向扫描信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极，所述第二晶体管的栅极接入所述上一级扫描驱动信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的栅极电性连接于所述第三控制时钟端，所述第三晶体管的源极接入所述反向扫描信号，所述第三晶体管的漏极电性连接于所述第四晶体管的源极，所述第四晶体管的栅极接入所述下一级扫描驱动信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极接入所述恒压低电平信号，所述第五晶体管的漏极电性连接于所述第二节点；
    所述输出模块包括：第六晶体管、第七晶体管以及第一电容；
    所述第六晶体管的栅极接入所述恒压高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第七晶体管的栅极，所述第七晶体管的源极电性连接于所述第一控制时钟端，所述第七晶体管的漏极电性连接于所述本级扫描驱动信号，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
  2. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第二电容；
    所述第八晶体管的栅极接入所述正向扫描信号，所述第八晶体管的源极电性连接于所述第三控制时钟端，所述第九晶体管的栅极接入所述反向扫描信号，所述第九晶体管的源极电性连接于所述第一控制时钟端，所述第八晶体管的漏极、所述第九晶体管的漏极电性连接于所述第十晶体管的栅极，所述第十晶体管的源极接入所述恒压高电平信号，所述第十晶体管的漏极、所述第十一晶体管的栅极、所述第十二晶体管的栅极电性连接于所述第二节点，所述第十一晶体管的源极以及所述第十二晶体管的源极接入所述恒压低电平信号，所述第十一晶体管的漏极电性连接于所述第一节点，所述第十二晶体管的漏极电性连接于所述本级扫描驱动信号，所述第二电容的一端电性连接于所述第二节点，所述第二电容的另一端电性连接于所述恒压低电平信号。
  3. 根据权利要求1所述的GOA电路，其中，所述GOA电路接收第一主时钟信号、第二主时钟信号、第三主时钟信号以及第四主时钟信号，所述第一主时钟信号、所述第二主时钟信号、所述第三主时钟信号以及所述第四主时钟信号在所述GOA电路的作用周期依次分时有效；
    其中，在第1+8k级GOA单元和第2+8k级GOA单元中，所述第二控制时钟端接入所述第一主时钟信号，所述第三控制时钟端接入所述第二主时钟信号，所述第一控制时钟端接入所述第四主时钟信号；
    在第3+8k级GOA单元和第4+8k级GOA单元中，所述第二控制时钟端接入所述第二主时钟信号，所述第三控制时钟端接入所述第三主时钟信号，所述第一控制时钟端接入所述第一主时钟信号；
    在第5+8k级GOA单元和第6+8k级GOA单元中，所述第二控制时钟端接入所述第三主时钟信号，所述第三控制时钟端接入所述第四主时钟信号，所述第一控制时钟端接入所述第二主时钟信号；
    在第7+8k级GOA单元和第8+8k级GOA单元中，所述第二控制时钟端接入所述第四主时钟信号，所述第三控制时钟端接入所述第一主时钟信号，所述第一控制时钟端接入所述第三主时钟信号；k为正整数。
  4. 根据权利要求1所述的GOA电路，其中，所述GOA电路接收第一次时钟信号、第二次时钟信号、第三次时钟信号、第四次时钟信号、第五次时钟信号、第六次时钟信号、第七次时钟信号以及第八次时钟信号，所述第一次时钟信号、所述第二次时钟信号、所述第三次时钟信号、所述第四次时钟信号、所述第五次时钟信号、所述第六次时钟信号、所述第七次时钟信号以及所述第八次时钟信号在所述GOA电路的作用周期依次分时有效；
    其中，在第1+8k级GOA单元中，所述第二控制时钟端接入所述第一次时钟信号，所述第三控制时钟端接入所述第三次时钟信号，所述第一控制时钟端接入所述第七次时钟信号；
    在第2+8k级GOA单元中，所述第二控制时钟端接入所述第二次时钟信号，所述第三控制时钟端接入所述第四次时钟信号，所述第一控制时钟端接入所述第八次时钟信号；
    在第3+8k级GOA单元中，所述第二控制时钟端接入所述第三次主时钟信号，所述第三控制时钟端接入所述第五次时钟信号，所述第一控制时钟端接入所述第一次时钟信号；
    在第4+8k级GOA单元中，所述第二控制时钟端接入所述第四次主时钟信号，所述第三控制时钟端接入所述第六次时钟信号，所述第一控制时钟端接入所述第二次时钟信号；
    在第5+8k级GOA单元中，所述第二控制时钟端接入所述第五次时钟信号，所述第三控制时钟端接入所述第七次时钟信号，所述第一控制时钟端接入所述第三次时钟信号；
    在第6+8k级GOA单元中，所述第二控制时钟端接入所述第六次时钟信号，所述第三控制时钟端接入所述第八次时钟信号，所述第一控制时钟端接入所述第四次时钟信号；
    在第7+8k级GOA单元中，所述第二控制时钟端接入所述第七次时钟信号，所述第三控制时钟端接入所述第一次时钟信号，所述第一控制时钟端接入所述第五次时钟信号；
    在第8+8k级GOA单元中，所述第二控制时钟端接入所述第八次时钟信号，所述第三控制时钟端接入所述第二次时钟信号，所述第一控制时钟端接入所述第六次时钟信号；k为正整数。
  5. 根据权利要求1所述的GOA电路，其中，所述GOA单元还包括功能控制模块，所述功能控制模块接入第一功能控制信号和第二功能控制信号，并电性连接于所述第一节点、所述第二节点以及所述本级扫描驱动信号，用于实现所述GOA电路的所有扫描驱动信号打开功能以及关闭功能。
  6. 根据权利要求5所述的GOA电路，其中，所述功能控制模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
    所述第十三晶体管的栅极、所述第十四晶体管的栅极以及所述第十五晶体管的源极、栅极接入所述第一功能控制信号，所述第十六晶体管的栅极接入所述第二功能控制信号，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十六晶体管的源极接入所述恒压低电平信号，所述第十三晶体管的漏极电性连接于所述第一节点，所述第十四晶体管的漏极电性连接于所述第二节点，所述第十五晶体管的漏极以及所述第十六晶体管的漏极电性连接于所述本级扫描驱动信号。
  7. 根据权利要求6所述的GOA电路，其中，所述GOA电路包括打开功能阶段以及关闭功能阶段；其中，在所述打开功能阶段，所述第一功能控制信号为高电平，所述第二功能控制信号为低电平；在所述关闭功能阶段，所述第一功能控制信号为低电平，所述第二功能控制信号为高电平。
  8. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括：正反扫描模块、输出模块以及下拉模块；
    所述正反扫描模块，接入上一级扫描驱动信号、正向扫描信号、下一级扫描驱动信号、反向扫描信号以及恒压低电平信号，并电性连接于第一控制时钟端、第三控制时钟端、第一节点以及第二节点，用于将所述正向扫描信号输出至所述第一节点，或用于将所述反向扫描信号输出至所述第一节点，并在所述第一节点的电位控制下将所述恒压低电平信号输出至所述第二节点；
    所述输出模块，接入所述恒压低电平信号以及恒压高电平信号，并电性连接于所述第一节点以及第二控制时钟端，用于输出本级扫描驱动信号；
    所述下拉模块，接入所述恒压低电平信号、所述正向扫描信号、所述反向扫描信号以及所述恒压高电平信号，并电性连接于所述第一控制时钟端、第三控制时钟端、所述第一节点以及所述本级扫描驱动信号，用于将所述第一节点的电位以及所述本级扫描驱动信号的电位下拉至所述恒压低电平信号的电位；
    其中，所述正向扫描信号以及所述反向扫描信号均为直流电源，且所述正向扫描信号的电位与所述反向扫描信号的电位相反。
  9. 根据权利要求8所述的GOA电路，其中，所述正反扫描模块包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
    所述第一晶体管的栅极电性连接于所述第一控制时钟端，所述第一晶体管的源极接入所述正向扫描信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极，所述第二晶体管的栅极接入所述上一级扫描驱动信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的栅极电性连接于所述第三控制时钟端，所述第三晶体管的源极接入所述反向扫描信号，所述第三晶体管的漏极电性连接于所述第四晶体管的源极，所述第四晶体管的栅极接入所述下一级扫描驱动信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极接入所述恒压低电平信号，所述第五晶体管的漏极电性连接于所述第二节点。
  10. 根据权利要求8所述的GOA电路，其中，所述输出模块包括：第六晶体管、第七晶体管以及第一电容；
    所述第六晶体管的栅极接入所述恒压高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第七晶体管的栅极，所述第七晶体管的源极电性连接于所述第一控制时钟端，所述第七晶体管的漏极电性连接于所述本级扫描驱动信号，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
  11. 根据权利要求8所述的GOA电路，其中，所述下拉模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第二电容；
    所述第八晶体管的栅极接入所述正向扫描信号，所述第八晶体管的源极电性连接于所述第三控制时钟端，所述第九晶体管的栅极接入所述反向扫描信号，所述第九晶体管的源极电性连接于所述第一控制时钟端，所述第八晶体管的漏极、所述第九晶体管的漏极电性连接于所述第十晶体管的栅极，所述第十晶体管的源极接入所述恒压高电平信号，所述第十晶体管的漏极、所述第十一晶体管的栅极、所述第十二晶体管的栅极电性连接于所述第二节点，所述第十一晶体管的源极以及所述第十二晶体管的源极接入所述恒压低电平信号，所述第十一晶体管的漏极电性连接于所述第一节点，所述第十二晶体管的漏极电性连接于所述本级扫描驱动信号，所述第二电容的一端电性连接于所述第二节点，所述第二电容的另一端电性连接于所述恒压低电平信号。
  12. 根据权利要求8所述的GOA电路，其中，所述GOA电路接收第一主时钟信号、第二主时钟信号、第三主时钟信号以及第四主时钟信号，所述第一主时钟信号、所述第二主时钟信号、所述第三主时钟信号以及所述第四主时钟信号在所述GOA电路的作用周期依次分时有效；
    其中，在第1+8k级GOA单元和第2+8k级GOA单元中，所述第二控制时钟端接入所述第一主时钟信号，所述第三控制时钟端接入所述第二主时钟信号，所述第一控制时钟端接入所述第四主时钟信号；
    在第3+8k级GOA单元和第4+8k级GOA单元中，所述第二控制时钟端接入所述第二主时钟信号，所述第三控制时钟端接入所述第三主时钟信号，所述第一控制时钟端接入所述第一主时钟信号；
    在第5+8k级GOA单元和第6+8k级GOA单元中，所述第二控制时钟端接入所述第三主时钟信号，所述第三控制时钟端接入所述第四主时钟信号，所述第一控制时钟端接入所述第二主时钟信号；
    在第7+8k级GOA单元和第8+8k级GOA单元中，所述第二控制时钟端接入所述第四主时钟信号，所述第三控制时钟端接入所述第一主时钟信号，所述第一控制时钟端接入所述第三主时钟信号；k为正整数。
  13. 根据权利要求8所述的GOA电路，其中，所述GOA电路接收第一次时钟信号、第二次时钟信号、第三次时钟信号、第四次时钟信号、第五次时钟信号、第六次时钟信号、第七次时钟信号以及第八次时钟信号，所述第一次时钟信号、所述第二次时钟信号、所述第三次时钟信号、所述第四次时钟信号、所述第五次时钟信号、所述第六次时钟信号、所述第七次时钟信号以及所述第八次时钟信号在所述GOA电路的作用周期依次分时有效；
    其中，在第1+8k级GOA单元中，所述第二控制时钟端接入所述第一次时钟信号，所述第三控制时钟端接入所述第三次时钟信号，所述第一控制时钟端接入所述第七次时钟信号；
    在第2+8k级GOA单元中，所述第二控制时钟端接入所述第二次时钟信号，所述第三控制时钟端接入所述第四次时钟信号，所述第一控制时钟端接入所述第八次时钟信号；
    在第3+8k级GOA单元中，所述第二控制时钟端接入所述第三次主时钟信号，所述第三控制时钟端接入所述第五次时钟信号，所述第一控制时钟端接入所述第一次时钟信号；
    在第4+8k级GOA单元中，所述第二控制时钟端接入所述第四次主时钟信号，所述第三控制时钟端接入所述第六次时钟信号，所述第一控制时钟端接入所述第二次时钟信号；
    在第5+8k级GOA单元中，所述第二控制时钟端接入所述第五次时钟信号，所述第三控制时钟端接入所述第七次时钟信号，所述第一控制时钟端接入所述第三次时钟信号；
    在第6+8k级GOA单元中，所述第二控制时钟端接入所述第六次时钟信号，所述第三控制时钟端接入所述第八次时钟信号，所述第一控制时钟端接入所述第四次时钟信号；
    在第7+8k级GOA单元中，所述第二控制时钟端接入所述第七次时钟信号，所述第三控制时钟端接入所述第一次时钟信号，所述第一控制时钟端接入所述第五次时钟信号；
    在第8+8k级GOA单元中，所述第二控制时钟端接入所述第八次时钟信号，所述第三控制时钟端接入所述第二次时钟信号，所述第一控制时钟端接入所述第六次时钟信号；k为正整数。
  14. 根据权利要求8所述的GOA电路，其中，所述GOA单元还包括功能控制模块，所述功能控制模块接入第一功能控制信号和第二功能控制信号，并电性连接于所述第一节点、所述第二节点以及所述本级扫描驱动信号，用于实现所述GOA电路的所有扫描驱动信号打开功能以及关闭功能。
  15. 根据权利要求14所述的GOA电路，其中，所述功能控制模块包括：第十三晶体管、第十四晶体管、第十五晶体管以及第十六晶体管；
    所述第十三晶体管的栅极、所述第十四晶体管的栅极以及所述第十五晶体管的源极、栅极接入所述第一功能控制信号，所述第十六晶体管的栅极接入所述第二功能控制信号，所述第十三晶体管的源极、所述第十四晶体管的源极以及所述第十六晶体管的源极接入所述恒压低电平信号，所述第十三晶体管的漏极电性连接于所述第一节点，所述第十四晶体管的漏极电性连接于所述第二节点，所述第十五晶体管的漏极以及所述第十六晶体管的漏极电性连接于所述本级扫描驱动信号。
  16. 根据权利要求15所述的GOA电路，其中，所述GOA电路包括打开功能阶段以及关闭功能阶段；其中，在所述打开功能阶段，所述第一功能控制信号为高电平，所述第二功能控制信号为低电平；在所述关闭功能阶段，所述第一功能控制信号为低电平，所述第二功能控制信号为高电平。
  17. 一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括：正反扫描模块、输出模块以及下拉模块；
    所述正反扫描模块，接入上一级扫描驱动信号、正向扫描信号、下一级扫描驱动信号、反向扫描信号以及恒压低电平信号，并电性连接于第一控制时钟端、第三控制时钟端、第一节点以及第二节点，用于将所述正向扫描信号输出至所述第一节点，或用于将所述反向扫描信号输出至所述第一节点，并在所述第一节点的电位控制下将所述恒压低电平信号输出至所述第二节点；
    所述输出模块，接入所述恒压低电平信号以及恒压高电平信号，并电性连接于所述第一节点以及第二控制时钟端，用于输出本级扫描驱动信号；
    所述下拉模块，接入所述恒压低电平信号、所述正向扫描信号、所述反向扫描信号以及所述恒压高电平信号，并电性连接于所述第一控制时钟端、第三控制时钟端、所述第一节点以及所述本级扫描驱动信号，用于将所述第一节点的电位以及所述本级扫描驱动信号的电位下拉至所述恒压低电平信号的电位。
  18. 根据权利要求17所述的显示面板，其中，所述正反扫描模块包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管以及第五晶体管；
    所述第一晶体管的栅极电性连接于所述第一控制时钟端，所述第一晶体管的源极接入所述正向扫描信号，所述第一晶体管的漏极电性连接于所述第二晶体管的源极，所述第二晶体管的栅极接入所述上一级扫描驱动信号，所述第二晶体管的漏极电性连接于所述第一节点，所述第三晶体管的栅极电性连接于所述第三控制时钟端，所述第三晶体管的源极接入所述反向扫描信号，所述第三晶体管的漏极电性连接于所述第四晶体管的源极，所述第四晶体管的栅极接入所述下一级扫描驱动信号，所述第四晶体管的漏极电性连接于所述第一节点，所述第五晶体管的栅极电性连接于所述第一节点，所述第五晶体管的源极接入所述恒压低电平信号，所述第五晶体管的漏极电性连接于所述第二节点。
  19. 根据权利要求17所述的显示面板，其中，所述输出模块包括：第六晶体管、第七晶体管以及第一电容；
    所述第六晶体管的栅极接入所述恒压高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于所述第七晶体管的栅极，所述第七晶体管的源极电性连接于所述第一控制时钟端，所述第七晶体管的漏极电性连接于所述本级扫描驱动信号，所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述恒压低电平信号。
  20. 根据权利要求17所述的显示面板，其中，所述下拉模块包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管以及第二电容；
    所述第八晶体管的栅极接入所述正向扫描信号，所述第八晶体管的源极电性连接于所述第三控制时钟端，所述第九晶体管的栅极接入所述反向扫描信号，所述第九晶体管的源极电性连接于所述第一控制时钟端，所述第八晶体管的漏极、所述第九晶体管的漏极电性连接于所述第十晶体管的栅极，所述第十晶体管的源极接入所述恒压高电平信号，所述第十晶体管的漏极、所述第十一晶体管的栅极、所述第十二晶体管的栅极电性连接于所述第二节点，所述第十一晶体管的源极以及所述第十二晶体管的源极接入所述恒压低电平信号，所述第十一晶体管的漏极电性连接于所述第一节点，所述第十二晶体管的漏极电性连接于所述本级扫描驱动信号，所述第二电容的一端电性连接于所述第二节点，所述第二电容的另一端电性连接于所述恒压低电平信号。
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