WO2020107671A1 - 半导体组件及其制造方法 - Google Patents

半导体组件及其制造方法 Download PDF

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WO2020107671A1
WO2020107671A1 PCT/CN2019/071289 CN2019071289W WO2020107671A1 WO 2020107671 A1 WO2020107671 A1 WO 2020107671A1 CN 2019071289 W CN2019071289 W CN 2019071289W WO 2020107671 A1 WO2020107671 A1 WO 2020107671A1
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layer
gate
inner dielectric
polysilicon layer
channel
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肖东辉
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/94—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma

Definitions

  • the invention relates to a semiconductor component and a manufacturing method thereof, in particular to a semiconductor component formed in a low-temperature polysilicon manufacturing process.
  • the amorphous silicon layer In the manufacturing process of the semiconductor device of the low-temperature polysilicon thin film transistor, the amorphous silicon layer must be subjected to high-temperature treatment to remove hydrogen atoms to avoid the formation of many defects due to hydrogen bond breakage in the subsequent process. Since most of these defects are caused by the broken bonds of silicon, hydrogen is used to fill these broken bonds, so-called hydrogenation.
  • the hydrogen content in the inner dielectric layer cannot reach uniformity, and the temperature uniformity of rapid thermal annealing is poor, and the hydrogenation temperature and high temperature of the inner dielectric layer are fast Tempering activates ions at different temperatures, which can cause insufficient or excessive hydrogenation. Therefore, it is necessary to provide an improved method to solve the problems in the prior art.
  • the main object of the present invention is to provide a semiconductor device which can improve the defects of insufficient hydrogenation or uneven hydrogenation of transistors in the process of low-temperature polysilicon.
  • An embodiment of the invention provides a semiconductor device of a thin film transistor formed by a low-temperature polysilicon process.
  • the semiconductor component includes a substrate; a polysilicon layer formed on the substrate, the polysilicon layer includes a source, a channel, and a drain, wherein the source and the drain are formed on both sides of the polysilicon layer, and the channel between the source and the drain is formed; A gate insulating layer formed on the polysilicon layer; a gate formed on the gate insulating layer, and the gate is formed directly above the channel; an inner dielectric layer formed on the gate and covering the gate, the inner layer
  • the dielectric layer is implanted with hydrogen atoms by ion implantation and rapidly tempered at high temperature to form a hydrogenated inner dielectric layer; metal wires passing through the upper surface of the hydrogenated inner dielectric layer, and respectively connected to the source and drain Contact; and a passivation layer covering the hydrogenated inner dielectric layer.
  • the semiconductor component further includes pixel electrodes.
  • the semiconductor device further includes a light shielding layer formed between the substrate and the polysilicon layer.
  • the polysilicon layer includes silicon oxide and silicon nitride.
  • ion implantation of hydrogen atoms can further implant hydrogen atoms into the channel.
  • a method for manufacturing a semiconductor device includes providing a substrate; forming a polysilicon layer on a substrate, wherein the polysilicon layer includes a source, a channel, and a drain, and the source and drain are formed on the polysilicon layer On both sides, the channel is formed between the source and drain; the gate insulating layer is formed on the polysilicon layer; the gate is formed on the gate insulating layer, and the gate is formed directly above the channel; the inner dielectric layer is formed Above the gate and covering the gate, wherein the inner dielectric layer is implanted with hydrogen atoms by ion implantation and rapidly tempered at a high temperature to form a hydrogenated inner dielectric layer; forming a metal wire, wherein the metal wire passes through the hydrogenated inner An upper surface of the dielectric layer, which is in contact with the source and the drain, respectively; and forming a passivation layer, wherein the passivation layer covers the hydrogenated inner dielectric layer.
  • the method for manufacturing a semiconductor device further includes forming pixel electrodes.
  • the method for manufacturing a semiconductor device further includes forming a light shielding layer between the substrate and the polysilicon layer.
  • the polysilicon layer includes silicon oxide and silicon nitride.
  • ion implantation of hydrogen atoms can further implant hydrogen atoms into the channel.
  • the semiconductor component provided by the invention can directly implant hydrogen atoms into the channel to achieve the hydrogenation effect, and because the uniformity of ion implantation is high, the uniformity of hydrogenation is good.
  • FIG. 1 is a manufacturing flowchart of a semiconductor component according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a semiconductor device having a low-temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • An embodiment of the present invention provides a semiconductor device of a thin film transistor formed in a low temperature polysilicon (LTPS) process.
  • the semiconductor component includes a substrate, a polysilicon layer formed on the substrate, source and drain electrodes formed on both sides of the polysilicon layer, a channel formed between the source electrode and the drain, a gate insulating layer formed on the polysilicon layer, and forming The gate on the gate insulating layer, the inner dielectric layer formed above the gate and covering the gate, the metal wire passing through the upper surface of the hydrogenated inner dielectric layer, and the hydrogenated inner dielectric layer Of the passivation layer.
  • LTPS low temperature polysilicon
  • the gate is formed directly above the channel, the inner dielectric layer is implanted with hydrogen atoms through ion implantation and is rapidly tempered at high temperature to form a hydrogenated inner dielectric layer, and the hydrogenated inner dielectric
  • the metal wires on the upper surface of the layer are in contact with the source and the drain, respectively.
  • the semiconductor component further includes pixel electrodes.
  • a light-shielding layer 20 is first formed on the substrate 10, wherein the light-shielding layer 20 prevents light leakage, and then a silicon nitride layer is deposited 30. Silicon oxide layer 40 and non-polysilicon layer.
  • the non-polysilicon layer is formed by an excimer laser annealing (Excimer-Laser Annealing, ELA).
  • ELA excimer laser annealing
  • a source and a drain are formed on both sides of the polysilicon layer 50 through an ion distribution procedure, and a channel is formed between the source and the drain, and then a gate insulating layer 60 is formed on the polysilicon layer 50, and A gate 70 is formed on the gate insulating layer 60, where the gate 70 is directly above the channel.
  • N-type metal-oxide-semiconductor n-MOS
  • P-MOS P-type metal-oxide-semiconductor
  • An inner dielectric layer is formed above, and the inner dielectric layer covers the gate electrode 70, wherein the inner dielectric layer includes a silicon nitride layer 80 and a silicon oxide layer 90. It is worth noting that during the process of crystallization to form the polysilicon layer 50, unsaturated bonds will be formed.
  • the embodiment of the present invention implants hydrogen atoms into the inner dielectric layer by ion implantation 100, and then forms it through rapid tempering at high temperature Hydrogenated inner dielectric layer.
  • the inner dielectric layer is formed in two steps, first forming the silicon nitride layer 80, then implanting hydrogen atoms into the silicon nitride layer 80 by ion implantation 100, and then performing high temperature rapid tempering to form hydrogenated nitrogen
  • the silicon oxide layer 80 in which high temperature rapid tempering is performed at 450°C, and the silicon oxide layer 90 is deposited over the hydrogenated silicon nitride layer 80. Since the uniformity of ion implantation is high, hydrogen atoms can also be directly implanted into the channel to achieve the hydrogenation effect, so the uniformity of hydrogenation is good.
  • the hydrogenated inner dielectric layer 100 is etched to form openings, and conductive metal is deposited in the openings to make metal wires (not shown).
  • the metal wires pass through the upper surface of the hydrogenated inner dielectric layer and are respectively
  • the source electrode and the drain electrode are in conductive contact (not shown), and then a passivation layer (not shown) covering the hydrogenated inner dielectric layer and the metal wire is formed.
  • Subsequent manufacturing processes can form pixel electrodes connected by the universal electrodes and the metal wires in sequence according to actual conditions according to ordinary technicians in the art, and finally encapsulate them, so they will not be repeated here.

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  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

一种半导体组件，包括基板（10）；形成在基板（10）上的多晶硅层（50），多晶硅层包括源极、通道及漏极，其中源极及漏极形成在多晶硅层（50）的二侧，形成在源极及漏极之间的通道；形成在多晶硅层（50）上的栅极绝缘层（60）；形成在栅极绝缘层（60）上的栅极（70），且栅极（70）形成在通道的正上方；形成在栅极（70）上方且覆盖栅极（70）的内层介电层（80、90），内层介电层（80、90）通过离子布植（100）植入氢原子且经高温快速回火形成氢化的内层介电层（80、90）；穿过氢化的内层介电层（80、90）的上表面的金属导线，且分别与源极及漏极接触；以及覆盖氢化的内层介电层（80、90）的钝化层。还公开一种上述半导体组件的制造方法。

Description

半导体组件及其制造方法 技术领域
本发明是有关于一种半导体组件及其制造方法，特别是有关于一种在低温多晶硅制程中形成的半导体组件。
 背景技术
在低温多晶硅薄膜晶体管的半导体组件的制程中，非晶硅层形成后必须进行高温处理来去除氢原子，以避免后续制程中因为氢键断裂而形成很多缺陷。由于这些缺陷大部分起因于硅的断键，因此利用氢来填补这些断键，也就是所谓的氢化作用。然而在习知技术中，内层介电层中的氢含量无法达到均一性，且高温快速回火(rapid thermal anneal)的温度均一性较差，且内层介电层氢化的温度与高温快速回火使离子活化的温度不相同，因此会造成氢化不足或氢化过度的情况发生。故，有必要提供一种改善方法以解决现有技术所存在的问题。
 技术问题
本发明的主要目的在于提供一种半导体组件，其可以改善晶体管在低温多晶硅的制程中氢化不足或氢化不均的缺陷。
 技术解决方案
本发明的一实施例提供一种以低温多晶硅制程形成的薄膜晶体管的半导体组件。半导体组件包括基板；形成在基板上的多晶硅层，多晶硅层包括源极、通道及漏极，其中源极及漏极形成在多晶硅层的二侧，形成在源极及漏极之间的通道；形成在多晶硅层上的栅极绝缘层；形成在栅极绝缘层上的栅极，且栅极形成在通道的正上方；形成在栅极上方且覆盖栅极的内层介电层，内层介电层通过离子布植植入氢原子且经高温快速回火形成氢化的内层介电层；穿过氢化的内层介电层的上表面的金属导线，且分别与源极及漏极接触；以及覆盖氢化的内层介电层的钝化层。
在本发明的一实施例中，半导体组件还包括画素电极。
在本发明的一实施例中，半导体组件还包括形成在基板与多晶硅层之间的遮光层。
在本发明的一实施例中，多晶硅层包括氧化硅及氮化硅。
在本发明的一实施例中，离子布植植入氢原子还能进一步植入氢原子到通道内。
根据本发明的另一实施例提供的半导体组件的制造方法，其包括提供基板；形成多晶硅层在基底上，其中多晶硅层包括源极、通道及漏极，源极及漏极形成在多晶硅层的二侧，通道形成在源极及漏极之间；形成栅极绝缘层在多晶硅层上；形成栅极在栅极绝缘层上，且栅极形成在通道的正上方；形成内层介电层在栅极上方且覆盖栅极，其中内层介电层通过离子布植植入氢原子且经高温快速回火形成氢化的内层介电层；形成金属导线，其中金属导线穿过氢化的内层介电层的上表面，且分别与源极及漏极接触；以及形成钝化层，其中钝化层覆盖氢化的内层介电层。
在本发明的一实施例中，半导体组件的制造方法还包括形成画素电极。
在本发明的一实施例中，半导体组件的制造方法还包括形成遮光层在基板与多晶硅层之间。
在本发明的一实施例中，多晶硅层包括氧化硅及氮化硅。
在本发明的一实施例中，离子布植植入氢原子还能进一步植入氢原子到通道内。
 有益效果
本发明提供的一种半导体组件能直接将氢原子植入到通道内，以达到氢化效果，且由于离子植入的均一性高，故氢化的均一性良好。
 附图说明
图1是本发明实施例的半导体组件的制造流程图；以及
图2是本发明实施例具有低温多晶硅薄膜晶体管的半导体组件的示意图。
 本发明的实施方式
为让本发明的上述内容能更明显易懂，下文配合所附图式作详细说明。
本发明的一实施例提供一种以低温多晶硅(LTPS)制程形成的薄膜晶体管的半导体组件。半导体组件包括基板、形成在基板上的多晶硅层、形成在多晶硅层二侧的源极及汲极、形成在源极及漏极之间的通道、形成在多晶硅层上的栅极绝缘层、形成在栅极绝缘层上的栅极、形成在栅极上方且覆盖栅极的内层介电层、穿过氢化的内层介电层的上表面的金属导线以及覆盖氢化的内层介电层的钝化层。具体而言，栅极形成在通道的正上方、内层介电层通过离子布植植入氢原子且经高温快速回火形成氢化的内层介电层，以及穿过氢化的内层介电层的上表面的金属导线分别与源极及漏极接触。在本发明的另外一实施例中，半导体组件还包括画素电极。
请参照图1及图2所示，在低温多晶硅薄膜晶体管的半导体组件的制程中，首先在基板10上形成遮光层20，其中遮光层20可防止光漏现象的发生，接着沉积氮化硅层30、氧化硅层40及非多晶硅层。非多晶硅层通过准分子激光回火(Excimer-Laser Annealing, ELA)形成多晶硅层50。遮光层20在基板10与多晶硅层50之间。形成多晶硅层50后，通过离子布值程序在多晶硅层50的二侧形成源极及漏极，且源极及漏极之间形成通道，接着形成栅极绝缘层60在多晶硅层50上，以及在栅极绝缘层60上形成栅极70，其中栅极70在通道的正上方。后续进一步形成N型金属-氧化物-半导体(n-MOS)及P型金属-氧化物-半导体(P-MOS)，以及在N型金属-氧化物-半导体及P型金属-氧化物-半导体上方形成内层介电层，且内层介电层覆盖所述栅极70，其中内层介电层包括氮化硅层80及氧化硅层90。值得注意的是，在结晶形成多晶硅层50的过程中会有不饱和键的形成。不饱和键会造成电荷载体陷阱(charge carrier traps)，影响电荷在通道中的移动，进而影响低温多晶硅薄膜晶体管的临界电压值偏光。因此，本发明实施例为了提高低温多晶硅薄膜晶体管的电流-电压特性及降低薄膜晶体管的临界电压值，通过离子布植100对内层介电层植入氢原子，接着且经高温快速回火形成氢化的内层介电层。详言之，内层介电层是通过两步骤形成，首先形成氮化硅层80，接着通过离子布植100对氮化硅层80植入氢原子，再进行高温快速回火形成氢化的氮化硅层80，其中高温快速回火是在450℃下进行，以及沉积氧化硅层90在氢化的氮化硅层80上方。由于离子植入的均一性高，还能直接将氢原子植入到通道内，以达到氢化效果，故氢化的均一性良好。接着对氢化的内层介电层100进行蚀刻以形成开孔，在开孔中沉积导电金属以制作金属导线(未图标)，金属导线穿过氢化的内层介电层的上表面且分别与源极及漏极做导电接触(未图示)，后续形成覆盖氢化的内层介电层及金属导线的钝化层(未图示)。后续制程可根据本领域通常技艺者依实际情况依序形成通用电极和金属导线连接的画素电极，最后再进行封装，因此不再赘述。
虽然本发明结合其具体实施例而被描述，应该理解的是，许多替代、修改及变化对于那些本领域的技术人员将是显而易见的。因此，其意在包含落入所附权利要求书的范围内的所有替代、修改及变化。

Claims (13)

  1. 一种半导体组件，包括：
    基板；
    多晶硅层，其中所述多晶硅层形成在所述基板上，所述多晶硅层包括源极、通道及漏极，所述源极及所述漏极形成在所述多晶硅层的二侧，所述通道形成在所述源极及所述漏极之间；
    栅极绝缘层，其中所述栅极绝缘层形成在所述多晶硅层上；
    栅极，其中所述栅极形成在所述栅极绝缘层上，且所述栅极形成在所述通道的正上方；
    内层介电层，其中所述内层介电层形成在所述栅极上方且覆盖所述栅极，所述内层介电层通过离子布植植入氢原子且经高温快速回火形成氢化的内层介电层；
    金属导线，其中所述金属导线穿过所述氢化的内层介电层的上表面，且分别与所述源极及所述漏极接触；
    钝化层，其中所述钝化层覆盖所述氢化的内层介电层；
    画素电极，其中所述画素电极与所述金属导线连接；以及
    遮光层，其中所述遮光层形成在所述基板与所述多晶硅层。
  2. 如权利要求1所述的半导体组件，其中，所述多晶硅层包括氧化硅及氮化硅。
  3. 如权利要求1所述的半导体组件，其中，所述离子布植植入氢原子还能进一步植入氢原子到所述通道内。
  4. 一种半导体组件，包括：
    基板；
    多晶硅层，其中所述多晶硅层形成在所述基板上，所述多晶硅层包括源极、通道及漏极，所述源极及所述漏极形成在所述多晶硅层的二侧，所述通道形成在所述源极及所述漏极之间；
    栅极绝缘层，其中所述栅极绝缘层形成在所述多晶硅层上；
    栅极，其中所述栅极形成在所述栅极绝缘层上，且所述栅极形成在所述通道的正上方；
    内层介电层，其中所述内层介电层形成在所述栅极上方且覆盖所述栅极，所述内层介电层通过离子布植植入氢原子且经高温快速回火形成氢化的内层介电层；
    金属导线，其中所述金属导线穿过所述氢化的内层介电层的上表面，且分别与所述源极及所述漏极接触；以及
    钝化层，其中所述钝化层覆盖所述氢化的内层介电层。
  5. 如权利要求4所述的半导体组件，其中，还包括画素电极，所述画素电极与所述金属导线连接。
  6. 如权利要求4所述的半导体组件，其中，还包括形成在所述基板与所述多晶硅层之间的遮光层。
  7. 如权利要求4所述的半导体组件，其中，所述多晶硅层包括氧化硅及氮化硅。
  8. 如权利要求4所述的半导体组件，其中，所述离子布植植入氢原子还能进一步植入氢原子到所述通道内。
  9. 一种半导体组件的制造方法，包括：
    提供基板；
    形成多晶硅层在所述基底上，其中所述多晶硅层包括源极、通道及漏极，所述源极及所述漏极形成在所述多晶硅层的二侧，所述通道形成在所述源极及所述漏极之间；
    形成栅极绝缘层在所述多晶硅层上；
    形成栅极在所述栅极绝缘层上，且所述栅极形成在所述通道的正上方；
    形成内层介电层在所述栅极上方且覆盖所述栅极，其中所述内层介电层通过离子布植植入氢原子且经高温快速回火形成氢化的内层介电层；
    形成金属导线，其中所述金属导线穿过所述氢化的内层介电层的上表面，且分别与所述源极及所述漏极接触；以及
    形成钝化层，其中所述钝化层覆盖所述氢化的内层介电层。
  10. 如权利要求9所述的半导体组件的制造方法，其中，还包括形成画素电极。
  11. 如权利要求9所述的半导体组件的制造方法，其中，还包括形成遮光层在所述基板与所述多晶硅层之间。
  12. 如权利要求9所述的半导体组件的制造方法，其中，所述多晶硅层包括氧化硅及氮化硅。
  13. 如权利要求9所述的半导体组件的制造方法，其中，所述离子布植植入氢原子还能进一步植入氢原子到所述通道内。
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CN101097369A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 液晶显示装置及其制造方法
CN102226997A (zh) * 2004-05-14 2011-10-26 株式会社半导体能源研究所 发光器件
CN106952963A (zh) * 2017-03-29 2017-07-14 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、阵列基板、显示装置
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CN101097369A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 液晶显示装置及其制造方法
CN106952963A (zh) * 2017-03-29 2017-07-14 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、阵列基板、显示装置
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