CN107507836A - 一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法 - Google Patents
一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法 Download PDFInfo
- Publication number
- CN107507836A CN107507836A CN201710655302.6A CN201710655302A CN107507836A CN 107507836 A CN107507836 A CN 107507836A CN 201710655302 A CN201710655302 A CN 201710655302A CN 107507836 A CN107507836 A CN 107507836A
- Authority
- CN
- China
- Prior art keywords
- manufacturing
- region
- film transistor
- thin film
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 239000010409 thin film Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000012212 insulator Substances 0.000 claims abstract description 37
- 239000010408 film Substances 0.000 claims abstract description 34
- 238000005984 hydrogenation reaction Methods 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 230000000694 effects Effects 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 38
- 239000007769 metal material Substances 0.000 claims description 19
- 238000003491 array Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims 2
- 238000005516 engineering process Methods 0.000 abstract description 13
- 239000000463 material Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000000034 method Methods 0.000 description 10
- 239000004411 aluminium Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000001994 activation Methods 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 2
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000011734 sodium Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
本发明公开了一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法,其中,低温多晶硅阵列基板的制程方法包括:提供基板;在基板上形成多晶硅半导体图案,对应于第一类型薄膜晶体管的多晶硅半导体图案中形成有第一沟道区域、第一源极区域和第一漏极区域;形成栅极绝缘层;进行活性处理;经过活性处理后,在栅极绝缘层上形成栅极;在栅极绝缘层和栅极上形成层间绝缘层;进行氢化处理;经过氢化处理后,在层间绝缘层上形成源/漏极图案,且使源/漏极图案分别通过通孔与多晶硅半导体图案中的源极区域和漏极区域相连。通过上述方式,本发明能够使得低温多晶硅技术应用至大尺寸屏幕中。
Description
技术领域
本发明涉及显示技术领域,特别是涉及一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法。
背景技术
在显示面板的制作过程中,低温多晶硅(Low Temperature Poly-silicon,LTPS)技术因具有高迁移率、低成本等优点逐渐占领了中小尺寸显示屏幕的市场。
目前,LTPS技术在制程方法中,需经过氢化和活化处理的步骤,使得LIPS技术所制作的产品只能使用钼等熔点较高的金属材料,而钼等熔点高的金属材料的阻值较高。
本申请的发明人在长期的研发过程中,发现LTPS技术的制程方法中,氢化和活化处理的步骤中,温度大于等于500摄氏度,使得LIPS 技术只能采用熔点较高的金属材料,无法满足大尺寸屏幕的需求,从而 LTPS技术无法应用至大尺寸显示屏幕的制作工艺中。
发明内容
本发明主要解决的技术问题是提供一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法,能够将熔点较低的金属材料应用至LTPS技术中,使得大尺寸屏幕可以采用LTPS技术制作,从而大尺寸屏幕同样具有高迁移率以及低成本的优点。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种低温多晶硅(LowTemperature Poly-Silicon)阵列基板的制程方法,所述低温多晶硅阵列基板包括像素区域和驱动区域,其中,所述像素区域包括多个阵列排列的像素,且每个像素包括一个对应的第一类型薄膜晶体管和一个对应的像素电极;而所述驱动区域包括CMOS电路所组成的驱动电路,每个CMOS电路包括一个第一类型薄膜晶体管和一个第二类型薄膜晶体管,其中,所述制程方法包括:
提供基板;
在所述基板上形成多晶硅半导体图案,其中,对应于所述第一类型薄膜晶体管的所述多晶硅半导体图案中形成有第一沟道区域、第一源极区域和第一漏极区域;
形成栅极绝缘层;
进行活性处理;
经过活性处理后,在所述栅极绝缘层上形成栅极;
在所述栅极绝缘层和所述栅极上形成层间绝缘层;
进行氢化处理;
经过氢化处理后,在所述层间绝缘层上形成源/漏极图案,且使所述源/漏极图案分别通过通孔与所述多晶硅半导体图案中的所述源极区域和所述漏极区域相连。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种低温多晶硅(Low Temperature Poly-Silicon)薄膜晶体管的制程方法,包括:
提供基板;
在所述基板上形成多晶硅半导体层,其中,形成的所述多晶硅半导体层中形成有沟道区域、源极区域和漏极区域;
形成栅极绝缘层;
进行活性处理;
经过活性处理后,在所述栅极绝缘层上形成栅极;
在所述栅极绝缘层和所述栅极上形成层间绝缘层;
经过氢化处理;
经过氢化处理后,在所述层间绝缘层上形成源/漏极,且使所述源/ 漏极分别通过通孔与所述多晶硅半导体层中的所述源极区域和所述漏极区域相连。
本发明的有益效果是:区别于现有技术的情况,本发明提供的低温多晶硅(LowTemperature Poly-Silicon)阵列基板的制程方法,所述低温多晶硅阵列基板包括像素区域和驱动区域,其中,所述像素区域包括多个阵列排列的像素,且每个像素包括一个对应的第一类型薄膜晶体管和一个对应的像素电极;而所述驱动区域包括CMOS电路所组成的驱动电路,每个CMOS电路包括一个第一类型薄膜晶体管和一个第二类型薄膜晶体管,所述制程方法包括:提供基板;在所述基板上形成多晶硅半导体图案,其中,对应于所述第一类型薄膜晶体管的所述多晶硅半导体图案中形成有第一沟道区域、第一源极区域和第一漏极区域;形成栅极绝缘层;进行活性处理;经过活性处理后,在所述栅极绝缘层上形成栅极;在所述栅极绝缘层和所述栅极上形成层间绝缘层;进行氢化处理;经过氢化处理后,在所述层间绝缘层上形成源/漏极图案,且使所述源/漏极图案分别通过通孔与所述多晶硅半导体图案中的所述源极区域和所述漏极区域相连。本发明提供的制程方法,经过活性处理后,在栅极绝缘层上形成栅极,进行氢化处理,如此,活性处理与氢化处理分开进行,氢化处理的温度可低于活性处理的温度,且活化处理在形成栅极的步骤之前进行。在该制程方法中,栅极的材料的选择不仅限于熔点较高的钼等金属材料,还可以为熔点较低的钛、铝、铜等金属材料,如此,LTPS 技术可以应用至大尺寸屏幕的制程方法中,使得大尺寸屏幕在保证品质的同时,还具有高迁移率、低成本的优点。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。其中:
图1是本发明低温多晶硅阵列基板的制程方法一实施方式的流程示意图;
图2(a)-图2(g)是本发明低温多晶硅阵列基板的制作方法过程中的结构流程示意图。
图3是本发明低温多晶硅薄膜晶体管的制程方法一实施方式的流程示意图;
图4是图3中的制程方法所制成的低温多晶硅薄膜晶体管的剖面结构示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
低温多晶硅(Low Temperature Poly-Silicon)阵列基板包括像素区域和驱动区域,其中,像素区域包括多个阵列排列的像素,且每个像素包括一个对应的第一类型薄膜晶体管和一个对应的像素电极;而驱动区域包括CMOS电路所组成的驱动电路,每个CMOS电路包括一个第一类型薄膜晶体管和一个第二类型薄膜晶体管,其中,第一类型薄膜晶体管为n型薄膜晶体管,第二类型薄膜晶体管为p型薄膜晶体管。
请参阅图1,本发明提供一实施方式的低温多晶硅阵列基板100的制程方法,制程方法包括如下步骤:
步骤S101,提供基板10。
在一实施方式中,基板10可以为玻璃基板。
步骤S102,请参阅图2(a),在基板10上形成至少一缓冲层20。
本实施方式中,在基板10上形成一缓冲层20。
可以理解,缓冲层20可以有效防止玻璃基板中的金属离子,例如铝、钡、钠等在后续工艺中扩散至有源区;另外,有利于降低热传导。
步骤S103,请参阅图2(b),在缓冲层20上形成多晶硅半导体图案30,其中,对应于第一类型薄膜晶体管的多晶硅半导体图案30中形成有第一沟道区域31、第一源极区域32和第一漏极区域33。
具体的,步骤S103包括:
形成多晶硅半导体图案30;
在对应于第一类型薄膜晶体管的多晶硅半导体图案30中进行沟道掺杂;
在对应于第一类型薄膜晶体管的多晶硅半导体图案30中进行源/漏区域掺杂以使对应于第一类型薄膜晶体管的多晶硅半导体图案30中形成第一沟道区域31、第一源极区域32和第一漏极区域33。
在一实施方式中,在形成缓冲层20之前,形成一遮光层图案,第一类型薄膜晶体管的多晶硅半导体图案30在光照射下会出现漏电的现象,通过在基板10上设置一遮光图案,使第一类型薄膜晶体管不受外界光照的影响而出现漏电的现象。
可以理解,进行沟道掺杂、源/漏区域掺杂是通过离子注入的方式。
可以理解,在一实施方式中,多晶硅半导体层30形成在基板10上。
步骤S104,请参阅图2(c),形成栅极绝缘层40。
其中,栅极绝缘层40为氧化硅层或氮化硅层与氧化硅层的复合层。
步骤S105,请参阅图2(d),对多晶硅半导体图案30进行轻掺杂,以在对应于第二类型薄膜晶体管的多晶硅半导体图案30中形成第二沟道区域35、第二源极区域36、第二漏极区域37,且在对应于第一类型薄膜晶体管的多晶硅半导体图案30的第一源极区域32/第一漏极区域33 与第一沟道区域31之间形成轻掺杂区域38。
在一实施方式中,通过离子注入的方式形成轻掺杂区域38。
步骤S106,进行活性处理。
其中,活性处理的温度大于等于500摄氏度。
可以理解,进行沟道掺杂、源/漏极区域掺杂以及轻掺杂时,多晶硅半导体中的原子与原子之间的化学键受到破坏,通过活性处理,可以有效将已破坏的化学键重新连接。
步骤S107,请参阅图2(e),经过活性处理后,在栅极绝缘层40 上形成栅极50。
在一实施方式中,栅极50的材料为熔点小于500摄氏度的金属材料,进一步的,栅极50的材料为熔点大于等于400摄氏度,且小于500 摄氏度的金属材料,例如钛、铝、铜等金属材料。
可以理解,栅极50间隔设置于栅极绝缘层40上。
步骤S108,请参阅图2(f),在栅极绝缘层40和栅极50上形成层间绝缘层60。
其中,在形成层间绝缘层60的过程中,进一步形成多个通孔61,多个通孔61贯穿层间绝缘层60以及栅极绝缘层40。
在一实施方式中,间绝缘层60可以为氮化硅、氧化硅或氮化硅与氧化硅的复合层。
步骤S109,进行氢化处理。
在一实施方式中,氢化处理的温度大于等于400摄氏度而小于500 摄氏度,以使得栅极50的材料可以为熔点大于等于400摄氏度,且小于500摄氏度的金属材料。
可以理解,多晶硅晶粒之间存在粒界态,多晶硅与氧化层间存在界面态,影响薄膜晶体管的电性,而氢化处理可以将间绝缘层60中的氢原子填补多晶硅原子的未结合键或未饱和键,粒界态、氧化层缺陷以及界面态,减少不稳态数目,提升迁移率,阈值电压均匀性。
步骤S110,请参阅图2(g),经过氢化处理后,在层间绝缘层60 上形成源/漏极图案70,且使源/漏极图案70分别通过通孔61与多晶硅半导体图案30中的源极区域和漏极区域相连。
区别于现有技术的情况,本实施方式提供的低温多晶硅(Low Temperature Poly-Silicon)阵列基板100的制程方法,低温多晶硅阵列基板10包括像素区域和驱动区域,其中,像素区域包括多个阵列排列的像素,且每个像素包括一个对应的第一类型薄膜晶体管和一个对应的像素电极;而驱动区域包括CMOS电路所组成的驱动电路,每个CMOS 电路包括一个第一类型薄膜晶体管和一个第二类型薄膜晶体管,其中,制程方法包括:提供基板10;在基板10上形成多晶硅半导体图案30,其中,对应于第一类型薄膜晶体管的多晶硅半导体图案30中形成有第一沟道区域、第一源极区域和第一漏极区域;形成栅极绝缘层40;进行活性处理;经过活性处理后,在栅极绝缘层40上形成栅极50;在栅极绝缘层40和栅极50上形成层间绝缘层60;进行氢化处理;经过氢化处理后,在层间绝缘层60上形成源/漏极图案70,且使源/漏极图案70分别通过通孔61与多晶硅半导体图案30中的源极区域和漏极区域相连。本实施方式提供的制程方法,经过活性处理后,在栅极绝缘层40上形成栅极50,进行氢化处理,如此,活性处理与氢化处理分开进行,氢化处理的温度可低于活性处理的温度,且活化处理在形成栅极50的步骤之前进行。在该制程方法中,栅极50的材料的选择不仅限于熔点较高的钼等金属材料,还可以为熔点较低的钛、铝、铜等金属材料,如此, LTPS技术可以应用至大尺寸屏幕的制程方法中,使得大尺寸屏幕在保证品质的同时,具有高迁移率、低成本的优点。
请结合参阅图3以及图4,本发明还提供一实施方式的低温多晶硅薄膜晶体管200的制程方法,包括:
步骤S201,提供基板210。
在一实施方式中,基板210可以为玻璃基板。
步骤S202,在基板210上形成至少一缓冲层220。
本实施方式中,在基板210上形成一缓冲层220。
可以理解,缓冲层220可以有效防止玻璃基板中的金属离子,例如铝、钡、钠等在后续工艺中扩散至有源区;另外,有利于降低热传导。
在一实施方式中,在形成缓冲层220之前,在基板210上形成遮光层。
其中,遮光层为不透光的材料制成。
步骤S203,在缓冲层220上形成多晶硅半导体层230,其中,形成的多晶硅半导体层230中形成有沟道区域231、源极区域232和漏极区域233。
具体的,步骤S203包括:
形成多晶硅半导体层230;
在多晶硅半导体层230上进行沟道掺杂;
在多晶硅半导体层230中进行源/漏区域掺杂以使多晶硅半导体层 230中形成沟道区域231、源极区域232和漏极区域233。
可以理解,进行沟道掺杂、源/漏区域掺杂是通过离子注入的方式。
可以理解,薄膜晶体管的多晶硅半导体图案在光照射下会出现漏电的现象,通过设置一遮光层,使薄膜晶体管不受外界光照的影响而出现漏电的现象。
可以理解,在一实施方式中,多晶硅半导体层230形成在基板210 上。
步骤S204,形成栅极绝缘层240。
在一实施方式中,栅极绝缘层240可以为氧化硅层或氮化硅层与氧化硅层的复合层。
步骤S205,对多晶硅半导体图案230进行轻掺杂,以在多晶硅半导体图案230的第一源极区域232/第一漏极区域233与第一沟道区域231 之间形成轻掺杂区域234。
步骤S206,进行活性处理。
其中,活性处理的温度大于等于500摄氏度。
可以理解,在形成有沟道区域231、源极区域232和漏极区域233 的过程,即进行沟道掺杂、源/漏极270区域掺杂时,多晶硅半导体中的原子与原子之间的化学键受到破坏,通过活性处理,可以有效将已破坏的化学键重新连接。
步骤S207,经过活性处理后,在栅极绝缘层240上形成栅极250。
其中,栅极250的材料为熔点小于500摄氏度的金属材料,进一步的,栅极的材料为熔点大于等于400摄氏度,小于500摄氏度的金属材料,例如钛、铝、铜等金属材料。
步骤S208,在栅极绝缘层240和栅极250上形成层间绝缘层260。
其中,在形成层间绝缘层260的过程中,形成有通孔261,通孔261 贯通层间绝缘层260以及栅极绝缘层240。
在一实施方式中,层间绝缘层260可为氮化硅、氧化硅或氮化硅与氧化硅的复合层。
步骤S209,经过氢化处理。
在一实施方式中,氢化处理的温度大于等于400摄氏度而小于500 摄氏度,使得栅极的材料可为熔点大于等于400摄氏度,小于500摄氏度的金属材料,例如钛、铝、铜等金属材料。
可以理解,多晶硅晶粒之间存在粒界态,多晶硅与氧化层间存在界面态,影响薄膜晶体管的电性,而氢化处理可以将间绝缘层中的氢原子填补多晶硅原子的未结合键或未饱和键,粒界态、氧化层缺陷以及界面态,减少不稳态数目,提升迁移率,阈值电压均匀性。
步骤S210,经过氢化处理后,在层间绝缘层260上形成源/漏极270,且使源/漏极270分别通过通孔261与多晶硅半导体层230中的源极区域 232和漏极区域233相连。
区别于现有技术的情况,本实施方式提供的低温多晶硅(Low Temperature Poly-Silicon)薄膜晶体管的制程方法,包括:提供基板210;在基板210上形成多晶硅半导体层230,其中,形成的多晶硅半导体层 230中形成有沟道区域231、源极区域232和漏极区域233;形成栅极绝缘层240;进行活性处理;经过活性处理后,在栅极绝缘层240上形成栅极;在栅极上形成层间绝缘层260;经过氢化处理;经过氢化处理后,在层间绝缘层260上形成源/漏极270,且使源/漏极270分别通过通孔 261与多晶硅半导体层230中的源极区域232和漏极区域233相连。本实施方式提供的制程方法,经过活性处理后,在栅极绝缘层240上形成栅极,进行氢化处理,如此,活性处理与氢化处理分开进行,氢化处理的温度可低于活性处理的温度,且活化处理在形成栅极的步骤之前进行。在该制程方法中,栅极的材料的选择不仅限于熔点较高的钼等金属材料,还可以为熔点较低的钛、铝、铜等金属材料,如此,LTPS技术可以应用至大尺寸屏幕的制程方法中,使得大尺寸屏幕在保证品质的同时,还具有高迁移率、低成本的优点。
以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。
Claims (10)
1.一种低温多晶硅(Low Temperature Poly-Silicon)阵列基板的制程方法,其特征在于,所述低温多晶硅阵列基板包括像素区域和驱动区域,其中,所述像素区域包括多个阵列排列的像素,且每个像素包括一个对应的第一类型薄膜晶体管和一个对应的像素电极;而所述驱动区域包括CMOS电路所组成的驱动电路,每个CMOS电路包括一个第一类型薄膜晶体管和一个第二类型薄膜晶体管,其中,所述制程方法包括:
提供基板;
在所述基板上形成多晶硅半导体图案,其中,对应于所述第一类型薄膜晶体管的所述多晶硅半导体图案中形成有第一沟道区域、第一源极区域和第一漏极区域;
形成栅极绝缘层;
进行活性处理;
经过活性处理后,在所述栅极绝缘层上形成栅极;
在所述栅极绝缘层和所述栅极上形成层间绝缘层;
进行氢化处理;
经过氢化处理后,在所述层间绝缘层上形成源/漏极图案,且使所述源/漏极图案分别通过通孔与所述多晶硅半导体图案中的所述源极区域和所述漏极区域相连。
2.根据权利要求1所述的制程方法,其特征在于,在所述基板上形成多晶硅半导体图案的步骤,进一步包括:
形成多晶硅半导体图案;
在对应于所述第一类型薄膜晶体管的所述多晶硅半导体图案中进行沟道掺杂;
在对应于所述第一类型薄膜晶体管的所述多晶硅半导体图案中进行源/漏区域掺杂以使对应于所述第一类型薄膜晶体管的所述多晶硅半导体图案中形成所述第一沟道区域、所述第一源极区域和所述第一漏极区域。
3.根据权利要求2所述的制程方法,其特征在于,在形成栅极绝缘层的步骤之后,所述制程方法进一步包括:
对所述多晶硅半导体图案进行轻掺杂,以在对应于所述第二类型薄膜晶体管的所述多晶硅半导体图案中形成第二沟道区域、第二源极区域和第二漏极区域,且在对应于所述第一类型薄膜晶体管的所述多晶硅半导体图案的所述第一源极区域/第一漏极区域与所述第一沟道区域之间形成轻掺杂区域。
4.根据权利要求1所述的制程方法,其特征在于,所述活性处理的温度大于等于500摄氏度,而所述氢化处理的温度大于等于400摄氏度而小于500摄氏度,以使所述栅极能够采用熔点小于500摄氏度的金属材料。
5.根据权利要求1所述的制程方法,其特征在于,所述第一类型薄膜晶体管为n型薄膜晶体管,而所述第二类型薄膜晶体管为p型薄膜晶体管。
6.根据权利要求1所述的制程方法,其特征在于,在所述基板上形成多晶硅半导体图案的步骤之前,所述制程方法进一步包括:
在所述基板上形成至少一缓冲层。
7.根据权利要求6所述的制程方法,其特征在于,在所述基板上形成至少一缓冲层的步骤之前,所述制程方法进一步包括:
在所述基板上形成遮光图案。
8.一种低温多晶硅(Low Temperature Poly-Silicon)薄膜晶体管的制程方法,其特征在于,包括:
提供基板;
在所述基板上形成多晶硅半导体层,其中,形成的所述多晶硅半导体层中形成有沟道区域、源极区域和漏极区域;
形成栅极绝缘层;
进行活性处理;
经过活性处理后,在所述栅极绝缘层上形成栅极;
在所述栅极绝缘层和所述栅极上形成层间绝缘层;
经过氢化处理;
经过氢化处理后,在所述层间绝缘层上形成源/漏极,且使所述源/漏极分别通过通孔与所述多晶硅半导体层中的所述源极区域和所述漏极区域相连。
9.根据权利要求8所述的制程方法,其特征在于,所述活性处理的温度大于等于500摄氏度,而所述氢化处理的温度大于等于400摄氏度而小于500摄氏度,以使所述栅极能够采用熔点小于500摄氏度的金属材料。
10.根据权利要求8所述的制程方法,其特征在于,在所述基板上形成多晶硅半导体层的步骤,进一步包括:
形成多晶硅半导体层;
在所述多晶硅半导体层上进行沟道掺杂;
在所述多晶硅半导体层中进行源/漏区域掺杂以使所述多晶硅半导体层中形成所述沟道区域、所述源极区域和所述漏极区域。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710655302.6A CN107507836A (zh) | 2017-08-02 | 2017-08-02 | 一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法 |
US15/737,131 US10658402B2 (en) | 2017-08-02 | 2017-09-21 | Manufacturing methods for low temperature poly-silicon array substrate and low temperature poly-silicon thin-film transistor |
PCT/CN2017/102658 WO2019024195A1 (zh) | 2017-08-02 | 2017-09-21 | 一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710655302.6A CN107507836A (zh) | 2017-08-02 | 2017-08-02 | 一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN107507836A true CN107507836A (zh) | 2017-12-22 |
Family
ID=60689708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710655302.6A Pending CN107507836A (zh) | 2017-08-02 | 2017-08-02 | 一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10658402B2 (zh) |
CN (1) | CN107507836A (zh) |
WO (1) | WO2019024195A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108962975A (zh) * | 2018-06-26 | 2018-12-07 | 武汉华星光电技术有限公司 | 一种低温多晶硅薄膜晶体管及其制作方法、显示装置 |
CN109509758A (zh) * | 2018-11-30 | 2019-03-22 | 武汉华星光电技术有限公司 | 半导体组件及其制造方法 |
WO2020113763A1 (zh) * | 2018-12-03 | 2020-06-11 | 武汉华星光电半导体显示技术有限公司 | 一种薄膜晶体管的制备方法 |
WO2021147655A1 (zh) * | 2020-01-20 | 2021-07-29 | 京东方科技集团股份有限公司 | 显示装置、阵列基板、薄膜晶体管及其制造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110752219B (zh) * | 2019-10-29 | 2022-07-26 | 昆山国显光电有限公司 | 一种薄膜晶体管和显示面板 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101083271A (zh) * | 1999-09-24 | 2007-12-05 | 株式会社半导体能源研究所 | 电致发光显示器及电子设备 |
US20080002081A1 (en) * | 2006-06-30 | 2008-01-03 | Lg Philips Lcd Co., Ltd. | Liquid crystal display device and method of fabricating the same |
CN101958250A (zh) * | 2010-06-28 | 2011-01-26 | 四川虹视显示技术有限公司 | 低温多晶硅tft的制作工艺 |
CN103296058A (zh) * | 2013-03-22 | 2013-09-11 | 友达光电股份有限公司 | 显示面板及其制作方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6590229B1 (en) * | 1999-01-21 | 2003-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and process for production thereof |
US8853696B1 (en) * | 1999-06-04 | 2014-10-07 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and electronic device |
JP4969001B2 (ja) * | 2001-09-20 | 2012-07-04 | 株式会社半導体エネルギー研究所 | 半導体装置及びその作製方法 |
-
2017
- 2017-08-02 CN CN201710655302.6A patent/CN107507836A/zh active Pending
- 2017-09-21 US US15/737,131 patent/US10658402B2/en active Active
- 2017-09-21 WO PCT/CN2017/102658 patent/WO2019024195A1/zh active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101083271A (zh) * | 1999-09-24 | 2007-12-05 | 株式会社半导体能源研究所 | 电致发光显示器及电子设备 |
US20080002081A1 (en) * | 2006-06-30 | 2008-01-03 | Lg Philips Lcd Co., Ltd. | Liquid crystal display device and method of fabricating the same |
CN101958250A (zh) * | 2010-06-28 | 2011-01-26 | 四川虹视显示技术有限公司 | 低温多晶硅tft的制作工艺 |
CN103296058A (zh) * | 2013-03-22 | 2013-09-11 | 友达光电股份有限公司 | 显示面板及其制作方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108962975A (zh) * | 2018-06-26 | 2018-12-07 | 武汉华星光电技术有限公司 | 一种低温多晶硅薄膜晶体管及其制作方法、显示装置 |
CN109509758A (zh) * | 2018-11-30 | 2019-03-22 | 武汉华星光电技术有限公司 | 半导体组件及其制造方法 |
WO2020107671A1 (zh) * | 2018-11-30 | 2020-06-04 | 武汉华星光电技术有限公司 | 半导体组件及其制造方法 |
WO2020113763A1 (zh) * | 2018-12-03 | 2020-06-11 | 武汉华星光电半导体显示技术有限公司 | 一种薄膜晶体管的制备方法 |
WO2021147655A1 (zh) * | 2020-01-20 | 2021-07-29 | 京东方科技集团股份有限公司 | 显示装置、阵列基板、薄膜晶体管及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2019024195A1 (zh) | 2019-02-07 |
US10658402B2 (en) | 2020-05-19 |
US20190386031A1 (en) | 2019-12-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107507836A (zh) | 一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法 | |
CN105489552A (zh) | Ltps阵列基板的制作方法 | |
JPH10335672A (ja) | 薄膜トランジスタ及び薄膜トランジスタを用いた半導体装置 | |
US10409115B2 (en) | Liquid crystal display panel, array substrate and manufacturing method thereof | |
CN104240633A (zh) | 薄膜晶体管和有源矩阵有机发光二极管组件及其制造方法 | |
CN104882485A (zh) | 薄膜晶体管及其制造方法 | |
CN111599824B (zh) | 一种阵列基板、制备方法以及显示装置 | |
US9773921B2 (en) | Combo amorphous and LTPS transistors | |
TW554538B (en) | TFT planar display panel structure and process for producing same | |
TW200302386A (en) | Semiconductor display device, method for making the same, and active matrix type display device | |
CN105679705A (zh) | 阵列基板的制作方法 | |
CN104091832A (zh) | 薄膜晶体管及其制作方法、阵列基板和显示装置 | |
CN103996655B (zh) | 一种阵列基板及其制备方法,显示面板、显示装置 | |
JP5328015B2 (ja) | 画像表示システム及びその製造方法 | |
CN105261636B (zh) | 一种薄膜晶体管、其制备方法、阵列基板及显示装置 | |
JP2006324431A (ja) | 半導体装置およびその製造方法 | |
CN109037232B (zh) | 阵列基板及其制造方法、显示面板以及显示装置 | |
CN114628529B (zh) | 驱动背板及其制备方法、显示面板 | |
CN109545798B (zh) | 一种阵列基板及其制作方法 | |
CN107256869A (zh) | 一种阵列基板及其制作方法 | |
KR100540885B1 (ko) | 박막 트랜지스터 및 그 제조방법 | |
KR20010041092A (ko) | Cmos 트랜지스터 및 관련 소자의 제조 방법 | |
JPH0279027A (ja) | 多結晶シリコン薄膜トランジスタ | |
JP4055317B2 (ja) | 薄膜トランジスタの製造方法 | |
KR100623230B1 (ko) | 박막 트랜지스터의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171222 |
|
RJ01 | Rejection of invention patent application after publication |