WO2020103190A1 - 一种显示装置的驱动电路和显示装置 - Google Patents

一种显示装置的驱动电路和显示装置

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Publication number
WO2020103190A1
WO2020103190A1 PCT/CN2018/119069 CN2018119069W WO2020103190A1 WO 2020103190 A1 WO2020103190 A1 WO 2020103190A1 CN 2018119069 W CN2018119069 W CN 2018119069W WO 2020103190 A1 WO2020103190 A1 WO 2020103190A1
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WIPO (PCT)
Prior art keywords
transmission signal
signal line
signal lines
clock signal
driving circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/119069
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English (en)
French (fr)
Inventor
何怀亮
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HKC Co Ltd
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HKC Co Ltd
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Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US16/349,985 priority Critical patent/US11361724B2/en
Publication of WO2020103190A1 publication Critical patent/WO2020103190A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, and in particular to a driving circuit and a display device of a display device.
  • the liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and has been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module (Backlight Module).
  • the liquid crystal panel includes a color filter substrate (Color Filter Substrate, CF Substrate, also known as a color filter substrate), an array substrate (Thin Film Transistor Substrate, TFT Substrate), and a transparent electrode exists on the opposite inner side of the substrate.
  • a layer of liquid crystal molecules (LiquidCrystal, LC) is sandwiched between the two substrates, and setting a shift register (GOA, gate on array) on the array substrate is an important technology in panel design.
  • the main advantage is that the door can be eliminated
  • the gate driver IC gate driver IC reduces the cost.
  • the original scan driver function uses the array substrate (array) exposure development method to generate a logic circuit to drive the scan data line.
  • the shift register uses the clock signal to pass through the gate The circuit drives the scan line.
  • the present application provides a driving circuit and a display device for a display device. What is to be solved is that the display panel has a uniform display effect.
  • a driving circuit for a display panel including:
  • the scan driving circuit includes: a plurality of groups of transmission signal lines; a group of clock signal lines, which are respectively connected to the timing drive circuit signals to obtain a gate driving clock signal; a compensation capacitor is provided in parallel with each transmission signal line;
  • Each transmission signal line in each group of transmission signal lines is respectively connected to a clock signal line corresponding to a group of clock signal lines;
  • the scan driving circuit includes a common electrode layer and a metal bridge hole; each of the transmission signal lines is connected to a corresponding one of the clock signal lines through the metal bridge hole;
  • the metal bridge hole includes a conductive layer, a first bridge hole and a second bridge hole
  • the clock signal line and the transmission signal line are in different processes; the conductive layer is connected to the clock signal line to form a first bridge hole; the conductive layer is connected to the transmission signal line to form a second bridge hole;
  • the common electrode layer and the conductive layer form a compensation capacitor
  • the metal bridge hole corresponding to the transmission signal line farthest from the timing driving circuit has at least one first bridge hole.
  • each transmission signal line connecting the same clock signal line in each transmission signal line connecting the same clock signal line, the number of first bridge holes corresponding to a transmission signal line closer to the timing driving circuit more.
  • the area of the conductive layer corresponding to one of the transmission signal lines close to the timing driving circuit is smaller.
  • the area of the conductive layer corresponding to a transmission signal line closer to the timing driving circuit is smaller .
  • the sum of the compensation capacitance of each transmission signal line and the parasitic capacitance of the corresponding transmission signal line is equal.
  • the present application also discloses a drive circuit for a display panel, including: a timing drive circuit and a scan drive circuit;
  • the scan driving circuit includes: a plurality of groups of transmission signal lines; a group of clock signal lines, which are respectively connected to the timing driving circuit signals to obtain a gate driving clock signal; a common electrode layer; and a metal bridge hole;
  • Each transmission signal line in each group of transmission signal lines is respectively connected to a clock signal line corresponding to a group of clock signal lines; each transmission signal line is connected to a corresponding one of the The clock signal line is connected;
  • the metal bridge hole includes a conductive layer, a first bridge hole and a second bridge hole;
  • the clock signal line and the transmission signal line are in different processes; the conductive layer is connected to the clock signal line to form a first bridge hole; the conductive layer is connected to the transmission signal line to form a second bridge hole;
  • the number of first bridge holes corresponding to a transmission signal line closer to the timing driving circuit is greater.
  • the present application also discloses a display device.
  • the display device includes a driving circuit, and the driving circuit includes:
  • the scan drive circuit includes:
  • a group of clock signal lines which are respectively signal-connected with the timing drive circuit to obtain the gate drive clock signal
  • the compensation capacitor is set in parallel with each of the transmission signal lines;
  • Each transmission signal line in each group of the transmission signal lines is respectively connected to a clock signal line corresponding to a group of the clock signal lines;
  • the compensation capacitor corresponding to the transmission signal line closer to the timing driving circuit is smaller.
  • the scan driving circuit includes a common electrode layer and a metal bridge hole; each of the transmission signal lines is connected to a corresponding one of the clock signal lines through the metal bridge hole;
  • the metal bridge hole includes a conductive layer, a first bridge hole and a second bridge hole;
  • the clock signal line and the transmission signal line are in different processes; the conductive layer is connected to the clock signal line to form a first bridge hole; the conductive layer is connected to the transmission signal line to form a second bridge hole;
  • the common electrode layer and the conductive layer form the compensation capacitor.
  • the closer to the timing drive circuit the greater the number of first bridge holes corresponding to the transmission signal lines.
  • the metal bridge hole corresponding to the transmission signal line farthest from the timing driving circuit has at least one first bridge hole.
  • the closer to the timing drive circuit is the number of first bridge holes corresponding to a transmission data line many.
  • the area of the conductive layer corresponding to one of the transmission signal lines close to the timing driving circuit is smaller.
  • the area of the conductive layer corresponding to a transmission data line closer to the timing drive circuit is smaller.
  • the sum of the compensation capacitance of each transmission signal line and the parasitic capacitance of the corresponding transmission signal line is equal.
  • the present application is directed to the same group of transmission signal lines connected to different clock signal lines.
  • the capacitance of the transmission signal line corresponding to the clock signal line close to the display area is connected to the clock signal line away from the display area.
  • the capacitance of the transmission signal line has different losses due to different capacitances.
  • reduce the capacitance of the corresponding transmission signal line connected to the clock signal line near the display area to balance the situation that the difference in capacitance caused by the difference in cable arrangement causes different losses In this way, the capacitance loss of one transmission signal line far away from the timing control chip in a group of transmission signal lines becomes smaller, which makes the display panel display more uniform.
  • FIG. 1 is a schematic diagram of a display device according to one embodiment of the present application.
  • FIG. 2 is a schematic diagram of another display device according to one embodiment of the present application.
  • FIG. 3 is a schematic diagram of a GOA circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a clock signal according to one embodiment of the present application.
  • FIG. 5 is a schematic diagram of another display panel according to one embodiment of the present application.
  • FIG. 6 is a schematic diagram of a scan driving circuit according to one embodiment of the present application.
  • FIG. 7 is a schematic diagram of another scan driving circuit according to one embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of a metal bridge hole along line AA 'according to one embodiment of the present application.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • the shift register GOA gate on array
  • the shift register GOA (gate on array) is provided on the array substrate in the panel design, which can eliminate the gate driver IC (gate driver IC), reduce costs, and the original scan driver (gate driver) ) Function uses the array substrate array exposure development method to generate a logic circuit to drive the scan data line, and the shift register uses the clock signal to drive the scan line through the gate circuit.
  • BP is the boost point
  • OP is the output.
  • Q is the Q-point precharge
  • G is the Gate output.
  • the principle of the GOA circuit is developed on the basis of the Thompson circuit.
  • the boost point has a precharge signal (st) to precharge the point, so that the boost point and the clock
  • the boost point reaches the high voltage level, and the thin film transistor (TFT) is turned on to allow the signal to pass smoothly.
  • a group of clock signal lines 17 includes eight clock signal lines 17, one clock signal line 17 corresponds to 135 scanning lines 14, and a group of scanning line 14 corresponds to eight scanning lines 14, and the corresponding eight
  • the transmission signal line 16 is connected to the eight clock signal lines 17 one by one.
  • an embodiment of the present application discloses a display panel drive circuit, including a timing drive circuit 20 and a scan drive circuit 13; the scan drive circuit 13 includes: multiple sets of transmission signal lines 16; and a set of clocks
  • the signal line 17 is respectively connected to the timing drive circuit 20 to obtain the gate driving clock signal; the compensation capacitor is provided in parallel with each transmission signal line 16; each transmission signal line 16 in each group of transmission signal lines 16 is respectively A clock signal line 17 corresponding to a group of clock signal lines 17 is signal-connected; in each group of transmission signal lines 16, the smaller the compensation capacitance corresponding to the transmission signal line 16 near the timing drive circuit 20, the smaller the compensation capacitance.
  • the transmission signal line 16 near the timing drive circuit 20 has a smaller signal transmission loss than the transmission signal line 16 far from the timing drive circuit 20, and the greater the signal transmission loss according to the larger the capacitance
  • the arrangement of the lines 16 causes signal transmission loss, so that the transmission loss of the signals in the transmission signal lines 16 of different distances is not much different, making the display panel display more uniform.
  • the scan driving circuit 13 includes a common electrode layer 19 and a metal bridge hole 18; each transmission signal line 16 is connected to a corresponding clock signal line 17 through the metal bridge hole 18; the metal bridge hole 18 includes conductive Layer 183, first bridge hole 181 and second bridge hole 182 clock signal line 17 and transmission signal line 16 are located in different processes; conductive layer 183 is connected to clock signal line 17 to form first bridge hole 181; conductive layer 183 and transmission signal The line 16 is connected to form a second bridge hole 182; the common electrode layer 19 and the conductive layer 183 form a compensation capacitor;
  • FIG. 8 which is a cross-sectional view along AA ′ in FIG. 7, a compensation capacitor is added at the position of the metal bridge hole 18 where the transmission signal line 16 and the clock signal line 17 are connected. Compensation capacitors are formed between them to balance the loss caused by the signal transmission process without affecting the circuit architecture.
  • the conductive layer 183 connects the clock data line and the transmission data line, which is generally array conductive glass (Array_ITO), Array_ITO and the common electrode layer 19 CF_com) forms a compensation capacitor; there is a second passivation layer 185 between the clock signal line 17 and the transmission signal line 16, and a first passivation layer 184 between the conductive layer 183 and the transmission signal line 16.
  • the number of first bridge holes 181 corresponding to one transmission signal line 16 close to the timing driving circuit 20 is greater.
  • the capacitance corresponding to one transmission signal line 16 close to the timing drive circuit 20 is greater than the capacitance corresponding to one transmission signal line 16 far from the timing drive circuit 20, increasing the first bridge hole
  • the number of 181 is equivalent to increasing the distance between the two electrodes of the capacitor. This method is used to reduce the capacitance, so that the capacitance corresponding to a transmission signal line 16 away from the timing drive circuit 20 and the transmission close to the timing drive circuit 20
  • the clock signal transmission loss is the same, which makes the display panel display more uniform.
  • the number of each transmission signal line 16 corresponding to the first bridge hole 181 increases in sequence.
  • first bridge holes 181 corresponding to one transmission signal line 16 close to the timing driving circuit 20, from approaching the timing driving circuit 20 to away from the timing driving circuit 20
  • the direction corresponding to the number of the first bridge hole 181 becomes three, and the one farthest becomes one.
  • the metal bridge hole 18 corresponding to the transmission signal line 16 farthest from the timing driving circuit 20 has at least one first bridge hole 181.
  • the metal bridge holes 18 need at least one first bridge hole 181 and one second bridge hole 182 to connect the clock signal line 17 and the transmission The signal line 16 is connected.
  • each transmission signal line 16 connected to the same clock signal line 17 between different groups of transmission signal lines 16 the closer to the first bridge corresponding to one transmission signal line 16 of the timing drive circuit 20 The greater the number of holes 181.
  • the signal transmission loss corresponding to one transmission signal line 16 close to the timing drive circuit 20 between different groups is small, and the signal transmission loss corresponding to one transmission signal line 16 far from the timing drive circuit 20 is large, reducing the distance from the timing drive
  • the number of the first bridge holes 181 corresponding to one transmission signal line 16 of the circuit 20 can increase the capacitance of the corresponding transmission signal line 16, thereby reducing the loss of the signal in the transmission process, making it far from the display of the timing driving circuit 20 The area is displayed evenly. Between different groups, from the direction away from the timing driving circuit 20 to the direction closer to the driving chip, the number of the first bridge holes 181 corresponding to each transmission signal line 16 increases in sequence.
  • the area of the conductive layer 183 corresponding to one transmission signal line 16 close to the timing driving circuit 20 is smaller.
  • increasing the area of the conductive layer 183 corresponds to a group of transmission signal lines 16, the farther away from the timing drive circuit
  • the conductive layer corresponding to one transmission signal line 16 closer to the timing driving circuit 20 The smaller the area of 183.
  • the signal transmission loss corresponding to one transmission signal line 16 close to the timing drive circuit 20 between different groups is small, and the signal transmission loss corresponding to one transmission signal line 16 far from the timing drive circuit 20 is large, increasing the distance from the timing
  • the area of the conductive layer 183 corresponding to one transmission signal line 16 of the driving circuit 20 can increase the capacitance of the corresponding transmission signal line 16, thereby reducing the loss of signals during transmission and making the display area far from the timing driving circuit 20 uniform display.
  • the area of each conductive signal line 16 corresponding to the conductive layer 183 decreases in sequence.
  • each group of transmission signal lines 16 the sum of the compensation capacitance of each transmission signal line 16 and the parasitic capacitance of the corresponding transmission signal line is equal.
  • the capacitance corresponding to each transmission signal line 16 is equal to the capacitance corresponding to each other transmission signal line 16, so that the loss of signal transmission on each transmission signal line 16 is consistent, making the panel display more Evenly.
  • a display panel drive circuit including: a timing drive circuit 20 and a scan drive circuit 13;
  • the scan drive circuit 13 includes: a plurality of sets of transmission signal lines 16; a set of clock signal lines 17, respectively connected to the timing drive circuit 20 to obtain gate drive clock signals; a common electrode layer 19; and a metal bridge hole 18;
  • Each transmission signal line 16 in each group of transmission signal lines 16 is respectively connected to a clock signal line 17 corresponding to a group of clock signal lines 17; each transmission signal line 16 is connected to the corresponding one through a metal bridge hole 18 A clock signal line 17 is connected;
  • the metal bridge hole 18 includes a conductive layer 183, a first bridge hole 181 and a second bridge hole 182;
  • the clock signal line 17 and the transmission signal line 16 are located in different processes; the conductive layer 183 is connected to the clock signal line 17 to form a first bridge hole 181; the conductive layer 183 is connected to the transmission signal line 16 to form a second bridge hole 182;
  • each group of transmission signal lines 16 the number of first bridge holes 181 corresponding to one transmission signal line 16 close to the timing driving circuit 20 is greater;
  • the number of the first bridge holes 181 corresponding to one transmission signal line 16 closer to the timing driving circuit 20 is greater.
  • This application is directed to the same group of transmission signal lines 16 connected to different clock signal lines 17, the capacitance of the transmission signal line 16 corresponding to the clock signal line 17 close to the display area and the transmission signal line connected to the clock signal line 17 far from the display area 16 capacitors, the losses caused by different capacitor sizes are different.
  • each group of transmission signal lines 16 connected to different clock signal lines 17 the capacitance of the transmission signal line 16 corresponding to the clock signal line 17 close to the display area becomes smaller to balance the capacitance caused by the difference in the cable
  • the capacitance loss of each transmission signal line 16 in a group of transmission signal lines 16 remains the same, so that the signal transmission loss in different areas of the display panel cable is the same, making the display panel display more uniform; specific By moving between the different groups, from the direction away from the timing drive circuit 20 to the direction closer to the driving chip, the area of each conductive signal line 16 corresponding to the conductive layer 183 decreases in turn.
  • each The number of the first transmission signal line 16 corresponding to the first bridge hole 181 increases sequentially; so that the capacitance corresponding to each transmission signal line 16 is the same as the capacitance corresponding to each other transmission signal line 16 between different groups, and each transmission signal line 16 The loss of the upper signal transmission is the same.
  • a display device As yet another embodiment of the present application, as shown in FIG. 5, a display device is disclosed.
  • the display device includes the above-mentioned driving circuit.
  • the technical solution of the present application can be widely used in various display panels, such as TN type display panel (full name Twisted Nematic, namely twisted nematic panel), IPS type display panel (In-Plane Switching, plane conversion), VA type display
  • TN type display panel full name Twisted Nematic, namely twisted nematic panel
  • IPS type display panel In-Plane Switching, plane conversion
  • the panel Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology
  • OLED display panel for short organic light emitting display panel

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示装置的扫描驱动电路（13）和显示装置。扫描驱动电路（13）包括多组传输信号线（16）；一组时钟信号线（17），分别与时序驱动电路（20）信号连接以获取门极驱动时钟信号；补偿电容，与每根传输信号线（16）并联设置；每一组传输信号线（16）中的每一根传输信号线（16）分别与一组时钟信号线（17）对应的一根时钟信号线（17）信号连接；其中，每一组传输信号线（16）中，靠近时序驱动电路（20）的传输信号线（16）对应的补偿电容越小。

Description

一种显示装置的驱动电路和显示装置
本申请要求于2018年11月21日提交中国专利局，申请号为201811389128.6，发明名称为“一种显示装置的驱动电路和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示装置的驱动电路和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着随着科技的发展和进步，液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(Backlight Module)。液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)、阵列基板(Thin Film Transistor Substrate，TFTSubstrate)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(LiquidCrystal，LC)，在阵列基板上设置移位暂存器(GOA，gate on array)在面板设计上是一项重要技术，主要优点是可以免去门极驱动芯片(gate driver IC)，降低成本，原本扫描驱动(gate driver)功能利用阵列基板(array)曝光显影方式产生逻辑电路以驱动扫描数据线，移位暂存器通过使用时钟信号通过门极电路驱动扫描线。
但是随着显示面板越来越大，数据线和扫描线的排列方式造成讯号传输损耗不一样，会出现不同位置处的显示效果不够均匀的问题。
发明内容
鉴于上述缺陷，本申请提供一种显示装置的驱动电路和显示装置，所要解决的是显示面板显示效果均匀。
为实现上述目的，本申请提供了一种显示面板的驱动电路，包括：
时序驱动电路和扫描驱动电路；
所述扫描驱动电路包括：多组传输信号线；一组时钟信号线，分别与所述时序驱动电路信号连接以获取门极驱动时钟信号；补偿电容，与每根传输信号线并联设置；
每一组传输信号线中的每一根传输信号线分别与一组时钟信号线对应的一根时钟信号线信号连接；
其中，所述的每一组传输信号线中，靠近所述时序驱动电路的所述传输信号线对应的补偿电容越小。
可选的，所述扫描驱动电路包括公共电极层和金属桥接洞；所述每一根传输信号线通过金属桥接洞与对应的一根所述时钟信号线相连；
所述金属桥接洞包括导电层、第一桥接洞和第二桥接洞
所述时钟信号线与传输信号线位于不同的制程；所述导电层与所述时钟信号线相连形成第一桥接洞；所述导电层与所述传输信号线相连形成第二桥接洞；
所述公共电极层与所述导电层形成补偿电容；
可选的，同一组的所述传输信号线中，靠近所述时序驱动电路的一根所述传输信号线对应的第一桥接洞数量越多。
可选的，同一组的所述传输信号线中，最远离所述时序驱动电路的一根所述传输信号线对应的金属桥接洞至少有一个第一桥接洞。
可选的，不同组的所述传输信号线之间，连接同一根时钟信号线的每一根传输信号线中，越靠近所述时序驱动电路的一根传输信号线对应的第一桥接洞数量越多。
可选的，同一组的所述传输信号线中，靠近所述时序驱动电路的一根所述传输信号线对应的导电层面积越小。
可选的，不同组的所述传输信号线之间，连接同一根时钟信号线的每一根传输信号线中，越靠近所述时序驱动电路的一根传输信号线对应的导电层面积越小。
可选的，每一组的所述传输信号线中，每一根传输信号线的补偿电容与对应传输信号线上的寄生电容的和都相等。
本申请还公开了一种显示面板的驱动电路，包括：时序驱动电路和扫描驱动电路；
所述扫描驱动电路包括：多组传输信号线；一组时钟信号线，分别与所述时序驱动电路信号连接以获取门极驱动时钟信号；公共电极层；以及金属桥接洞；
每一组传输信号线中的每一根传输信号线分别与一组时钟信号线对应的一根时钟信号线信号连接；所述每一根传输信号线通过金属桥接洞与对应的一根所述时钟信号线相连；
所述金属桥接洞包括导电层、第一桥接洞和第二桥接洞；
所述时钟信号线与传输信号线位于不同的制程；所述导电层与所述时钟信号线相连形成第一桥接洞；所述导电层与所述传输信号线相连形成第二桥接洞；
同一组的所述传输信号线中，靠近所述时序驱动电路的一根所述传输信号线对应的第一桥接洞数量越多；
不同组所述传输信号线之间，连接同一根时钟信号线的每一根传输信号线中，越靠近所述时序驱动电路的一根传输信号线对应的第一桥接洞数量越多。
本申请还公开了一种显示装置，所述显示装置包括驱动电路，所述驱动电路包括：
时序驱动电路；
扫描驱动电路；
所述扫描驱动电路包括：
多组传输信号线；
一组时钟信号线，分别与所述时序驱动电路信号连接以获取门极驱动时钟信号；
补偿电容，与每根所述传输信号线并联设置；
每一组所述传输信号线中的每一根传输信号线分别与一组所述时钟信号线对应的一根时钟信号线信号连接；
其中，所述的每一组传输信号线中，越靠近所述时序驱动电路的所述传输信号线对应的补偿电容越小。
可选的，所述扫描驱动电路包括公共电极层和金属桥接洞；所述每一根传输信号线通过金属桥接洞与对应的一根所述时钟信号线相连；
所述金属桥接洞包括导电层、第一桥接洞和第二桥接洞；
所述时钟信号线与传输信号线位于不同的制程；所述导电层与所述时钟信号线相连形成第一桥接洞；所述导电层与所述传输信号线相连形成第二桥接洞；
所述公共电极层与所述导电层形成所述补偿电容。
可选的，同一组的所述传输信号线中，越靠近所述时序驱动电路的所述传输信号线对应的第一桥接洞数量越多。
可选的，同一组的所述传输信号线中，离所述时序驱动电路最远的所述传输信号线对应的金属桥接洞至少有一个第一桥接洞。
可选的，不同组的所述传输信号线之间，连接同一根时钟信号线的每根传输信号线中，越靠近所述时序驱动电路的一根传输数据线对应的第一桥接洞数量越多。
可选的，同一组的所述传输信号线中，靠近所述时序驱动电路的一根所述传输信号线对应的导电层面积越小。
可选的，不同组的所述传输信号线之间，连接同一根时钟信号线的每根传输信号线中，越靠近所述时序驱动电路的一根传输数据线对应的导电层面积越小。
可选的，每一组的所述传输信号线中，每一根传输信号线的补偿电容与对应传输信号线上的寄生电容的和都相等。
相对于示范性的显示面板，本申请针对同一组与不同时钟信号线连接的传输信号线，靠近显示区的时钟信号线对应连接的传输信号线的电容与远离显示区的时钟信号线对应连接的传输信号线的电容，不同的电容大小造成的损耗也不一样。在同一组与不同时钟信号线连接的传输信号线中，将靠近显示区的时钟信号线对应连接的传输信号线的电容变小，来平衡 排线差异造成的电容不等造成损耗不一样的情况，使得一组传输信号线中远离时序控制芯片的一根传输信号线的电容损耗变小，使得显示面板显示更均匀。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请其中一个实施例的一种显示装置的示意图；
图2是本申请其中一个实施例的另一种显示装置的示意图；
图3是本申请其中一个实施例的一种GOA电路的示意图；
图4是本申请其中一个实施例的一种时钟信号的示意图；
图5是本申请其中一个实施例的另一种显示面板的示意图；
图6是本申请其中一个实施例的一种扫描驱动电路的示意图；
图7是本申请其中一个实施例的另一种扫描驱动电路的示意图；
图8是本申请其中一个实施例的沿AA’线金属桥接洞的横截示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申 请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
如图1至图4，在阵列基板上设置移位暂存器GOA(gate on array)在面板设计上，可以免去门极驱动芯片(gate driver IC)，降低成本，原本扫描驱动(gate driver)功能利用阵列基板array曝光显影方式产生逻辑电路以驱动扫描数据线，移位暂存器通过使用时钟信号通过门极电路驱动扫描线。如图3，图中BP为升压点(boost point)，OP为输出(Output)，如图4，Q为Q点预充，G为Gate输出。GOA电路原理都是在汤普森电路(Tompson circuit)基础上发展，一般GOA在工作时，升压点(boost point)有一个预充讯号(st)进行对该点预充，使得升压点与时钟信号耦合(coupling)时，升压点达到高电压准位，薄膜晶体管(TFT)打开让信号顺利传递。
如图6，传输信号线16通过移位寄存器15与扫描线连接，扫描线14是根据屏幕解析度而定,例如解析度FHD(1920x1080)的解析度,扫描线14在像素pixel 1G1D排列下，扫描线14即1080条,然而时钟信号的目的是要负责提供信号驱动这些扫描线14，时钟信号会根据信号数对扫描线14进行分配。如图2，以8根时钟信号线17为例，在1080根扫描线14的情况下，一个时钟信号线17所要负责1080/8＝135根扫描线14。在图2中，一组时钟信号线17包括8根时钟信号线17，一根时钟信号线17对应有135根扫描线14，一组扫描线14对应8根扫描线14，通过对应的8根传输信号线16与8根时钟信号线17一一连接。
下面结合附图和实施例对本申请作说明。
如图5至图8所示，本申请实施例公布了一种显示面板的驱动电路，包括时序驱动电路20和扫描驱动电路13；扫描驱动电路13包括：多组传输信号线16；一组时钟信号线17，分别与时序驱动电路20信号连接以获取门极驱动时钟信号；补偿电容，与每根传输信号线16并联设置；每一组传输信号线16中的每一根传输信号线16分别与一组时钟信号线17对应的一根时钟信号线17信号连接；其中，每一组传输信号线16中，靠近时序驱动电路20的传输信号线16对应的补偿电容越小。
本方案中，在一组传输信号线16中，靠近时序驱动电路20的传输信号线16对比远离时序驱动电路20的传输信号线16的信号传输损耗较小，根据电容越大对信号传输损耗越小，对应远离时序驱动电路20的传输信号线16的补偿电容越大，对应使得远离时序驱动电路20的传输信号线16传输信号的损耗越小，来平衡GOA电路中时钟信号线17与传输信号线 16排列造成信号传输损耗，使得信号在不同远近的传输信号线16中传输损耗差异不大，使得显示面板显示更均匀。
在一实施例中，扫描驱动电路13包括公共电极层19和金属桥接洞18；每一根传输信号线16通过金属桥接洞18与对应的一根时钟信号线17相连；金属桥接洞18包括导电层183、第一桥接洞181和第二桥接洞182时钟信号线17与传输信号线16位于不同的制程；导电层183与时钟信号线17相连形成第一桥接洞181；导电层183与传输信号线16相连形成第二桥接洞182；公共电极层19与导电层183形成补偿电容；
本方案中，如图8，是图7中沿AA’的剖面图，在传输信号线16与时钟信号线17连接处的金属桥接洞18位置增加补偿电容，通过公共电极层19与导电层183之间形成补偿电容，在不影响电路架构的同时平衡信号传输过程中造成的损耗，导电层183连接时钟数据线与传输数据线，一般为阵列导电玻璃(Array_ITO)，Array_ITO与公共电极层19(CF_com)形成补偿电容；时钟信号线17与传输信号线16中间有第二钝化层185，导电层183与传输信号线16之间有第一钝化层184。
在一实施例中，同一组传输信号线16中，靠近时序驱动电路20的一根传输信号线16对应的第一桥接洞181数量越多。
本方案中，一组传输信号线16中，靠近时序驱动电路20的一根传输信号线16对应的电容大于远离时序驱动电路20的一根传输信号线16对应的电容，增大第一桥接洞181的数量，相当于增大电容两块电极之间的距离，用此手段来减少电容，使得远离时序驱动电路20的一根传输信号线16对应的电容与靠近时序驱动电路20的一根传输信号线16对应的电容，在相等的情况下，时钟信号传输损耗一致，使得显示面板显示更均匀。在同一组中，从远离时序驱动电路20到靠近驱动芯片方向，每一根传输信号线16对应第一桥接洞181数量依次增多。
如图7，以3根时钟信号线17为一组，对应靠近时序驱动电路20的一根传输信号线16的第一桥接洞181为5个，从靠近时序驱动电路20到远离时序驱动电路20的方向，对应第一桥接洞181数量变为3个，最远离的变为1个。
在一实施例中，同一组传输信号线16中，最远离时序驱动电路20的一根传输信号线16对应的金属桥接洞18至少有一个第一桥接洞181。
本方案中，在每一组传输信号线16中，最远离时序驱动电路20的一根传输信号线16的信号传输损耗越大，减少金属桥接洞18的数量可以增大对应的电容，也就使得这根传输信号线16上的损耗越小，对应的金属桥接洞18的数量不能没有，金属桥接洞18至少需要一个第一桥接洞181和一个第二桥接洞182将时钟信号线17和传输信号线16连接起来。
在一实施例中，不同组传输信号线16之间，连接同一根时钟信号线17的每一根传输信 号线16中，越靠近时序驱动电路20的一根传输信号线16对应的第一桥接洞181数量越多。
本方案中，不同组之间靠近时序驱动电路20的一根传输信号线16对应的信号传输损耗小，远离时序驱动电路20的一根传输信号线16对应的信号传输损耗大，减少远离时序驱动电路20的一根传输信号线16对应的第一桥接洞181的数量，可以增大对应传输信号线16的电容，由此可以减少信号在传输过程中的损耗，使得远离时序驱动电路20的显示区均匀显示。在不同一组之间，从远离时序驱动电路20到靠近驱动芯片方向，每一根传输信号线16对应第一桥接洞181数量依次增多。
在一实施例中，同一组传输信号线16中，靠近时序驱动电路20的一根传输信号线16对应的导电层183面积越小。
本方案中，增大导电层183的面积，也就是增大了导电层183与公共电极层19的电容面积，也就是增大了电容，对应一组传输信号线16中，越远离时序驱动电路20的传输信号线16对应的导电层183面积越大，则电容越大，则信号在对应传输信号线16中的损耗越小，损耗越小，对应显示面板显示越均匀；在同一组中，从远离时序驱动电路20到靠近驱动芯片方向，每一根传输信号线16对应导电层183面积依次减小。
在一实施例中，不同组的传输信号线16之间，连接同一根时钟信号线17的每一根传输信号线16中，越靠近时序驱动电路20的一根传输信号线16对应的导电层183面积越小。
本方案中，不同组之间靠近时序驱动电路20的一根传输信号线16对应的信号传输损耗小，远离时序驱动电路20的一根传输信号线16对应的信号传输损耗大，增大远离时序驱动电路20的一根传输信号线16对应的导电层183面积，可以增大对应传输信号线16的电容，由此可以减少信号在传输过程中的损耗，使得远离时序驱动电路20的显示区均匀显示。在不同一组之间，从远离时序驱动电路20到靠近驱动芯片方向，每一根传输信号线16对应导电层183面积依次减小。
在一实施例中，每一组传输信号线16中，每一根传输信号线16的补偿电容与对应传输信号线上的寄生电容的和都相等。
本方案中，不同组之间，每一条传输信号线16对应的电容都与其它每一条传输信号线16对应的电容相等，使得每一条传输信号线16上信号传输的损耗一致，使得面板显示更均匀。
作为本申请的另一实施例，如图7至图8所示，公开了一种显示面板的驱动电路，包括：时序驱动电路20和扫描驱动电路13；
扫描驱动电路13包括：多组传输信号线16；一组时钟信号线17，分别与时序驱动电路20信号连接以获取门极驱动时钟信号；公共电极层19；以及金属桥接洞18；
每一组传输信号线16中的每一根传输信号线16分别与一组时钟信号线17对应的一根 时钟信号线17信号连接；每一根传输信号线16通过金属桥接洞18与对应的一根时钟信号线17相连；
金属桥接洞18包括导电层183、第一桥接洞181和第二桥接洞182；
时钟信号线17与传输信号线16位于不同的制程；导电层183与时钟信号线17相连形成第一桥接洞181；导电层183与传输信号线16相连形成第二桥接洞182；
每一组传输信号线16中，靠近时序驱动电路20的一根传输信号线16对应的第一桥接洞181数量越多；
不同组传输信号线16之间，连接同一根时钟信号线17的每一根传输信号线16中，越靠近时序驱动电路20的一根传输信号线16对应的第一桥接洞181数量越多。
本申请针对同一组与不同时钟信号线17连接的传输信号线16，靠近显示区的时钟信号线17对应连接的传输信号线16的电容与远离显示区的时钟信号线17对应连接的传输信号线16的电容，不同的电容大小造成的损耗也不一样。在每一组与不同时钟信号线17连接的传输信号线16中，将靠近显示区的时钟信号线17对应连接的传输信号线16的电容变小，来平衡排线差异造成的电容不等造成损耗不一样的情况，使得一组传输信号线16中每一根传输信号线16的电容损耗保持一致，使得显示面板排线远近的不同区域的信号传输损耗一样，使得显示面板显示更均匀；具体通过在不同一组之间，从远离时序驱动电路20到靠近驱动芯片方向，每一根传输信号线16对应导电层183面积依次减小，从远离时序驱动电路20到靠近驱动芯片方向，每一根传输信号线16对应第一桥接洞181数量依次增多；使得不同组之间，每一条传输信号线16对应的电容都与其它每一条传输信号线16对应的电容相等，每一条传输信号线16上信号传输的损耗一致。
作为本申请的又一实施例，如图5所示，公开了一种显示装置，显示装置包括上述的驱动电路。
本申请的技术方案可以广泛用于各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Multi-domain Vertica Alignment，多象限垂直配向技术)，当然，也可以是其他类型的显示面板，如有机发光显示面板(organic light emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的实施方式对本申请所作的详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示装置的驱动电路，包括：
    时序驱动电路；
    扫描驱动电路；
    所述扫描驱动电路包括：
    多组传输信号线；
    一组时钟信号线，分别与所述时序驱动电路信号连接以获取门极驱动时钟信号；
    补偿电容，与每根所述传输信号线并联设置；
    每一组所述传输信号线中的每一根传输信号线分别与一组所述时钟信号线对应的一根时钟信号线信号连接；
    其中，所述的每一组传输信号线中，越靠近所述时序驱动电路的所述传输信号线对应的补偿电容越小。
  2. 如权利要求1所述的一种显示装置的驱动电路，其中，所述扫描驱动电路包括公共电极层和金属桥接洞；所述每一根传输信号线通过金属桥接洞与对应的一根所述时钟信号线相连；
    所述金属桥接洞包括导电层、第一桥接洞和第二桥接洞；
    所述时钟信号线与传输信号线位于不同的制程；所述导电层与所述时钟信号线相连形成第一桥接洞；所述导电层与所述传输信号线相连形成第二桥接洞；
    所述公共电极层与所述导电层形成所述补偿电容。
  3. 如权利要求2所述的一种显示装置的驱动电路，其中，同一组的所述传输信号线中，越靠近所述时序驱动电路的所述传输信号线对应的第一桥接洞数量越多。
  4. 如权利要求2所述的一种显示装置的驱动电路，其中，同一组的所述传输信号线中，离所述时序驱动电路最远的所述传输信号线对应的金属桥接洞至少有一个第一桥接洞。
  5. 如权利要求2所述的一种显示装置的驱动电路，其中，不同组的所述传输信号线之间，连接同一根时钟信号线的每根传输信号线中，越靠近所述时序驱动电路的一根传输数据线对应的第一桥接洞数量越多。
  6. 如权利要求2所述的一种显示装置的驱动电路，其中，同一组的所述传输信号线中，靠近所述时序驱动电路的一根所述传输信号线对应的导电层面积越小。
  7. 如权利要求2所述的一种显示装置的驱动电路，其中，不同组的所述传输信号线之间，连接同一根时钟信号线的每根传输信号线中，越靠近所述时序驱动电路的一根传输数据 线对应的导电层面积越小。
  8. 如权利要求1所述的一种显示装置的驱动电路，其中，每一组的所述传输信号线中，每一根传输信号线的补偿电容与对应传输信号线上的寄生电容的和都相等。
  9. 一种显示装置的驱动电路，包括：
    时序驱动电路；
    扫描驱动电路；
    所述扫描驱动电路包括：
    多组传输信号线；
    一组时钟信号线，分别与所述时序驱动电路信号连接以获取门极驱动时钟信号；
    公共电极层；
    以及金属桥接洞；
    每一组传输信号线中的每一根传输信号线分别与一组时钟信号线对应的一根时钟信号线信号连接；所述每一根传输信号线通过金属桥接洞与对应的一根所述时钟信号线相连；
    所述金属桥接洞包括导电层、第一桥接洞和第二桥接洞；
    所述时钟信号线与传输信号线位于不同的制程；所述导电层与所述时钟信号线相连形成第一桥接洞；所述导电层与所述传输信号线相连形成第二桥接洞；
    同一组所述传输信号线中，靠近所述时序驱动电路的一根所述传输信号线对应的第一桥接洞数量越多；
    不同组所述传输信号线之间，连接同一根时钟信号线的每根传输信号线中，越靠近所述时序驱动电路的一根传输数据线对应的第一桥接洞数量越多。
  10. 一种显示装置，包括驱动电路，所述驱动电路包括：
    时序驱动电路；
    扫描驱动电路；
    所述扫描驱动电路包括：
    多组传输信号线；
    一组时钟信号线，分别与所述时序驱动电路信号连接以获取门极驱动时钟信号；
    补偿电容，与每根所述传输信号线并联设置；
    每一组所述传输信号线中的每一根传输信号线分别与一组所述时钟信号线对应的一根时钟信号线信号连接；
    其中，所述的每一组传输信号线中，越靠近所述时序驱动电路的所述传输信号线对应的补偿电容越小。
  11. 如权利要求10所述的一种显示装置，其中，所述扫描驱动电路包括公共电极层和金属桥接洞；所述每一根传输信号线通过金属桥接洞与对应的一根所述时钟信号线相连；
    所述金属桥接洞包括导电层、第一桥接洞和第二桥接洞；
    所述时钟信号线与传输信号线位于不同的制程；所述导电层与所述时钟信号线相连形成第一桥接洞；所述导电层与所述传输信号线相连形成第二桥接洞；
    所述公共电极层与所述导电层形成所述补偿电容。
  12. 如权利要求11所述的一种显示装置，其中，同一组的所述传输信号线中，越靠近所述时序驱动电路的所述传输信号线对应的第一桥接洞数量越多。
  13. 如权利要求11所述的一种显示装置，其中，同一组的所述传输信号线中，离所述时序驱动电路最远的所述传输信号线对应的金属桥接洞至少有一个第一桥接洞。
  14. 如权利要求11所述的一种显示装置，其中，不同组的所述传输信号线之间，连接同一根时钟信号线的每根传输信号线中，越靠近所述时序驱动电路的一根传输数据线对应的第一桥接洞数量越多。
  15. 如权利要求11所述的一种显示装置，其中，同一组的所述传输信号线中，靠近所述时序驱动电路的一根所述传输信号线对应的导电层面积越小。
  16. 如权利要求11所述的一种显示装置，其中，不同组的所述传输信号线之间，连接同一根时钟信号线的每根传输信号线中，越靠近所述时序驱动电路的一根传输数据线对应的导电层面积越小。
  17. 如权利要求10所述的一种显示装置，其中，每一组的所述传输信号线中，每一根传输信号线的补偿电容与对应传输信号线上的寄生电容的和都相等。
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