WO2020073547A1 - 薄膜晶体管及其制造方法 - Google Patents

薄膜晶体管及其制造方法 Download PDF

Info

Publication number
WO2020073547A1
WO2020073547A1 PCT/CN2019/070329 CN2019070329W WO2020073547A1 WO 2020073547 A1 WO2020073547 A1 WO 2020073547A1 CN 2019070329 W CN2019070329 W CN 2019070329W WO 2020073547 A1 WO2020073547 A1 WO 2020073547A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
drain
channel region
passivation
gate
Prior art date
Application number
PCT/CN2019/070329
Other languages
English (en)
French (fr)
Inventor
孟小龙
张瑞军
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2020073547A1 publication Critical patent/WO2020073547A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present application relates to the technical field of thin film transistors, and in particular to a thin film transistor and a manufacturing method thereof.
  • Thin film transistor As a switching device is widely used in display panels, such as liquid crystal display panels, organic light-emitting diodes (Organic Light Emitting Diode (OLED) display panel, etc., its electrical stability is one of the key factors affecting the performance of the display panel.
  • display panels such as liquid crystal display panels, organic light-emitting diodes (Organic Light Emitting Diode (OLED) display panel, etc.
  • OLED Organic Light Emitting Diode
  • the semiconductor channel layer is a structural part of the TFT. It is easy to form electron hole pairs after being exposed to light, thereby forming a current, which will adversely affect the electrical characteristics of the TFT and reduce the stability of the TFT.
  • the TFT In the working environment of the TFT, such as when applied to a liquid crystal display panel, the TFT will be irradiated by the backlight and external light, and these light rays will have a certain influence on the electrical characteristics of the TFT.
  • the existing technology usually increases the gate The area of the layer is used to block the backlight to reduce the light irradiated to the TFT channel layer. However, increasing the area of the gate layer will sacrifice part of the area of the pixel electrode accordingly, reducing the aperture ratio of the display panel.
  • the embodiments of the present application provide a thin film transistor and a manufacturing method thereof, which can ensure the aperture ratio and reduce the light irradiated on the channel region of the semiconductor layer of the thin film transistor, which is beneficial to improve the stability of the thin film transistor.
  • An embodiment of the present application provides a thin film transistor, which includes:
  • a gate insulating layer formed on the substrate and covering the gate layer
  • a semiconductor layer formed on the gate insulating layer, the semiconductor layer includes a channel region
  • a source layer and a drain layer formed on the semiconductor layer, the source layer and the drain layer are oppositely arranged across the channel region;
  • the passivation layer corresponding to the channel region has a concave-convex surface
  • the passivation layer corresponding to the drain layer is provided with a through hole, and the through hole is used to realize the drain layer and the transparent electrode layer.
  • the passivation layer is a SiN x layer
  • the semiconductor layer is an A-si layer.
  • the uneven surface is a zigzag surface with uniform unevenness.
  • the vertical projection area of the channel region is located in the vertical projection area of the gate layer, and the passivation layer corresponding to the gate layer has an uneven surface.
  • An embodiment of the present application further provides a thin film transistor, including:
  • a gate insulating layer formed on the substrate and covering the gate layer
  • a semiconductor layer formed on the gate insulating layer, the semiconductor layer includes a channel region
  • a source layer and a drain layer formed on the semiconductor layer, the source layer and the drain layer are oppositely arranged across the channel region;
  • the passivation layer corresponding to the channel region has an uneven surface.
  • the uneven surface is a zigzag surface with uniform unevenness.
  • the vertical projection area of the channel region is located in the vertical projection area of the gate layer, and the passivation layer corresponding to the gate layer has an uneven surface.
  • the passivation layer corresponding to the drain layer is provided with a through hole, and the through hole is used to realize the connection between the drain layer and the transparent electrode layer.
  • the passivation layer is a SiN x layer
  • the semiconductor layer is an A-si layer.
  • An embodiment of the present application also provides a method for manufacturing a thin film transistor, including:
  • Source layer and the drain layer Forming a source layer and a drain layer on the semiconductor layer, the source layer and the drain layer being spaced apart to form a channel of the semiconductor layer between the source layer and the drain layer Area;
  • the passivation layer is etched so that the passivation layer corresponding to the channel region has an uneven surface.
  • the etching the passivation layer includes:
  • the width of the first light-transmitting holes is smaller than the resolution of the exposure machine
  • the width of the second light transmitting hole is greater than the resolution of the exposure machine.
  • the plurality of first light-transmitting holes are located above the photoresist layer corresponding to the gate layer;
  • the source layer and the drain layer are formed on the semiconductor layer, the source layer and the drain layer are spaced apart to form the semiconductor layer between the source layer and the drain layer
  • the channel region includes: positioning the vertical projection region of the channel region within the vertical projection region of the gate layer.
  • the etching the passivation layer includes:
  • the photomask is provided with a semi-permeable membrane area and a light-transmitting hole;
  • the pattern in the semi-transparent film area is that a plurality of semi-transparent film layers and light blocking layers are alternately arranged.
  • the light transmittance of the semi-permeable membrane layer is 50%.
  • the light transmittances of the plurality of semi-permeable membrane layers are the same.
  • the light transmittances of the plurality of semi-permeable membrane layers are different.
  • the passivation layer is a SiN x layer
  • the semiconductor layer is an A-si layer.
  • the forming of the source layer and the drain layer on the semiconductor layer includes:
  • the metal layer is patterned to form a source layer and a drain layer.
  • the forming the gate layer on the substrate includes:
  • the metal layer is patterned to form a gate layer.
  • the passivation layer is formed on the gate insulating layer and the source layer ,
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present application.
  • FIG. 2 is another schematic structural diagram of a thin film transistor provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the present application
  • FIG. 4 is a schematic flow chart of etching a passivation layer in the method for manufacturing a thin film transistor provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural view of a photomask in the method for manufacturing a thin film transistor provided by an embodiment of the present application.
  • the thin film transistor includes a substrate 10, a gate layer 11, a gate insulating layer 12, a semiconductor layer 13, a source layer 14, a drain layer 15 and a passivation layer 16 .
  • the substrate 10 may be, for example, a glass substrate or a substrate of other materials.
  • the gate layer 11 is formed on the substrate 10 as the gate of the thin film transistor, and the gate insulating layer 12 is formed on the substrate 10 and covers the gate layer 11.
  • the semiconductor layer 13 may be, for example, an A-si (amorphous silicon) layer formed on the gate insulating layer 12 and including a channel region 131.
  • the source layer 14 and the drain layer 15 serve as the source and drain of the thin film transistor, respectively, and are formed on the semiconductor layer 13, and the source layer 14 and the drain layer 15 are oppositely disposed across the channel region 131, that is, located at the source
  • the semiconductor layer between the layer 14 and the drain layer 15 is the channel region 131.
  • the passivation layer 16 may be, for example, a SiN x (silicon nitride) layer, which is formed on the channel region 131 of the gate insulating layer 12, the source layer 14, the drain layer 15 and the semiconductor layer 13 to play a protective role.
  • SiN x silicon nitride
  • the passivation layer 161 corresponding to the channel region 131 has an uneven surface, that is, in this embodiment, the surface of the passivation layer 161 over the channel region 131 and covering the channel region 131 is an uneven surface, which is The uneven surface, so that through the uneven surface, the light irradiated to the uneven surface can be refracted, total reflection, diffuse reflection, etc., so that the light reaching the channel region 131 can be reduced to reduce the groove of the semiconductor layer
  • the influence of the channel region 131 is beneficial to improve the electrical stability of the thin film transistor, and at the same time, the manufacturing process can be simplified. Also, since there is no need to sacrifice the area of the pixel electrode, the aperture ratio can be ensured.
  • the uneven surface may be a serrated surface with uniform unevenness, or the uneven surface may also be a surface with uneven unevenness.
  • the passivation layer 16 corresponding to the drain layer 15 is provided with a through hole 162, that is, the passivation layer 16 on the drain layer 15 is provided with a through hole 162.
  • the through hole 162 is used to connect the drain layer 15 and the transparent electrode layer 17.
  • the transparent electrode layer 17 may be a pixel electrode, for example.
  • the vertical projection area of the channel region 131 of the semiconductor layer 13 is located in the vertical projection area of the gate layer 11.
  • the passivation layer 163 corresponding to the gate layer 11 has an uneven surface
  • the passivation layer 163 includes a passivation layer corresponding to the channel region 131, that is, in this embodiment, the passivation layer 16 is enlarged
  • the range of the uneven surface of the passivation layer makes the surfaces of the passivation layer 163 corresponding to the gate layer 11 are uneven surfaces, which can cause more light to reflect and refract, etc., to further reduce the impact of the light on the channel region 131, and at the same time can ensure Opening rate.
  • an embodiment of the present application further provides a method for manufacturing a thin film transistor, which is used to manufacture the thin film transistor of the foregoing embodiments.
  • the manufacturing method may specifically include the following steps:
  • a substrate For example, it may be a glass substrate or a substrate of other materials.
  • a metal layer can be deposited on the substrate, and then the metal layer can be patterned using a photomask with a pattern of the gate layer, so that the gate layer can be obtained.
  • the semiconductor layer may be, for example, an A-si layer.
  • S305 Form a source layer and a drain layer on the semiconductor layer, and the source layer and the drain layer are spaced apart to form a channel region of the semiconductor layer between the source layer and the drain layer.
  • a metal layer can be deposited on the semiconductor layer, and then the metal layer can be patterned to form a source layer and a drain layer.
  • the formed source layer and drain layer are arranged oppositely, between the two
  • the semiconductor layer is the channel region.
  • the passivation layer may be a SiN x layer, for example.
  • the passivation layer can be used for protection and isolation.
  • part of the passivation layer is removed by etching, so that the surface of the passivation layer corresponding to the channel region is an uneven surface.
  • step S307 may include the following sub-steps:
  • a photomask 40 which is provided with a plurality of first light-transmitting holes 401 and a second light-transmitting hole 402, the width of the first light-transmitting hole 401 is smaller than the resolution of the exposure machine.
  • the first light-transmitting hole 401 and the second light-transmitting hole 402 are both through holes penetrating the photomask 40.
  • a photoresist layer 18 is formed on the passivation layer 16, and a photomask 40 is placed on the photoresist layer 18, wherein the plurality of first light-transmitting holes 401 are located on the channel Above the photoresist layer corresponding to the region 131, the second light-transmitting hole 402 is located above the photoresist layer corresponding to the drain layer 15.
  • the width of the second light-transmitting holes 402 is greater than the resolution of the exposure machine, and by making the widths of the plurality of first light-transmitting holes 401 smaller than the resolution of the exposure machine, therefore, when performing exposure, under the same exposure conditions Next, the photoresist layer corresponding to the second light transmitting hole 402 can be fully exposed, and since the width of the first light transmitting hole 401 is smaller than the resolution of the exposure machine, the light passing through the first light transmitting hole 401 can be reduced, thereby The light energy received by the photoresist layer corresponding to the first light transmitting hole 401 is reduced, so that the photoresist layer corresponding to the first light transmitting hole 401 is not completely exposed, that is, partially exposed.
  • the exposed photoresist layer 18 is subjected to a development process to remove the exposed photoresist layer.
  • the photoresist layer corresponding to the first light-transmitting hole 401 is incompletely exposed, that is, only a partial thickness of the photoresist layer is exposed, and the photoresist layer corresponding to the second light-transmitting hole 402 is completely exposed, so After the development process, a part of the photoresist layer corresponding to the plurality of first light-transmitting holes 401 can be removed to form a photoresist layer with uneven surface, while the photoresist layer corresponding to the second light-transmitting holes 402 is completely removed. Thus, a through hole is formed on the photoresist layer 18 to expose a part of the passivation layer 16.
  • the passivation layer 16 is etched using the developed photoresist layer 18 as a mask, so that the passivation layer 161 corresponding to the channel region 131 has a concave-convex surface, and passivation corresponding to the drain layer 15 Through hole 162 is formed in layer 16.
  • the photoresist layer corresponding to the plurality of first light-transmitting holes 401 corresponds to the photoresist layer of the channel region 131. Therefore, a part of the photoresist layer corresponding to the channel region 131 is removed after development. Therefore, When the passivation layer 16 is etched, under the same etching conditions, the passivation layer 16 exposed on the drain layer 15 will be completely etched away, so that the passivation layer 16 on the drain layer 15 forms a through hole 162,
  • the passivation layer 161 corresponding to the channel region 131 has a photoresist layer 18 with a certain thickness above it, and is a photoresist layer with different thicknesses.
  • the photoresist layer 18 is etched, and as the etching progresses, after the exposed passivation layer 16 on the drain layer 15 is completely etched, the passivation layer 161 on the channel region 131 is only partially etched away, so that A passivation layer 161 with an uneven surface is formed.
  • step S403 of FIG. 4 After removing the remaining photoresist layer, a passivation layer 161 corresponding to the channel region 131 and having an uneven surface is obtained, and the passivation layer 16 corresponding to the drain layer 15 is formed
  • the through hole 162 exposes a portion of the drain layer 15, so that the through hole 162 can realize the connection between the drain layer 15 and the transparent electrode layer 17.
  • the uneven surface of the passivation layer can also be formed by a semi-transparent film mask.
  • the etching of the passivation layer in step S307 may specifically include the following sub-steps:
  • (21) Provide a photomask with a semi-permeable membrane area and a light-transmitting hole.
  • the photomask 50 in this embodiment may be a semi-transparent film photomask, that is, the passivation layer is etched using a semi-transparent film photomask process to form an uneven surface.
  • the photomask 50 is provided with a semi-transparent film area 51 and a light-transmitting hole 52, and other parts of the photomask 50 are opaque areas.
  • the pattern in the semi-transparent film area 51 may be, for example, a plurality of semi-transparent film layers 511 and light-blocking layers (shaded areas) 512 are alternately arranged.
  • the semi-transparent film layer 511 can be a semi-transparent film that allows 50% light to pass through, or can be a semi-transparent film that allows 60% light to pass, and so on.
  • the light-blocking layer 512 is an opaque layer, and the light-transmitting hole 52 is a through-hole in the reticle 50, which can fully transmit light.
  • the light transmittance of the plurality of semi-transparent film layers 511 may be the same or different.
  • (22) Form a photoresist layer on the passivation layer, and place the photomask on the photoresist layer, where the semi-transparent film region is located above the photoresist layer corresponding to the channel region, and the light-transmitting hole is located corresponding to the drain layer Above the photoresist layer.
  • the semi-permeable membrane area 51 has a plurality of semi-permeable membrane layers 511, and the light-transmitting holes 52 are totally light-transmitting, so during exposure, under the same exposure conditions, when the photoresist layer corresponding to the light-transmitting holes 52 is completely exposed At this time, the photoresist layer corresponding to the semi-transparent film layer 511 is only partially exposed due to the semi-transmissive effect of the semi-transparent film layer 511 (only a partial thickness of the photoresist layer is exposed).
  • the exposed photoresist layer is developed to remove the exposed photoresist layer.
  • the photoresist layer corresponding to the semi-permeable film layer 511 since the photoresist layer corresponding to the semi-permeable film layer 511 is partially exposed, and the photoresist layer corresponding to the light-transmitting hole 52 is completely exposed, the photoresist layer corresponding to the semi-permeable film layer 511 can be removed after the development process Part of the photoresist layer to form a photoresist layer with uneven surface, and the photoresist layer corresponding to the light-transmitting hole 52 is completely removed, thereby forming a through hole in the photoresist layer to expose part of the passivation layer.
  • the passivation layer is etched using the developed photoresist layer as a mask, so that the passivation layer corresponding to the channel region has an uneven surface, and a through hole is formed in the passivation layer corresponding to the drain layer .
  • the photoresist layer corresponding to the plurality of semi-transmissive film layers 511 also corresponds to the photoresist layer in the channel region, so the photoresist layer corresponding to the channel region is partially removed after development.
  • the layer is etched, under the same etching conditions, when the exposed passivation layer on the drain layer is completely etched away to form a through hole in the passivation layer on the drain layer, it corresponds to the passivation layer of the channel region, Because there is still a certain thickness of photoresist layer above it, and it is a photoresist layer with different thickness, so when etching, the photoresist layer above the passivation layer is first etched, and as the etching progresses, the drain After the exposed passivation layer on the layer is completely etched, the passivation layer on the channel region is only partially etched away, thereby forming a passivation layer on the uneven surface.
  • the passivation layer 161 above the channel region 131 have a concave-convex surface
  • the light irradiated to the concave-convex surface can be refracted, totally reflected, diffused, etc.
  • the light reaching the channel region 131 can be reduced to reduce the influence of the light on the channel region 131 of the semiconductor layer, which is beneficial to improve the electrical stability of the thin film transistor, and since there is no need to sacrifice the area of the pixel electrode, it can ensure Opening rate.
  • it is only necessary to add a first light-transmitting hole on the photomask which is simple and convenient to manufacture, is beneficial to reduce costs, and can simplify the manufacturing process.
  • the uneven surface of the passivation layer may be a serrated surface with uniform unevenness, or an uneven surface, which may be selected according to actual needs, for example, by designing the first light-transmitting hole (or semi-permeable membrane layer)
  • the shape of the surface determines the unevenness of the uneven surface, or the unevenness of the uneven surface is determined by etching.
  • the vertical projection area of the channel region is within the vertical projection area of the gate layer, and the passivation layer corresponding to the gate layer may have a concave-convex surface.
  • the passivation layer corresponding to the gate layer may have a concave-convex surface.
  • only a photomask is required
  • the plurality of first light-transmitting holes or semi-transparent film regions need only be located above the photoresist layer corresponding to the gate layer, so that after the exposure and development treatment, the photoresist layer corresponding to the gate layer can be made into an uneven surface
  • the thickness of the photoresist layer varies, so that when the passivation layer is etched, the surface of the passivation layer corresponding to the gate layer can be etched into an uneven surface.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管及其制造方法，所述薄膜晶体管中，通过在基板（10）上依次形成栅极层（11）、栅极绝缘层（12）、半导体层（13）、源极层（14）、漏极层（15）以及钝化层（16），钝化层（16）形成在栅极绝缘层（12）、源极层（14）、漏极层（15）以及含有沟道区（131）的半导体层（13）上，其中对应于沟道区（131）的钝化层（16）具有凹凸表面。

Description

薄膜晶体管及其制造方法 技术领域
本申请涉及薄膜晶体管技术领域，具体涉及一种薄膜晶体管及其制造方法。
 背景技术
薄膜晶体管（Thin Film Transistor，TFT ）作为一种开关器件广泛应用于显示面板中，如液晶显示面板、有机发光二极管（Organic Light Emitting Diode，OLED）显示面板等，其电性稳定性是影响显示面板性能的关键因素之一。
半导体沟道层是TFT的结构组成部分，其在受到光照后容易形成电子空穴对，从而形成电流，将会对TFT的电性特性造成不良影响，降低TFT的稳定性。而在TFT的工作环境中，如应用于液晶显示面板时，TFT将会受到背光和外界光的照射，这些光线都会对TFT的电性特性产生一定的影响，现有技术通常是加大栅极层的面积来阻挡背光，以减少照射到TFT沟道层的光线，然而加大栅极层的面积将会相应地牺牲像素电极的部分面积，降低显示面板的开口率。
 技术问题
本申请实施例提供一种薄膜晶体管及其制造方法，能够确保开口率的同时，可以减少照射到薄膜晶体管的半导体层沟道区上的光线，有利于提升薄膜晶体管的稳定性。
 技术解决方案
本申请实施例提供一种薄膜晶体管，其包括：
基板；
形成于所述基板上的栅极层；
形成于所述基板上、且覆盖所述栅极层的栅极绝缘层；
形成于所述栅极绝缘层上的半导体层，所述半导体层包括沟道区；
形成于所述半导体层上的源极层和漏极层，所述源极层和漏极层间隔所述沟道区而相对设置；
形成于所述栅极绝缘层、源极层、漏极层以及所述半导体层的沟道区上的钝化层；
其中，对应于所述沟道区的钝化层具有凹凸表面，对应于所述漏极层的钝化层设置有通孔，所述通孔用于实现所述漏极层和透明电极层的连接，所述钝化层为SiN x层，所述半导体层为A-si层。
在本申请所述的薄膜晶体管中，所述凹凸表面为凹凸均匀的锯齿状表面。
在本申请所述的薄膜晶体管中，所述沟道区的垂直投影区域位于所述栅极层的垂直投影区域内，对应于所述栅极层的钝化层具有凹凸表面。
本申请实施例还提供一种薄膜晶体管，包括：
基板；
形成于所述基板上的栅极层；
形成于所述基板上、且覆盖所述栅极层的栅极绝缘层；
形成于所述栅极绝缘层上的半导体层，所述半导体层包括沟道区；
形成于所述半导体层上的源极层和漏极层，所述源极层和漏极层间隔所述沟道区而相对设置；
形成于所述栅极绝缘层、源极层、漏极层以及所述半导体层的沟道区上的钝化层；
其中，对应于所述沟道区的钝化层具有凹凸表面。
在本申请所述的薄膜晶体管中，所述凹凸表面为凹凸均匀的锯齿状表面。
在本申请所述的薄膜晶体管中，所述沟道区的垂直投影区域位于所述栅极层的垂直投影区域内，对应于所述栅极层的钝化层具有凹凸表面。
在本申请所述的薄膜晶体管中，对应于所述漏极层的钝化层设置有通孔，所述通孔用于实现所述漏极层和透明电极层的连接。
在本申请所述的薄膜晶体管中，所述钝化层为SiN x层，所述半导体层为A-si层。
本申请实施例还提供一种薄膜晶体管的制造方法，包括：
提供基板；
在所述基板上形成栅极层；
在所述基板上和所述栅极层上形成栅极绝缘层；
在所述栅极绝缘层上形成半导体层；
在所述半导体层上形成源极层和漏极层，所述源极层和漏极层间隔设置，以在所述源极层和所述漏极层之间形成所述半导体层的沟道区；
在所述栅极绝缘层、源极层、漏极层以及所述半导体层的沟道区上形成钝化层；
对所述钝化层进行蚀刻，以使得对应于所述沟道区的钝化层具有凹凸表面。
在本申请所述的制造方法中，所述对所述钝化层进行蚀刻，包括：
提供一光罩，所述光罩上设置有多个第一透光孔和一个第二透光孔，所述第一透光孔的宽度小于曝光机的解析度；
在所述钝化层上形成光阻层，并将光罩罩设在所述光阻层上，其中所述多个第一透光孔位于与所述沟道区对应的光阻层上方，所述第二透光孔位于与所述漏极层对应的光阻上方；
利用所述曝光机对光阻层进行曝光；
对曝光后的所述光阻层进行显影处理，以除去曝光的光阻层；
以显影后的光阻层为掩模对所述钝化层进行蚀刻，以使得对应于所述沟道区的钝化层具有凹凸表面，并在对应于所述漏极层的钝化层中形成通孔。
在本申请所述的制造方法中，所述第二透光孔的宽度大于曝光机的解析度。
在本申请所述的制造方法中，所述多个第一透光孔位于与所述栅极层对应的光阻层上方；
所述在所述半导体层上形成源极层和漏极层，所述源极层和漏极层间隔设置，以在所述源极层和所述漏极层之间形成所述半导体层的沟道区，包括：使所述沟道区的垂直投影区域位于所述栅极层的垂直投影区域内。
在本申请所述的制造方法中，所述对所述钝化层进行蚀刻，包括：
提供一光罩，所述光罩上设置有半透膜区域以及一透光孔；
在所述钝化层上形成光阻层，并将光罩罩设在所述光阻层上，其中所述半透膜区域位于与所述沟道区对应的光阻层上方，所述透光孔位于与所述漏极层对应的光阻层上方；
利用曝光机对光阻层进行曝光；
对曝光后的所述光阻层进行显影处理，以除去曝光的光阻层；
以显影后的光阻层为掩模对所述钝化层进行蚀刻，以使得对应于所述沟道区的钝化层具有凹凸表面，并在对应于所述漏极层的钝化层中形成通孔。
在本申请所述的制造方法中，所述半透膜区域中的图形为多个半透膜层和挡光层交替排列。
在本申请所述的制造方法中，所述半透膜层的透光率为50%。
在本申请所述的制造方法中，所述多个半透膜层的透光率相同。
在本申请所述的制造方法中，所述多个半透膜层的透光率不相同。
在本申请所述的制造方法中，所述钝化层为SiN x层，所述半导体层为A-si层。
在本申请所述的制造方法中，所述在所述半导体层上形成源极层和漏极层，包括：
在所述半导体层上沉积一金属层；
对所述金属层进行图案化处理，以形成源极层和漏极层。
在本申请所述的制造方法中，所述在基板上形成栅极层，包括：
在所述基板上沉积一金属层；
对所述金属层进行图案化处理，以形成栅极层。
 有益效果
本申请的薄膜晶体管中，通过在基板上依次形成栅极层、栅极绝缘层、半导体层、源极层、漏极层以及钝化层，钝化层形成在栅极绝缘层、源极层、漏极层以及沟道区的半导体层上，其中对应于沟道区的钝化层具有凹凸表面，由此可以使得照射至该凹凸表面的光线产生折射、全反射、漫反射等，从而可以减少到达沟道区的光线，以减少光照对半导体层沟道区的影响，有利于提升薄膜晶体管的电性稳定性，并且不需要牺牲像素电极的面积，可以确保开口率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的薄膜晶体管的一结构示意图；
图2是本申请实施例提供的薄膜晶体管的另一结构示意图；
图3是本申请实施例提供的薄膜晶体管的制造方法的流程示意图；
图4是本申请实施例提供的薄膜晶体管的制造方法中，对钝化层进行蚀刻的流程示意图；
图5是本申请实施例提供的薄膜晶体管的制造方法中，光罩的一结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参阅图1，本申请一实施例提供的薄膜晶体管中，薄膜晶体管包括基板10、栅极层11、栅极绝缘层12、半导体层13、源极层14、漏极层15以及钝化层16。
其中，基板10例如可以是玻璃基板或者其他材质的基板。栅极层11作为薄膜晶体管的栅极，形成在基板10上，栅极绝缘层12形成在基板10上并且覆盖栅极层11。半导体层13比如可以是A-si（非晶硅）层，形成在栅极绝缘层12上，其包括沟道区131。源极层14和漏极层15分别作为薄膜晶体管的源极和漏极，形成在半导体层13上，且源极层14和漏极层15间隔沟道区131而相对设置，即位于源极层14和漏极层15之间的半导体层为沟道区131。钝化层16比如可以是SiN x（氮化硅）层，其形成在栅极绝缘层12、源极层14、漏极层15以及半导体层13的沟道区131上，起到保护作用。
如图所示，对应于沟道区131的钝化层161具有凹凸表面，即本实施例中，在沟道区131上方、覆盖沟道区131的钝化层161的表面为凹凸表面，为不平整的表面，由此通过该凹凸表面，可以使得照射至该凹凸表面的光线产生折射、全反射、漫反射等，从而可以减少到达沟道区131的光线，以减少光照对半导体层的沟道区131的影响，有利于提升薄膜晶体管的电性稳定性，同时还可以简化制程。并且，由于不需要牺牲像素电极的面积，可以确保开口率。
其中，该凹凸表面可以是凹凸均匀的锯齿状表面，或者凹凸表面也可以是凹凸不均匀的表面。
其中，对应于漏极层15的钝化层16中设置有通孔162，即在位于漏极层15上的钝化层16中设置有通孔162，当将薄膜晶体管应用于液晶显示面板等面板结构中时，该通孔162用于实现漏极层15和透明电极层17的连接，该透明电极层17例如可以为像素电极。
参阅图2，在本申请另一实施例中，半导体层13的沟道区131的垂直投影区域位于栅极层11的垂直投影区域内。钝化层16中，对应于栅极层11的钝化层163具有凹凸表面，该钝化层163包含对应于沟道区131的钝化层，即在本实施例中，扩大钝化层16的凹凸表面范围，使对应于栅极层11的钝化层163的表面均为凹凸表面，可以使得更多光线产生反射及折射等，以进一步减少光照对沟道区131的影响，同时可以确保开口率。
参阅图3，本申请实施例还提供一种薄膜晶体管的制造方法，用于制造上述各实施例的薄膜晶体管，该制造方法具体可以包括如下步骤：
S301、提供基板。比如，可以是玻璃基板或者其他材质的基板。
S302、在基板上形成栅极层。
例如，可以先在基板上沉积一层金属层，然后利用具有栅极层图案的光罩对金属层进行图案化处理，从而可以得到栅极层。
S303、在基板和栅极层上形成栅极绝缘层。从而使得栅极绝缘层覆盖栅极层，以起到绝缘作用。
S304、在栅极绝缘层上形成半导体层。该半导体层例如可以是A-si层。
S305、在半导体层上形成源极层和漏极层，源极层和漏极层间隔设置，以在源极层和漏极层之间形成半导体层的沟道区。
譬如，可以先在半导体层上沉积一层金属层，然后对金属层进行图案化处理，以形成源极层和漏极层，所形成的源极层和漏极层相对设置，两者之间的半导体层为沟道区。
S306、在栅极绝缘层、源极层、漏极层以及半导体层的沟道区上形成钝化层。
钝化层如可以是SiN x层。通过在裸露的栅极绝缘层、源极层、漏极层以及沟道区上形成钝化层，从而利用钝化层可以起到保护和隔绝作用。
S307、对钝化层进行蚀刻，以使得对应于沟道区的钝化层具有凹凸表面。
本实施例中，通过蚀刻的方式除去部分钝化层，以使得对应于沟道区的钝化层的表面为凹凸表面。
在一种实现方式中，可以采用具有小于曝光机解析度的透光孔的光罩来形成钝化层的凹凸表面，具体地，结合图4，步骤S307可以包括如下子步骤：
（11）提供一光罩40，光罩40上设置有多个第一透光孔401和一个第二透光孔402，第一透光孔401的宽度小于曝光机的解析度。
其中第一透光孔401和第二透光孔402均为贯穿光罩40的通孔。
（12）结合图4的步骤S401，在钝化层16上形成光阻层18，并将光罩40罩设在光阻层18上，其中，多个第一透光孔401位于与沟道区131对应的光阻层上方，第二透光孔402位于与漏极层15对应的光阻层上方。
（13）利用曝光机对光阻层18进行曝光。
本实施例中，第二透光孔402的宽度大于曝光机的解析度，并且通过使多个第一透光孔401的宽度小于曝光机的解析度，因此在进行曝光时，在同等曝光条件下，可以使得与第二透光孔402对应的光阻层完全曝光，而由于第一透光孔401的宽度小于曝光机的解析度，因此可以减少通过第一透光孔401的光线，从而减少对应第一透光孔401的光阻层所受到的光能量，使得对应第一透光孔401的光阻层不完全曝光，即部分曝光。
（14）结合图4的步骤S402，对曝光后的光阻层18进行显影处理，以除去曝光的光阻层。
其中，由于与第一透光孔401对应的光阻层为不完全曝光，即仅是曝光了部分厚度的光阻层，而与第二透光孔402对应的光阻层为完全曝光，因此在显影处理后，可以除去与多个第一透光孔401对应的部分光阻层，从而形成表面凹凸不平的光阻层，而与第二透光孔402对应的光阻层则完全除去，从而在光阻层18上形成通孔，以暴露部分钝化层16。
（15）以显影后的光阻层18为掩模对钝化层16进行蚀刻，以使得对应于沟道区131的钝化层161具有凹凸表面，并在对应于漏极层15的钝化层16中形成通孔162。
其中，多个第一透光孔401所对应的光阻层也即对应于沟道区131的光阻层，因此对应于沟道区131的光阻层在显影后被除去一部分，因此，在对钝化层16进行蚀刻时，在同等蚀刻条件下，在漏极层15上暴露的钝化层16将被完全蚀刻掉，从而在漏极层15上的钝化层16形成通孔162，而对应于沟道区131的钝化层161，由于其上方还存在一定厚度的光阻层18，且是厚度不一的光阻层，因此在进行蚀刻时是先对钝化层161上方的光阻层18进行蚀刻，且随着蚀刻的进行，漏极层15上暴露的钝化层16被完全蚀刻之后，沟道区131上的钝化层161仅是部分被蚀刻掉，由此可形成凹凸表面的钝化层161。
（16）除去残余的光阻层。如图4所示的步骤S403，除去残余的光阻层后，得到与沟道区131对应的且具有凹凸表面的钝化层161，以及使得对应于漏极层15的钝化层16中形成通孔162，以暴露部分漏极层15，从而利用通孔162可以实现漏极层15和透明电极层17的连接。
与图4所示实施例不同的是，在另一实施方式中，还可以通过半透膜光罩来形成钝化层的凹凸表面。例如，步骤S307中对钝化层进行蚀刻具体可以包括如下子步骤：
（21）提供一光罩，光罩上设置有半透膜区域以及一透光孔。
其中，如图5所示，本实施例的光罩50可以是半透膜光罩，即利用半透膜光罩工艺来对钝化层进行蚀刻，以形成凹凸表面。例如，光罩50上设置有半透膜区域51和透光孔52，光罩50的其它部分为不透光区域。半透膜区域51中的图形例如可以是多个半透膜层511和挡光层（阴影区域）512交替排列，半透膜层511允许通过部分光线，其透光率可以根据实际需要进行设置，比如可以设置为50%或60%等，即半透膜层511可以是允许透过50%光线的半透膜，或者可以是允许透过60%光线的半透膜，等等。挡光层512为不透光层，而透光孔52为光罩50上的贯穿孔，可以全透光。
其中，多个半透膜层511的透光率可以相同，也可以不同。
（22）在钝化层上形成光阻层，并将光罩罩设在光阻层上，其中半透膜区域位于与沟道区对应的光阻层上方，透光孔位于漏极层对应的光阻层上方。
（23）利用曝光机对光阻层进行曝光。
其中，在半透膜区域51具有多个半透膜层511，而透光孔52为全透光，因此在曝光时，在同等曝光条件下，当透光孔52对应的光阻层完全曝光时，半透膜层511对应的光阻层由于半透膜层511的半透光作用仅是部分曝光（仅是曝光了部分厚度的光阻层）。
（24）对曝光后的光阻层进行显影处理，以除去曝光的光阻层。
其中，由于与半透膜层511对应的光阻层为部分曝光，而与透光孔52对应的光阻层为完全曝光，因此在显影处理后，可以除去与半透膜层511对应对应的部分光阻层，从而形成表面凹凸不平的光阻层，而与透光孔52对应的光阻层则完全除去，从而在光阻层上形成通孔，以暴露部分钝化层。
（25）以显影后的光阻层为掩模对钝化层进行蚀刻，以使得对应于沟道区的钝化层具有凹凸表面，并在对应于漏极层的钝化层中形成通孔。
其中，多个半透膜层511所对应的光阻层也即对应于沟道区的光阻层，因此对应于沟道区的光阻层在显影后被除去一部分，因此，在对钝化层进行蚀刻时，在同等蚀刻条件下，当漏极层上暴露的钝化层被完全蚀刻掉以在漏极层上的钝化层形成通孔时，对应于沟道区的钝化层，由于其上方还存在一定厚度的光阻层，且是厚度不一的光阻层，因此在进行蚀刻时是先对钝化层上方的光阻层进行蚀刻，且随着蚀刻的进行，漏极层上暴露的钝化层被完全蚀刻之后，沟道区上的钝化层仅是部分被蚀刻掉，由此可形成凹凸表面的钝化层。
本申请实施例的制造方法中，通过使沟道区131上方的钝化层161具有凹凸表面，由此通过该凹凸表面，可以使得照射至该凹凸表面的光线产生折射、全反射、漫反射等，从而可以减少到达沟道区131的光线，以减少光照对半导体层的沟道区131的影响，有利于提升薄膜晶体管的电性稳定性，并且，由于不需要牺牲像素电极的面积，可以确保开口率。此外，在制造过程中，只需在光罩上增设第一透光孔，制作简单方便，有利于降低成本，且可以简化制程。
其中，钝化层的凹凸表面可以是凹凸均匀的锯齿状表面，也可以是凹凸不均匀的表面，具体可以根据实际需要进行选择，比如可以通过设计第一透光孔（或者半透膜层）的形状来决定凹凸表面的凹凸状，或者通过蚀刻方式来决定凹凸表面的凹凸状等。
在本申请另一实施例中，沟道区的垂直投影区域在栅极层的垂直投影区域内，还可以使得对应于栅极层的钝化层具有凹凸表面，此时，只需设置光罩的多个第一透光孔或半透膜区域位于与栅极层对应的光阻层上方即可，从而在进行曝光显影处理之后，可以使得与栅极层对应的光阻层为凹凸不平表面的光阻层，使得该部分光阻层的厚度不一，从而在对钝化层进行蚀刻时，可以使得对应于栅极层的钝化层的表面被蚀刻为凹凸不平的表面。
以上对本申请实施例所提供的一种薄膜晶体管及其制造方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种薄膜晶体管，其中，包括：
    基板；
    形成于所述基板上的栅极层；
    形成于所述基板上、且覆盖所述栅极层的栅极绝缘层；
    形成于所述栅极绝缘层上的半导体层，所述半导体层包括沟道区；
    形成于所述半导体层上的源极层和漏极层，所述源极层和漏极层间隔所述沟道区而相对设置；
    形成于所述栅极绝缘层、源极层、漏极层以及所述半导体层的沟道区上的钝化层；
    其中，对应于所述沟道区的钝化层具有凹凸表面，对应于所述漏极层的钝化层设置有通孔，所述通孔用于实现所述漏极层和透明电极层的连接，所述钝化层为SiN x层，所述半导体层为A-si层。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述凹凸表面为凹凸均匀的锯齿状表面。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述沟道区的垂直投影区域位于所述栅极层的垂直投影区域内，对应于所述栅极层的钝化层具有凹凸表面。
  4. 一种薄膜晶体管，其中，包括：
    基板；
    形成于所述基板上的栅极层；
    形成于所述基板上、且覆盖所述栅极层的栅极绝缘层；
    形成于所述栅极绝缘层上的半导体层，所述半导体层包括沟道区；
    形成于所述半导体层上的源极层和漏极层，所述源极层和漏极层间隔所述沟道区而相对设置；
    形成于所述栅极绝缘层、源极层、漏极层以及所述半导体层的沟道区上的钝化层；
    其中，对应于所述沟道区的钝化层具有凹凸表面。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述凹凸表面为凹凸均匀的锯齿状表面。
  6. 根据权利要求4所述的薄膜晶体管，其中，所述沟道区的垂直投影区域位于所述栅极层的垂直投影区域内，对应于所述栅极层的钝化层具有凹凸表面。
  7. 根据权利要求4所述的薄膜晶体管，其中，对应于所述漏极层的钝化层设置有通孔，所述通孔用于实现所述漏极层和透明电极层的连接。
  8. 根据权利要求4所述的薄膜晶体管，其中，所述钝化层为SiN x层，所述半导体层为A-si层。
  9. 一种薄膜晶体管的制造方法，其中，包括：
    提供基板；
    在所述基板上形成栅极层；
    在所述基板上和所述栅极层上形成栅极绝缘层；
    在所述栅极绝缘层上形成半导体层；
    在所述半导体层上形成源极层和漏极层，所述源极层和漏极层间隔设置，以在所述源极层和所述漏极层之间形成所述半导体层的沟道区；
    在所述栅极绝缘层、源极层、漏极层以及所述半导体层的沟道区上形成钝化层；
    对所述钝化层进行蚀刻，以使得对应于所述沟道区的钝化层具有凹凸表面。
  10. 根据权利要求9所述的制造方法，其中，所述对所述钝化层进行蚀刻，包括：
    提供一光罩，所述光罩上设置有多个第一透光孔和一个第二透光孔，所述第一透光孔的宽度小于曝光机的解析度；
    在所述钝化层上形成光阻层，并将光罩罩设在所述光阻层上，其中所述多个第一透光孔位于与所述沟道区对应的光阻层上方，所述第二透光孔位于与所述漏极层对应的光阻层上方；
    利用所述曝光机对光阻层进行曝光；
    对曝光后的所述光阻层进行显影处理，以除去曝光的光阻层；
    以显影后的光阻层为掩模对所述钝化层进行蚀刻，以使得对应于所述沟道区的钝化层具有凹凸表面，并在对应于所述漏极层的钝化层中形成通孔。
  11. 根据权利要求10所述的制造方法，其特征在于，所述第二透光孔的宽度大于曝光机的解析度。
  12. 根据权利要求10所述的制造方法，其中，所述多个第一透光孔位于与所述栅极层对应的光阻层上方；
    所述在所述半导体层上形成源极层和漏极层，所述源极层和漏极层间隔设置，以在所述源极层和所述漏极层之间形成所述半导体层的沟道区，包括：使所述沟道区的垂直投影区域位于所述栅极层的垂直投影区域内。
  13. 根据权利要求9所述的制造方法，其中，所述对所述钝化层进行蚀刻，包括：
    提供一光罩，所述光罩上设置有半透膜区域以及一透光孔；
    在所述钝化层上形成光阻层，并将光罩罩设在所述光阻层上，其中所述半透膜区域位于与所述沟道区对应的光阻层上方，所述透光孔位于与所述漏极层对应的光阻层上方；
    利用曝光机对光阻层进行曝光；
    对曝光后的所述光阻层进行显影处理，以除去曝光的光阻层；
    以显影后的光阻层为掩模对所述钝化层进行蚀刻，以使得对应于所述沟道区的钝化层具有凹凸表面，并在对应于所述漏极层的钝化层中形成通孔。
  14. 根据权利要求13所述的制造方法，其中，所述半透膜区域中的图形为多个半透膜层和挡光层交替排列。
  15. 根据权利要求14所述的制造方法，其中，所述半透膜层的透光率为50%。
  16. 根据权利要求14所述的制造方法，其中，所述多个半透膜层的透光率相同。
  17. 根据权利要求14所述的制造方法，其中，所述多个半透膜层的透光率不相同。
  18. 根据权利要求9所述的制造方法，其中，所述钝化层为SiN x层，所述半导体层为A-si层。
  19. 根据权利要求9所述的制造方法，其中，所述在所述半导体层上形成源极层和漏极层，包括：
    在所述半导体层上沉积一金属层；
    对所述金属层进行图案化处理，以形成源极层和漏极层。
  20. 根据权利要求9所述的制造方法，其中，所述在基板上形成栅极层，包括：
    在所述基板上沉积一金属层；
    对所述金属层进行图案化处理，以形成栅极层。
PCT/CN2019/070329 2018-10-11 2019-01-04 薄膜晶体管及其制造方法 WO2020073547A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811183212.2 2018-10-11
CN201811183212.2A CN109378345A (zh) 2018-10-11 2018-10-11 薄膜晶体管及其制造方法

Publications (1)

Publication Number Publication Date
WO2020073547A1 true WO2020073547A1 (zh) 2020-04-16

Family

ID=65402957

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/070329 WO2020073547A1 (zh) 2018-10-11 2019-01-04 薄膜晶体管及其制造方法

Country Status (2)

Country Link
CN (1) CN109378345A (zh)
WO (1) WO2020073547A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110120427A (zh) * 2019-04-28 2019-08-13 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管结构
CN113488517B (zh) * 2021-06-28 2022-09-27 深圳市华星光电半导体显示技术有限公司 显示面板的制作方法及光罩

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105470268A (zh) * 2016-01-11 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN205789970U (zh) * 2016-05-03 2016-12-07 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN106298646A (zh) * 2016-08-17 2017-01-04 深圳市华星光电技术有限公司 Tft基板的制作方法
CN106684103A (zh) * 2017-02-28 2017-05-17 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN107731853A (zh) * 2017-09-27 2018-02-23 武汉华星光电技术有限公司 一种阵列基板、掩膜板及阵列基板制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105470268A (zh) * 2016-01-11 2016-04-06 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN205789970U (zh) * 2016-05-03 2016-12-07 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN106298646A (zh) * 2016-08-17 2017-01-04 深圳市华星光电技术有限公司 Tft基板的制作方法
CN106684103A (zh) * 2017-02-28 2017-05-17 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN107731853A (zh) * 2017-09-27 2018-02-23 武汉华星光电技术有限公司 一种阵列基板、掩膜板及阵列基板制作方法

Also Published As

Publication number Publication date
CN109378345A (zh) 2019-02-22

Similar Documents

Publication Publication Date Title
KR101255616B1 (ko) 다중톤 광마스크, 이의 제조방법 및 이를 이용한박막트랜지스터 기판의 제조방법
KR100759627B1 (ko) 박막의 패턴닝 방법 및 그것을 이용한 tft 어레이 기판 및그 제조 방법
KR101322885B1 (ko) 어레이 기판과 액정 디스플레이
WO2018210186A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示面板
JP4594292B2 (ja) フォトマスク及びこれを利用した液晶表示装置用アレイ基板の製造方法
WO2014205998A1 (zh) Coa基板及其制造方法、显示装置
KR20140042697A (ko) 활성층 이온 주입 방법 및 박막 트랜지스터용 활성층 이온 주입 방법
CN106206456A (zh) 一种阵列基板的制作方法、阵列基板及显示装置
TWI333279B (en) Method for manufacturing an array substrate
WO2013143321A1 (zh) 阵列基板及其制造方法和显示装置
JP2006030319A (ja) グレートーンマスク及びグレートーンマスクの製造方法
WO2022183822A1 (zh) 阵列基板的制备方法及阵列基板
WO2014205987A1 (zh) 一种阵列基板及其制造方法、显示装置
WO2020073547A1 (zh) 薄膜晶体管及其制造方法
WO2018166022A1 (zh) Tft基板的制作方法及tft基板
KR102316173B1 (ko) 마스크 및 어레이 기판의 제조방법
WO2018205596A1 (zh) 薄膜晶体管及其制造方法、阵列基板、显示面板及显示装置
WO2014153866A1 (zh) 一种掩膜板及其制造方法
JP2020519958A (ja) フォトマスク構造及びアレイ基板の製造方法
JP2004014622A (ja) 薄膜半導体装置の製造方法及びそのレジストパターン形成方法
WO2021128508A1 (zh) Tft阵列基板及其制作方法
KR100309212B1 (ko) 노광마스크와 노광방법
CN111627929B (zh) 高穿透性液晶显示面板及制备方法
US10345697B2 (en) Mask plates and manufacturing methods of array substrates
CN111584424B (zh) 一种阵列基板制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19870561

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19870561

Country of ref document: EP

Kind code of ref document: A1