WO2020062497A1 - 低温多晶硅层、薄膜晶体管及其制作方法 - Google Patents

低温多晶硅层、薄膜晶体管及其制作方法 Download PDF

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Publication number
WO2020062497A1
WO2020062497A1 PCT/CN2018/116173 CN2018116173W WO2020062497A1 WO 2020062497 A1 WO2020062497 A1 WO 2020062497A1 CN 2018116173 W CN2018116173 W CN 2018116173W WO 2020062497 A1 WO2020062497 A1 WO 2020062497A1
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polysilicon layer
low
region
channel region
layer
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French (fr)
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李立胜
何鹏
颜源
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/344,018 priority Critical patent/US11101387B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2922—Materials being non-crystalline insulating materials, e.g. glass or polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3248—Layer structure consisting of two layers
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a low-temperature polysilicon layer, a thin film transistor, and a manufacturing method thereof.
  • LTPS Low temperature poly silicon
  • TFT LCD thin film transistor-liquid crystal display
  • AMOLED organic light emitting diode
  • thin film transistors usually include a top gate structure and a light shielding layer.
  • shield layer (LS) in which the preparation of the light-shielding layer requires an additional process of forming a light-shielding mask, so the number of photomasks required for the manufacture of the thin film transistor array substrate is longer and the product manufacturing cycle is longer.
  • the channel of a thin film transistor is likely to cause photo-generated leakage current. Excessive leakage current will significantly affect the optical display effect of the display, such as crosstalk. , Flicker, contrast reduction, etc.
  • thin film transistors usually include a top gate structure and a light shielding layer.
  • shield layer (LS) in which the preparation of the light-shielding layer requires an additional process of forming a light-shielding mask, so the number of photomasks required for the manufacture of the thin film transistor array substrate is longer and the product manufacturing cycle is longer.
  • the channel of a thin film transistor is likely to cause photo-generated leakage current. Excessive leakage current will significantly affect the optical display effect of the display, such as crosstalk. , Flicker, contrast reduction, etc.
  • the present disclosure provides a method for manufacturing a low-temperature polysilicon layer, including: providing a substrate; forming at least one buffer layer on the substrate; forming a polysilicon layer on the at least one buffer layer; and patterning the polysilicon Layer to form a channel region, two sides of the channel region including two lowly doped regions arranged symmetrically, and an outer side of the low doped region including two highly doped regions arranged symmetrically; in the polysilicon layer An island-shaped photoresist layer is deposited on the channel region, the low-doped region, and the highly-doped region; removing the island-shaped light covering the edge of the channel region and the low-doped region A resist layer to expose the edge of the channel region and the low-doped region; and etch the edge of the channel region and at least part of the low-doped region so that the channel region A thickness of the edge and at least part of the low-doped region is smaller than a thickness of other positions of the polysili
  • the lowly doped region is an N lowly doped region
  • the highly doped region is an N highly doped region.
  • the island-shaped photoresist layer has a first thickness and a second thickness, the first thickness is smaller than the second thickness, and the island-shaped photoresist layer having the first thickness covers all of the channel region. The edge and the low-doped region.
  • the island-shaped photoresist layer is exposed and developed through a half-tone mask to form the island-shaped photoresist layer.
  • the half-tone mask has an opaque region and a light-transmitting region. The transparent region corresponds to the edge of the channel region and the low-doped region, and the opaque region of the halftone mask corresponds to the other positions of the polysilicon layer.
  • the channel regions of the polysilicon layer have different thicknesses, and the edges of the channel region of the polysilicon layer and at least a portion of the low-doped regions have different thicknesses.
  • the thickness is smaller than the thickness of other positions of the channel region of the polysilicon layer.
  • the highly doped regions of the polysilicon layer have different thicknesses, and edges of the highly doped regions of the polysilicon layer contact the lowly doped regions and the highly doped regions
  • the thickness of the edge of the doped region is equal to the thickness of the edge of the channel region of the polysilicon layer and at least a portion of the lowly doped region, and the thickness of other positions of the highly doped region It is equal to the thickness of other positions of the channel region of the polysilicon layer.
  • the present disclosure also provides a method for manufacturing a low-temperature polysilicon layer, including: providing a substrate; forming at least one buffer layer on the substrate; forming a polysilicon layer on the at least one buffer layer; and patterning the polysilicon layer to form a channel Region, two sides of the channel region include two lowly doped regions symmetrically arranged, and the outside of the low doped region includes two highly doped regions symmetrically arranged; the channel of the polysilicon layer Depositing an island-shaped photoresist layer on the region, the low-doped region, and the highly-doped region; removing the island-shaped photoresist layer covering the edge of the channel region and the low-doped region to expose The edge of the channel region and the low-doped region are etched; the edge of the channel region and at least part of the low-doped region are etched, so that the edge and At least part of the thickness of the low-doped region is smaller than the thickness of other positions of the polysilicon layer to form an
  • the method further includes forming an amorphous silicon layer on the at least one buffer layer, and performing an excimer laser on the amorphous silicon layer, so that the amorphous silicon layer becomes an amorphous silicon layer.
  • the polysilicon layer the polysilicon layer not covered by the island-shaped photoresist layer is removed by etching.
  • the low-doped region is an N-lowly-doped region
  • the highly-doped region is an N-highly-doped region
  • the island-shaped photoresist layer has a first thickness and a second thickness, the first thickness is smaller than the second thickness, and the island-shaped light having the first thickness is A resist layer covers the edge of the channel region and at least a portion of the low-doped region.
  • the island-shaped photoresist layer is exposed and developed through a half-tone mask to form the island-shaped photoresist layer.
  • the half-tone mask has an opaque region and a transparent layer. Light region, the light-transmitting region of the half-tone mask corresponds to the edge and the low-doped region of the channel region, and the opaque region of the half-tone mask corresponds to The other positions of the polysilicon layer.
  • a photoresist ashing treatment is performed on the island-shaped photoresist layer covering the edge of the channel region and the low-doped region by introducing oxygen to remove the cover. The edge of the channel region and the island-shaped photoresist layer of the low-doped region.
  • the channel regions of the polysilicon layer have different thicknesses, and the edges of the channel region of the polysilicon layer and at least a portion of the low-doped regions have different thicknesses.
  • the thickness is smaller than the thickness of other positions of the channel region of the polysilicon layer.
  • the highly doped regions of the polysilicon layer have different thicknesses, and edges of the highly doped regions of the polysilicon layer contact the lowly doped regions and the highly doped regions
  • the thickness of the edge of the doped region is equal to the thickness of the edge of the channel region of the polysilicon layer and at least a portion of the lowly doped region, and the thickness of other positions of the highly doped region It is equal to the thickness of other positions of the channel region of the polysilicon layer.
  • the present disclosure also provides a method for manufacturing a thin film transistor, including: providing a low temperature polysilicon layer and forming a gate insulation layer, a gate electrode, an interlayer dielectric insulation layer, two vias, a source electrode, and a drain electrode on the low temperature polysilicon layer,
  • the vias penetrate the gate insulating layer and the interlayer dielectric insulating layer, and the source electrode and the drain electrode are in contact with both ends of the low-temperature polysilicon layer through corresponding vias, and the low-temperature polysilicon layer It is made by the aforementioned method for manufacturing the low-temperature polysilicon layer.
  • a distance between the gate electrode and the edge of the channel region of the polysilicon layer is smaller than other positions of the gate electrode and the channel region of the polysilicon layer. the distance.
  • a distance between the gate electrode and at least a portion of the low-doped region of the polysilicon layer is smaller than the other of the gate electrode and the channel region of the polysilicon layer. The distance of the location.
  • the present disclosure also provides a low-temperature polysilicon layer, including a substrate, at least one buffer layer, and a polysilicon layer.
  • the at least one buffer layer is disposed on the substrate.
  • the polysilicon layer is disposed on the at least one buffer layer.
  • the polysilicon layer includes a channel region, two low-doped regions disposed on both sides of the channel region, and two highly-doped regions disposed outside the low-doped region. A thickness of an edge of the channel region and at least a part of the low-doped region is smaller than a thickness of other positions of the polysilicon layer.
  • the low-doped region is an N-lowly-doped region
  • the highly-doped region is an N-highly-doped region
  • the channel regions of the polysilicon layer have different thicknesses, and the edges of the channel region of the polysilicon layer and at least a portion of the low-doped regions have different thicknesses.
  • the thickness is smaller than the thickness of other positions of the channel region of the polysilicon layer.
  • the highly doped regions of the polysilicon layer have different thicknesses, and edges of the highly doped regions of the polysilicon layer contact the lowly doped regions and the highly doped regions
  • the thickness of the edge of the doped region is equal to the thickness of the edge of the channel region of the polysilicon layer and at least a portion of the lowly doped region, and the thickness of other positions of the highly doped region It is equal to the thickness of other positions of the channel region of the polysilicon layer.
  • the present disclosure also provides a thin film transistor including the aforementioned low-temperature polysilicon layer and a gate insulating layer, a gate electrode, an interlayer dielectric insulating layer, two vias, a source electrode, and a drain electrode disposed on the low-temperature polysilicon layer.
  • the via hole penetrates the gate insulating layer and the interlayer dielectric insulating layer, and the source electrode and the drain electrode are in contact with both ends of the low-temperature polysilicon layer through corresponding via holes.
  • a distance between the gate electrode and the edge of the channel region of the polysilicon layer is smaller than other positions of the gate electrode and the channel region of the polysilicon layer. the distance.
  • a distance between the gate electrode and at least a portion of the low-doped region of the polysilicon layer is smaller than the other of the gate electrode and the channel region of the polysilicon layer. The distance of the location.
  • the present disclosure provides a low-temperature polysilicon layer, a thin film transistor, and a method for manufacturing the same.
  • the thickness is smaller than the thickness of other positions of the polysilicon layer, which can reduce the absorption of photons by the low-temperature polysilicon layer and the photo-generated leakage current of the low-temperature polysilicon layer.
  • FIG. 1 shows a flowchart of a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 2 is a schematic diagram showing a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 3 is a schematic diagram showing a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 4 is a schematic diagram showing a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 5 is a schematic diagram of a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 6 is a schematic diagram of a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 7 shows a schematic diagram of a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 8 is a schematic diagram showing a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 9 shows a schematic diagram of a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure.
  • FIG. 10 shows a schematic diagram of a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 11 is a schematic diagram showing a method for manufacturing a low-temperature polysilicon layer according to an embodiment of the disclosure
  • FIG. 12 shows a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the disclosure
  • FIG. 13 is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • FIG. 14 is a schematic structural diagram of a low-temperature polysilicon layer according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a method for manufacturing a low-temperature polysilicon layer, including the following steps.
  • step 1 provides a substrate 110.
  • the substrate 110 is, for example, a glass substrate.
  • step 2 forms at least one buffer layer 120 on the substrate 110.
  • the material of the at least one buffer layer 120 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination thereof.
  • the at least one buffer layer 120 may have a structure of two buffer layers. The materials of the two buffer layers may be different. Since the at least one buffer layer 120 is disposed on the substrate 110, it has the functions of blocking ion diffusion and heat preservation, and preventing the substrate 110 from being damaged.
  • an amorphous silicon layer 130 is formed on at least one buffer layer 120.
  • step 4 performing an excimer laser on the amorphous silicon layer 130 to make the amorphous silicon layer 130 a polysilicon layer 140.
  • the polysilicon layer 140 is patterned to form a channel region 142. Both sides of the channel region 142 include two lowly doped regions 144 disposed symmetrically, and the outer side of the low doped region 144 includes two highly doped regions 146 disposed symmetrically.
  • the low-doped region 144 is an N-lowly-doped region
  • the highly-doped region 146 is an N-highly-doped region.
  • an island-shaped photoresist layer 150 is deposited on the channel region 142, the low-doped region 144 and the highly-doped region 146 of the polysilicon layer 140.
  • the island-shaped photoresist layer 150 has a first thickness and a second thickness, and the first thickness is smaller than the second thickness.
  • the island-shaped photoresist layer 150 with the first thickness covers the edge of the channel region 142 and the low-doped region.
  • the island-shaped photoresist layer 150 is exposed and developed through the half-tone mask 160 to form the island-shaped photoresist layer 150.
  • the half-tone mask 160 has an opaque region 162 and a light-transmissive region 164.
  • the light-transmissive region 164 of the half-tone mask 160 corresponds to the edge of the channel region 142 and the low-doped region 144, and the The light-transmitting region 162 corresponds to other positions of the polysilicon layer 140.
  • step 7 the polysilicon layer 140 that is not covered by the island-shaped photoresist layer 150 is removed by etching.
  • step 8 the island-shaped photoresist layer 150 covering the edge of the channel region 142 and the low-doped region 144 is removed to expose the edge of the channel region 142 and the low-doped region 146.
  • the island-shaped photoresist layer 150 covering the edge of the highly doped region 146 is also removed to expose the edge of the highly doped region 146, and the edge of the highly doped region 146 contacts the lowly doped region 144.
  • the island-shaped photoresist layer 150 covering the edges of the channel region 142, the edges of the low-doped region 144, and the edges of the highly-doped region 146 is photoresisted with oxygen (O2). (ash) processing to remove the island-shaped photoresist layer 150 covering the edges of the channel region 142, the edges of the low-doped region 144, and the edges of the highly-doped region 146.
  • O2 oxygen
  • the edges of the channel region 142 and at least a portion of the low-doped region 144 are etched, so that the thickness of the edge of the channel region 142 and the low-doped region 144 is smaller than that of other positions of the polysilicon layer 140 Thickness to form an island-shaped polysilicon layer.
  • the edge of the channel region 142 and the thickness of the low-doped region 144 are controlled by the etching time to form an island-shaped polysilicon layer.
  • the polysilicon layer 140 is, for example, a convex island-shaped polysilicon layer.
  • the channel region 142 of the polysilicon layer 140 has different thicknesses, and the edges of the channel region 142 of the polysilicon layer 140 and the thickness of at least a portion of the low-doped region 144 are smaller than the thickness of other positions of the channel region 142 of the polysilicon layer 140. .
  • the entire low-doped region 144 is not etched.
  • the left and right 0.5-1um need to be etched, and the width of the low-doped region 144144 is 0.7- Between 1.5um, the low-doped region 144 may not be completely etched, but the entire etch may even extend to a portion of the highly-doped region 146.
  • the highly doped regions 146 of the polysilicon layer 140 have different thicknesses.
  • the edges of the highly doped regions 146 of the polysilicon layer 140 contact the lowly doped regions 144 and the thickness of the edges of the highly doped regions 146 is equal to the trenches of the polysilicon layer 140.
  • the thickness of the edge of the channel region 142 and at least a portion of the low-doped region 144 and the thickness of other positions of the highly-doped region 146 are equal to the thickness of other positions of the channel region 142 of the polysilicon layer 140.
  • the thickness of the other regions of the channel region 142 of the polysilicon layer 140 in the embodiment of the present disclosure is relatively large, which can provide good carrier transmission performance.
  • the thickness of the edges of the channel region 142 and at least a part of the low-doped region 144 is larger than that of the channel region 142. Small, can reduce the absorption of photons.
  • step 10 the island-shaped photoresist layer 150 is peeled.
  • the low-temperature polysilicon layer 10 of the embodiment of the present disclosure does not need to be provided with a light shielding layer.
  • layer (LS) which saves at least one process of masking the light-shielding layer, so the number of photomasks required for manufacturing the low-temperature polysilicon layer 10 is smaller and the product manufacturing cycle is shorter.
  • Both the low-doped region 144 and the channel region 142 of the polysilicon layer 140 can generate photo-generated electron-hole pairs under the illumination of the backlight 170 (as shown in FIG. 13), but only at the edges and low-doped regions of the channel region 142.
  • Carriers near the hetero region 144 can be effectively separated under the action of an applied electric field or a PN junction, and the photogenerated electron-holes located in the middle of the channel region 142 will soon recombine. There may be no obvious leakage of light. Contribution. Therefore, the embodiments of the present disclosure mainly reduce the photo-generated leakage current by reducing the generation of photo-generated electron-hole pairs in the channel region 142 and the low-doped region 144 and reducing the separation efficiency of the photo-generated electron-hole pairs.
  • a P-type semiconductor and an N-type semiconductor are fabricated on the same semiconductor substrate, and a space charge region is formed at the interface between the P-type semiconductor and the N-type semiconductor, which is called a PN junction.
  • the low-temperature polysilicon layer 10 saves a light-shielding layer, and at least one process of manufacturing a light-shielding mask. Therefore, the number of photomasks required for manufacturing the low-temperature polysilicon layer 10 is shorter and the product manufacturing cycle is shorter.
  • the channel region 142 can provide good carrier transport performance, reduce the generation of photo-generated electron-hole pairs in the channel region 142 and the low-doped region 144, and reduce the separation efficiency of the photo-generated electron-hole pairs, thereby reducing photo-generated leakage. Current.
  • an embodiment of the present disclosure provides a method for manufacturing a thin film transistor, including the following steps.
  • a low-temperature polysilicon layer 10 is provided.
  • the low-temperature polysilicon layer 10 is prepared by the method for manufacturing the low-temperature polysilicon layer 10 described above, that is, as described in steps 1 to 12 above.
  • a gate insulating layer 210, a gate electrode 220, an interlayer dielectric insulating layer 230, two via holes 240, a source electrode 250 and a drain electrode 260 are formed on the low-temperature polysilicon layer 10.
  • the via hole 240 penetrates the gate insulating layer 210 and the interlayer dielectric insulating layer 230, and the source electrode 250 and the drain electrode 260 contact the two ends of the low-temperature polysilicon layer 10 through the corresponding via hole 240.
  • the material of the gate insulating layer 210 includes silicon oxide (SiOx).
  • the material of the gate electrode 220 includes molybdenum (Mo).
  • the material of the interlayer dielectric insulating layer 230 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.
  • the material of the source electrode 250 and the drain electrode 260 includes aluminum (Al).
  • the source electrode 250 and the drain electrode 260 are in contact with the highly doped region 146 of the polysilicon layer 140 through corresponding via holes 240.
  • the distance between the gate electrode 220 and the edge of the channel region 142 of the polysilicon layer 140 is smaller than the distance between the gate electrode 220 and other positions of the channel region 142 of the polysilicon layer 140, so the electric field strength at the edge of the channel region 142 can be reduced. , Reduce dark current and inhibit the separation of photo-generated electron-hole pairs.
  • the distance between the gate electrode 220 and at least a part of the low-doped region 144 of the polysilicon layer 140 is smaller than the distance between the gate electrode 220 and the other positions of the channel region 142 of the polysilicon layer 140, so that the The strength of the electric field reduces the dark current and suppresses the separation of photogenerated electron-hole pairs.
  • the thin film transistor 20 is, for example, an N-type thin film transistor.
  • the thin film transistor 20 of the embodiment of the present disclosure saves a light-shielding layer and at least one process of manufacturing a light-shielding mask. Therefore, the number of light-shielding masks required for manufacturing the low-temperature polysilicon layer 10 is shorter and the product manufacturing cycle is shorter.
  • the channel region 142 can provide good carrier transport performance, reduce the generation of photo-generated electron-hole pairs in the channel region 142 and the low-doped region 144, and reduce the separation efficiency of the photo-generated electron-hole pairs, thereby reducing the trench
  • the electric field strength at the edge of the track region 142 reduces the dark current, thereby reducing the photo-generated leakage current and improving the optical display effect of the product, such as crosstalk. , Flicker, contrast reduction, etc.
  • FIG. 14 a schematic diagram of a structure of a low-temperature polysilicon layer 10 is provided according to an embodiment of the present disclosure.
  • the low-temperature polysilicon layer 10 includes a substrate 110, at least one buffer layer 120, and a polysilicon layer 140. At least one buffer layer 120 is disposed on the substrate 110. The polysilicon layer 140 is disposed on at least one buffer layer 120. The polysilicon layer 140 includes a channel region 142, two low-doped regions 144 disposed on both sides of the channel region 142, and two highly-doped regions 146 disposed outside the low-doped region 144. The thickness of the edge of the channel region 142 and at least a portion of the low-doped region 144 is smaller than the thickness of other positions of the polysilicon layer 140.
  • the polysilicon layer 140 is, for example, a convex island-shaped polysilicon layer.
  • the substrate 110 is, for example, a glass substrate.
  • the material of the at least one buffer layer 120 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination thereof.
  • the at least one buffer layer 120 may have a structure of two buffer layers. The materials of the two buffer layers may be different. Since the at least one buffer layer 120 is disposed on the substrate 110, it has the functions of blocking ion diffusion and heat preservation, and preventing the substrate 110 from being damaged.
  • the low-doped region 144 is an N-lowly-doped region
  • the highly-doped region 146 is an N-highly-doped region.
  • the channel region 142 of the polysilicon layer 140 has different thicknesses, and the edges of the channel region 142 of the polysilicon layer 140 and the thickness of at least a portion of the low-doped region 144 are smaller than the thickness of other positions of the channel region 142 of the polysilicon layer 140. . Therefore, the low-doped region 144 having a smaller thickness can suppress hot carriers.
  • the highly doped regions 146 of the polysilicon layer 140 have different thicknesses.
  • the edges of the highly doped regions 146 of the polysilicon layer 140 contact the lowly doped regions 144 and the thickness of the edges of the highly doped regions 146 is equal to the trenches of the polysilicon layer 140.
  • the thickness of the edge of the channel region 142 and at least a portion of the low-doped region 144 and the thickness of other positions of the highly-doped region 146 are equal to the thickness of other positions of the channel region 142 of the polysilicon layer 140.
  • the thickness of the channel region 142 at other positions of the polysilicon layer 140 in the embodiment of the present disclosure is large, which can provide good carrier transport performance, and the thickness of the edge of the channel region 142 and the low-doped region 144 is small. Can reduce the absorption of photons.
  • the low-temperature polysilicon layer 10 of the embodiment of the present disclosure saves a light-shielding layer, and the channel region 142 can provide good carrier transport performance, reducing the generation of photo-generated electron-hole pairs in the channel region 142 and the low-doped region 144. And reduce the separation efficiency of photogenerated electron-hole pairs, thereby reducing photogenerated leakage current.
  • FIG. 15 a schematic diagram of a thin film transistor 20 is provided according to an embodiment of the present disclosure.
  • the thin film transistor 20 of the embodiment of the present disclosure includes the aforementioned low-temperature polysilicon layer 10 and the gate insulating layer 210, the gate electrode 220, the interlayer dielectric insulating layer 230, two via holes 240, and a source electrode disposed on the low-temperature polysilicon layer 10. 250 and drain electrode 260.
  • the via hole 240 penetrates the gate insulating layer 210 and the interlayer dielectric insulating layer 230, and the source electrode 250 and the drain electrode 260 contact the two ends of the low-temperature polysilicon layer 10 through the corresponding via hole 240.
  • the material of the gate insulating layer 210 includes silicon oxide (SiOx).
  • the material of the gate electrode 220 includes molybdenum (Mo).
  • the material of the interlayer dielectric insulating layer 230 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.
  • the material of the source electrode 250 and the drain electrode 260 includes aluminum (Al).
  • the source electrode 250 and the drain electrode 260 are in contact with the highly doped region 146 of the polysilicon layer 140 through corresponding via holes 240.
  • the distance between the gate electrode 220 and the edge of the channel region 142 of the polysilicon layer 140 is smaller than the distance between the gate electrode 220 and other positions of the channel region of the polysilicon layer 140, so the electric field strength at the edge of the channel region 142 can be reduced. Reduction of dark current and suppression of separation of photogenerated electron-hole pairs.
  • the distance between the gate electrode 220 and at least a part of the low-doped region 144 of the polysilicon layer 140 is smaller than the distance between the gate electrode 220 and other positions of the channel region 142 of the polysilicon layer 140, so that the electric field strength of the low-doped region 144 can be reduced. , Reduce dark current and inhibit the separation of photo-generated electron-hole pairs.
  • the thin film transistor 20 of the embodiment of the present disclosure saves a light-shielding layer, and the channel region 142 can provide good carrier transmission performance, reducing the generation and sum of photo-generated electron-hole pairs in the channel region 142 and the low-doped region 144. Reduce the separation efficiency of photo-generated electron-hole pairs, so it can reduce the electric field strength at the edge of the channel region 142, reduce dark current, thereby reducing photo-generated leakage current and improving the optical display effect of the product, such as crosstalk, flicker , Decreased contrast, etc.
  • the thickness of the edge of the channel region of the polysilicon layer and at least a part of the low-doped region in the embodiment of the present disclosure is smaller than the thickness of other positions of the polysilicon layer.
  • the polysilicon layer is an island-shaped polysilicon layer. The embodiments of the present disclosure can reduce the absorption of photons by the low-temperature polysilicon layer and the photo-generated leakage current of the low-temperature polysilicon layer.

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Abstract

一种低温多晶硅层、薄膜晶体管及其制作方法。低温多晶硅层包括基板（110）、至少一缓冲层（120）以及多晶硅层（140），多晶硅层（140）设置在至少一缓冲层（120）上，多晶硅层（140）包括沟道区域（142）、设置在沟道区域（142）的两侧的两个低掺杂区域（144）、设置在低掺杂区域（144）的外侧的两个高掺杂区域（146），沟道区域（142）的边缘及至少部分低掺杂区域（144）的厚度小于多晶硅层（140）的其他位置的厚度。

Description

低温多晶硅层、薄膜晶体管及其制作方法 技术领域
本揭示涉及显示技术领域，特别涉及一种低温多晶硅层、薄膜晶体管及其制作方法。
 背景技术
低温多晶硅(low temperature poly silicon, LTPS)技术具有高载流子迁移率，被广泛用于具有高分辨率的中小尺寸的薄膜晶体管液晶显示器(thin film transistor-liquid crystal display, TFT LCD)和有源矩阵有机发光二极体(active-matrix organic light emitting diode, AMOLED)面板的制作，因而具有广阔的应用前景。
在传统的低温多晶硅技术中，薄膜晶体管通常包括顶栅(top gate)结构及遮光层(light shield layer，LS)，其中遮光层的制备需要增加一道遮光层光罩的制程，因此薄膜晶体管阵列基板制作所需的光罩数量更多及产品制作周期更长。
在另一传统的低温多晶硅技术中，薄膜晶体管的沟道容易引起光生漏电流，过大的漏电流将显着影响显示器的光学显示效果，如串扰(crosstalk) 、闪烁(flicker)、对比度降低等。
故，有需要提供一种低温多晶硅层、薄膜晶体管及其制作方法，以解决现有技术存在的问题。
 技术问题
在传统的低温多晶硅技术中，薄膜晶体管通常包括顶栅(top gate)结构及遮光层(light shield layer，LS)，其中遮光层的制备需要增加一道遮光层光罩的制程，因此薄膜晶体管阵列基板制作所需的光罩数量更多及产品制作周期更长。
在另一传统的低温多晶硅技术中，薄膜晶体管的沟道容易引起光生漏电流，过大的漏电流将显着影响显示器的光学显示效果，如串扰(crosstalk) 、闪烁(flicker)、对比度降低等。
 技术解决方案
为解决上述技术问题，本揭示提供一低温多晶硅层的制作方法，包括:提供基板；在所述基板上形成至少一缓冲层；在所述至少一缓冲层上形成多晶硅层；图案化所述多晶硅层以形成沟道区域，所述沟道区域的两侧包括对称设置的两个低掺杂区域，所述低掺杂区域的外侧包括对称设置的两个高掺杂区域；在所述多晶硅层的所述沟道区域、所述低掺杂区域及所述高掺杂区域上沉积岛状光阻层；去除覆盖所述沟道区域的边缘及所述低掺杂区域的所述岛状光阻层，以暴露出所述沟道区域的所述边缘及所述低掺杂区域；刻蚀所述沟道区域的所述边缘及至少部分所述低掺杂区域，使得所述沟道区域的所述边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度，以形成岛状多晶硅层；以及剥离所述岛状光阻层。所述低掺杂区域是N低掺杂区域，所述高掺杂区域是N高掺杂区域。所述岛状光阻层具有第一厚度及第二厚度，所述第一厚度小于所述第二厚度，具有所述第一厚度的所述岛状光阻层覆盖所述沟道区域的所述边缘及所述低掺杂区域。通过半色调掩膜对所述岛状光阻层进行曝光及显影以形成所述岛状光阻层，所述半色调掩膜具有不透光区域及透光区域，所述半色调掩膜的所述透光区域对应于所述沟道区域的所述边缘及所述低掺杂区域，以及所述半色调掩膜的所述不透光区域对应于所述多晶硅层的所述其他位置。
于本揭示其中的一实施例中，所述多晶硅层的所述沟道区域具有不同的厚度，所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度小于所述多晶硅层的所述沟道区域的其他位置的厚度。
于本揭示其中的一实施例中，所述多晶硅层的所述高掺杂区域具有不同的厚度，所述多晶硅层的所述高掺杂区域的边缘接触所述低掺杂区域且所述高掺杂区域的所述边缘的厚度等于所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度，以及所述高掺杂区域的其他位置的厚度等于所述多晶硅层的所述沟道区域的其他位置的厚度。
本揭示还提供一低温多晶硅层的制作方法，包括:提供基板；在所述基板上形成至少一缓冲层；在所述至少一缓冲层上形成多晶硅层；图案化所述多晶硅层以形成沟道区域，所述沟道区域的两侧包括对称设置的两个低掺杂区域，所述低掺杂区域的外侧包括对称设置的两个高掺杂区域；在所述多晶硅层的所述沟道区域、所述低掺杂区域及所述高掺杂区域上沉积岛状光阻层；去除覆盖所述沟道区域的边缘及所述低掺杂区域的所述岛状光阻层，以暴露出所述沟道区域的所述边缘及所述低掺杂区域；刻蚀所述沟道区域的所述边缘及至少部分所述低掺杂区域，使得所述沟道区域的所述边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度，以形成岛状多晶硅层；以及剥离所述岛状光阻层。
于本揭示其中的一实施例中，所述方法还包括在所述至少一缓冲层上形成非晶硅层，对所述非晶硅层进行准分子镭射，使所述非晶硅层成为所述多晶硅层，通过蚀刻去除未被所述岛状光阻层覆盖的所述多晶硅层。
于本揭示其中的一实施例中，所述低掺杂区域是N低掺杂区域，所述高掺杂区域是N高掺杂区域。
于本揭示其中的一实施例中，所述岛状光阻层具有第一厚度及第二厚度，所述第一厚度小于所述第二厚度，具有所述第一厚度的所述岛状光阻层覆盖所述沟道区域的所述边缘及至少部分所述低掺杂区域。
于本揭示其中的一实施例中，通过半色调掩膜对所述岛状光阻层进行曝光及显影以形成所述岛状光阻层，所述半色调掩膜具有不透光区域及透光区域，所述半色调掩膜的所述透光区域对应于所述沟道区域的所述边缘及所述低掺杂区域，以及所述半色调掩膜的所述不透光区域对应于所述多晶硅层的所述其他位置。
于本揭示其中的一实施例中，通入氧气对覆盖所述沟道区域的所述边缘及所述低掺杂区域的所述岛状光阻层进行光阻灰化处理以去除覆盖所述沟道区域的所述边缘及所述低掺杂区域的所述岛状光阻层。
于本揭示其中的一实施例中，所述多晶硅层的所述沟道区域具有不同的厚度，所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度小于所述多晶硅层的所述沟道区域的其他位置的厚度。
于本揭示其中的一实施例中，所述多晶硅层的所述高掺杂区域具有不同的厚度，所述多晶硅层的所述高掺杂区域的边缘接触所述低掺杂区域且所述高掺杂区域的所述边缘的厚度等于所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度，以及所述高掺杂区域的其他位置的厚度等于所述多晶硅层的所述沟道区域的其他位置的厚度。
本揭示还提供薄膜晶体管的制作方法，包括:提供低温多晶硅层及在所述低温多晶硅层上形成栅绝缘层、栅电极、层间介电绝缘层、两个过孔、源电极和漏电极，所述过孔贯穿所述栅绝缘层和所述层间介电绝缘层，所述源电极和所述漏电极通过对应的过孔与所述低温多晶硅层的两端接触，所述低温多晶硅层是前述的低温多晶硅层的制作方法制得。
于本揭示其中的一实施例中，所述栅电极与所述多晶硅层的所述沟道区域的所述边缘的距离小于所述栅电极与所述多晶硅层的所述沟道区域的其他位置的距离。
于本揭示其中的一实施例中，所述栅电极与所述多晶硅层的至少部分所述低掺杂区域的距离小于所述栅电极与所述多晶硅层的所述沟道区域的所述其他位置的距离。
本揭示还提供低温多晶硅层，包括基板、至少一缓冲层以及多晶硅层。所述至少一缓冲层设置在所述基板上。所述多晶硅层设置在所述至少一缓冲层上。所述多晶硅层包括沟道区域、设置在所述沟道区域的两侧的两个低掺杂区域以及设置在所述低掺杂区域的外侧的两个高掺杂区域。所述沟道区域的边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度。
于本揭示其中的一实施例中，所述低掺杂区域是N低掺杂区域，所述高掺杂区域是N高掺杂区域。
于本揭示其中的一实施例中，所述多晶硅层的所述沟道区域具有不同的厚度，所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度小于所述多晶硅层的所述沟道区域的其他位置的厚度。
于本揭示其中的一实施例中，所述多晶硅层的所述高掺杂区域具有不同的厚度，所述多晶硅层的所述高掺杂区域的边缘接触所述低掺杂区域且所述高掺杂区域的所述边缘的厚度等于所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度，以及所述高掺杂区域的其他位置的厚度等于所述多晶硅层的所述沟道区域的其他位置的厚度。
本揭示还提供薄膜晶体管，包括前述的低温多晶硅层及设置在所述低温多晶硅层上的栅绝缘层、栅电极、层间介电绝缘层、两个过孔、源电极和漏电极。所述过孔贯穿所述栅绝缘层和所述层间介电绝缘层，所述源电极和所述漏电极通过对应的过孔与所述低温多晶硅层的两端接触。
于本揭示其中的一实施例中，所述栅电极与所述多晶硅层的所述沟道区域的所述边缘的距离小于所述栅电极与所述多晶硅层的所述沟道区域的其他位置的距离。
于本揭示其中的一实施例中，所述栅电极与所述多晶硅层的至少部分所述低掺杂区域的距离小于所述栅电极与所述多晶硅层的所述沟道区域的所述其他位置的距离。
 有益效果
相较于现有技术，为解决上述技术问题，本揭示提供低温多晶硅层、薄膜晶体管及其制作方法，本揭示的实施例中的多晶硅层的沟道区域的边缘及至少部分低掺杂区域的厚度小于多晶硅层的其他位置的厚度，能减少低温多晶硅层对光子的吸收及降低低温多晶硅层的光生漏电流。
 附图说明
图1显示根据本揭示的一实施例的低温多晶硅层的制作方法的流程图；
图2显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图3显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图4显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图5显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图6显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图7显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图8显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图9显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图10显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图11显示根据本揭示的一实施例的低温多晶硅层的制作方法的示意图；
图12显示根据本揭示的一实施例的薄膜晶体管的制作方法的流程图；
图13显示根据本揭示的一实施例的薄膜晶体管的制作方法的示意图；
图14显示根据本揭示的一实施例的低温多晶硅层的结构示意图；以及
图15显示根据本揭示的一实施例的薄膜晶体管的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1，本揭示的一实施例提供低温多晶硅层的制作方法，包括如下步骤。
参照图1及图2，步骤1、提供基板110。
具体地，基板110例如是玻璃基板。
参照图1及图3，步骤2、在基板110上形成至少一缓冲层120。
具体地，至少一缓冲层120的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。至少一缓冲层120可为两层缓冲层的结构。此两层缓冲层的材料可不同。由于至少一缓冲层120设置在基板110上，具有阻绝离子扩散及保温作用，避免基板110受到破坏。
参照图1及图4，步骤3、在至少一缓冲层120上形成非晶硅层130。
参照图1及图5，步骤4、对非晶硅层130进行准分子镭射，使非晶硅层130成为多晶硅层140。
参照图1及图6，步骤5、图案化多晶硅层140以形成沟道区域142。沟道区域142的两侧包括对称设置的两个低掺杂区域144，低掺杂区域144的外侧包括对称设置的两个高掺杂区域146。
具体地，低掺杂区域144是N低掺杂区域，高掺杂区域146是N高掺杂区域。
参照图1及图7，步骤6、在多晶硅层140的沟道区域142、低掺杂区域144及高掺杂区域146上沉积岛状光阻层150。
具体地，岛状光阻层150具有第一厚度及第二厚度，第一厚度小于第二厚度，具有第一厚度的岛状光阻层150覆盖沟道区域142的边缘及低掺杂区域。
具体地，通过半色调掩膜160对岛状光阻层150进行曝光及显影以形成岛状光阻层150。半色调掩膜160具有不透光区域162及透光区域164，半色调掩膜160的透光区域164对应于沟道区域142的边缘及低掺杂区域144，以及半色调掩膜160的不透光区域162对应于多晶硅层140的其他位置。
参照图1及图8，步骤7、通过蚀刻去除未被岛状光阻层150覆盖的多晶硅层140。
参照图1及图9，步骤8、去除覆盖沟道区域142的边缘及低掺杂区域144的岛状光阻层150，以暴露出沟道区域142的边缘及低掺杂区域146。
具体地，还去除覆盖高掺杂区域146的边缘的岛状光阻层150，以暴露出高掺杂区域146的边缘，且高掺杂区域146的边缘接触低掺杂区域144。
具体地，通入氧气(O2)对覆盖沟道区域142的边缘、低掺杂区域144及高掺杂区域146的边缘的岛状光阻层150进行光阻灰化(photoresist ash)处理以去除覆盖沟道区域142的边缘、低掺杂区域144及高掺杂区域146的边缘的岛状光阻层150。
参照图1及图10，步骤9、刻蚀沟道区域142的边缘及至少部分低掺杂区域144，使得沟道区域142的边缘及低掺杂区域144的厚度小于多晶硅层140的其他位置的厚度，以形成岛状多晶硅层。例如通过蚀刻的时间控制沟道区域142的边缘及低掺杂区域144的厚度以形成岛状多晶硅层。
具体地，多晶硅层140例如为凸字形的岛状多晶硅层。
具体地，多晶硅层140的沟道区域142具有不同的厚度，多晶硅层140的沟道区域142的边缘及至少部分低掺杂区域144的厚度小于多晶硅层140的沟道区域142的其他位置的厚度。
具体地，并不是整个低掺杂区域144都被刻蚀，例如，以沟道区域142的边界处为界，左右0.5-1um处需被刻蚀，而低掺杂区域144144的宽度在0.7-1.5um之间，故低掺杂区域144可不全部刻蚀，但全部刻蚀甚至延伸至部分高掺杂区域146也可以。
具体地，多晶硅层140的高掺杂区域146具有不同的厚度，多晶硅层140的高掺杂区域146的边缘接触低掺杂区域144且高掺杂区域146的边缘的厚度等于多晶硅层140的沟道区域142的边缘及至少部分低掺杂区域144的厚度，以及高掺杂区域146的其他位置的厚度等于多晶硅层140的沟道区域142的其他位置的厚度。
因此，本揭示的实施例的多晶硅层140的沟道区域142的其他位置的厚度较大能提供良好的载流子传输性能，沟道区域142的边缘及至少部分低掺杂区域144的厚度较小，能减少对光子的吸收。
参照图1及图11，步骤10、剥离岛状光阻层150。
至此，完成了低温多晶硅层10的制作。
本揭示的实施例的低温多晶硅层10不需设置遮光层(light shield layer，LS)，至少节省了一道遮光层光罩的制程，因此低温多晶硅层10制作所需的光罩数量更少及产品制作周期更短。多晶硅层140的低掺杂区域144及沟道区域142在背光源170(如图13所示)的照射下都能够产生光生电子-空穴对，但只有位于沟道区域142的边缘及低掺杂区域144附近的载流子在外加电场或PN结(PN junction)的作用下能够被有效分离，而位于沟道区域142的中间的光生电子-空穴会很快复合对光漏电可能没有明显的贡献。因此本揭示的实施例降低光生漏电流主要途径是减少沟道区域142的及低掺杂区域144的光生电子-空穴对的生成和降低光生电子空穴对的分离效率。
需要说明的是，将P型半导体与N型半导体制作在同一块半导体基片上，在P型半导体与N型半导体的交界面形成空间电荷区称为PN结。
本揭示的实施例的低温多晶硅层10节省了遮光层，至少节省了一道遮光层光罩的制程，因此低温多晶硅层10制作所需的光罩数量更少及产品制作周期更短。沟道区域142能提供良好的载流子传输性能，减少沟道区域142的及低掺杂区域144的光生电子-空穴对的生成和降低光生电子空穴对的分离效率，从而降低光生漏电流。
参照图12，本揭示的一实施例提供薄膜晶体管的制作方法，包括如下步骤。
参照图12及图13，步骤21、提供低温多晶硅层10。
具体地，低温多晶硅层10是通过如前述的低温多晶硅层10的制作方法制得，即如前述的步骤1至步骤12。
参照图12及图13，步骤22、在低温多晶硅层10上形成栅绝缘层210、栅电极220、层间介电绝缘层230、两个过孔240、源电极250和漏电极260。过孔240贯穿栅绝缘层210和层间介电绝缘层230，源电极250和漏电极260通过对应的过孔240与低温多晶硅层10的两端接触。
具体地，栅绝缘层210的材料包括氧化硅(SiOx)。栅电极220的材料包括钼(Mo)。层间介电绝缘层230的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。源电极250和漏电极260的材料包括铝(Al)。
具体地，源电极250和漏电极260通过对应的过孔240与多晶硅层140的高掺杂区域146接触。
具体地，栅电极220与多晶硅层140的沟道区域142的边缘的距离小于栅电极220与多晶硅层140的沟道区域142的其他位置的距离，因此能降低沟道区域142的边缘的电场强度，减少暗电流和抑制光生电子空穴对的分离。
具体地，栅电极220与多晶硅层140的至少部分低掺杂区域144的距离小于栅电极220与多晶硅层140的沟道区域142的所述其他位置的距离，因此能降低低掺杂区域144的电场强度，减少暗电流和抑制光生电子空穴对的分离。
至此，完成了薄膜晶体管20的制作。
薄膜晶体管20例如为N型薄膜晶体管。
本揭示的实施例的薄膜晶体管20节省了遮光层，至少节省了一道遮光层光罩的制程，因此低温多晶硅层10制作所需的光罩数量更少及产品制作周期更短。沟道区域142能提供良好的载流子传输性能，减少沟道区域142的及低掺杂区域144的光生电子-空穴对的生成和降低光生电子空穴对的分离效率，因此能降低沟道区域142的边缘的电场强度，减少暗电流，从而降低光生漏电流及提升产品的光学显示效果，如串扰(crosstalk) 、闪烁(flicker)、对比度降低等。
参照图14，本揭示的一实施例提供低温多晶硅层10的结构示意图。
本揭示的实施例的低温多晶硅层10包括基板110、至少一缓冲层120以及多晶硅层140。至少一缓冲层120设置在基板110上。多晶硅层140设置在至少一缓冲层120上。多晶硅层140包括沟道区域142、设置在沟道区域142的两侧的两个低掺杂区域144以及设置在低掺杂区域144的外侧的两个高掺杂区域146。沟道区域142的边缘及至少部分低掺杂区域144的厚度小于多晶硅层140的其他位置的厚度。
具体地，多晶硅层140例如为凸字形的岛状多晶硅层。基板110例如是玻璃基板。
具体地，至少一缓冲层120的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。至少一缓冲层120可为两层缓冲层的结构。此两层缓冲层的材料可不同。由于至少一缓冲层120设置在基板110上，具有阻绝离子扩散及保温作用，避免基板110受到破坏。
具体地，低掺杂区域144是N低掺杂区域，高掺杂区域146是N高掺杂区域。
具体地，多晶硅层140的沟道区域142具有不同的厚度，多晶硅层140的沟道区域142的边缘及至少部分低掺杂区域144的厚度小于多晶硅层140的沟道区域142的其他位置的厚度。因此，具有较小厚度的低掺杂区域144能抑制热载流子。
具体地，多晶硅层140的高掺杂区域146具有不同的厚度，多晶硅层140的高掺杂区域146的边缘接触低掺杂区域144且高掺杂区域146的边缘的厚度等于多晶硅层140的沟道区域142的边缘及至少部分低掺杂区域144的厚度，以及高掺杂区域146的其他位置的厚度等于多晶硅层140的沟道区域142的其他位置的厚度。
因此，本揭示的实施例的多晶硅层140的沟道区域142的其他位置的厚度较大能提供良好的载流子传输性能，沟道区域142的边缘及低掺杂区域144的厚度较小，能减少对光子的吸收。
本揭示的实施例的低温多晶硅层10节省了遮光层，沟道区域142能提供良好的载流子传输性能，减少沟道区域142的及低掺杂区域144的光生电子-空穴对的生成和降低光生电子空穴对的分离效率，从而降低光生漏电流。
参照图15，本揭示的一实施例提供薄膜晶体管20的结构示意图。
本揭示的实施例的薄膜晶体管20包括前述的低温多晶硅层10及设置在低温多晶硅层10上的栅绝缘层210、栅电极220、层间介电绝缘层230、两个过孔240、源电极250和漏电极260。过孔240贯穿栅绝缘层210和层间介电绝缘层230，源电极250和漏电极260通过对应的过孔240与低温多晶硅层10的两端接触。
具体地，栅绝缘层210的材料包括氧化硅(SiOx)。栅电极220的材料包括钼(Mo)。层间介电绝缘层230的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。源电极250和漏电极260的材料包括铝(Al)。
具体地，源电极250和漏电极260通过对应的过孔240与多晶硅层140的高掺杂区域146接触。
具体地，栅电极220与多晶硅层140的沟道区域142的边缘的距离小于栅电极220与多晶硅层140的沟道区域的其他位置的距离，因此能降低沟道区域142的边缘的电场强度，减少暗电流和抑制光生电子空穴对的分离。
具体地，栅电极220与多晶硅层140的至少部分低掺杂区域144的距离小于栅电极220与多晶硅层140的沟道区域142的其他位置的距离，因此能降低低掺杂区域144的电场强度，减少暗电流和抑制光生电子空穴对的分离。
本揭示的实施例的薄膜晶体管20节省了遮光层，沟道区域142能提供良好的载流子传输性能，减少沟道区域142的及低掺杂区域144的光生电子-空穴对的生成和降低光生电子空穴对的分离效率，因此能降低沟道区域142的边缘的电场强度，减少暗电流，从而降低光生漏电流及提升产品的光学显示效果，如串扰(crosstalk) 、闪烁(flicker)、对比度降低等。
由于本揭示的实施例中的多晶硅层的沟道区域的边缘及至少部分低掺杂区域的厚度小于多晶硅层的其他位置的厚度。多晶硅层是岛状多晶硅层。本揭示的实施例能减少低温多晶硅层对光子的吸收及降低低温多晶硅层的光生漏电流。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (20)

  1. 一种低温多晶硅层的制作方法，包括:
    提供基板；
    在所述基板上形成至少一缓冲层；
    在所述至少一缓冲层上形成多晶硅层；
    图案化所述多晶硅层以形成沟道区域，所述沟道区域的两侧包括对称设置的两个低掺杂区域，所述低掺杂区域的外侧包括对称设置的两个高掺杂区域；
    在所述多晶硅层的所述沟道区域、所述低掺杂区域及所述高掺杂区域上沉积岛状光阻层；
    去除覆盖所述沟道区域的边缘及所述低掺杂区域的所述岛状光阻层，以暴露出所述沟道区域的所述边缘及所述低掺杂区域；
    刻蚀所述沟道区域的所述边缘及至少部分所述低掺杂区域，使得所述沟道区域的所述边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度，以形成岛状多晶硅层；以及
    剥离所述岛状光阻层；
    其中所述低掺杂区域是N低掺杂区域，所述高掺杂区域是N高掺杂区域；
    其中所述岛状光阻层具有第一厚度及第二厚度，所述第一厚度小于所述第二厚度，具有所述第一厚度的所述岛状光阻层覆盖所述沟道区域的所述边缘及所述低掺杂区域；
    其中通过半色调掩膜对所述岛状光阻层进行曝光及显影以形成所述岛状光阻层，所述半色调掩膜具有不透光区域及透光区域，所述半色调掩膜的所述透光区域对应于所述沟道区域的所述边缘及所述低掺杂区域，以及所述半色调掩膜的所述不透光区域对应于所述多晶硅层的所述其他位置。
  2. 如权利要求1所述的低温多晶硅层的制作方法，其中所述多晶硅层的所述沟道区域具有不同的厚度，所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度小于所述多晶硅层的所述沟道区域的其他位置的厚度。
  3. 如权利要求1所述的低温多晶硅层的制作方法，其中所述多晶硅层的所述高掺杂区域具有不同的厚度，所述多晶硅层的所述高掺杂区域的边缘接触所述低掺杂区域且所述高掺杂区域的所述边缘的厚度等于所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度，以及所述高掺杂区域的其他位置的厚度等于所述多晶硅层的所述沟道区域的其他位置的厚度。
  4. 一种低温多晶硅层的制作方法，包括:
    提供基板；
    在所述基板上形成至少一缓冲层；
    在所述至少一缓冲层上形成多晶硅层；
    图案化所述多晶硅层以形成沟道区域，所述沟道区域的两侧包括对称设置的两个低掺杂区域，所述低掺杂区域的外侧包括对称设置的两个高掺杂区域；
    在所述多晶硅层的所述沟道区域、所述低掺杂区域及所述高掺杂区域上沉积岛状光阻层；
    去除覆盖所述沟道区域的边缘及所述低掺杂区域的所述岛状光阻层，以暴露出所述沟道区域的所述边缘及所述低掺杂区域；
    刻蚀所述沟道区域的所述边缘及至少部分所述低掺杂区域，使得所述沟道区域的所述边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度，以形成岛状多晶硅层；以及
    剥离所述岛状光阻层。
  5. 如权利要求4所述的低温多晶硅层的制作方法，还包括在所述至少一缓冲层上形成非晶硅层，对所述非晶硅层进行准分子镭射，使所述非晶硅层成为所述多晶硅层，通过蚀刻去除未被所述岛状光阻层覆盖的所述多晶硅层。
  6. 如权利要求4所述的低温多晶硅层的制作方法，其中所述低掺杂区域是N低掺杂区域，所述高掺杂区域是N高掺杂区域。
  7. 如权利要求4所述的低温多晶硅层的制作方法，其中所述岛状光阻层具有第一厚度及第二厚度，所述第一厚度小于所述第二厚度，具有所述第一厚度的所述岛状光阻层覆盖所述沟道区域的所述边缘及所述低掺杂区域。
  8. 如权利要求7所述的低温多晶硅层的制作方法，其中通过半色调掩膜对所述岛状光阻层进行曝光及显影以形成所述岛状光阻层，所述半色调掩膜具有不透光区域及透光区域，所述半色调掩膜的所述透光区域对应于所述沟道区域的所述边缘及所述低掺杂区域，以及所述半色调掩膜的所述不透光区域对应于所述多晶硅层的所述其他位置。
  9. 如权利要求4所述的低温多晶硅层的制作方法，其中通入氧气对覆盖所述沟道区域的所述边缘及所述低掺杂区域的所述岛状光阻层进行光阻灰化处理以去除覆盖所述沟道区域的所述边缘及所述低掺杂区域的所述岛状光阻层。
  10.      如权利要求4所述的低温多晶硅层的制作方法，其中所述多晶硅层的所述沟道区域具有不同的厚度，所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度小于所述多晶硅层的所述沟道区域的其他位置的厚度。
  11.      如权利要求4所述的低温多晶硅层的制作方法，其中所述多晶硅层的所述高掺杂区域具有不同的厚度，所述多晶硅层的所述高掺杂区域的边缘接触所述低掺杂区域且所述高掺杂区域的所述边缘的厚度等于所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度，以及所述高掺杂区域的其他位置的厚度等于所述多晶硅层的所述沟道区域的其他位置的厚度。
  12. 一种薄膜晶体管的制作方法，包括:提供低温多晶硅层及在所述低温多晶硅层上形成栅绝缘层、栅电极、层间介电绝缘层、两个过孔、源电极和漏电极，所述过孔贯穿所述栅绝缘层和所述层间介电绝缘层，所述源电极和所述漏电极通过对应的过孔与所述低温多晶硅层的两端接触，所述低温多晶硅层是通过低温多晶硅层的制作方法制得，所述低温多晶硅层的制作方法，包括:
    提供基板；
    在所述基板上形成至少一缓冲层；
    在所述至少一缓冲层上形成多晶硅层；
    图案化所述多晶硅层以形成沟道区域，所述沟道区域的两侧包括对称设置的两个低掺杂区域，所述低掺杂区域的外侧包括对称设置的两个高掺杂区域；
    在所述多晶硅层的所述沟道区域、所述低掺杂区域及所述高掺杂区域上沉积岛状光阻层；
    去除覆盖所述沟道区域的边缘及所述低掺杂区域的所述岛状光阻层，以暴露出所述沟道区域的所述边缘及所述低掺杂区域；
    刻蚀所述沟道区域的所述边缘及至少部分所述低掺杂区域，使得所述沟道区域的所述边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度，以形成岛状多晶硅层；以及
    剥离所述岛状光阻层。
  13. 如权利要求12所述的薄膜晶体管的制作方法，其中所述栅电极与所述多晶硅层的所述沟道区域的所述边缘的距离小于所述栅电极与所述多晶硅层的所述沟道区域的其他位置的距离。
  14. 如权利要求13所述的薄膜晶体管的制作方法，其中所述栅电极与所述多晶硅层的至少部分所述低掺杂区域的距离小于所述栅电极与所述多晶硅层的所述沟道区域的所述其他位置的距离。
  15.      一种低温多晶硅层，包括:
    基板；
    至少一缓冲层，设置在所述基板上；以及
    多晶硅层，设置在所述至少一缓冲层上，所述多晶硅层包括沟道区域、设置在所述沟道区域的两侧的两个低掺杂区域以及设置在所述低掺杂区域的外侧的两个高掺杂区域，所述沟道区域的边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度。
  16.      如权利要求15所述的低温多晶硅层，其中所述多晶硅层的所述沟道区域具有不同的厚度，所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度小于所述多晶硅层的所述沟道区域的其他位置的厚度。
  17.      如权利要求15所述的低温多晶硅层，其中所述多晶硅层的所述高掺杂区域具有不同的厚度，所述多晶硅层的所述高掺杂区域的边缘接触所述低掺杂区域且所述高掺杂区域的所述边缘的厚度等于所述多晶硅层的所述沟道区域的所述边缘及至少部分所述低掺杂区域的所述厚度，以及所述高掺杂区域的其他位置的厚度等于所述多晶硅层的所述沟道区域的其他位置的厚度。
  18. 一种薄膜晶体管，包括:
    低温多晶硅层及设置在所述低温多晶硅层上的栅绝缘层、栅电极、层间介电绝缘层、两个过孔、源电极和漏电极，所述过孔贯穿所述栅绝缘层和所述层间介电绝缘层，所述源电极和所述漏电极通过对应的过孔与所述低温多晶硅层的两端接触，所述低温多晶硅层包括:
    基板；
    至少一缓冲层，设置在所述基板上；以及
    多晶硅层，设置在所述至少一缓冲层上，所述多晶硅层包括沟道区域、设置在所述沟道区域的两侧的两个低掺杂区域以及设置在所述低掺杂区域的外侧的两个高掺杂区域，所述沟道区域的边缘及至少部分所述低掺杂区域的厚度小于所述多晶硅层的其他位置的厚度。
  19. 如权利要求18所述的薄膜晶体管，其中所述栅电极与所述多晶硅层的所述沟道区域的所述边缘的距离小于所述栅电极与所述多晶硅层的所述沟道区域的其他位置的距离。
  20. 如权利要求19所述的薄膜晶体管，其中所述栅电极与所述多晶硅层的至少部分所述低掺杂区域的距离小于所述栅电极与所述多晶硅层的所述沟道区域的所述其他位置的距离。
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