WO2020051962A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2020051962A1
WO2020051962A1 PCT/CN2018/109289 CN2018109289W WO2020051962A1 WO 2020051962 A1 WO2020051962 A1 WO 2020051962A1 CN 2018109289 W CN2018109289 W CN 2018109289W WO 2020051962 A1 WO2020051962 A1 WO 2020051962A1
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WO
WIPO (PCT)
Prior art keywords
layer
bumps
display panel
thin film
display area
Prior art date
Application number
PCT/CN2018/109289
Other languages
English (en)
French (fr)
Inventor
王少波
陈彩琴
王一伊
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/344,019 priority Critical patent/US11056548B1/en
Publication of WO2020051962A1 publication Critical patent/WO2020051962A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel.
  • thin-film encapsulation is required after the light-emitting layer process is completed to greatly reduce the erosion of the device from external water and oxygen, and increase the device life.
  • the thin-film encapsulation layer 10 covers the entire display area 11 while encapsulating the peripheral GOA circuits 12 together; due to PECVD
  • the film quality requirements are high, and the film formation temperature is as high as 350 ° C or more.
  • the light emitting material is very sensitive to temperature, it can only be performed at low temperature during packaging, about 80 to 100 ° C.
  • the film quality of the thin-film encapsulation layer 10 is different from that of the ILD film 13 layer of the TFT substrate, so the stress is difficult to be consistent. Once the stress gap is too large, it is easy to cause peeling and fall off, and it is difficult to achieve the packaging effect.
  • the most susceptible to peeling off is the edge portion distributed around the glass substrate.
  • the present application provides a display panel, which can improve the risk of the film packaging layer and the underlying display panel film layer falling off.
  • the present application provides a display panel, including:
  • a flexible substrate including a display area and a non-display area around the display area;
  • a groove surrounding the display area is formed at a position of the thin film transistor layer corresponding to the non-display area;
  • a pixel definition layer provided on the flat layer and defining a pixel area
  • the flat layer and the pixel definition layer are formed into bumps after patterning a part of the non-display area, and the bumps are located between two adjacent grooves;
  • a light emitting layer is prepared on the flat layer corresponding to the pixel region
  • a thin-film encapsulation layer prepared on the light-emitting layer and used to wrap the light-emitting layer;
  • the thin film encapsulation layer covers the bumps and the grooves in the non-display area.
  • the bumps or the grooves are spaced from the edge corresponding to the light emitting layer to the edge of the thin film encapsulation layer located on the same side.
  • a plurality of the grooves with different depths are distributed on the film layer from the thin film transistor layer to the surface of the flexible substrate.
  • a cross-sectional shape of the thin film encapsulation layer corresponding to the non-display area matches a shape of the bump or the groove.
  • a cross-sectional shape of the groove is trapezoidal or stepped.
  • the bump includes a first bump formed after the flat layer is patterned, and the first bump is correspondingly located between two adjacent grooves.
  • a pattern formed by patterning the pixel definition layer is superimposed on part of the first bumps to form a second bump, and the second bumps are located in two adjacent grooves. between.
  • an organic spacer layer is further prepared on the pixel definition layer, and a pattern formed on the non-display region after patterning is superimposed on a portion of the second bump to form a third bump,
  • the third bump is located between two adjacent grooves.
  • a cross-sectional shape of the bump is trapezoidal or stepped.
  • the present application further provides a display panel, including:
  • a flexible substrate including a display area and a non-display area around the display area;
  • a groove surrounding the display area is formed at a position of the thin film transistor layer corresponding to the non-display area;
  • a pixel definition layer provided on the flat layer and defining a pixel area
  • the flat layer and the pixel definition layer are formed into bumps after patterning a part of the non-display area, and the bumps are located between two adjacent grooves;
  • a light emitting layer is prepared on the flat layer corresponding to the pixel region
  • a thin-film encapsulation layer prepared on the light-emitting layer and used to wrap the light-emitting layer;
  • the thin film encapsulation layer covers the bumps and the grooves in the non-display area, and the bumps and the grooves are disposed at segmented intervals corresponding to the thin film transistor layer of the non-display area .
  • the bumps or the grooves are spaced from the edge corresponding to the light emitting layer to the edge of the thin film encapsulation layer located on the same side.
  • a plurality of the grooves with different depths are distributed on the film layer from the thin film transistor layer to the surface of the flexible substrate.
  • a cross-sectional shape of the thin film encapsulation layer corresponding to the non-display area matches a shape of the bump or the groove.
  • a cross-sectional shape of the groove is trapezoidal or stepped.
  • the bump includes a first bump formed after the flat layer is patterned, and the first bump is correspondingly located between two adjacent grooves.
  • a pattern formed by patterning the pixel definition layer is superimposed on part of the first bumps to form a second bump, and the second bumps are located in two adjacent grooves. between.
  • an organic spacer layer is further prepared on the pixel definition layer, and a pattern formed on the non-display region after patterning is superimposed on a portion of the second bump to form a third bump,
  • the third bump is located between two adjacent grooves.
  • a cross-sectional shape of the bump is trapezoidal or stepped.
  • a groove or a groove is formed around the display area in the non-display area.
  • Bumps during the thin film encapsulation process, allow the thin film encapsulation layer to cover the grooves or bumps in the non-display area, so that the thin film encapsulation layer and other layers below it are fitted to each other, and the thin film encapsulation layer and the lower layer film The layers are tightly attached and not easy to fall off.
  • the inorganic layer in the thin film encapsulation layer can contact the inorganic film layer in the lower film layer through the groove, so that the sealing effect of the thin film encapsulation layer is better.
  • this design increases the thin film encapsulation.
  • the contact area between the layer and the film layer below it can further increase the adhesion and make the film layer difficult to fall off.
  • FIG. 1 is a schematic diagram of a display panel package in the prior art
  • FIG. 2 is a schematic diagram of a partial structure of a display panel provided in Embodiment 1 of the present application;
  • FIG. 3 is a schematic structural diagram of a display panel according to a second embodiment of the present application.
  • FIG. 4 is a schematic diagram of a partial structure of a display panel provided in Embodiment 2 of the present application.
  • FIG. 5 is a top view of a display panel according to an embodiment of the present application.
  • This application is directed to the display panel of the prior art, because the packaging can only be performed at a low temperature, so the film quality of the thin film encapsulation layer is different from the ILD film layer that it is in contact with, and the technical problem of peeling and peeling of the thin film encapsulation layer is very easy. This embodiment can solve this defect.
  • a schematic diagram of a partial structure of a display panel provided in Embodiment 1 of the present application includes a flexible substrate 20 including a display area and a non-display area around the display area; a buffer layer 21 Is prepared on the flexible substrate 20; a thin film transistor layer 22 is prepared on the buffer layer 21; a groove surrounding the display area is formed at a position of the thin film transistor layer 22 corresponding to the non-display area ( See Figure 3 for details); a flat layer 23 provided on the thin film transistor layer 22; an anode layer 24 provided on the flat layer 23; a pixel definition layer 25 provided on the flat layer 23, and A pixel region is defined corresponding to the position of the anode layer 24; a spacer 26 is formed on the pixel definition layer 25 around the pixel region, and the spacer 26 can be used as a support to vaporize and emit light in the pixel region.
  • a thin-film encapsulation layer prepared on the light-emitting layer and used to wrap the light-emitting layer.
  • trenches are usually provided for filling organic materials to improve the flexibility of the display panel in the corresponding area.
  • it includes a first trench 28 and a second trench 27, the first trench 28 and the second trench 27 may be located at the same position, and the first trench 28 and the second trench 27 may be The thin film transistor layer 22 and the buffer layer 21 are penetrated.
  • the display panel of the present application may form the first trench 28, the second trench 27, and the source-drain vias 220 of the thin film transistor layer 22 while surrounding the non-display area.
  • Corresponding grooves are formed around the display area, and edges of the thin film encapsulation layer extend to the grooves, so that the thin film encapsulation layer covers the bumps and the grooves in the non-display area.
  • FIG. 3 a schematic structural diagram of a display panel provided in Embodiment 2 of the present application.
  • the difference between this embodiment and the above-mentioned Embodiment 1 is that in this embodiment, protrusions staggered with the grooves 36 are formed on the thin film transistor layer.
  • Block 37, the bump 37 is formed during the patterning process of the flat layer, the pixel definition layer, and the organic spacer layer used to form the spacer in the first embodiment, and the protrusion
  • the block 37 is located between two adjacent grooves 36.
  • the groove 36 includes a first groove 360, a second groove 362, and a third groove 361.
  • the first groove 360 passes through the first groove and the second groove.
  • the first groove 360 penetrates the inter-insulating layer 33, the second gate insulating layer 32, the first gate insulating layer 31 and the buffer layer 30 in this order.
  • the second groove 362 is formed by implementing a process with the second trench, the second groove 362 penetrates the inter-insulating layer 33, and the third groove 361 is formed by communicating with the source.
  • the drain via is formed by a process, and the third groove 361 penetrates the inter-insulating layer 33, the second gate insulating layer 32, and the first gate insulating layer 31 in this order.
  • the first groove 360, the second groove 362, and the third groove 361 may be sequentially spaced from the boundary of the light emitting layer 34 to the periphery of the display panel.
  • the arrangement order of 360, the second groove 362 and the third groove 361 is not limited.
  • the bump 37 includes: a first bump 372 formed by performing the same process as the flat layer patterning, and the first bump 372 is located between two adjacent grooves 36; the pixel defining layer A pattern formed after patterning is superimposed on part of the first bump 372 to form a second bump 371, and the second bump 371 is located between two adjacent grooves 36; A layer of the organic spacer layer is prepared, and a pattern formed in the non-display region after the organic spacer layer is patterned is superimposed on a portion of the second bump 371 to form a third bump 370, and the third bump 370 is located between two adjacent grooves 36. After the organic spacer layer is patterned, the spacer is formed in the display area at the same time.
  • the cross-sectional shape of the bump 37 is trapezoidal or stepped, and the like is not limited herein.
  • the bumps 37 and the grooves 36 are spaced around the non-display area.
  • a thin film encapsulation layer 35 is prepared on the light emitting layer 34, and a portion of the thin film encapsulation layer 35 corresponding to the non-display area covers the bumps 37 and the grooves 36.
  • FIG. 4 a schematic diagram of a partial structure of a display panel provided in Embodiment 2 of the present application.
  • the thin film encapsulation layer 40 corresponding to the non-display area and other film layers of the display panel below it are fitted to each other.
  • the thin film encapsulation layer 40 includes The inorganic layer and the organic layer that are arranged in multiple layers are only the first inorganic layer 401, the first organic layer 402, and the second inorganic layer 403.
  • the display panel is provided with a plurality of grooves 42 on the periphery of the light emitting layer 41.
  • the cross-sectional shape of the thin film encapsulation layer 40 corresponding to the non-display area matches the shapes of the bumps 43 and the grooves 42.
  • the first inorganic layer 401 is in contact with the underlying inorganic material film layer through the first groove, the second groove, and the third groove, respectively, so as to further strengthen the thin film encapsulation layer 40.
  • Packaging performance; the portion of the first inorganic layer 401 corresponding to the two adjacent grooves 42 is formed on the flat layer, the pixel defining layer, and the bump formed after patterning the organic spacer layer 43; wherein, for the formation and the positional relationship between the groove 42 and the bump 43, please refer to the description of FIG. 3 above, which will not be repeated here.
  • the groove 42 may also partially penetrate the inter-insulating layer 44, or partially penetrate the second gate insulating layer 45, or partially penetrate the first gate insulating layer 46, or The buffer layer 47 is partially penetrated;
  • the bump 43 may be a pattern of different heights formed by superposing the flat layer, the pixel definition layer, and the organic spacer layer, or may be formed by different film thicknesses.
  • the flat layer, the pixel defining layer, and the organic spacer layer are formed after being patterned, which are not limited herein.
  • a thin-film encapsulation layer 50 covers a light-emitting layer 52 in a display area, and grooves / bumps 51 are provided on a thin-film transistor layer in contact with edges around the thin-film encapsulation layer 50.
  • the grooves / the bumps 51 are spaced from the edge side corresponding to the light emitting layer 52 to the edge side corresponding to the thin film encapsulation layer 50.
  • the groove / bump 51 may continuously surround the light-emitting layer 52 in a circle, or may be arranged in intervals at intervals, or may be disposed at different positions in sections; preferably, corresponding to all corners around the thin film transistor layer.
  • the grooves / the bumps 51 and the grooves / the bumps 51 on the four sides of the thin film transistor layer are arranged at intervals, so that the stress in the four corner regions of the display panel can be relieved.
  • a groove or a bump is formed around the display area in the non-display area at the same time as the photolithography process of different films, and the thin film encapsulation process is performed.
  • the thin film encapsulation layer covers the grooves or bumps in the non-display area, so that the thin film encapsulation layer and the other film layers below it are fitted with each other, so that the thin film encapsulation layer and the lower film layer are closely adhered to each other and are not easy to fall off.
  • the inorganic layer in the thin film encapsulation layer can be in contact with the inorganic film layer in the lower film layer through the groove, so that the sealing effect of the thin film encapsulation layer is better.
  • this design increases the thin film encapsulation layer and the film layer below it. The contact area can further increase the adhesion and make the film layer not easy to fall off.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本申请提供一种显示面板，包括：柔性衬底，其包括显示区域与非显示区域；薄膜晶体管层设于所述柔性衬底上，且对应所述非显示区域形成有凹槽；平坦层与像素定义层分别设于所述薄膜晶体管层上，且图案化后在所述非显示区域形成凸块；所述平坦层上依次设有发光层、薄膜封装层；所述薄膜封装层覆盖所述凸块和所述凹槽。

Description

一种显示面板 技术领域
本申请涉及显示屏技术领域，尤其涉及一种显示面板。
 背景技术
鉴于OLED发光器件对于水氧的敏感性，在发光层工艺完成以后需要对其进行薄膜封装，以大幅度减弱来自于外界水氧对器件的侵蚀，增加器件寿命。
OLED器件的封装(Thin Film Encapsulation）是在发光层工艺完成后进行的，如图1所示，薄膜封装层10覆盖整个显示区11的同时将外围的GOA电路12也一起封装在内；由于PECVD成ILD膜13时，对膜质要求较高，成膜温度高达350℃以上，通过调整工艺条件不断改善膜与膜之间的应力可以达到良好的膜层之间的匹配度，不会出现同一个位置应力差异过大造成膜层起皮脱落的现象，然而在薄膜封装时，由于发光材料对温度非常敏感，所以在封装时只能在低温下进行，大概80至100℃左右，在此工艺条件下薄膜封装层10的膜质与TFT基板的ILD膜13层不同，所以应力也难以一致，一旦应力差距过大，极易造成起皮脱落，就难以实现封装效果。对于玻璃衬底上的显示面板（panel）来说，最容易起皮脱落的是分布在玻璃衬底四周的边缘部分。
因此，有必要提供一种显示面板，以解决现有技术所存在的问题。
 技术问题
本申请提供一种显示面板，能够改善薄膜封装层与下层的显示面板膜层脱落的风险。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括：
柔性衬底，所述柔性衬底包括显示区域与所述显示区域外围的非显示区域；
薄膜晶体管层，制备于所述柔性衬底上；
所述薄膜晶体管层对应所述非显示区域的位置形成有围绕所述显示区域的凹槽；
平坦层，设置于所述薄膜晶体管层上；
像素定义层，设置于所述平坦层上，且定义出像素区域；
所述平坦层和所述像素定义层在所述非显示区域的部分经图案化后形成凸块，且所述凸块位于相邻两所述凹槽之间；
发光层，对应所述像素区域制备于所述平坦层上；
薄膜封装层，制备于所述发光层上并用于包裹所述发光层；
其中，所述薄膜封装层在所述非显示区域覆盖所述凸块和所述凹槽。
在本申请的显示面板中，所述凸块或所述凹槽由对应所述发光层的边缘向位于同侧的所述薄膜封装层的边缘间隔分布。
在本申请的显示面板中，由所述薄膜晶体管层至所述柔性衬底表面的膜层上分布有多个不同深度的所述凹槽。
在本申请的显示面板中，对应所述非显示区域的所述薄膜封装层的截面形状与所述凸块或所述凹槽的形状相匹配。
在本申请的显示面板中，所述凹槽的截面形状为梯形或阶梯状。
在本申请的显示面板中，所述凸块包括所述平坦层图案化后形成的第一凸块，所述第一凸块对应位于相邻两所述凹槽之间。
在本申请的显示面板中，所述像素定义层图案化后形成的图案叠加至部分所述第一凸块上，形成第二凸块，所述第二凸块位于相邻两所述凹槽之间。
在本申请的显示面板中，所述像素定义层上还制备有一层有机间隔层，图案化后在所述非显示区域形成的图案叠加至部分所述第二凸块上形成第三凸块，所述第三凸块位于相邻两所述凹槽之间。
在本申请的显示面板中，所述凸块的截面形状为梯形或阶梯状。
为解决上述问题，本申请还提供一种显示面板，包括：
柔性衬底，所述柔性衬底包括显示区域与所述显示区域外围的非显示区域；
薄膜晶体管层，制备于所述柔性衬底上；
所述薄膜晶体管层对应所述非显示区域的位置形成有围绕所述显示区域的凹槽；
平坦层，设置于所述薄膜晶体管层上；
像素定义层，设置于所述平坦层上，且定义出像素区域；
所述平坦层和所述像素定义层在所述非显示区域的部分经图案化后形成凸块，且所述凸块位于相邻两所述凹槽之间；
发光层，对应所述像素区域制备于所述平坦层上；
薄膜封装层，制备于所述发光层上并用于包裹所述发光层；
其中，所述薄膜封装层在所述非显示区域覆盖所述凸块和所述凹槽，所述凸块和所述凹槽对应所述非显示区域的所述薄膜晶体管层呈分段间隔设置。
在本申请的显示面板中，所述凸块或所述凹槽由对应所述发光层的边缘向位于同侧的所述薄膜封装层的边缘间隔分布。
在本申请的显示面板中，由所述薄膜晶体管层至所述柔性衬底表面的膜层上分布有多个不同深度的所述凹槽。
在本申请的显示面板中，对应所述非显示区域的所述薄膜封装层的截面形状与所述凸块或所述凹槽的形状相匹配。
在本申请的显示面板中，所述凹槽的截面形状为梯形或阶梯状。
在本申请的显示面板中，所述凸块包括所述平坦层图案化后形成的第一凸块，所述第一凸块对应位于相邻两所述凹槽之间。
在本申请的显示面板中，所述像素定义层图案化后形成的图案叠加至部分所述第一凸块上，形成第二凸块，所述第二凸块位于相邻两所述凹槽之间。
在本申请的显示面板中，所述像素定义层上还制备有一层有机间隔层，图案化后在所述非显示区域形成的图案叠加至部分所述第二凸块上形成第三凸块，所述第三凸块位于相邻两所述凹槽之间。
在本申请的显示面板中，所述凸块的截面形状为梯形或阶梯状。
 有益效果
本申请的有益效果为：本申请提供的显示面板，在该显示面板的阵列基板的制备过程中，通过在不同膜层光刻工艺的同时，在非显示区域围绕显示区域的四周形成凹槽或凸块，在薄膜封装制程中使得薄膜封装层在非显示区域的部分覆盖该凹槽或凸块，从而使得薄膜封装层与其下层的其他膜层相互嵌合设置，进而使薄膜封装层与下层膜层紧密贴合，不易脱落；同时薄膜封装层中的无机层可以通过凹槽与下层膜层中的无机膜层接触，使得薄膜封装层的密封效果更好，另外这样的设计增大了薄膜封装层与其下层的膜层的接触面积，可以进一步增加粘附性，使得膜层不易脱落。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术的显示面板封装示意图；
图2为本申请实施例一提供的一种显示面板局部结构示意图；
图3为本申请实施例二提供的一种显示面板结构示意图；
图4为本申请实施例二提供的显示面板局部结构示意图；
图5为本申请实施例提供的显示面板俯视图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请针对现有技术的显示面板，由于封装时只能在低温下进行，因此导致薄膜封装层的膜质与之接触的ILD膜层不同，极易造成薄膜封装层起皮脱落的技术问题，本实施例能够解决该缺陷。
参阅图2，为本申请实施例一提供的一种显示面板局部结构示意图，包括：柔性衬底20，所述柔性衬底20包括显示区域与所述显示区域外围的非显示区域；缓冲层21，制备于所述柔性衬底20上；薄膜晶体管层22，制备于所述缓冲层21上；所述薄膜晶体管层22对应所述非显示区域的位置形成有围绕所述显示区域的凹槽（详见图3所示）；平坦层23，设置于所述薄膜晶体管层22上；阳极层24，制备于所述平坦层23上；像素定义层25，设置于所述平坦层23上，且对应所述阳极层24的位置定义出像素区域；间隔垫26，围绕所述像素区域形成于所述像素定义层25上，所述间隔垫26作为支撑可用于在所述像素区域内蒸镀发光层（图示未标出）；薄膜封装层，制备于所述发光层上并用于包裹所述发光层。在所述非显示区域的绑定区域等特定的弯折区域，通常设置有挖槽，用于填充有机材料，以改善相应区域显示面板的柔性。比如包括第一挖槽28与第二挖槽27，所述第一挖槽28与所述第二挖槽27可以位于同一位置，所述第一挖槽28与所述第二挖槽27可以贯穿所述薄膜晶体管层22以及所述缓冲层21。本申请的所述显示面板可以在所述第一挖槽28与所述第二挖槽27以及所述薄膜晶体管层22的源漏极过孔220形成的同时，在所述非显示区域围绕所述显示区域的四周分别形成相应的凹槽，所述薄膜封装层的边缘延伸至所述凹槽处，使得所述薄膜封装层在所述非显示区域覆盖所述凸块和所述凹槽。
参阅图3，为本申请实施例二提供的一种显示面板结构示意图，本实施例与上述实施例一的区别在于：本实施例在所述薄膜晶体管层上形成与凹槽36交错设置的凸块37，所述凸块37是上述实施例一中的所述平坦层、所述像素定义层以及用于形成所述间隔垫的有机间隔层在图案化制程时一道形成的，且所述凸块37位于相邻两所述凹槽36之间。
具体地，所述凹槽36包括第一凹槽360、第二凹槽362以及第三凹槽361；所述第一凹槽360是通过与所述第一挖槽以及所述第二挖槽实施一道制程叠加形成的，所述第一凹槽360依次贯穿间绝缘层33、第二栅绝缘层32、第一栅绝缘层31以及缓冲层30。所述第二凹槽362是通过与所述第二挖槽实施一道制程形成的，所述第二凹槽362贯穿所述间绝缘层33；所述第三凹槽361是通过与所述源漏极过孔实施一道制程形成的，所述第三凹槽361依次贯穿所述间绝缘层33、所述第二栅绝缘层32以及所述第一栅绝缘层31。所述第一凹槽360、所述第二凹槽362以及所述第三凹槽361可从发光层34的边界向所述显示面板四周依次间隔设置，具体本申请对所述第一凹槽360、所述第二凹槽362以及所述第三凹槽361的排列顺序不做限制。
所述凸块37包括：与所述平坦层图案化实施同一道制程形成的第一凸块372，所述第一凸块372位于相邻两所述凹槽36之间；所述像素定义层图案化后形成的图案叠加至部分所述第一凸块372上形成第二凸块371，所述第二凸块371位于相邻两所述凹槽36之间；所述像素定义层上还制备有一层所述有机间隔层，所述有机间隔层图案化后在所述非显示区域形成的图案叠加至部分所述第二凸块371上形成第三凸块370，所述第三凸块370位于相邻两所述凹槽36之间。所述有机间隔层图案化后同时在所述显示区域形成所述间隔垫。其中，所述凸块37的截面形状为梯形或阶梯状等，此处不做限制。
所述凸块37与所述凹槽36间隔的分布于所述非显示区域的四周。薄膜封装层35制备于所述发光层34上，且所述薄膜封装层35对应所述非显示区域的部分覆盖所述凸块37和所述凹槽36。
参阅图4，为本申请实施例二提供的显示面板局部结构示意图，对应所述非显示区域的薄膜封装层40与其下层的显示面板的其他膜层相互嵌合设置，所述薄膜封装层40包括多层层叠设置的无机层与有机层，图示仅为第一无机层401、第一有机层402、第二无机层403；所述显示面板在发光层41的外围设置有多个凹槽42以及凸块43，对应所述非显示区域的所述薄膜封装层40的截面形状与所述凸块43和所述凹槽42的形状相匹配。其中，所述第一无机层401分别通过所述第一凹槽、所述第二凹槽、所述第三凹槽与下层的无机材料膜层接触，从而进一步加强所述薄膜封装层40的封装性能；所述第一无机层401对应相邻两所述凹槽42之间的部分形成在所述平坦层、所述像素定义层、所述有机间隔层图案化后形成的所述凸块43上；其中，所述凹槽42与所述凸块43的形成以及位置关系请参考上述对图3的描述，此处不再赘述。
当然，在其他实施例中，所述凹槽42也可以是部分贯穿所述间绝缘层44，或部分贯穿所述第二栅绝缘层45，或部分贯穿所述第一栅绝缘层46，或者部分贯穿所述缓冲层47；所述凸块43可以是所述平坦层、所述像素定义层、所述有机间隔层叠加后形成的不同高度的图案，也可以是分别由不同膜厚的所述平坦层、所述像素定义层、所述有机间隔层图案化后形成的，此处不做限定。
参阅图5，为本申请实施例提供的显示面板俯视图，薄膜封装层50包裹显示区域的发光层52，与所述薄膜封装层50四周边缘接触的薄膜晶体管层上设置有凹槽/凸块51，所述凹槽/所述凸块51由对应所述发光层52的边缘一侧向对应所述薄膜封装层50的边缘一侧间隔分布。其中，所述凹槽/所述凸块51可以连续围绕所述发光层52一圈，也可以分段间隔设置，亦或者分段错位设置；优选的，对应所述薄膜晶体管层四周角落的所述凹槽/所述凸块51与所述薄膜晶体管层四边的所述凹槽/所述凸块51分段间隔设置，这样可以缓解显示面板四个边角区域的应力。
本申请提供的显示面板，在该显示面板的阵列基板的制备过程中，通过在不同膜层光刻工艺的同时，在非显示区域围绕显示区域的四周形成凹槽或凸块，在薄膜封装制程中使得薄膜封装层在非显示区域的部分覆盖该凹槽或凸块，从而使得薄膜封装层与其下层的其他膜层相互嵌合设置，进而使薄膜封装层与下层膜层紧密贴合，不易脱落；同时薄膜封装层中的无机层可以通过凹槽与下层膜层中的无机膜层接触，使得薄膜封装层的密封效果更好，另外这样的设计增大了薄膜封装层与其下层的膜层的接触面积，可以进一步增加粘附性，使得膜层不易脱落。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种显示面板，其包括：
    柔性衬底，所述柔性衬底包括显示区域与所述显示区域外围的非显示区域；
    薄膜晶体管层，制备于所述柔性衬底上；
    所述薄膜晶体管层对应所述非显示区域的位置形成有围绕所述显示区域的凹槽；
    平坦层，设置于所述薄膜晶体管层上；
    像素定义层，设置于所述平坦层上，且定义出像素区域；
    所述平坦层和所述像素定义层在所述非显示区域的部分经图案化后形成凸块，且所述凸块位于相邻两所述凹槽之间；
    发光层，对应所述像素区域制备于所述平坦层上；
    薄膜封装层，制备于所述发光层上并用于包裹所述发光层；
    其中，所述薄膜封装层在所述非显示区域覆盖所述凸块和所述凹槽。
  2. 根据权利要求1所述的显示面板，其中，所述凸块或所述凹槽由对应所述发光层的边缘向位于同侧的所述薄膜封装层的边缘间隔分布。
  3. 根据权利要求1所述的显示面板，其中，由所述薄膜晶体管层至所述柔性衬底表面的膜层上分布有多个不同深度的所述凹槽。
  4. 根据权利要求1所述的显示面板，其中，对应所述非显示区域的所述薄膜封装层的截面形状与所述凸块或所述凹槽的形状相匹配。
  5. 根据权利要求1所述的显示面板，其中，所述凹槽的截面形状为梯形或阶梯状。
  6. 根据权利要求1所述的显示面板，其中，所述凸块包括所述平坦层图案化后形成的第一凸块，所述第一凸块对应位于相邻两所述凹槽之间。
  7. 根据权利要求6所述的显示面板，其中，所述像素定义层图案化后形成的图案叠加至部分所述第一凸块上，形成第二凸块，所述第二凸块位于相邻两所述凹槽之间。
  8. 根据权利要求7所述的显示面板，其中，所述像素定义层上还制备有一层有机间隔层，图案化后在所述非显示区域形成的图案叠加至部分所述第二凸块上形成第三凸块，所述第三凸块位于相邻两所述凹槽之间。
  9. 根据权利要求1所述的显示面板，其中，所述凸块的截面形状为梯形或阶梯状。
  10. 一种显示面板，其包括：
    柔性衬底，所述柔性衬底包括显示区域与所述显示区域外围的非显示区域；
    薄膜晶体管层，制备于所述柔性衬底上；
    所述薄膜晶体管层对应所述非显示区域的位置形成有围绕所述显示区域的凹槽；
    平坦层，设置于所述薄膜晶体管层上；
    像素定义层，设置于所述平坦层上，且定义出像素区域；
    所述平坦层和所述像素定义层在所述非显示区域的部分经图案化后形成凸块，且所述凸块位于相邻两所述凹槽之间；
    发光层，对应所述像素区域制备于所述平坦层上；
    薄膜封装层，制备于所述发光层上并用于包裹所述发光层；
    其中，所述薄膜封装层在所述非显示区域覆盖所述凸块和所述凹槽，所述凸块和所述凹槽对应所述非显示区域的所述薄膜晶体管层呈分段间隔设置。。
  11. 根据权利要求10所述的显示面板，其中，所述凸块或所述凹槽由对应所述发光层的边缘向位于同侧的所述薄膜封装层的边缘间隔分布。
  12. 根据权利要求10所述的显示面板，其中，由所述薄膜晶体管层至所述柔性衬底表面的膜层上分布有多个不同深度的所述凹槽。
  13. 根据权利要求10所述的显示面板，其中，对应所述非显示区域的所述薄膜封装层的截面形状与所述凸块或所述凹槽的形状相匹配。
  14. 根据权利要求10所述的显示面板，其中，所述凹槽的截面形状为梯形或阶梯状。
  15. 根据权利要求10所述的显示面板，其中，所述凸块包括所述平坦层图案化后形成的第一凸块，所述第一凸块对应位于相邻两所述凹槽之间。
  16. 根据权利要求15所述的显示面板，其中，所述像素定义层图案化后形成的图案叠加至部分所述第一凸块上，形成第二凸块，所述第二凸块位于相邻两所述凹槽之间。
  17. 根据权利要求16所述的显示面板，其中，所述像素定义层上还制备有一层有机间隔层，图案化后在所述非显示区域形成的图案叠加至部分所述第二凸块上形成第三凸块，所述第三凸块位于相邻两所述凹槽之间。
  18. 根据权利要求10所述的显示面板，其中，所述凸块的截面形状为梯形或阶梯状。
PCT/CN2018/109289 2018-09-12 2018-10-08 一种显示面板 WO2020051962A1 (zh)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111128010B (zh) * 2018-11-01 2021-10-29 京东方科技集团股份有限公司 显示面板及其制造方法及显示装置
CN109888116A (zh) * 2019-02-14 2019-06-14 固安翌光科技有限公司 一种高稳定性的oled器件及其制备方法
CN110190104B (zh) * 2019-06-03 2021-09-14 武汉天马微电子有限公司 一种显示面板及其制造方法
CN110335962A (zh) * 2019-06-20 2019-10-15 武汉华星光电半导体显示技术有限公司 Oled显示面板
CN110491910B (zh) * 2019-07-30 2022-04-26 武汉华星光电半导体显示技术有限公司 一种显示面板及其制备方法、显示装置
CN110491929B (zh) * 2019-09-05 2022-05-24 京东方科技集团股份有限公司 显示基板、制备方法及显示装置
CN110854289B (zh) * 2019-10-29 2022-05-31 深圳市华星光电半导体显示技术有限公司 一种oled显示面板及显示装置
CN111129034A (zh) * 2019-12-20 2020-05-08 武汉华星光电半导体显示技术有限公司 一种显示面板
CN111180489B (zh) * 2019-12-31 2022-12-09 武汉天马微电子有限公司 显示面板和显示装置
CN111640881B (zh) * 2020-06-17 2023-05-12 昆山国显光电有限公司 阵列基板及其制备方法
CN111834546A (zh) * 2020-07-07 2020-10-27 武汉华星光电半导体显示技术有限公司 显示装置、显示面板及其制作方法
CN112863342B (zh) * 2021-01-12 2022-07-12 武汉华星光电半导体显示技术有限公司 可拉伸显示模组及可拉伸显示设备
CN113488510B (zh) * 2021-06-17 2023-06-30 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170069873A1 (en) * 2015-09-07 2017-03-09 Samsung Display Co., Ltd. Display apparatus
CN107644946A (zh) * 2017-09-15 2018-01-30 武汉华星光电半导体显示技术有限公司 Oled显示面板的封装方法及封装结构
CN207116481U (zh) * 2017-08-31 2018-03-16 京东方科技集团股份有限公司 显示基板、显示装置
CN207381403U (zh) * 2017-08-31 2018-05-18 京东方科技集团股份有限公司 显示基板、显示面板
CN108281458A (zh) * 2017-01-03 2018-07-13 昆山工研院新型平板显示技术中心有限公司 柔性oled显示装置及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102362189B1 (ko) 2015-04-16 2022-02-11 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102388711B1 (ko) * 2015-04-27 2022-04-20 삼성디스플레이 주식회사 표시 장치
KR101763616B1 (ko) * 2015-07-29 2017-08-02 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102446425B1 (ko) * 2015-11-17 2022-09-23 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
EP3324457A4 (en) * 2015-12-30 2019-04-10 Shenzhen Royole Technologies Co., Ltd. FLEXIBLE DISPLAY SHEET AND MANUFACTURING METHOD THEREFOR
CN207637803U (zh) * 2017-12-26 2018-07-20 上海和辉光电有限公司 一种显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170069873A1 (en) * 2015-09-07 2017-03-09 Samsung Display Co., Ltd. Display apparatus
CN108281458A (zh) * 2017-01-03 2018-07-13 昆山工研院新型平板显示技术中心有限公司 柔性oled显示装置及其制备方法
CN207116481U (zh) * 2017-08-31 2018-03-16 京东方科技集团股份有限公司 显示基板、显示装置
CN207381403U (zh) * 2017-08-31 2018-05-18 京东方科技集团股份有限公司 显示基板、显示面板
CN107644946A (zh) * 2017-09-15 2018-01-30 武汉华星光电半导体显示技术有限公司 Oled显示面板的封装方法及封装结构

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